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Linux 4.16.11
[linux/fpc-iii.git] / drivers / pci / host / pci-v3-semi.c
blob7fef64869d19914a36003db6f8192498b0c0f34d
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Support for V3 Semiconductor PCI Local Bus to PCI Bridge
4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
5 *
6 * Based on the code from arch/arm/mach-integrator/pci_v3.c
7 * Copyright (C) 1999 ARM Limited
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
9 *
10 * Contributors to the old driver include:
11 * Russell King <linux@armlinux.org.uk>
12 * David A. Rusling <david.rusling@linaro.org> (uHAL, ARM Firmware suite)
13 * Rob Herring <robh@kernel.org>
14 * Liviu Dudau <Liviu.Dudau@arm.com>
15 * Grant Likely <grant.likely@secretlab.ca>
16 * Arnd Bergmann <arnd@arndb.de>
17 * Bjorn Helgaas <bhelgaas@google.com>
18 */
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/of_address.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_pci.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30 #include <linux/bitops.h>
31 #include <linux/irq.h>
32 #include <linux/mfd/syscon.h>
33 #include <linux/regmap.h>
34 #include <linux/clk.h>
35
36 #define V3_PCI_VENDOR 0x00000000
37 #define V3_PCI_DEVICE 0x00000002
38 #define V3_PCI_CMD 0x00000004
39 #define V3_PCI_STAT 0x00000006
40 #define V3_PCI_CC_REV 0x00000008
41 #define V3_PCI_HDR_CFG 0x0000000C
42 #define V3_PCI_IO_BASE 0x00000010
43 #define V3_PCI_BASE0 0x00000014
44 #define V3_PCI_BASE1 0x00000018
45 #define V3_PCI_SUB_VENDOR 0x0000002C
46 #define V3_PCI_SUB_ID 0x0000002E
47 #define V3_PCI_ROM 0x00000030
48 #define V3_PCI_BPARAM 0x0000003C
49 #define V3_PCI_MAP0 0x00000040
50 #define V3_PCI_MAP1 0x00000044
51 #define V3_PCI_INT_STAT 0x00000048
52 #define V3_PCI_INT_CFG 0x0000004C
53 #define V3_LB_BASE0 0x00000054
54 #define V3_LB_BASE1 0x00000058
55 #define V3_LB_MAP0 0x0000005E
56 #define V3_LB_MAP1 0x00000062
57 #define V3_LB_BASE2 0x00000064
58 #define V3_LB_MAP2 0x00000066
59 #define V3_LB_SIZE 0x00000068
60 #define V3_LB_IO_BASE 0x0000006E
61 #define V3_FIFO_CFG 0x00000070
62 #define V3_FIFO_PRIORITY 0x00000072
63 #define V3_FIFO_STAT 0x00000074
64 #define V3_LB_ISTAT 0x00000076
65 #define V3_LB_IMASK 0x00000077
66 #define V3_SYSTEM 0x00000078
67 #define V3_LB_CFG 0x0000007A
68 #define V3_PCI_CFG 0x0000007C
69 #define V3_DMA_PCI_ADR0 0x00000080
70 #define V3_DMA_PCI_ADR1 0x00000090
71 #define V3_DMA_LOCAL_ADR0 0x00000084
72 #define V3_DMA_LOCAL_ADR1 0x00000094
73 #define V3_DMA_LENGTH0 0x00000088
74 #define V3_DMA_LENGTH1 0x00000098
75 #define V3_DMA_CSR0 0x0000008B
76 #define V3_DMA_CSR1 0x0000009B
77 #define V3_DMA_CTLB_ADR0 0x0000008C
78 #define V3_DMA_CTLB_ADR1 0x0000009C
79 #define V3_DMA_DELAY 0x000000E0
80 #define V3_MAIL_DATA 0x000000C0
81 #define V3_PCI_MAIL_IEWR 0x000000D0
82 #define V3_PCI_MAIL_IERD 0x000000D2
83 #define V3_LB_MAIL_IEWR 0x000000D4
84 #define V3_LB_MAIL_IERD 0x000000D6
85 #define V3_MAIL_WR_STAT 0x000000D8
86 #define V3_MAIL_RD_STAT 0x000000DA
87 #define V3_QBA_MAP 0x000000DC
88
89 /* PCI STATUS bits */
90 #define V3_PCI_STAT_PAR_ERR BIT(15)
91 #define V3_PCI_STAT_SYS_ERR BIT(14)
92 #define V3_PCI_STAT_M_ABORT_ERR BIT(13)
93 #define V3_PCI_STAT_T_ABORT_ERR BIT(12)
94
95 /* LB ISTAT bits */
96 #define V3_LB_ISTAT_MAILBOX BIT(7)
97 #define V3_LB_ISTAT_PCI_RD BIT(6)
98 #define V3_LB_ISTAT_PCI_WR BIT(5)
99 #define V3_LB_ISTAT_PCI_INT BIT(4)
100 #define V3_LB_ISTAT_PCI_PERR BIT(3)
101 #define V3_LB_ISTAT_I2O_QWR BIT(2)
102 #define V3_LB_ISTAT_DMA1 BIT(1)
103 #define V3_LB_ISTAT_DMA0 BIT(0)
104
105 /* PCI COMMAND bits */
106 #define V3_COMMAND_M_FBB_EN BIT(9)
107 #define V3_COMMAND_M_SERR_EN BIT(8)
108 #define V3_COMMAND_M_PAR_EN BIT(6)
109 #define V3_COMMAND_M_MASTER_EN BIT(2)
110 #define V3_COMMAND_M_MEM_EN BIT(1)
111 #define V3_COMMAND_M_IO_EN BIT(0)
112
113 /* SYSTEM bits */
114 #define V3_SYSTEM_M_RST_OUT BIT(15)
115 #define V3_SYSTEM_M_LOCK BIT(14)
116 #define V3_SYSTEM_UNLOCK 0xa05f
117
118 /* PCI CFG bits */
119 #define V3_PCI_CFG_M_I2O_EN BIT(15)
120 #define V3_PCI_CFG_M_IO_REG_DIS BIT(14)
121 #define V3_PCI_CFG_M_IO_DIS BIT(13)
122 #define V3_PCI_CFG_M_EN3V BIT(12)
123 #define V3_PCI_CFG_M_RETRY_EN BIT(10)
124 #define V3_PCI_CFG_M_AD_LOW1 BIT(9)
125 #define V3_PCI_CFG_M_AD_LOW0 BIT(8)
126 /*
127 * This is the value applied to C/BE[3:1], with bit 0 always held 0
128 * during DMA access.
129 */
130 #define V3_PCI_CFG_M_RTYPE_SHIFT 5
131 #define V3_PCI_CFG_M_WTYPE_SHIFT 1
132 #define V3_PCI_CFG_TYPE_DEFAULT 0x3
133
134 /* PCI BASE bits (PCI -> Local Bus) */
135 #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000U
136 #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00U
137 #define V3_PCI_BASE_M_PREFETCH BIT(3)
138 #define V3_PCI_BASE_M_TYPE (3 << 1)
139 #define V3_PCI_BASE_M_IO BIT(0)
140
141 /* PCI MAP bits (PCI -> Local bus) */
142 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000U
143 #define V3_PCI_MAP_M_RD_POST_INH BIT(15)
144 #define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
145 #define V3_PCI_MAP_M_SWAP (3 << 8)
146 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0U
147 #define V3_PCI_MAP_M_REG_EN BIT(1)
148 #define V3_PCI_MAP_M_ENABLE BIT(0)
149
150 /* LB_BASE0,1 bits (Local bus -> PCI) */
151 #define V3_LB_BASE_ADR_BASE 0xfff00000U
152 #define V3_LB_BASE_SWAP (3 << 8)
153 #define V3_LB_BASE_ADR_SIZE (15 << 4)
154 #define V3_LB_BASE_PREFETCH BIT(3)
155 #define V3_LB_BASE_ENABLE BIT(0)
156
157 #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
158 #define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
159 #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
160 #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
161 #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
162 #define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
163 #define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
164 #define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
165 #define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
166 #define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
167 #define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
168 #define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
169
170 #define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
171
172 /* LB_MAP0,1 bits (Local bus -> PCI) */
173 #define V3_LB_MAP_MAP_ADR 0xfff0U
174 #define V3_LB_MAP_TYPE (7 << 1)
175 #define V3_LB_MAP_AD_LOW_EN BIT(0)
176
177 #define V3_LB_MAP_TYPE_IACK (0 << 1)
178 #define V3_LB_MAP_TYPE_IO (1 << 1)
179 #define V3_LB_MAP_TYPE_MEM (3 << 1)
180 #define V3_LB_MAP_TYPE_CONFIG (5 << 1)
181 #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
182
183 #define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
184
185 /* LB_BASE2 bits (Local bus -> PCI IO) */
186 #define V3_LB_BASE2_ADR_BASE 0xff00U
187 #define V3_LB_BASE2_SWAP_AUTO (3 << 6)
188 #define V3_LB_BASE2_ENABLE BIT(0)
189
190 #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
191
192 /* LB_MAP2 bits (Local bus -> PCI IO) */
193 #define V3_LB_MAP2_MAP_ADR 0xff00U
194
195 #define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
196
197 /* FIFO priority bits */
198 #define V3_FIFO_PRIO_LOCAL BIT(12)
199 #define V3_FIFO_PRIO_LB_RD1_FLUSH_EOB BIT(10)
200 #define V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 BIT(11)
201 #define V3_FIFO_PRIO_LB_RD1_FLUSH_ANY (BIT(10)|BIT(11))
202 #define V3_FIFO_PRIO_LB_RD0_FLUSH_EOB BIT(8)
203 #define V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 BIT(9)
204 #define V3_FIFO_PRIO_LB_RD0_FLUSH_ANY (BIT(8)|BIT(9))
205 #define V3_FIFO_PRIO_PCI BIT(4)
206 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_EOB BIT(2)
207 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 BIT(3)
208 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_ANY (BIT(2)|BIT(3))
209 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_EOB BIT(0)
210 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1 BIT(1)
211 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_ANY (BIT(0)|BIT(1))
212
213 /* Local bus configuration bits */
214 #define V3_LB_CFG_LB_TO_64_CYCLES 0x0000
215 #define V3_LB_CFG_LB_TO_256_CYCLES BIT(13)
216 #define V3_LB_CFG_LB_TO_512_CYCLES BIT(14)
217 #define V3_LB_CFG_LB_TO_1024_CYCLES (BIT(13)|BIT(14))
218 #define V3_LB_CFG_LB_RST BIT(12)
219 #define V3_LB_CFG_LB_PPC_RDY BIT(11)
220 #define V3_LB_CFG_LB_LB_INT BIT(10)
221 #define V3_LB_CFG_LB_ERR_EN BIT(9)
222 #define V3_LB_CFG_LB_RDY_EN BIT(8)
223 #define V3_LB_CFG_LB_BE_IMODE BIT(7)
224 #define V3_LB_CFG_LB_BE_OMODE BIT(6)
225 #define V3_LB_CFG_LB_ENDIAN BIT(5)
226 #define V3_LB_CFG_LB_PARK_EN BIT(4)
227 #define V3_LB_CFG_LB_FBB_DIS BIT(2)
228
229 /* ARM Integrator-specific extended control registers */
230 #define INTEGRATOR_SC_PCI_OFFSET 0x18
231 #define INTEGRATOR_SC_PCI_ENABLE BIT(0)
232 #define INTEGRATOR_SC_PCI_INTCLR BIT(1)
233 #define INTEGRATOR_SC_LBFADDR_OFFSET 0x20
234 #define INTEGRATOR_SC_LBFCODE_OFFSET 0x24
235
236 struct v3_pci {
237 struct device *dev;
238 void __iomem *base;
239 void __iomem *config_base;
240 struct pci_bus *bus;
241 u32 config_mem;
242 u32 io_mem;
243 u32 non_pre_mem;
244 u32 pre_mem;
245 phys_addr_t io_bus_addr;
246 phys_addr_t non_pre_bus_addr;
247 phys_addr_t pre_bus_addr;
248 struct regmap *map;
249 };
250
251 /*
252 * The V3 PCI interface chip in Integrator provides several windows from
253 * local bus memory into the PCI memory areas. Unfortunately, there
254 * are not really enough windows for our usage, therefore we reuse
255 * one of the windows for access to PCI configuration space. On the
256 * Integrator/AP, the memory map is as follows:
257 *
258 * Local Bus Memory Usage
259 *
260 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
261 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
262 * 60000000 - 60FFFFFF PCI IO. 16M
263 * 61000000 - 61FFFFFF PCI Configuration. 16M
264 *
265 * There are three V3 windows, each described by a pair of V3 registers.
266 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
267 * Base0 and Base1 can be used for any type of PCI memory access. Base2
268 * can be used either for PCI I/O or for I20 accesses. By default, uHAL
269 * uses this only for PCI IO space.
270 *
271 * Normally these spaces are mapped using the following base registers:
272 *
273 * Usage Local Bus Memory Base/Map registers used
274 *
275 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
276 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
277 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
278 * Cfg 61000000 - 61FFFFFF
279 *
280 * This means that I20 and PCI configuration space accesses will fail.
281 * When PCI configuration accesses are needed (via the uHAL PCI
282 * configuration space primitives) we must remap the spaces as follows:
283 *
284 * Usage Local Bus Memory Base/Map registers used
285 *
286 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
287 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
288 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
289 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
290 *
291 * To make this work, the code depends on overlapping windows working.
292 * The V3 chip translates an address by checking its range within
293 * each of the BASE/MAP pairs in turn (in ascending register number
294 * order). It will use the first matching pair. So, for example,
295 * if the same address is mapped by both LB_BASE0/LB_MAP0 and
296 * LB_BASE1/LB_MAP1, the V3 will use the translation from
297 * LB_BASE0/LB_MAP0.
298 *
299 * To allow PCI Configuration space access, the code enlarges the
300 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
301 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
302 * be remapped for use by configuration cycles.
303 *
304 * At the end of the PCI Configuration space accesses,
305 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
306 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
307 * reveal the now restored LB_BASE1/LB_MAP1 window.
308 *
309 * NOTE: We do not set up I2O mapping. I suspect that this is only
310 * for an intelligent (target) device. Using I2O disables most of
311 * the mappings into PCI memory.
312 */
313 static void __iomem *v3_map_bus(struct pci_bus *bus,
314 unsigned int devfn, int offset)
315 {
316 struct v3_pci *v3 = bus->sysdata;
317 unsigned int address, mapaddress, busnr;
318
319 busnr = bus->number;
320 if (busnr == 0) {
321 int slot = PCI_SLOT(devfn);
322
323 /*
324 * local bus segment so need a type 0 config cycle
325 *
326 * build the PCI configuration "address" with one-hot in
327 * A31-A11
328 *
329 * mapaddress:
330 * 3:1 = config cycle (101)
331 * 0 = PCI A1 & A0 are 0 (0)
332 */
333 address = PCI_FUNC(devfn) << 8;
334 mapaddress = V3_LB_MAP_TYPE_CONFIG;
335
336 if (slot > 12)
337 /*
338 * high order bits are handled by the MAP register
339 */
340 mapaddress |= BIT(slot - 5);
341 else
342 /*
343 * low order bits handled directly in the address
344 */
345 address |= BIT(slot + 11);
346 } else {
347 /*
348 * not the local bus segment so need a type 1 config cycle
349 *
350 * address:
351 * 23:16 = bus number
352 * 15:11 = slot number (7:3 of devfn)
353 * 10:8 = func number (2:0 of devfn)
354 *
355 * mapaddress:
356 * 3:1 = config cycle (101)
357 * 0 = PCI A1 & A0 from host bus (1)
358 */
359 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
360 address = (busnr << 16) | (devfn << 8);
361 }
362
363 /*
364 * Set up base0 to see all 512Mbytes of memory space (not
365 * prefetchable), this frees up base1 for re-use by
366 * configuration memory
367 */
368 writel(v3_addr_to_lb_base(v3->non_pre_mem) |
369 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE,
370 v3->base + V3_LB_BASE0);
371
372 /*
373 * Set up base1/map1 to point into configuration space.
374 * The config mem is always 16MB.
375 */
376 writel(v3_addr_to_lb_base(v3->config_mem) |
377 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE,
378 v3->base + V3_LB_BASE1);
379 writew(mapaddress, v3->base + V3_LB_MAP1);
380
381 return v3->config_base + address + offset;
382 }
383
384 static void v3_unmap_bus(struct v3_pci *v3)
385 {
386 /*
387 * Reassign base1 for use by prefetchable PCI memory
388 */
389 writel(v3_addr_to_lb_base(v3->pre_mem) |
390 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
391 V3_LB_BASE_ENABLE,
392 v3->base + V3_LB_BASE1);
393 writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
394 V3_LB_MAP_TYPE_MEM, /* was V3_LB_MAP_TYPE_MEM_MULTIPLE */
395 v3->base + V3_LB_MAP1);
396
397 /*
398 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
399 */
400 writel(v3_addr_to_lb_base(v3->non_pre_mem) |
401 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE,
402 v3->base + V3_LB_BASE0);
403 }
404
405 static int v3_pci_read_config(struct pci_bus *bus, unsigned int fn,
406 int config, int size, u32 *value)
407 {
408 struct v3_pci *v3 = bus->sysdata;
409 int ret;
410
411 dev_dbg(&bus->dev,
412 "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
413 PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
414 ret = pci_generic_config_read(bus, fn, config, size, value);
415 v3_unmap_bus(v3);
416 return ret;
417 }
418
419 static int v3_pci_write_config(struct pci_bus *bus, unsigned int fn,
420 int config, int size, u32 value)
421 {
422 struct v3_pci *v3 = bus->sysdata;
423 int ret;
424
425 dev_dbg(&bus->dev,
426 "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
427 PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
428 ret = pci_generic_config_write(bus, fn, config, size, value);
429 v3_unmap_bus(v3);
430 return ret;
431 }
432
433 static struct pci_ops v3_pci_ops = {
434 .map_bus = v3_map_bus,
435 .read = v3_pci_read_config,
436 .write = v3_pci_write_config,
437 };
438
439 static irqreturn_t v3_irq(int irq, void *data)
440 {
441 struct v3_pci *v3 = data;
442 struct device *dev = v3->dev;
443 u32 status;
444
445 status = readw(v3->base + V3_PCI_STAT);
446 if (status & V3_PCI_STAT_PAR_ERR)
447 dev_err(dev, "parity error interrupt\n");
448 if (status & V3_PCI_STAT_SYS_ERR)
449 dev_err(dev, "system error interrupt\n");
450 if (status & V3_PCI_STAT_M_ABORT_ERR)
451 dev_err(dev, "master abort error interrupt\n");
452 if (status & V3_PCI_STAT_T_ABORT_ERR)
453 dev_err(dev, "target abort error interrupt\n");
454 writew(status, v3->base + V3_PCI_STAT);
455
456 status = readb(v3->base + V3_LB_ISTAT);
457 if (status & V3_LB_ISTAT_MAILBOX)
458 dev_info(dev, "PCI mailbox interrupt\n");
459 if (status & V3_LB_ISTAT_PCI_RD)
460 dev_err(dev, "PCI target LB->PCI READ abort interrupt\n");
461 if (status & V3_LB_ISTAT_PCI_WR)
462 dev_err(dev, "PCI target LB->PCI WRITE abort interrupt\n");
463 if (status & V3_LB_ISTAT_PCI_INT)
464 dev_info(dev, "PCI pin interrupt\n");
465 if (status & V3_LB_ISTAT_PCI_PERR)
466 dev_err(dev, "PCI parity error interrupt\n");
467 if (status & V3_LB_ISTAT_I2O_QWR)
468 dev_info(dev, "I2O inbound post queue interrupt\n");
469 if (status & V3_LB_ISTAT_DMA1)
470 dev_info(dev, "DMA channel 1 interrupt\n");
471 if (status & V3_LB_ISTAT_DMA0)
472 dev_info(dev, "DMA channel 0 interrupt\n");
473 /* Clear all possible interrupts on the local bus */
474 writeb(0, v3->base + V3_LB_ISTAT);
475 if (v3->map)
476 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
477 INTEGRATOR_SC_PCI_ENABLE |
478 INTEGRATOR_SC_PCI_INTCLR);
479
480 return IRQ_HANDLED;
481 }
482
483 static int v3_integrator_init(struct v3_pci *v3)
484 {
485 unsigned int val;
486
487 v3->map =
488 syscon_regmap_lookup_by_compatible("arm,integrator-ap-syscon");
489 if (IS_ERR(v3->map)) {
490 dev_err(v3->dev, "no syscon\n");
491 return -ENODEV;
492 }
493
494 regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val);
495 /* Take the PCI bridge out of reset, clear IRQs */
496 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
497 INTEGRATOR_SC_PCI_ENABLE |
498 INTEGRATOR_SC_PCI_INTCLR);
499
500 if (!(val & INTEGRATOR_SC_PCI_ENABLE)) {
501 /* If we were in reset we need to sleep a bit */
502 msleep(230);
503
504 /* Set the physical base for the controller itself */
505 writel(0x6200, v3->base + V3_LB_IO_BASE);
506
507 /* Wait for the mailbox to settle after reset */
508 do {
509 writeb(0xaa, v3->base + V3_MAIL_DATA);
510 writeb(0x55, v3->base + V3_MAIL_DATA + 4);
511 } while (readb(v3->base + V3_MAIL_DATA) != 0xaa &&
512 readb(v3->base + V3_MAIL_DATA) != 0x55);
513 }
514
515 dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n");
516
517 return 0;
518 }
519
520 static int v3_pci_setup_resource(struct v3_pci *v3,
521 resource_size_t io_base,
522 struct pci_host_bridge *host,
523 struct resource_entry *win)
524 {
525 struct device *dev = v3->dev;
526 struct resource *mem;
527 struct resource *io;
528 int ret;
529
530 switch (resource_type(win->res)) {
531 case IORESOURCE_IO:
532 io = win->res;
533 io->name = "V3 PCI I/O";
534 v3->io_mem = io_base;
535 v3->io_bus_addr = io->start - win->offset;
536 dev_dbg(dev, "I/O window %pR, bus addr %pap\n",
537 io, &v3->io_bus_addr);
538 ret = pci_remap_iospace(io, io_base);
539 if (ret) {
540 dev_warn(dev,
541 "error %d: failed to map resource %pR\n",
542 ret, io);
543 return ret;
544 }
545 /* Setup window 2 - PCI I/O */
546 writel(v3_addr_to_lb_base2(v3->io_mem) |
547 V3_LB_BASE2_ENABLE,
548 v3->base + V3_LB_BASE2);
549 writew(v3_addr_to_lb_map2(v3->io_bus_addr),
550 v3->base + V3_LB_MAP2);
551 break;
552 case IORESOURCE_MEM:
553 mem = win->res;
554 if (mem->flags & IORESOURCE_PREFETCH) {
555 mem->name = "V3 PCI PRE-MEM";
556 v3->pre_mem = mem->start;
557 v3->pre_bus_addr = mem->start - win->offset;
558 dev_dbg(dev, "PREFETCHABLE MEM window %pR, bus addr %pap\n",
559 mem, &v3->pre_bus_addr);
560 if (resource_size(mem) != SZ_256M) {
561 dev_err(dev, "prefetchable memory range is not 256MB\n");
562 return -EINVAL;
563 }
564 if (v3->non_pre_mem &&
565 (mem->start != v3->non_pre_mem + SZ_256M)) {
566 dev_err(dev,
567 "prefetchable memory is not adjacent to non-prefetchable memory\n");
568 return -EINVAL;
569 }
570 /* Setup window 1 - PCI prefetchable memory */
571 writel(v3_addr_to_lb_base(v3->pre_mem) |
572 V3_LB_BASE_ADR_SIZE_256MB |
573 V3_LB_BASE_PREFETCH |
574 V3_LB_BASE_ENABLE,
575 v3->base + V3_LB_BASE1);
576 writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
577 V3_LB_MAP_TYPE_MEM, /* Was V3_LB_MAP_TYPE_MEM_MULTIPLE */
578 v3->base + V3_LB_MAP1);
579 } else {
580 mem->name = "V3 PCI NON-PRE-MEM";
581 v3->non_pre_mem = mem->start;
582 v3->non_pre_bus_addr = mem->start - win->offset;
583 dev_dbg(dev, "NON-PREFETCHABLE MEM window %pR, bus addr %pap\n",
584 mem, &v3->non_pre_bus_addr);
585 if (resource_size(mem) != SZ_256M) {
586 dev_err(dev,
587 "non-prefetchable memory range is not 256MB\n");
588 return -EINVAL;
589 }
590 /* Setup window 0 - PCI non-prefetchable memory */
591 writel(v3_addr_to_lb_base(v3->non_pre_mem) |
592 V3_LB_BASE_ADR_SIZE_256MB |
593 V3_LB_BASE_ENABLE,
594 v3->base + V3_LB_BASE0);
595 writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) |
596 V3_LB_MAP_TYPE_MEM,
597 v3->base + V3_LB_MAP0);
598 }
599 break;
600 case IORESOURCE_BUS:
601 dev_dbg(dev, "BUS %pR\n", win->res);
602 host->busnr = win->res->start;
603 break;
604 default:
605 dev_info(dev, "Unknown resource type %lu\n",
606 resource_type(win->res));
607 break;
608 }
609
610 return 0;
611 }
612
613 static int v3_get_dma_range_config(struct v3_pci *v3,
614 struct of_pci_range *range,
615 u32 *pci_base, u32 *pci_map)
616 {
617 struct device *dev = v3->dev;
618 u64 cpu_end = range->cpu_addr + range->size - 1;
619 u64 pci_end = range->pci_addr + range->size - 1;
620 u32 val;
621
622 if (range->pci_addr & ~V3_PCI_BASE_M_ADR_BASE) {
623 dev_err(dev, "illegal range, only PCI bits 31..20 allowed\n");
624 return -EINVAL;
625 }
626 val = ((u32)range->pci_addr) & V3_PCI_BASE_M_ADR_BASE;
627 *pci_base = val;
628
629 if (range->cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) {
630 dev_err(dev, "illegal range, only CPU bits 31..20 allowed\n");
631 return -EINVAL;
632 }
633 val = ((u32)range->cpu_addr) & V3_PCI_MAP_M_MAP_ADR;
634
635 switch (range->size) {
636 case SZ_1M:
637 val |= V3_LB_BASE_ADR_SIZE_1MB;
638 break;
639 case SZ_2M:
640 val |= V3_LB_BASE_ADR_SIZE_2MB;
641 break;
642 case SZ_4M:
643 val |= V3_LB_BASE_ADR_SIZE_4MB;
644 break;
645 case SZ_8M:
646 val |= V3_LB_BASE_ADR_SIZE_8MB;
647 break;
648 case SZ_16M:
649 val |= V3_LB_BASE_ADR_SIZE_16MB;
650 break;
651 case SZ_32M:
652 val |= V3_LB_BASE_ADR_SIZE_32MB;
653 break;
654 case SZ_64M:
655 val |= V3_LB_BASE_ADR_SIZE_64MB;
656 break;
657 case SZ_128M:
658 val |= V3_LB_BASE_ADR_SIZE_128MB;
659 break;
660 case SZ_256M:
661 val |= V3_LB_BASE_ADR_SIZE_256MB;
662 break;
663 case SZ_512M:
664 val |= V3_LB_BASE_ADR_SIZE_512MB;
665 break;
666 case SZ_1G:
667 val |= V3_LB_BASE_ADR_SIZE_1GB;
668 break;
669 case SZ_2G:
670 val |= V3_LB_BASE_ADR_SIZE_2GB;
671 break;
672 default:
673 dev_err(v3->dev, "illegal dma memory chunk size\n");
674 return -EINVAL;
675 break;
676 };
677 val |= V3_PCI_MAP_M_REG_EN | V3_PCI_MAP_M_ENABLE;
678 *pci_map = val;
679
680 dev_dbg(dev,
681 "DMA MEM CPU: 0x%016llx -> 0x%016llx => "
682 "PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n",
683 range->cpu_addr, cpu_end,
684 range->pci_addr, pci_end,
685 *pci_base, *pci_map);
686
687 return 0;
688 }
689
690 static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3,
691 struct device_node *np)
692 {
693 struct of_pci_range range;
694 struct of_pci_range_parser parser;
695 struct device *dev = v3->dev;
696 int i = 0;
697
698 if (of_pci_dma_range_parser_init(&parser, np)) {
699 dev_err(dev, "missing dma-ranges property\n");
700 return -EINVAL;
701 }
702
703 /*
704 * Get the dma-ranges from the device tree
705 */
706 for_each_of_pci_range(&parser, &range) {
707 int ret;
708 u32 pci_base, pci_map;
709
710 ret = v3_get_dma_range_config(v3, &range, &pci_base, &pci_map);
711 if (ret)
712 return ret;
713
714 if (i == 0) {
715 writel(pci_base, v3->base + V3_PCI_BASE0);
716 writel(pci_map, v3->base + V3_PCI_MAP0);
717 } else if (i == 1) {
718 writel(pci_base, v3->base + V3_PCI_BASE1);
719 writel(pci_map, v3->base + V3_PCI_MAP1);
720 } else {
721 dev_err(dev, "too many ranges, only two supported\n");
722 dev_err(dev, "range %d ignored\n", i);
723 }
724 i++;
725 }
726 return 0;
727 }
728
729 static int v3_pci_probe(struct platform_device *pdev)
730 {
731 struct device *dev = &pdev->dev;
732 struct device_node *np = dev->of_node;
733 resource_size_t io_base;
734 struct resource *regs;
735 struct resource_entry *win;
736 struct v3_pci *v3;
737 struct pci_host_bridge *host;
738 struct clk *clk;
739 u16 val;
740 int irq;
741 int ret;
742 LIST_HEAD(res);
743
744 host = pci_alloc_host_bridge(sizeof(*v3));
745 if (!host)
746 return -ENOMEM;
747
748 host->dev.parent = dev;
749 host->ops = &v3_pci_ops;
750 host->busnr = 0;
751 host->msi = NULL;
752 host->map_irq = of_irq_parse_and_map_pci;
753 host->swizzle_irq = pci_common_swizzle;
754 v3 = pci_host_bridge_priv(host);
755 host->sysdata = v3;
756 v3->dev = dev;
757
758 /* Get and enable host clock */
759 clk = devm_clk_get(dev, NULL);
760 if (IS_ERR(clk)) {
761 dev_err(dev, "clock not found\n");
762 return PTR_ERR(clk);
763 }
764 ret = clk_prepare_enable(clk);
765 if (ret) {
766 dev_err(dev, "unable to enable clock\n");
767 return ret;
768 }
769
770 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
771 v3->base = devm_ioremap_resource(dev, regs);
772 if (IS_ERR(v3->base))
773 return PTR_ERR(v3->base);
774 /*
775 * The hardware has a register with the physical base address
776 * of the V3 controller itself, verify that this is the same
777 * as the physical memory we've remapped it from.
778 */
779 if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16))
780 dev_err(dev, "V3_LB_IO_BASE = %08x but device is @%pR\n",
781 readl(v3->base + V3_LB_IO_BASE), regs);
782
783 /* Configuration space is 16MB directly mapped */
784 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
785 if (resource_size(regs) != SZ_16M) {
786 dev_err(dev, "config mem is not 16MB!\n");
787 return -EINVAL;
788 }
789 v3->config_mem = regs->start;
790 v3->config_base = devm_ioremap_resource(dev, regs);
791 if (IS_ERR(v3->config_base))
792 return PTR_ERR(v3->config_base);
793
794 ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &io_base);
795 if (ret)
796 return ret;
797
798 ret = devm_request_pci_bus_resources(dev, &res);
799 if (ret)
800 return ret;
801
802 /* Get and request error IRQ resource */
803 irq = platform_get_irq(pdev, 0);
804 if (irq <= 0) {
805 dev_err(dev, "unable to obtain PCIv3 error IRQ\n");
806 return -ENODEV;
807 }
808 ret = devm_request_irq(dev, irq, v3_irq, 0,
809 "PCIv3 error", v3);
810 if (ret < 0) {
811 dev_err(dev,
812 "unable to request PCIv3 error IRQ %d (%d)\n",
813 irq, ret);
814 return ret;
815 }
816
817 /*
818 * Unlock V3 registers, but only if they were previously locked.
819 */
820 if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
821 writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM);
822
823 /* Disable all slave access while we set up the windows */
824 val = readw(v3->base + V3_PCI_CMD);
825 val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
826 writew(val, v3->base + V3_PCI_CMD);
827
828 /* Put the PCI bus into reset */
829 val = readw(v3->base + V3_SYSTEM);
830 val &= ~V3_SYSTEM_M_RST_OUT;
831 writew(val, v3->base + V3_SYSTEM);
832
833 /* Retry until we're ready */
834 val = readw(v3->base + V3_PCI_CFG);
835 val |= V3_PCI_CFG_M_RETRY_EN;
836 writew(val, v3->base + V3_PCI_CFG);
837
838 /* Set up the local bus protocol */
839 val = readw(v3->base + V3_LB_CFG);
840 val |= V3_LB_CFG_LB_BE_IMODE; /* Byte enable input */
841 val |= V3_LB_CFG_LB_BE_OMODE; /* Byte enable output */
842 val &= ~V3_LB_CFG_LB_ENDIAN; /* Little endian */
843 val &= ~V3_LB_CFG_LB_PPC_RDY; /* TODO: when using on PPC403Gx, set to 1 */
844 writew(val, v3->base + V3_LB_CFG);
845
846 /* Enable the PCI bus master */
847 val = readw(v3->base + V3_PCI_CMD);
848 val |= PCI_COMMAND_MASTER;
849 writew(val, v3->base + V3_PCI_CMD);
850
851 /* Get the I/O and memory ranges from DT */
852 resource_list_for_each_entry(win, &res) {
853 ret = v3_pci_setup_resource(v3, io_base, host, win);
854 if (ret) {
855 dev_err(dev, "error setting up resources\n");
856 return ret;
857 }
858 }
859 ret = v3_pci_parse_map_dma_ranges(v3, np);
860 if (ret)
861 return ret;
862
863 /*
864 * Disable PCI to host IO cycles, enable I/O buffers @3.3V,
865 * set AD_LOW0 to 1 if one of the LB_MAP registers choose
866 * to use this (should be unused).
867 */
868 writel(0x00000000, v3->base + V3_PCI_IO_BASE);
869 val = V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS |
870 V3_PCI_CFG_M_EN3V | V3_PCI_CFG_M_AD_LOW0;
871 /*
872 * DMA read and write from PCI bus commands types
873 */
874 val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_RTYPE_SHIFT;
875 val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_WTYPE_SHIFT;
876 writew(val, v3->base + V3_PCI_CFG);
877
878 /*
879 * Set the V3 FIFO such that writes have higher priority than
880 * reads, and local bus write causes local bus read fifo flush
881 * on aperture 1. Same for PCI.
882 */
883 writew(V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 |
884 V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 |
885 V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 |
886 V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1,
887 v3->base + V3_FIFO_PRIORITY);
888
889
890 /*
891 * Clear any error interrupts, and enable parity and write error
892 * interrupts
893 */
894 writeb(0, v3->base + V3_LB_ISTAT);
895 val = readw(v3->base + V3_LB_CFG);
896 val |= V3_LB_CFG_LB_LB_INT;
897 writew(val, v3->base + V3_LB_CFG);
898 writeb(V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR,
899 v3->base + V3_LB_IMASK);
900
901 /* Special Integrator initialization */
902 if (of_device_is_compatible(np, "arm,integrator-ap-pci")) {
903 ret = v3_integrator_init(v3);
904 if (ret)
905 return ret;
906 }
907
908 /* Post-init: enable PCI memory and invalidate (master already on) */
909 val = readw(v3->base + V3_PCI_CMD);
910 val |= PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE;
911 writew(val, v3->base + V3_PCI_CMD);
912
913 /* Clear pending interrupts */
914 writeb(0, v3->base + V3_LB_ISTAT);
915 /* Read or write errors and parity errors cause interrupts */
916 writeb(V3_LB_ISTAT_PCI_RD | V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR,
917 v3->base + V3_LB_IMASK);
918
919 /* Take the PCI bus out of reset so devices can initialize */
920 val = readw(v3->base + V3_SYSTEM);
921 val |= V3_SYSTEM_M_RST_OUT;
922 writew(val, v3->base + V3_SYSTEM);
923
924 /*
925 * Re-lock the system register.
926 */
927 val = readw(v3->base + V3_SYSTEM);
928 val |= V3_SYSTEM_M_LOCK;
929 writew(val, v3->base + V3_SYSTEM);
930
931 list_splice_init(&res, &host->windows);
932 ret = pci_scan_root_bus_bridge(host);
933 if (ret) {
934 dev_err(dev, "failed to register host: %d\n", ret);
935 return ret;
936 }
937 v3->bus = host->bus;
938
939 pci_bus_assign_resources(v3->bus);
940 pci_bus_add_devices(v3->bus);
941
942 return 0;
943 }
944
945 static const struct of_device_id v3_pci_of_match[] = {
946 {
947 .compatible = "v3,v360epc-pci",
948 },
949 {},
950 };
951
952 static struct platform_driver v3_pci_driver = {
953 .driver = {
954 .name = "pci-v3-semi",
955 .of_match_table = of_match_ptr(v3_pci_of_match),
956 .suppress_bind_attrs = true,
957 },
958 .probe = v3_pci_probe,
959 };
960 builtin_platform_driver(v3_pci_driver);
Linux with added FPC-III support