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Linux 4.16.11
[linux/fpc-iii.git] / drivers / pci / host / pci-xgene.c
blob0a0d7ee6d3c9275374ad12128f5b330b964d34cc
1 // SPDX-License-Identifier: GPL-2.0+
2 /**
3 * APM X-Gene PCIe Driver
4 *
5 * Copyright (c) 2014 Applied Micro Circuits Corporation.
6 *
7 * Author: Tanmay Inamdar <tinamdar@apm.com>.
8 */
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/io.h>
12 #include <linux/jiffies.h>
13 #include <linux/memblock.h>
14 #include <linux/init.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_pci.h>
19 #include <linux/pci.h>
20 #include <linux/pci-acpi.h>
21 #include <linux/pci-ecam.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24
25 #define PCIECORE_CTLANDSTATUS 0x50
26 #define PIM1_1L 0x80
27 #define IBAR2 0x98
28 #define IR2MSK 0x9c
29 #define PIM2_1L 0xa0
30 #define IBAR3L 0xb4
31 #define IR3MSKL 0xbc
32 #define PIM3_1L 0xc4
33 #define OMR1BARL 0x100
34 #define OMR2BARL 0x118
35 #define OMR3BARL 0x130
36 #define CFGBARL 0x154
37 #define CFGBARH 0x158
38 #define CFGCTL 0x15c
39 #define RTDID 0x160
40 #define BRIDGE_CFG_0 0x2000
41 #define BRIDGE_CFG_4 0x2010
42 #define BRIDGE_STATUS_0 0x2600
43
44 #define LINK_UP_MASK 0x00000100
45 #define AXI_EP_CFG_ACCESS 0x10000
46 #define EN_COHERENCY 0xF0000000
47 #define EN_REG 0x00000001
48 #define OB_LO_IO 0x00000002
49 #define XGENE_PCIE_VENDORID 0x10E8
50 #define XGENE_PCIE_DEVICEID 0xE004
51 #define SZ_1T (SZ_1G*1024ULL)
52 #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
53
54 #define XGENE_V1_PCI_EXP_CAP 0x40
55
56 /* PCIe IP version */
57 #define XGENE_PCIE_IP_VER_UNKN 0
58 #define XGENE_PCIE_IP_VER_1 1
59 #define XGENE_PCIE_IP_VER_2 2
60
61 #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
62 struct xgene_pcie_port {
63 struct device_node *node;
64 struct device *dev;
65 struct clk *clk;
66 void __iomem *csr_base;
67 void __iomem *cfg_base;
68 unsigned long cfg_addr;
69 bool link_up;
70 u32 version;
71 };
72
73 static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg)
74 {
75 return readl(port->csr_base + reg);
76 }
77
78 static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val)
79 {
80 writel(val, port->csr_base + reg);
81 }
82
83 static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
84 {
85 return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
86 }
87
88 static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus)
89 {
90 struct pci_config_window *cfg;
91
92 if (acpi_disabled)
93 return (struct xgene_pcie_port *)(bus->sysdata);
94
95 cfg = bus->sysdata;
96 return (struct xgene_pcie_port *)(cfg->priv);
97 }
98
99 /*
100 * When the address bit [17:16] is 2'b01, the Configuration access will be
101 * treated as Type 1 and it will be forwarded to external PCIe device.
102 */
103 static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
104 {
105 struct xgene_pcie_port *port = pcie_bus_to_port(bus);
106
107 if (bus->number >= (bus->primary + 1))
108 return port->cfg_base + AXI_EP_CFG_ACCESS;
109
110 return port->cfg_base;
111 }
112
113 /*
114 * For Configuration request, RTDID register is used as Bus Number,
115 * Device Number and Function number of the header fields.
116 */
117 static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
118 {
119 struct xgene_pcie_port *port = pcie_bus_to_port(bus);
120 unsigned int b, d, f;
121 u32 rtdid_val = 0;
122
123 b = bus->number;
124 d = PCI_SLOT(devfn);
125 f = PCI_FUNC(devfn);
126
127 if (!pci_is_root_bus(bus))
128 rtdid_val = (b << 8) | (d << 3) | f;
129
130 xgene_pcie_writel(port, RTDID, rtdid_val);
131 /* read the register back to ensure flush */
132 xgene_pcie_readl(port, RTDID);
133 }
134
135 /*
136 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
137 * the translation from PCI bus to native BUS. Entire DDR region
138 * is mapped into PCIe space using these registers, so it can be
139 * reached by DMA from EP devices. The BAR0/1 of bridge should be
140 * hidden during enumeration to avoid the sizing and resource allocation
141 * by PCIe core.
142 */
143 static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
144 {
145 if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
146 (offset == PCI_BASE_ADDRESS_1)))
147 return true;
148
149 return false;
150 }
151
152 static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
153 int offset)
154 {
155 if ((pci_is_root_bus(bus) && devfn != 0) ||
156 xgene_pcie_hide_rc_bars(bus, offset))
157 return NULL;
158
159 xgene_pcie_set_rtdid_reg(bus, devfn);
160 return xgene_pcie_get_cfg_base(bus) + offset;
161 }
162
163 static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
164 int where, int size, u32 *val)
165 {
166 struct xgene_pcie_port *port = pcie_bus_to_port(bus);
167
168 if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
169 PCIBIOS_SUCCESSFUL)
170 return PCIBIOS_DEVICE_NOT_FOUND;
171
172 /*
173 * The v1 controller has a bug in its Configuration Request
174 * Retry Status (CRS) logic: when CRS is enabled and we read the
175 * Vendor and Device ID of a non-existent device, the controller
176 * fabricates return data of 0xFFFF0001 ("device exists but is not
177 * ready") instead of 0xFFFFFFFF ("device does not exist"). This
178 * causes the PCI core to retry the read until it times out.
179 * Avoid this by not claiming to support CRS.
180 */
181 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
182 ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))
183 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
184
185 if (size <= 2)
186 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
187
188 return PCIBIOS_SUCCESSFUL;
189 }
190 #endif
191
192 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
193 static int xgene_get_csr_resource(struct acpi_device *adev,
194 struct resource *res)
195 {
196 struct device *dev = &adev->dev;
197 struct resource_entry *entry;
198 struct list_head list;
199 unsigned long flags;
200 int ret;
201
202 INIT_LIST_HEAD(&list);
203 flags = IORESOURCE_MEM;
204 ret = acpi_dev_get_resources(adev, &list,
205 acpi_dev_filter_resource_type_cb,
206 (void *) flags);
207 if (ret < 0) {
208 dev_err(dev, "failed to parse _CRS method, error code %d\n",
209 ret);
210 return ret;
211 }
212
213 if (ret == 0) {
214 dev_err(dev, "no IO and memory resources present in _CRS\n");
215 return -EINVAL;
216 }
217
218 entry = list_first_entry(&list, struct resource_entry, node);
219 *res = *entry->res;
220 acpi_dev_free_resource_list(&list);
221 return 0;
222 }
223
224 static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)
225 {
226 struct device *dev = cfg->parent;
227 struct acpi_device *adev = to_acpi_device(dev);
228 struct xgene_pcie_port *port;
229 struct resource csr;
230 int ret;
231
232 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
233 if (!port)
234 return -ENOMEM;
235
236 ret = xgene_get_csr_resource(adev, &csr);
237 if (ret) {
238 dev_err(dev, "can't get CSR resource\n");
239 return ret;
240 }
241 port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);
242 if (IS_ERR(port->csr_base))
243 return PTR_ERR(port->csr_base);
244
245 port->cfg_base = cfg->win;
246 port->version = ipversion;
247
248 cfg->priv = port;
249 return 0;
250 }
251
252 static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
253 {
254 return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1);
255 }
256
257 struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
258 .bus_shift = 16,
259 .init = xgene_v1_pcie_ecam_init,
260 .pci_ops = {
261 .map_bus = xgene_pcie_map_bus,
262 .read = xgene_pcie_config_read32,
263 .write = pci_generic_config_write,
264 }
265 };
266
267 static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg)
268 {
269 return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2);
270 }
271
272 struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
273 .bus_shift = 16,
274 .init = xgene_v2_pcie_ecam_init,
275 .pci_ops = {
276 .map_bus = xgene_pcie_map_bus,
277 .read = xgene_pcie_config_read32,
278 .write = pci_generic_config_write,
279 }
280 };
281 #endif
282
283 #if defined(CONFIG_PCI_XGENE)
284 static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
285 u32 flags, u64 size)
286 {
287 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
288 u32 val32 = 0;
289 u32 val;
290
291 val32 = xgene_pcie_readl(port, addr);
292 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
293 xgene_pcie_writel(port, addr, val);
294
295 val32 = xgene_pcie_readl(port, addr + 0x04);
296 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
297 xgene_pcie_writel(port, addr + 0x04, val);
298
299 val32 = xgene_pcie_readl(port, addr + 0x04);
300 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
301 xgene_pcie_writel(port, addr + 0x04, val);
302
303 val32 = xgene_pcie_readl(port, addr + 0x08);
304 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
305 xgene_pcie_writel(port, addr + 0x08, val);
306
307 return mask;
308 }
309
310 static void xgene_pcie_linkup(struct xgene_pcie_port *port,
311 u32 *lanes, u32 *speed)
312 {
313 u32 val32;
314
315 port->link_up = false;
316 val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
317 if (val32 & LINK_UP_MASK) {
318 port->link_up = true;
319 *speed = PIPE_PHY_RATE_RD(val32);
320 val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
321 *lanes = val32 >> 26;
322 }
323 }
324
325 static int xgene_pcie_init_port(struct xgene_pcie_port *port)
326 {
327 struct device *dev = port->dev;
328 int rc;
329
330 port->clk = clk_get(dev, NULL);
331 if (IS_ERR(port->clk)) {
332 dev_err(dev, "clock not available\n");
333 return -ENODEV;
334 }
335
336 rc = clk_prepare_enable(port->clk);
337 if (rc) {
338 dev_err(dev, "clock enable failed\n");
339 return rc;
340 }
341
342 return 0;
343 }
344
345 static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
346 struct platform_device *pdev)
347 {
348 struct device *dev = port->dev;
349 struct resource *res;
350
351 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
352 port->csr_base = devm_pci_remap_cfg_resource(dev, res);
353 if (IS_ERR(port->csr_base))
354 return PTR_ERR(port->csr_base);
355
356 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
357 port->cfg_base = devm_ioremap_resource(dev, res);
358 if (IS_ERR(port->cfg_base))
359 return PTR_ERR(port->cfg_base);
360 port->cfg_addr = res->start;
361
362 return 0;
363 }
364
365 static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
366 struct resource *res, u32 offset,
367 u64 cpu_addr, u64 pci_addr)
368 {
369 struct device *dev = port->dev;
370 resource_size_t size = resource_size(res);
371 u64 restype = resource_type(res);
372 u64 mask = 0;
373 u32 min_size;
374 u32 flag = EN_REG;
375
376 if (restype == IORESOURCE_MEM) {
377 min_size = SZ_128M;
378 } else {
379 min_size = 128;
380 flag |= OB_LO_IO;
381 }
382
383 if (size >= min_size)
384 mask = ~(size - 1) | flag;
385 else
386 dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
387 (u64)size, min_size);
388
389 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
390 xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
391 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
392 xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
393 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
394 xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
395 }
396
397 static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)
398 {
399 u64 addr = port->cfg_addr;
400
401 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
402 xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
403 xgene_pcie_writel(port, CFGCTL, EN_REG);
404 }
405
406 static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
407 struct list_head *res,
408 resource_size_t io_base)
409 {
410 struct resource_entry *window;
411 struct device *dev = port->dev;
412 int ret;
413
414 resource_list_for_each_entry(window, res) {
415 struct resource *res = window->res;
416 u64 restype = resource_type(res);
417
418 dev_dbg(dev, "%pR\n", res);
419
420 switch (restype) {
421 case IORESOURCE_IO:
422 xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base,
423 res->start - window->offset);
424 ret = pci_remap_iospace(res, io_base);
425 if (ret < 0)
426 return ret;
427 break;
428 case IORESOURCE_MEM:
429 if (res->flags & IORESOURCE_PREFETCH)
430 xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
431 res->start,
432 res->start -
433 window->offset);
434 else
435 xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
436 res->start,
437 res->start -
438 window->offset);
439 break;
440 case IORESOURCE_BUS:
441 break;
442 default:
443 dev_err(dev, "invalid resource %pR\n", res);
444 return -EINVAL;
445 }
446 }
447 xgene_pcie_setup_cfg_reg(port);
448 return 0;
449 }
450
451 static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg,
452 u64 pim, u64 size)
453 {
454 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
455 xgene_pcie_writel(port, pim_reg + 0x04,
456 upper_32_bits(pim) | EN_COHERENCY);
457 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
458 xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
459 }
460
461 /*
462 * X-Gene PCIe support maximum 3 inbound memory regions
463 * This function helps to select a region based on size of region
464 */
465 static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
466 {
467 if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
468 *ib_reg_mask |= (1 << 1);
469 return 1;
470 }
471
472 if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
473 *ib_reg_mask |= (1 << 0);
474 return 0;
475 }
476
477 if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
478 *ib_reg_mask |= (1 << 2);
479 return 2;
480 }
481
482 return -EINVAL;
483 }
484
485 static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
486 struct of_pci_range *range, u8 *ib_reg_mask)
487 {
488 void __iomem *cfg_base = port->cfg_base;
489 struct device *dev = port->dev;
490 void *bar_addr;
491 u32 pim_reg;
492 u64 cpu_addr = range->cpu_addr;
493 u64 pci_addr = range->pci_addr;
494 u64 size = range->size;
495 u64 mask = ~(size - 1) | EN_REG;
496 u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
497 u32 bar_low;
498 int region;
499
500 region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
501 if (region < 0) {
502 dev_warn(dev, "invalid pcie dma-range config\n");
503 return;
504 }
505
506 if (range->flags & IORESOURCE_PREFETCH)
507 flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
508
509 bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
510 switch (region) {
511 case 0:
512 xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size);
513 bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
514 writel(bar_low, bar_addr);
515 writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
516 pim_reg = PIM1_1L;
517 break;
518 case 1:
519 xgene_pcie_writel(port, IBAR2, bar_low);
520 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
521 pim_reg = PIM2_1L;
522 break;
523 case 2:
524 xgene_pcie_writel(port, IBAR3L, bar_low);
525 xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
526 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
527 xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
528 pim_reg = PIM3_1L;
529 break;
530 }
531
532 xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
533 }
534
535 static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
536 {
537 struct device_node *np = port->node;
538 struct of_pci_range range;
539 struct of_pci_range_parser parser;
540 struct device *dev = port->dev;
541 u8 ib_reg_mask = 0;
542
543 if (of_pci_dma_range_parser_init(&parser, np)) {
544 dev_err(dev, "missing dma-ranges property\n");
545 return -EINVAL;
546 }
547
548 /* Get the dma-ranges from DT */
549 for_each_of_pci_range(&parser, &range) {
550 u64 end = range.cpu_addr + range.size - 1;
551
552 dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
553 range.flags, range.cpu_addr, end, range.pci_addr);
554 xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
555 }
556 return 0;
557 }
558
559 /* clear BAR configuration which was done by firmware */
560 static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
561 {
562 int i;
563
564 for (i = PIM1_1L; i <= CFGCTL; i += 4)
565 xgene_pcie_writel(port, i, 0);
566 }
567
568 static int xgene_pcie_setup(struct xgene_pcie_port *port, struct list_head *res,
569 resource_size_t io_base)
570 {
571 struct device *dev = port->dev;
572 u32 val, lanes = 0, speed = 0;
573 int ret;
574
575 xgene_pcie_clear_config(port);
576
577 /* setup the vendor and device IDs correctly */
578 val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
579 xgene_pcie_writel(port, BRIDGE_CFG_0, val);
580
581 ret = xgene_pcie_map_ranges(port, res, io_base);
582 if (ret)
583 return ret;
584
585 ret = xgene_pcie_parse_map_dma_ranges(port);
586 if (ret)
587 return ret;
588
589 xgene_pcie_linkup(port, &lanes, &speed);
590 if (!port->link_up)
591 dev_info(dev, "(rc) link down\n");
592 else
593 dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);
594 return 0;
595 }
596
597 static struct pci_ops xgene_pcie_ops = {
598 .map_bus = xgene_pcie_map_bus,
599 .read = xgene_pcie_config_read32,
600 .write = pci_generic_config_write32,
601 };
602
603 static int xgene_pcie_probe(struct platform_device *pdev)
604 {
605 struct device *dev = &pdev->dev;
606 struct device_node *dn = dev->of_node;
607 struct xgene_pcie_port *port;
608 resource_size_t iobase = 0;
609 struct pci_bus *bus, *child;
610 struct pci_host_bridge *bridge;
611 int ret;
612 LIST_HEAD(res);
613
614 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
615 if (!bridge)
616 return -ENOMEM;
617
618 port = pci_host_bridge_priv(bridge);
619
620 port->node = of_node_get(dn);
621 port->dev = dev;
622
623 port->version = XGENE_PCIE_IP_VER_UNKN;
624 if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
625 port->version = XGENE_PCIE_IP_VER_1;
626
627 ret = xgene_pcie_map_reg(port, pdev);
628 if (ret)
629 return ret;
630
631 ret = xgene_pcie_init_port(port);
632 if (ret)
633 return ret;
634
635 ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase);
636 if (ret)
637 return ret;
638
639 ret = devm_request_pci_bus_resources(dev, &res);
640 if (ret)
641 goto error;
642
643 ret = xgene_pcie_setup(port, &res, iobase);
644 if (ret)
645 goto error;
646
647 list_splice_init(&res, &bridge->windows);
648 bridge->dev.parent = dev;
649 bridge->sysdata = port;
650 bridge->busnr = 0;
651 bridge->ops = &xgene_pcie_ops;
652 bridge->map_irq = of_irq_parse_and_map_pci;
653 bridge->swizzle_irq = pci_common_swizzle;
654
655 ret = pci_scan_root_bus_bridge(bridge);
656 if (ret < 0)
657 goto error;
658
659 bus = bridge->bus;
660
661 pci_assign_unassigned_bus_resources(bus);
662 list_for_each_entry(child, &bus->children, node)
663 pcie_bus_configure_settings(child);
664 pci_bus_add_devices(bus);
665 return 0;
666
667 error:
668 pci_free_resource_list(&res);
669 return ret;
670 }
671
672 static const struct of_device_id xgene_pcie_match_table[] = {
673 {.compatible = "apm,xgene-pcie",},
674 {},
675 };
676
677 static struct platform_driver xgene_pcie_driver = {
678 .driver = {
679 .name = "xgene-pcie",
680 .of_match_table = of_match_ptr(xgene_pcie_match_table),
681 .suppress_bind_attrs = true,
682 },
683 .probe = xgene_pcie_probe,
684 };
685 builtin_platform_driver(xgene_pcie_driver);
686 #endif
Linux with added FPC-III support