drivers/pci/host/pcie-altera.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright Altera Corporation (C) 2013-2015. All rights reserved
   4  *
   5  * Author: Ley Foon Tan <lftan@altera.com>
   6  * Description: Altera PCIe host controller driver
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/irqchip/chained_irq.h>
  12 #include <linux/init.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/of_pci.h>
  16 #include <linux/pci.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19
  20 #define RP_TX_REG0                      0x2000
  21 #define RP_TX_REG1                      0x2004
  22 #define RP_TX_CNTRL                     0x2008
  23 #define RP_TX_EOP                       0x2
  24 #define RP_TX_SOP                       0x1
  25 #define RP_RXCPL_STATUS                 0x2010
  26 #define RP_RXCPL_EOP                    0x2
  27 #define RP_RXCPL_SOP                    0x1
  28 #define RP_RXCPL_REG0                   0x2014
  29 #define RP_RXCPL_REG1                   0x2018
  30 #define P2A_INT_STATUS                  0x3060
  31 #define P2A_INT_STS_ALL                 0xf
  32 #define P2A_INT_ENABLE                  0x3070
  33 #define P2A_INT_ENA_ALL                 0xf
  34 #define RP_LTSSM                        0x3c64
  35 #define RP_LTSSM_MASK                   0x1f
  36 #define LTSSM_L0                        0xf
  37
  38 #define PCIE_CAP_OFFSET                 0x80
  39 /* TLP configuration type 0 and 1 */
  40 #define TLP_FMTTYPE_CFGRD0              0x04    /* Configuration Read Type 0 */
  41 #define TLP_FMTTYPE_CFGWR0              0x44    /* Configuration Write Type 0 */
  42 #define TLP_FMTTYPE_CFGRD1              0x05    /* Configuration Read Type 1 */
  43 #define TLP_FMTTYPE_CFGWR1              0x45    /* Configuration Write Type 1 */
  44 #define TLP_PAYLOAD_SIZE                0x01
  45 #define TLP_READ_TAG                    0x1d
  46 #define TLP_WRITE_TAG                   0x10
  47 #define RP_DEVFN                        0
  48 #define TLP_REQ_ID(bus, devfn)          (((bus) << 8) | (devfn))
  49 #define TLP_CFGRD_DW0(pcie, bus)                                        \
  50     ((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0                  \
  51                                     : TLP_FMTTYPE_CFGRD1) << 24) |      \
  52      TLP_PAYLOAD_SIZE)
  53 #define TLP_CFGWR_DW0(pcie, bus)                                        \
  54     ((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0                  \
  55                                     : TLP_FMTTYPE_CFGWR1) << 24) |      \
  56      TLP_PAYLOAD_SIZE)
  57 #define TLP_CFG_DW1(pcie, tag, be)      \
  58     (((TLP_REQ_ID(pcie->root_bus_nr,  RP_DEVFN)) << 16) | (tag << 8) | (be))
  59 #define TLP_CFG_DW2(bus, devfn, offset) \
  60                                 (((bus) << 24) | ((devfn) << 16) | (offset))
  61 #define TLP_COMP_STATUS(s)              (((s) >> 13) & 7)
  62 #define TLP_HDR_SIZE                    3
  63 #define TLP_LOOP                        500
  64
  65 #define LINK_UP_TIMEOUT                 HZ
  66 #define LINK_RETRAIN_TIMEOUT            HZ
  67
  68 #define DWORD_MASK                      3
  69
  70 struct altera_pcie {
  71         struct platform_device  *pdev;
  72         void __iomem            *cra_base;      /* DT Cra */
  73         int                     irq;
  74         u8                      root_bus_nr;
  75         struct irq_domain       *irq_domain;
  76         struct resource         bus_range;
  77         struct list_head        resources;
  78 };
  79
  80 struct tlp_rp_regpair_t {
  81         u32 ctrl;
  82         u32 reg0;
  83         u32 reg1;
  84 };
  85
  86 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
  87                               const u32 reg)
  88 {
  89         writel_relaxed(value, pcie->cra_base + reg);
  90 }
  91
  92 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
  93 {
  94         return readl_relaxed(pcie->cra_base + reg);
  95 }
  96
  97 static bool altera_pcie_link_up(struct altera_pcie *pcie)
  98 {
  99         return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
 100 }
 101
 102 /*
 103  * Altera PCIe port uses BAR0 of RC's configuration space as the translation
 104  * from PCI bus to native BUS.  Entire DDR region is mapped into PCIe space
 105  * using these registers, so it can be reached by DMA from EP devices.
 106  * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
 107  * from EP devices, eventually trigger interrupt to GIC.  The BAR0 of bridge
 108  * should be hidden during enumeration to avoid the sizing and resource
 109  * allocation by PCIe core.
 110  */
 111 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int  devfn,
 112                                     int offset)
 113 {
 114         if (pci_is_root_bus(bus) && (devfn == 0) &&
 115             (offset == PCI_BASE_ADDRESS_0))
 116                 return true;
 117
 118         return false;
 119 }
 120
 121 static void tlp_write_tx(struct altera_pcie *pcie,
 122                          struct tlp_rp_regpair_t *tlp_rp_regdata)
 123 {
 124         cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
 125         cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
 126         cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
 127 }
 128
 129 static bool altera_pcie_valid_device(struct altera_pcie *pcie,
 130                                      struct pci_bus *bus, int dev)
 131 {
 132         /* If there is no link, then there is no device */
 133         if (bus->number != pcie->root_bus_nr) {
 134                 if (!altera_pcie_link_up(pcie))
 135                         return false;
 136         }
 137
 138         /* access only one slot on each root port */
 139         if (bus->number == pcie->root_bus_nr && dev > 0)
 140                 return false;
 141
 142          return true;
 143 }
 144
 145 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
 146 {
 147         int i;
 148         bool sop = 0;
 149         u32 ctrl;
 150         u32 reg0, reg1;
 151         u32 comp_status = 1;
 152
 153         /*
 154          * Minimum 2 loops to read TLP headers and 1 loop to read data
 155          * payload.
 156          */
 157         for (i = 0; i < TLP_LOOP; i++) {
 158                 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
 159                 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
 160                         reg0 = cra_readl(pcie, RP_RXCPL_REG0);
 161                         reg1 = cra_readl(pcie, RP_RXCPL_REG1);
 162
 163                         if (ctrl & RP_RXCPL_SOP) {
 164                                 sop = true;
 165                                 comp_status = TLP_COMP_STATUS(reg1);
 166                         }
 167
 168                         if (ctrl & RP_RXCPL_EOP) {
 169                                 if (comp_status)
 170                                         return PCIBIOS_DEVICE_NOT_FOUND;
 171
 172                                 if (value)
 173                                         *value = reg0;
 174
 175                                 return PCIBIOS_SUCCESSFUL;
 176                         }
 177                 }
 178                 udelay(5);
 179         }
 180
 181         return PCIBIOS_DEVICE_NOT_FOUND;
 182 }
 183
 184 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
 185                              u32 data, bool align)
 186 {
 187         struct tlp_rp_regpair_t tlp_rp_regdata;
 188
 189         tlp_rp_regdata.reg0 = headers[0];
 190         tlp_rp_regdata.reg1 = headers[1];
 191         tlp_rp_regdata.ctrl = RP_TX_SOP;
 192         tlp_write_tx(pcie, &tlp_rp_regdata);
 193
 194         if (align) {
 195                 tlp_rp_regdata.reg0 = headers[2];
 196                 tlp_rp_regdata.reg1 = 0;
 197                 tlp_rp_regdata.ctrl = 0;
 198                 tlp_write_tx(pcie, &tlp_rp_regdata);
 199
 200                 tlp_rp_regdata.reg0 = data;
 201                 tlp_rp_regdata.reg1 = 0;
 202         } else {
 203                 tlp_rp_regdata.reg0 = headers[2];
 204                 tlp_rp_regdata.reg1 = data;
 205         }
 206
 207         tlp_rp_regdata.ctrl = RP_TX_EOP;
 208         tlp_write_tx(pcie, &tlp_rp_regdata);
 209 }
 210
 211 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
 212                               int where, u8 byte_en, u32 *value)
 213 {
 214         u32 headers[TLP_HDR_SIZE];
 215
 216         headers[0] = TLP_CFGRD_DW0(pcie, bus);
 217         headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
 218         headers[2] = TLP_CFG_DW2(bus, devfn, where);
 219
 220         tlp_write_packet(pcie, headers, 0, false);
 221
 222         return tlp_read_packet(pcie, value);
 223 }
 224
 225 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
 226                                int where, u8 byte_en, u32 value)
 227 {
 228         u32 headers[TLP_HDR_SIZE];
 229         int ret;
 230
 231         headers[0] = TLP_CFGWR_DW0(pcie, bus);
 232         headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
 233         headers[2] = TLP_CFG_DW2(bus, devfn, where);
 234
 235         /* check alignment to Qword */
 236         if ((where & 0x7) == 0)
 237                 tlp_write_packet(pcie, headers, value, true);
 238         else
 239                 tlp_write_packet(pcie, headers, value, false);
 240
 241         ret = tlp_read_packet(pcie, NULL);
 242         if (ret != PCIBIOS_SUCCESSFUL)
 243                 return ret;
 244
 245         /*
 246          * Monitor changes to PCI_PRIMARY_BUS register on root port
 247          * and update local copy of root bus number accordingly.
 248          */
 249         if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
 250                 pcie->root_bus_nr = (u8)(value);
 251
 252         return PCIBIOS_SUCCESSFUL;
 253 }
 254
 255 static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
 256                                  unsigned int devfn, int where, int size,
 257                                  u32 *value)
 258 {
 259         int ret;
 260         u32 data;
 261         u8 byte_en;
 262
 263         switch (size) {
 264         case 1:
 265                 byte_en = 1 << (where & 3);
 266                 break;
 267         case 2:
 268                 byte_en = 3 << (where & 3);
 269                 break;
 270         default:
 271                 byte_en = 0xf;
 272                 break;
 273         }
 274
 275         ret = tlp_cfg_dword_read(pcie, busno, devfn,
 276                                  (where & ~DWORD_MASK), byte_en, &data);
 277         if (ret != PCIBIOS_SUCCESSFUL)
 278                 return ret;
 279
 280         switch (size) {
 281         case 1:
 282                 *value = (data >> (8 * (where & 0x3))) & 0xff;
 283                 break;
 284         case 2:
 285                 *value = (data >> (8 * (where & 0x2))) & 0xffff;
 286                 break;
 287         default:
 288                 *value = data;
 289                 break;
 290         }
 291
 292         return PCIBIOS_SUCCESSFUL;
 293 }
 294
 295 static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
 296                                   unsigned int devfn, int where, int size,
 297                                   u32 value)
 298 {
 299         u32 data32;
 300         u32 shift = 8 * (where & 3);
 301         u8 byte_en;
 302
 303         switch (size) {
 304         case 1:
 305                 data32 = (value & 0xff) << shift;
 306                 byte_en = 1 << (where & 3);
 307                 break;
 308         case 2:
 309                 data32 = (value & 0xffff) << shift;
 310                 byte_en = 3 << (where & 3);
 311                 break;
 312         default:
 313                 data32 = value;
 314                 byte_en = 0xf;
 315                 break;
 316         }
 317
 318         return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
 319                                    byte_en, data32);
 320 }
 321
 322 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
 323                                 int where, int size, u32 *value)
 324 {
 325         struct altera_pcie *pcie = bus->sysdata;
 326
 327         if (altera_pcie_hide_rc_bar(bus, devfn, where))
 328                 return PCIBIOS_BAD_REGISTER_NUMBER;
 329
 330         if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn))) {
 331                 *value = 0xffffffff;
 332                 return PCIBIOS_DEVICE_NOT_FOUND;
 333         }
 334
 335         return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
 336                                      value);
 337 }
 338
 339 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
 340                                  int where, int size, u32 value)
 341 {
 342         struct altera_pcie *pcie = bus->sysdata;
 343
 344         if (altera_pcie_hide_rc_bar(bus, devfn, where))
 345                 return PCIBIOS_BAD_REGISTER_NUMBER;
 346
 347         if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
 348                 return PCIBIOS_DEVICE_NOT_FOUND;
 349
 350         return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
 351                                      value);
 352 }
 353
 354 static struct pci_ops altera_pcie_ops = {
 355         .read = altera_pcie_cfg_read,
 356         .write = altera_pcie_cfg_write,
 357 };
 358
 359 static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
 360                                 unsigned int devfn, int offset, u16 *value)
 361 {
 362         u32 data;
 363         int ret;
 364
 365         ret = _altera_pcie_cfg_read(pcie, busno, devfn,
 366                                     PCIE_CAP_OFFSET + offset, sizeof(*value),
 367                                     &data);
 368         *value = data;
 369         return ret;
 370 }
 371
 372 static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
 373                                  unsigned int devfn, int offset, u16 value)
 374 {
 375         return _altera_pcie_cfg_write(pcie, busno, devfn,
 376                                       PCIE_CAP_OFFSET + offset, sizeof(value),
 377                                       value);
 378 }
 379
 380 static void altera_wait_link_retrain(struct altera_pcie *pcie)
 381 {
 382         struct device *dev = &pcie->pdev->dev;
 383         u16 reg16;
 384         unsigned long start_jiffies;
 385
 386         /* Wait for link training end. */
 387         start_jiffies = jiffies;
 388         for (;;) {
 389                 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
 390                                      PCI_EXP_LNKSTA, &reg16);
 391                 if (!(reg16 & PCI_EXP_LNKSTA_LT))
 392                         break;
 393
 394                 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
 395                         dev_err(dev, "link retrain timeout\n");
 396                         break;
 397                 }
 398                 udelay(100);
 399         }
 400
 401         /* Wait for link is up */
 402         start_jiffies = jiffies;
 403         for (;;) {
 404                 if (altera_pcie_link_up(pcie))
 405                         break;
 406
 407                 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
 408                         dev_err(dev, "link up timeout\n");
 409                         break;
 410                 }
 411                 udelay(100);
 412         }
 413 }
 414
 415 static void altera_pcie_retrain(struct altera_pcie *pcie)
 416 {
 417         u16 linkcap, linkstat, linkctl;
 418
 419         if (!altera_pcie_link_up(pcie))
 420                 return;
 421
 422         /*
 423          * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
 424          * current speed is 2.5 GB/s.
 425          */
 426         altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
 427                              &linkcap);
 428         if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
 429                 return;
 430
 431         altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
 432                              &linkstat);
 433         if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
 434                 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
 435                                      PCI_EXP_LNKCTL, &linkctl);
 436                 linkctl |= PCI_EXP_LNKCTL_RL;
 437                 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
 438                                       PCI_EXP_LNKCTL, linkctl);
 439
 440                 altera_wait_link_retrain(pcie);
 441         }
 442 }
 443
 444 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 445                                 irq_hw_number_t hwirq)
 446 {
 447         irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
 448         irq_set_chip_data(irq, domain->host_data);
 449         return 0;
 450 }
 451
 452 static const struct irq_domain_ops intx_domain_ops = {
 453         .map = altera_pcie_intx_map,
 454         .xlate = pci_irqd_intx_xlate,
 455 };
 456
 457 static void altera_pcie_isr(struct irq_desc *desc)
 458 {
 459         struct irq_chip *chip = irq_desc_get_chip(desc);
 460         struct altera_pcie *pcie;
 461         struct device *dev;
 462         unsigned long status;
 463         u32 bit;
 464         u32 virq;
 465
 466         chained_irq_enter(chip, desc);
 467         pcie = irq_desc_get_handler_data(desc);
 468         dev = &pcie->pdev->dev;
 469
 470         while ((status = cra_readl(pcie, P2A_INT_STATUS)
 471                 & P2A_INT_STS_ALL) != 0) {
 472                 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
 473                         /* clear interrupts */
 474                         cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
 475
 476                         virq = irq_find_mapping(pcie->irq_domain, bit);
 477                         if (virq)
 478                                 generic_handle_irq(virq);
 479                         else
 480                                 dev_err(dev, "unexpected IRQ, INT%d\n", bit);
 481                 }
 482         }
 483
 484         chained_irq_exit(chip, desc);
 485 }
 486
 487 static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
 488 {
 489         int err, res_valid = 0;
 490         struct device *dev = &pcie->pdev->dev;
 491         struct device_node *np = dev->of_node;
 492         struct resource_entry *win;
 493
 494         err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
 495                                                NULL);
 496         if (err)
 497                 return err;
 498
 499         err = devm_request_pci_bus_resources(dev, &pcie->resources);
 500         if (err)
 501                 goto out_release_res;
 502
 503         resource_list_for_each_entry(win, &pcie->resources) {
 504                 struct resource *res = win->res;
 505
 506                 if (resource_type(res) == IORESOURCE_MEM)
 507                         res_valid |= !(res->flags & IORESOURCE_PREFETCH);
 508         }
 509
 510         if (res_valid)
 511                 return 0;
 512
 513         dev_err(dev, "non-prefetchable memory resource required\n");
 514         err = -EINVAL;
 515
 516 out_release_res:
 517         pci_free_resource_list(&pcie->resources);
 518         return err;
 519 }
 520
 521 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
 522 {
 523         struct device *dev = &pcie->pdev->dev;
 524         struct device_node *node = dev->of_node;
 525
 526         /* Setup INTx */
 527         pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
 528                                         &intx_domain_ops, pcie);
 529         if (!pcie->irq_domain) {
 530                 dev_err(dev, "Failed to get a INTx IRQ domain\n");
 531                 return -ENOMEM;
 532         }
 533
 534         return 0;
 535 }
 536
 537 static int altera_pcie_parse_dt(struct altera_pcie *pcie)
 538 {
 539         struct device *dev = &pcie->pdev->dev;
 540         struct platform_device *pdev = pcie->pdev;
 541         struct resource *cra;
 542
 543         cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
 544         pcie->cra_base = devm_ioremap_resource(dev, cra);
 545         if (IS_ERR(pcie->cra_base))
 546                 return PTR_ERR(pcie->cra_base);
 547
 548         /* setup IRQ */
 549         pcie->irq = platform_get_irq(pdev, 0);
 550         if (pcie->irq < 0) {
 551                 dev_err(dev, "failed to get IRQ: %d\n", pcie->irq);
 552                 return pcie->irq;
 553         }
 554
 555         irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
 556         return 0;
 557 }
 558
 559 static void altera_pcie_host_init(struct altera_pcie *pcie)
 560 {
 561         altera_pcie_retrain(pcie);
 562 }
 563
 564 static int altera_pcie_probe(struct platform_device *pdev)
 565 {
 566         struct device *dev = &pdev->dev;
 567         struct altera_pcie *pcie;
 568         struct pci_bus *bus;
 569         struct pci_bus *child;
 570         struct pci_host_bridge *bridge;
 571         int ret;
 572
 573         bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
 574         if (!bridge)
 575                 return -ENOMEM;
 576
 577         pcie = pci_host_bridge_priv(bridge);
 578         pcie->pdev = pdev;
 579
 580         ret = altera_pcie_parse_dt(pcie);
 581         if (ret) {
 582                 dev_err(dev, "Parsing DT failed\n");
 583                 return ret;
 584         }
 585
 586         INIT_LIST_HEAD(&pcie->resources);
 587
 588         ret = altera_pcie_parse_request_of_pci_ranges(pcie);
 589         if (ret) {
 590                 dev_err(dev, "Failed add resources\n");
 591                 return ret;
 592         }
 593
 594         ret = altera_pcie_init_irq_domain(pcie);
 595         if (ret) {
 596                 dev_err(dev, "Failed creating IRQ Domain\n");
 597                 return ret;
 598         }
 599
 600         /* clear all interrupts */
 601         cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
 602         /* enable all interrupts */
 603         cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
 604         altera_pcie_host_init(pcie);
 605
 606         list_splice_init(&pcie->resources, &bridge->windows);
 607         bridge->dev.parent = dev;
 608         bridge->sysdata = pcie;
 609         bridge->busnr = pcie->root_bus_nr;
 610         bridge->ops = &altera_pcie_ops;
 611         bridge->map_irq = of_irq_parse_and_map_pci;
 612         bridge->swizzle_irq = pci_common_swizzle;
 613
 614         ret = pci_scan_root_bus_bridge(bridge);
 615         if (ret < 0)
 616                 return ret;
 617
 618         bus = bridge->bus;
 619
 620         pci_assign_unassigned_bus_resources(bus);
 621
 622         /* Configure PCI Express setting. */
 623         list_for_each_entry(child, &bus->children, node)
 624                 pcie_bus_configure_settings(child);
 625
 626         pci_bus_add_devices(bus);
 627         return ret;
 628 }
 629
 630 static const struct of_device_id altera_pcie_of_match[] = {
 631         { .compatible = "altr,pcie-root-port-1.0", },
 632         {},
 633 };
 634
 635 static struct platform_driver altera_pcie_driver = {
 636         .probe          = altera_pcie_probe,
 637         .driver = {
 638                 .name   = "altera-pcie",
 639                 .of_match_table = altera_pcie_of_match,
 640                 .suppress_bind_attrs = true,
 641         },
 642 };
 643
 644 builtin_platform_driver(altera_pcie_driver);