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Linux 4.16.11
[linux/fpc-iii.git] / drivers / pci / host / pcie-mediatek.c
bloba8b20c5012a98605f33b2a201b201394a5c616ee
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek PCIe host controller driver.
4 *
5 * Copyright (c) 2017 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 * Honghui Zhang <honghui.zhang@mediatek.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/kernel.h>
16 #include <linux/of_address.h>
17 #include <linux/of_pci.h>
18 #include <linux/of_platform.h>
19 #include <linux/pci.h>
20 #include <linux/phy/phy.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/reset.h>
24
25 /* PCIe shared registers */
26 #define PCIE_SYS_CFG 0x00
27 #define PCIE_INT_ENABLE 0x0c
28 #define PCIE_CFG_ADDR 0x20
29 #define PCIE_CFG_DATA 0x24
30
31 /* PCIe per port registers */
32 #define PCIE_BAR0_SETUP 0x10
33 #define PCIE_CLASS 0x34
34 #define PCIE_LINK_STATUS 0x50
35
36 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
37 #define PCIE_PORT_PERST(x) BIT(1 + (x))
38 #define PCIE_PORT_LINKUP BIT(0)
39 #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
40
41 #define PCIE_BAR_ENABLE BIT(0)
42 #define PCIE_REVISION_ID BIT(0)
43 #define PCIE_CLASS_CODE (0x60400 << 8)
44 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
45 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
46 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
47 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
48 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
49 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \
50 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
51 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
52
53 /* MediaTek specific configuration registers */
54 #define PCIE_FTS_NUM 0x70c
55 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
56 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
57
58 #define PCIE_FC_CREDIT 0x73c
59 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
60 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
61
62 /* PCIe V2 share registers */
63 #define PCIE_SYS_CFG_V2 0x0
64 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
65 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
66
67 /* PCIe V2 per-port registers */
68 #define PCIE_MSI_VECTOR 0x0c0
69 #define PCIE_INT_MASK 0x420
70 #define INTX_MASK GENMASK(19, 16)
71 #define INTX_SHIFT 16
72 #define PCIE_INT_STATUS 0x424
73 #define MSI_STATUS BIT(23)
74 #define PCIE_IMSI_STATUS 0x42c
75 #define PCIE_IMSI_ADDR 0x430
76 #define MSI_MASK BIT(23)
77 #define MTK_MSI_IRQS_NUM 32
78
79 #define PCIE_AHB_TRANS_BASE0_L 0x438
80 #define PCIE_AHB_TRANS_BASE0_H 0x43c
81 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
82 #define PCIE_AXI_WINDOW0 0x448
83 #define WIN_ENABLE BIT(7)
84
85 /* PCIe V2 configuration transaction header */
86 #define PCIE_CFG_HEADER0 0x460
87 #define PCIE_CFG_HEADER1 0x464
88 #define PCIE_CFG_HEADER2 0x468
89 #define PCIE_CFG_WDATA 0x470
90 #define PCIE_APP_TLP_REQ 0x488
91 #define PCIE_CFG_RDATA 0x48c
92 #define APP_CFG_REQ BIT(0)
93 #define APP_CPL_STATUS GENMASK(7, 5)
94
95 #define CFG_WRRD_TYPE_0 4
96 #define CFG_WR_FMT 2
97 #define CFG_RD_FMT 0
98
99 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
100 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
101 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
102 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
103 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
104 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
105 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
106 #define CFG_HEADER_DW0(type, fmt) \
107 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
108 #define CFG_HEADER_DW1(where, size) \
109 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
110 #define CFG_HEADER_DW2(regn, fun, dev, bus) \
111 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
112 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
113
114 #define PCIE_RST_CTRL 0x510
115 #define PCIE_PHY_RSTB BIT(0)
116 #define PCIE_PIPE_SRSTB BIT(1)
117 #define PCIE_MAC_SRSTB BIT(2)
118 #define PCIE_CRSTB BIT(3)
119 #define PCIE_PERSTB BIT(8)
120 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
121 #define PCIE_LINK_STATUS_V2 0x804
122 #define PCIE_PORT_LINKUP_V2 BIT(10)
123
124 struct mtk_pcie_port;
125
126 /**
127 * struct mtk_pcie_soc - differentiate between host generations
128 * @has_msi: whether this host supports MSI interrupts or not
129 * @ops: pointer to configuration access functions
130 * @startup: pointer to controller setting functions
131 * @setup_irq: pointer to initialize IRQ functions
132 */
133 struct mtk_pcie_soc {
134 bool has_msi;
135 struct pci_ops *ops;
136 int (*startup)(struct mtk_pcie_port *port);
137 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
138 };
139
140 /**
141 * struct mtk_pcie_port - PCIe port information
142 * @base: IO mapped register base
143 * @list: port list
144 * @pcie: pointer to PCIe host info
145 * @reset: pointer to port reset control
146 * @sys_ck: pointer to transaction/data link layer clock
147 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
148 * and RC initiated MMIO access
149 * @axi_ck: pointer to application layer MMIO channel operating clock
150 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
151 * when pcie_mac_ck/pcie_pipe_ck is turned off
152 * @obff_ck: pointer to OBFF functional block operating clock
153 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
154 * @phy: pointer to PHY control block
155 * @lane: lane count
156 * @slot: port slot
157 * @irq_domain: legacy INTx IRQ domain
158 * @msi_domain: MSI IRQ domain
159 * @msi_irq_in_use: bit map for assigned MSI IRQ
160 */
161 struct mtk_pcie_port {
162 void __iomem *base;
163 struct list_head list;
164 struct mtk_pcie *pcie;
165 struct reset_control *reset;
166 struct clk *sys_ck;
167 struct clk *ahb_ck;
168 struct clk *axi_ck;
169 struct clk *aux_ck;
170 struct clk *obff_ck;
171 struct clk *pipe_ck;
172 struct phy *phy;
173 u32 lane;
174 u32 slot;
175 struct irq_domain *irq_domain;
176 struct irq_domain *msi_domain;
177 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
178 };
179
180 /**
181 * struct mtk_pcie - PCIe host information
182 * @dev: pointer to PCIe device
183 * @base: IO mapped register base
184 * @free_ck: free-run reference clock
185 * @io: IO resource
186 * @pio: PIO resource
187 * @mem: non-prefetchable memory resource
188 * @busn: bus range
189 * @offset: IO / Memory offset
190 * @ports: pointer to PCIe port information
191 * @soc: pointer to SoC-dependent operations
192 */
193 struct mtk_pcie {
194 struct device *dev;
195 void __iomem *base;
196 struct clk *free_ck;
197
198 struct resource io;
199 struct resource pio;
200 struct resource mem;
201 struct resource busn;
202 struct {
203 resource_size_t mem;
204 resource_size_t io;
205 } offset;
206 struct list_head ports;
207 const struct mtk_pcie_soc *soc;
208 };
209
210 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
211 {
212 struct device *dev = pcie->dev;
213
214 clk_disable_unprepare(pcie->free_ck);
215
216 if (dev->pm_domain) {
217 pm_runtime_put_sync(dev);
218 pm_runtime_disable(dev);
219 }
220 }
221
222 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
223 {
224 struct mtk_pcie *pcie = port->pcie;
225 struct device *dev = pcie->dev;
226
227 devm_iounmap(dev, port->base);
228 list_del(&port->list);
229 devm_kfree(dev, port);
230 }
231
232 static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
233 {
234 struct mtk_pcie_port *port, *tmp;
235
236 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
237 phy_power_off(port->phy);
238 phy_exit(port->phy);
239 clk_disable_unprepare(port->pipe_ck);
240 clk_disable_unprepare(port->obff_ck);
241 clk_disable_unprepare(port->axi_ck);
242 clk_disable_unprepare(port->aux_ck);
243 clk_disable_unprepare(port->ahb_ck);
244 clk_disable_unprepare(port->sys_ck);
245 mtk_pcie_port_free(port);
246 }
247
248 mtk_pcie_subsys_powerdown(pcie);
249 }
250
251 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
252 {
253 u32 val;
254 int err;
255
256 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
257 !(val & APP_CFG_REQ), 10,
258 100 * USEC_PER_MSEC);
259 if (err)
260 return PCIBIOS_SET_FAILED;
261
262 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
263 return PCIBIOS_SET_FAILED;
264
265 return PCIBIOS_SUCCESSFUL;
266 }
267
268 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
269 int where, int size, u32 *val)
270 {
271 u32 tmp;
272
273 /* Write PCIe configuration transaction header for Cfgrd */
274 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
275 port->base + PCIE_CFG_HEADER0);
276 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
277 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
278 port->base + PCIE_CFG_HEADER2);
279
280 /* Trigger h/w to transmit Cfgrd TLP */
281 tmp = readl(port->base + PCIE_APP_TLP_REQ);
282 tmp |= APP_CFG_REQ;
283 writel(tmp, port->base + PCIE_APP_TLP_REQ);
284
285 /* Check completion status */
286 if (mtk_pcie_check_cfg_cpld(port))
287 return PCIBIOS_SET_FAILED;
288
289 /* Read cpld payload of Cfgrd */
290 *val = readl(port->base + PCIE_CFG_RDATA);
291
292 if (size == 1)
293 *val = (*val >> (8 * (where & 3))) & 0xff;
294 else if (size == 2)
295 *val = (*val >> (8 * (where & 3))) & 0xffff;
296
297 return PCIBIOS_SUCCESSFUL;
298 }
299
300 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
301 int where, int size, u32 val)
302 {
303 /* Write PCIe configuration transaction header for Cfgwr */
304 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
305 port->base + PCIE_CFG_HEADER0);
306 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
307 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
308 port->base + PCIE_CFG_HEADER2);
309
310 /* Write Cfgwr data */
311 val = val << 8 * (where & 3);
312 writel(val, port->base + PCIE_CFG_WDATA);
313
314 /* Trigger h/w to transmit Cfgwr TLP */
315 val = readl(port->base + PCIE_APP_TLP_REQ);
316 val |= APP_CFG_REQ;
317 writel(val, port->base + PCIE_APP_TLP_REQ);
318
319 /* Check completion status */
320 return mtk_pcie_check_cfg_cpld(port);
321 }
322
323 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
324 unsigned int devfn)
325 {
326 struct mtk_pcie *pcie = bus->sysdata;
327 struct mtk_pcie_port *port;
328
329 list_for_each_entry(port, &pcie->ports, list)
330 if (port->slot == PCI_SLOT(devfn))
331 return port;
332
333 return NULL;
334 }
335
336 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
337 int where, int size, u32 *val)
338 {
339 struct mtk_pcie_port *port;
340 u32 bn = bus->number;
341 int ret;
342
343 port = mtk_pcie_find_port(bus, devfn);
344 if (!port) {
345 *val = ~0;
346 return PCIBIOS_DEVICE_NOT_FOUND;
347 }
348
349 ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
350 if (ret)
351 *val = ~0;
352
353 return ret;
354 }
355
356 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
357 int where, int size, u32 val)
358 {
359 struct mtk_pcie_port *port;
360 u32 bn = bus->number;
361
362 port = mtk_pcie_find_port(bus, devfn);
363 if (!port)
364 return PCIBIOS_DEVICE_NOT_FOUND;
365
366 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
367 }
368
369 static struct pci_ops mtk_pcie_ops_v2 = {
370 .read = mtk_pcie_config_read,
371 .write = mtk_pcie_config_write,
372 };
373
374 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
375 {
376 struct mtk_pcie *pcie = port->pcie;
377 struct resource *mem = &pcie->mem;
378 u32 val;
379 size_t size;
380 int err;
381
382 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
383 if (pcie->base) {
384 val = readl(pcie->base + PCIE_SYS_CFG_V2);
385 val |= PCIE_CSR_LTSSM_EN(port->slot) |
386 PCIE_CSR_ASPM_L1_EN(port->slot);
387 writel(val, pcie->base + PCIE_SYS_CFG_V2);
388 }
389
390 /* Assert all reset signals */
391 writel(0, port->base + PCIE_RST_CTRL);
392
393 /*
394 * Enable PCIe link down reset, if link status changed from link up to
395 * link down, this will reset MAC control registers and configuration
396 * space.
397 */
398 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
399
400 /* De-assert PHY, PE, PIPE, MAC and configuration reset */
401 val = readl(port->base + PCIE_RST_CTRL);
402 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
403 PCIE_MAC_SRSTB | PCIE_CRSTB;
404 writel(val, port->base + PCIE_RST_CTRL);
405
406 /* 100ms timeout value should be enough for Gen1/2 training */
407 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
408 !!(val & PCIE_PORT_LINKUP_V2), 20,
409 100 * USEC_PER_MSEC);
410 if (err)
411 return -ETIMEDOUT;
412
413 /* Set INTx mask */
414 val = readl(port->base + PCIE_INT_MASK);
415 val &= ~INTX_MASK;
416 writel(val, port->base + PCIE_INT_MASK);
417
418 /* Set AHB to PCIe translation windows */
419 size = mem->end - mem->start;
420 val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
421 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
422
423 val = upper_32_bits(mem->start);
424 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
425
426 /* Set PCIe to AXI translation memory space.*/
427 val = fls(0xffffffff) | WIN_ENABLE;
428 writel(val, port->base + PCIE_AXI_WINDOW0);
429
430 return 0;
431 }
432
433 static int mtk_pcie_msi_alloc(struct mtk_pcie_port *port)
434 {
435 int msi;
436
437 msi = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
438 if (msi < MTK_MSI_IRQS_NUM)
439 set_bit(msi, port->msi_irq_in_use);
440 else
441 return -ENOSPC;
442
443 return msi;
444 }
445
446 static void mtk_pcie_msi_free(struct mtk_pcie_port *port, unsigned long hwirq)
447 {
448 clear_bit(hwirq, port->msi_irq_in_use);
449 }
450
451 static int mtk_pcie_msi_setup_irq(struct msi_controller *chip,
452 struct pci_dev *pdev, struct msi_desc *desc)
453 {
454 struct mtk_pcie_port *port;
455 struct msi_msg msg;
456 unsigned int irq;
457 int hwirq;
458 phys_addr_t msg_addr;
459
460 port = mtk_pcie_find_port(pdev->bus, pdev->devfn);
461 if (!port)
462 return -EINVAL;
463
464 hwirq = mtk_pcie_msi_alloc(port);
465 if (hwirq < 0)
466 return hwirq;
467
468 irq = irq_create_mapping(port->msi_domain, hwirq);
469 if (!irq) {
470 mtk_pcie_msi_free(port, hwirq);
471 return -EINVAL;
472 }
473
474 chip->dev = &pdev->dev;
475
476 irq_set_msi_desc(irq, desc);
477
478 /* MT2712/MT7622 only support 32-bit MSI addresses */
479 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
480 msg.address_hi = 0;
481 msg.address_lo = lower_32_bits(msg_addr);
482 msg.data = hwirq;
483
484 pci_write_msi_msg(irq, &msg);
485
486 return 0;
487 }
488
489 static void mtk_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
490 {
491 struct pci_dev *pdev = to_pci_dev(chip->dev);
492 struct irq_data *d = irq_get_irq_data(irq);
493 irq_hw_number_t hwirq = irqd_to_hwirq(d);
494 struct mtk_pcie_port *port;
495
496 port = mtk_pcie_find_port(pdev->bus, pdev->devfn);
497 if (!port)
498 return;
499
500 irq_dispose_mapping(irq);
501 mtk_pcie_msi_free(port, hwirq);
502 }
503
504 static struct msi_controller mtk_pcie_msi_chip = {
505 .setup_irq = mtk_pcie_msi_setup_irq,
506 .teardown_irq = mtk_msi_teardown_irq,
507 };
508
509 static struct irq_chip mtk_msi_irq_chip = {
510 .name = "MTK PCIe MSI",
511 .irq_enable = pci_msi_unmask_irq,
512 .irq_disable = pci_msi_mask_irq,
513 .irq_mask = pci_msi_mask_irq,
514 .irq_unmask = pci_msi_unmask_irq,
515 };
516
517 static int mtk_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
518 irq_hw_number_t hwirq)
519 {
520 irq_set_chip_and_handler(irq, &mtk_msi_irq_chip, handle_simple_irq);
521 irq_set_chip_data(irq, domain->host_data);
522
523 return 0;
524 }
525
526 static const struct irq_domain_ops msi_domain_ops = {
527 .map = mtk_pcie_msi_map,
528 };
529
530 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
531 {
532 u32 val;
533 phys_addr_t msg_addr;
534
535 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
536 val = lower_32_bits(msg_addr);
537 writel(val, port->base + PCIE_IMSI_ADDR);
538
539 val = readl(port->base + PCIE_INT_MASK);
540 val &= ~MSI_MASK;
541 writel(val, port->base + PCIE_INT_MASK);
542 }
543
544 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
545 irq_hw_number_t hwirq)
546 {
547 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
548 irq_set_chip_data(irq, domain->host_data);
549
550 return 0;
551 }
552
553 static const struct irq_domain_ops intx_domain_ops = {
554 .map = mtk_pcie_intx_map,
555 };
556
557 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
558 struct device_node *node)
559 {
560 struct device *dev = port->pcie->dev;
561 struct device_node *pcie_intc_node;
562
563 /* Setup INTx */
564 pcie_intc_node = of_get_next_child(node, NULL);
565 if (!pcie_intc_node) {
566 dev_err(dev, "no PCIe Intc node found\n");
567 return -ENODEV;
568 }
569
570 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
571 &intx_domain_ops, port);
572 if (!port->irq_domain) {
573 dev_err(dev, "failed to get INTx IRQ domain\n");
574 return -ENODEV;
575 }
576
577 if (IS_ENABLED(CONFIG_PCI_MSI)) {
578 port->msi_domain = irq_domain_add_linear(node, MTK_MSI_IRQS_NUM,
579 &msi_domain_ops,
580 &mtk_pcie_msi_chip);
581 if (!port->msi_domain) {
582 dev_err(dev, "failed to create MSI IRQ domain\n");
583 return -ENODEV;
584 }
585 mtk_pcie_enable_msi(port);
586 }
587
588 return 0;
589 }
590
591 static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
592 {
593 struct mtk_pcie_port *port = (struct mtk_pcie_port *)data;
594 unsigned long status;
595 u32 virq;
596 u32 bit = INTX_SHIFT;
597
598 while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) {
599 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
600 /* Clear the INTx */
601 writel(1 << bit, port->base + PCIE_INT_STATUS);
602 virq = irq_find_mapping(port->irq_domain,
603 bit - INTX_SHIFT);
604 generic_handle_irq(virq);
605 }
606 }
607
608 if (IS_ENABLED(CONFIG_PCI_MSI)) {
609 while ((status = readl(port->base + PCIE_INT_STATUS)) & MSI_STATUS) {
610 unsigned long imsi_status;
611
612 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
613 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
614 /* Clear the MSI */
615 writel(1 << bit, port->base + PCIE_IMSI_STATUS);
616 virq = irq_find_mapping(port->msi_domain, bit);
617 generic_handle_irq(virq);
618 }
619 }
620 /* Clear MSI interrupt status */
621 writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
622 }
623 }
624
625 return IRQ_HANDLED;
626 }
627
628 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
629 struct device_node *node)
630 {
631 struct mtk_pcie *pcie = port->pcie;
632 struct device *dev = pcie->dev;
633 struct platform_device *pdev = to_platform_device(dev);
634 int err, irq;
635
636 irq = platform_get_irq(pdev, port->slot);
637 err = devm_request_irq(dev, irq, mtk_pcie_intr_handler,
638 IRQF_SHARED, "mtk-pcie", port);
639 if (err) {
640 dev_err(dev, "unable to request IRQ %d\n", irq);
641 return err;
642 }
643
644 err = mtk_pcie_init_irq_domain(port, node);
645 if (err) {
646 dev_err(dev, "failed to init PCIe IRQ domain\n");
647 return err;
648 }
649
650 return 0;
651 }
652
653 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
654 unsigned int devfn, int where)
655 {
656 struct mtk_pcie *pcie = bus->sysdata;
657
658 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
659 bus->number), pcie->base + PCIE_CFG_ADDR);
660
661 return pcie->base + PCIE_CFG_DATA + (where & 3);
662 }
663
664 static struct pci_ops mtk_pcie_ops = {
665 .map_bus = mtk_pcie_map_bus,
666 .read = pci_generic_config_read,
667 .write = pci_generic_config_write,
668 };
669
670 static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
671 {
672 struct mtk_pcie *pcie = port->pcie;
673 u32 func = PCI_FUNC(port->slot << 3);
674 u32 slot = PCI_SLOT(port->slot << 3);
675 u32 val;
676 int err;
677
678 /* assert port PERST_N */
679 val = readl(pcie->base + PCIE_SYS_CFG);
680 val |= PCIE_PORT_PERST(port->slot);
681 writel(val, pcie->base + PCIE_SYS_CFG);
682
683 /* de-assert port PERST_N */
684 val = readl(pcie->base + PCIE_SYS_CFG);
685 val &= ~PCIE_PORT_PERST(port->slot);
686 writel(val, pcie->base + PCIE_SYS_CFG);
687
688 /* 100ms timeout value should be enough for Gen1/2 training */
689 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
690 !!(val & PCIE_PORT_LINKUP), 20,
691 100 * USEC_PER_MSEC);
692 if (err)
693 return -ETIMEDOUT;
694
695 /* enable interrupt */
696 val = readl(pcie->base + PCIE_INT_ENABLE);
697 val |= PCIE_PORT_INT_EN(port->slot);
698 writel(val, pcie->base + PCIE_INT_ENABLE);
699
700 /* map to all DDR region. We need to set it before cfg operation. */
701 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
702 port->base + PCIE_BAR0_SETUP);
703
704 /* configure class code and revision ID */
705 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
706
707 /* configure FC credit */
708 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
709 pcie->base + PCIE_CFG_ADDR);
710 val = readl(pcie->base + PCIE_CFG_DATA);
711 val &= ~PCIE_FC_CREDIT_MASK;
712 val |= PCIE_FC_CREDIT_VAL(0x806c);
713 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
714 pcie->base + PCIE_CFG_ADDR);
715 writel(val, pcie->base + PCIE_CFG_DATA);
716
717 /* configure RC FTS number to 250 when it leaves L0s */
718 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
719 pcie->base + PCIE_CFG_ADDR);
720 val = readl(pcie->base + PCIE_CFG_DATA);
721 val &= ~PCIE_FTS_NUM_MASK;
722 val |= PCIE_FTS_NUM_L0(0x50);
723 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
724 pcie->base + PCIE_CFG_ADDR);
725 writel(val, pcie->base + PCIE_CFG_DATA);
726
727 return 0;
728 }
729
730 static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
731 {
732 struct mtk_pcie *pcie = port->pcie;
733 struct device *dev = pcie->dev;
734 int err;
735
736 err = clk_prepare_enable(port->sys_ck);
737 if (err) {
738 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
739 goto err_sys_clk;
740 }
741
742 err = clk_prepare_enable(port->ahb_ck);
743 if (err) {
744 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
745 goto err_ahb_clk;
746 }
747
748 err = clk_prepare_enable(port->aux_ck);
749 if (err) {
750 dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
751 goto err_aux_clk;
752 }
753
754 err = clk_prepare_enable(port->axi_ck);
755 if (err) {
756 dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
757 goto err_axi_clk;
758 }
759
760 err = clk_prepare_enable(port->obff_ck);
761 if (err) {
762 dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
763 goto err_obff_clk;
764 }
765
766 err = clk_prepare_enable(port->pipe_ck);
767 if (err) {
768 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
769 goto err_pipe_clk;
770 }
771
772 reset_control_assert(port->reset);
773 reset_control_deassert(port->reset);
774
775 err = phy_init(port->phy);
776 if (err) {
777 dev_err(dev, "failed to initialize port%d phy\n", port->slot);
778 goto err_phy_init;
779 }
780
781 err = phy_power_on(port->phy);
782 if (err) {
783 dev_err(dev, "failed to power on port%d phy\n", port->slot);
784 goto err_phy_on;
785 }
786
787 if (!pcie->soc->startup(port))
788 return;
789
790 dev_info(dev, "Port%d link down\n", port->slot);
791
792 phy_power_off(port->phy);
793 err_phy_on:
794 phy_exit(port->phy);
795 err_phy_init:
796 clk_disable_unprepare(port->pipe_ck);
797 err_pipe_clk:
798 clk_disable_unprepare(port->obff_ck);
799 err_obff_clk:
800 clk_disable_unprepare(port->axi_ck);
801 err_axi_clk:
802 clk_disable_unprepare(port->aux_ck);
803 err_aux_clk:
804 clk_disable_unprepare(port->ahb_ck);
805 err_ahb_clk:
806 clk_disable_unprepare(port->sys_ck);
807 err_sys_clk:
808 mtk_pcie_port_free(port);
809 }
810
811 static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
812 struct device_node *node,
813 int slot)
814 {
815 struct mtk_pcie_port *port;
816 struct resource *regs;
817 struct device *dev = pcie->dev;
818 struct platform_device *pdev = to_platform_device(dev);
819 char name[10];
820 int err;
821
822 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
823 if (!port)
824 return -ENOMEM;
825
826 err = of_property_read_u32(node, "num-lanes", &port->lane);
827 if (err) {
828 dev_err(dev, "missing num-lanes property\n");
829 return err;
830 }
831
832 snprintf(name, sizeof(name), "port%d", slot);
833 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
834 port->base = devm_ioremap_resource(dev, regs);
835 if (IS_ERR(port->base)) {
836 dev_err(dev, "failed to map port%d base\n", slot);
837 return PTR_ERR(port->base);
838 }
839
840 snprintf(name, sizeof(name), "sys_ck%d", slot);
841 port->sys_ck = devm_clk_get(dev, name);
842 if (IS_ERR(port->sys_ck)) {
843 dev_err(dev, "failed to get sys_ck%d clock\n", slot);
844 return PTR_ERR(port->sys_ck);
845 }
846
847 /* sys_ck might be divided into the following parts in some chips */
848 snprintf(name, sizeof(name), "ahb_ck%d", slot);
849 port->ahb_ck = devm_clk_get(dev, name);
850 if (IS_ERR(port->ahb_ck)) {
851 if (PTR_ERR(port->ahb_ck) == -EPROBE_DEFER)
852 return -EPROBE_DEFER;
853
854 port->ahb_ck = NULL;
855 }
856
857 snprintf(name, sizeof(name), "axi_ck%d", slot);
858 port->axi_ck = devm_clk_get(dev, name);
859 if (IS_ERR(port->axi_ck)) {
860 if (PTR_ERR(port->axi_ck) == -EPROBE_DEFER)
861 return -EPROBE_DEFER;
862
863 port->axi_ck = NULL;
864 }
865
866 snprintf(name, sizeof(name), "aux_ck%d", slot);
867 port->aux_ck = devm_clk_get(dev, name);
868 if (IS_ERR(port->aux_ck)) {
869 if (PTR_ERR(port->aux_ck) == -EPROBE_DEFER)
870 return -EPROBE_DEFER;
871
872 port->aux_ck = NULL;
873 }
874
875 snprintf(name, sizeof(name), "obff_ck%d", slot);
876 port->obff_ck = devm_clk_get(dev, name);
877 if (IS_ERR(port->obff_ck)) {
878 if (PTR_ERR(port->obff_ck) == -EPROBE_DEFER)
879 return -EPROBE_DEFER;
880
881 port->obff_ck = NULL;
882 }
883
884 snprintf(name, sizeof(name), "pipe_ck%d", slot);
885 port->pipe_ck = devm_clk_get(dev, name);
886 if (IS_ERR(port->pipe_ck)) {
887 if (PTR_ERR(port->pipe_ck) == -EPROBE_DEFER)
888 return -EPROBE_DEFER;
889
890 port->pipe_ck = NULL;
891 }
892
893 snprintf(name, sizeof(name), "pcie-rst%d", slot);
894 port->reset = devm_reset_control_get_optional_exclusive(dev, name);
895 if (PTR_ERR(port->reset) == -EPROBE_DEFER)
896 return PTR_ERR(port->reset);
897
898 /* some platforms may use default PHY setting */
899 snprintf(name, sizeof(name), "pcie-phy%d", slot);
900 port->phy = devm_phy_optional_get(dev, name);
901 if (IS_ERR(port->phy))
902 return PTR_ERR(port->phy);
903
904 port->slot = slot;
905 port->pcie = pcie;
906
907 if (pcie->soc->setup_irq) {
908 err = pcie->soc->setup_irq(port, node);
909 if (err)
910 return err;
911 }
912
913 INIT_LIST_HEAD(&port->list);
914 list_add_tail(&port->list, &pcie->ports);
915
916 return 0;
917 }
918
919 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
920 {
921 struct device *dev = pcie->dev;
922 struct platform_device *pdev = to_platform_device(dev);
923 struct resource *regs;
924 int err;
925
926 /* get shared registers, which are optional */
927 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
928 if (regs) {
929 pcie->base = devm_ioremap_resource(dev, regs);
930 if (IS_ERR(pcie->base)) {
931 dev_err(dev, "failed to map shared register\n");
932 return PTR_ERR(pcie->base);
933 }
934 }
935
936 pcie->free_ck = devm_clk_get(dev, "free_ck");
937 if (IS_ERR(pcie->free_ck)) {
938 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
939 return -EPROBE_DEFER;
940
941 pcie->free_ck = NULL;
942 }
943
944 if (dev->pm_domain) {
945 pm_runtime_enable(dev);
946 pm_runtime_get_sync(dev);
947 }
948
949 /* enable top level clock */
950 err = clk_prepare_enable(pcie->free_ck);
951 if (err) {
952 dev_err(dev, "failed to enable free_ck\n");
953 goto err_free_ck;
954 }
955
956 return 0;
957
958 err_free_ck:
959 if (dev->pm_domain) {
960 pm_runtime_put_sync(dev);
961 pm_runtime_disable(dev);
962 }
963
964 return err;
965 }
966
967 static int mtk_pcie_setup(struct mtk_pcie *pcie)
968 {
969 struct device *dev = pcie->dev;
970 struct device_node *node = dev->of_node, *child;
971 struct of_pci_range_parser parser;
972 struct of_pci_range range;
973 struct resource res;
974 struct mtk_pcie_port *port, *tmp;
975 int err;
976
977 if (of_pci_range_parser_init(&parser, node)) {
978 dev_err(dev, "missing \"ranges\" property\n");
979 return -EINVAL;
980 }
981
982 for_each_of_pci_range(&parser, &range) {
983 err = of_pci_range_to_resource(&range, node, &res);
984 if (err < 0)
985 return err;
986
987 switch (res.flags & IORESOURCE_TYPE_BITS) {
988 case IORESOURCE_IO:
989 pcie->offset.io = res.start - range.pci_addr;
990
991 memcpy(&pcie->pio, &res, sizeof(res));
992 pcie->pio.name = node->full_name;
993
994 pcie->io.start = range.cpu_addr;
995 pcie->io.end = range.cpu_addr + range.size - 1;
996 pcie->io.flags = IORESOURCE_MEM;
997 pcie->io.name = "I/O";
998
999 memcpy(&res, &pcie->io, sizeof(res));
1000 break;
1001
1002 case IORESOURCE_MEM:
1003 pcie->offset.mem = res.start - range.pci_addr;
1004
1005 memcpy(&pcie->mem, &res, sizeof(res));
1006 pcie->mem.name = "non-prefetchable";
1007 break;
1008 }
1009 }
1010
1011 err = of_pci_parse_bus_range(node, &pcie->busn);
1012 if (err < 0) {
1013 dev_err(dev, "failed to parse bus ranges property: %d\n", err);
1014 pcie->busn.name = node->name;
1015 pcie->busn.start = 0;
1016 pcie->busn.end = 0xff;
1017 pcie->busn.flags = IORESOURCE_BUS;
1018 }
1019
1020 for_each_available_child_of_node(node, child) {
1021 int slot;
1022
1023 err = of_pci_get_devfn(child);
1024 if (err < 0) {
1025 dev_err(dev, "failed to parse devfn: %d\n", err);
1026 return err;
1027 }
1028
1029 slot = PCI_SLOT(err);
1030
1031 err = mtk_pcie_parse_port(pcie, child, slot);
1032 if (err)
1033 return err;
1034 }
1035
1036 err = mtk_pcie_subsys_powerup(pcie);
1037 if (err)
1038 return err;
1039
1040 /* enable each port, and then check link status */
1041 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1042 mtk_pcie_enable_port(port);
1043
1044 /* power down PCIe subsys if slots are all empty (link down) */
1045 if (list_empty(&pcie->ports))
1046 mtk_pcie_subsys_powerdown(pcie);
1047
1048 return 0;
1049 }
1050
1051 static int mtk_pcie_request_resources(struct mtk_pcie *pcie)
1052 {
1053 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1054 struct list_head *windows = &host->windows;
1055 struct device *dev = pcie->dev;
1056 int err;
1057
1058 pci_add_resource_offset(windows, &pcie->pio, pcie->offset.io);
1059 pci_add_resource_offset(windows, &pcie->mem, pcie->offset.mem);
1060 pci_add_resource(windows, &pcie->busn);
1061
1062 err = devm_request_pci_bus_resources(dev, windows);
1063 if (err < 0)
1064 return err;
1065
1066 pci_remap_iospace(&pcie->pio, pcie->io.start);
1067
1068 return 0;
1069 }
1070
1071 static int mtk_pcie_register_host(struct pci_host_bridge *host)
1072 {
1073 struct mtk_pcie *pcie = pci_host_bridge_priv(host);
1074 struct pci_bus *child;
1075 int err;
1076
1077 host->busnr = pcie->busn.start;
1078 host->dev.parent = pcie->dev;
1079 host->ops = pcie->soc->ops;
1080 host->map_irq = of_irq_parse_and_map_pci;
1081 host->swizzle_irq = pci_common_swizzle;
1082 host->sysdata = pcie;
1083 if (IS_ENABLED(CONFIG_PCI_MSI) && pcie->soc->has_msi)
1084 host->msi = &mtk_pcie_msi_chip;
1085
1086 err = pci_scan_root_bus_bridge(host);
1087 if (err < 0)
1088 return err;
1089
1090 pci_bus_size_bridges(host->bus);
1091 pci_bus_assign_resources(host->bus);
1092
1093 list_for_each_entry(child, &host->bus->children, node)
1094 pcie_bus_configure_settings(child);
1095
1096 pci_bus_add_devices(host->bus);
1097
1098 return 0;
1099 }
1100
1101 static int mtk_pcie_probe(struct platform_device *pdev)
1102 {
1103 struct device *dev = &pdev->dev;
1104 struct mtk_pcie *pcie;
1105 struct pci_host_bridge *host;
1106 int err;
1107
1108 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1109 if (!host)
1110 return -ENOMEM;
1111
1112 pcie = pci_host_bridge_priv(host);
1113
1114 pcie->dev = dev;
1115 pcie->soc = of_device_get_match_data(dev);
1116 platform_set_drvdata(pdev, pcie);
1117 INIT_LIST_HEAD(&pcie->ports);
1118
1119 err = mtk_pcie_setup(pcie);
1120 if (err)
1121 return err;
1122
1123 err = mtk_pcie_request_resources(pcie);
1124 if (err)
1125 goto put_resources;
1126
1127 err = mtk_pcie_register_host(host);
1128 if (err)
1129 goto put_resources;
1130
1131 return 0;
1132
1133 put_resources:
1134 if (!list_empty(&pcie->ports))
1135 mtk_pcie_put_resources(pcie);
1136
1137 return err;
1138 }
1139
1140 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1141 .ops = &mtk_pcie_ops,
1142 .startup = mtk_pcie_startup_port,
1143 };
1144
1145 static const struct mtk_pcie_soc mtk_pcie_soc_v2 = {
1146 .has_msi = true,
1147 .ops = &mtk_pcie_ops_v2,
1148 .startup = mtk_pcie_startup_port_v2,
1149 .setup_irq = mtk_pcie_setup_irq,
1150 };
1151
1152 static const struct of_device_id mtk_pcie_ids[] = {
1153 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1154 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1155 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_v2 },
1156 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_v2 },
1157 {},
1158 };
1159
1160 static struct platform_driver mtk_pcie_driver = {
1161 .probe = mtk_pcie_probe,
1162 .driver = {
1163 .name = "mtk-pcie",
1164 .of_match_table = mtk_pcie_ids,
1165 .suppress_bind_attrs = true,
1166 },
1167 };
1168 builtin_platform_driver(mtk_pcie_driver);
Linux with added FPC-III support