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Linux 4.16.11
[linux/fpc-iii.git] / drivers / pci / host / pcie-rcar.c
blobb4c4aad2cf66847b11f8ba8a01ae667d145cbafb
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014 Renesas Electronics Europe Ltd
5 *
6 * Based on:
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
10 *
11 * Author: Phil Edworthy <phil.edworthy@renesas.com>
12 */
13
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/msi.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_pci.h>
25 #include <linux/of_platform.h>
26 #include <linux/pci.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30
31 #define PCIECAR 0x000010
32 #define PCIECCTLR 0x000018
33 #define CONFIG_SEND_ENABLE (1 << 31)
34 #define TYPE0 (0 << 8)
35 #define TYPE1 (1 << 8)
36 #define PCIECDR 0x000020
37 #define PCIEMSR 0x000028
38 #define PCIEINTXR 0x000400
39 #define PCIEMSITXR 0x000840
40
41 /* Transfer control */
42 #define PCIETCTLR 0x02000
43 #define CFINIT 1
44 #define PCIETSTR 0x02004
45 #define DATA_LINK_ACTIVE 1
46 #define PCIEERRFR 0x02020
47 #define UNSUPPORTED_REQUEST (1 << 4)
48 #define PCIEMSIFR 0x02044
49 #define PCIEMSIALR 0x02048
50 #define MSIFE 1
51 #define PCIEMSIAUR 0x0204c
52 #define PCIEMSIIER 0x02050
53
54 /* root port address */
55 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
56
57 /* local address reg & mask */
58 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
59 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
60 #define LAM_PREFETCH (1 << 3)
61 #define LAM_64BIT (1 << 2)
62 #define LAR_ENABLE (1 << 1)
63
64 /* PCIe address reg & mask */
65 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
66 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
67 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
68 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
69 #define PAR_ENABLE (1 << 31)
70 #define IO_SPACE (1 << 8)
71
72 /* Configuration */
73 #define PCICONF(x) (0x010000 + ((x) * 0x4))
74 #define PMCAP(x) (0x010040 + ((x) * 0x4))
75 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
76 #define VCCAP(x) (0x010100 + ((x) * 0x4))
77
78 /* link layer */
79 #define IDSETR1 0x011004
80 #define TLCTLR 0x011048
81 #define MACSR 0x011054
82 #define SPCHGFIN (1 << 4)
83 #define SPCHGFAIL (1 << 6)
84 #define SPCHGSUC (1 << 7)
85 #define LINK_SPEED (0xf << 16)
86 #define LINK_SPEED_2_5GTS (1 << 16)
87 #define LINK_SPEED_5_0GTS (2 << 16)
88 #define MACCTLR 0x011058
89 #define SPEED_CHANGE (1 << 24)
90 #define SCRAMBLE_DISABLE (1 << 27)
91 #define MACS2R 0x011078
92 #define MACCGSPSETR 0x011084
93 #define SPCNGRSN (1 << 31)
94
95 /* R-Car H1 PHY */
96 #define H1_PCIEPHYADRR 0x04000c
97 #define WRITE_CMD (1 << 16)
98 #define PHY_ACK (1 << 24)
99 #define RATE_POS 12
100 #define LANE_POS 8
101 #define ADR_POS 0
102 #define H1_PCIEPHYDOUTR 0x040014
103 #define H1_PCIEPHYSR 0x040018
104
105 /* R-Car Gen2 PHY */
106 #define GEN2_PCIEPHYADDR 0x780
107 #define GEN2_PCIEPHYDATA 0x784
108 #define GEN2_PCIEPHYCTRL 0x78c
109
110 #define INT_PCI_MSI_NR 32
111
112 #define RCONF(x) (PCICONF(0)+(x))
113 #define RPMCAP(x) (PMCAP(0)+(x))
114 #define REXPCAP(x) (EXPCAP(0)+(x))
115 #define RVCCAP(x) (VCCAP(0)+(x))
116
117 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
118 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
119 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
120
121 #define RCAR_PCI_MAX_RESOURCES 4
122 #define MAX_NR_INBOUND_MAPS 6
123
124 struct rcar_msi {
125 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
126 struct irq_domain *domain;
127 struct msi_controller chip;
128 unsigned long pages;
129 struct mutex lock;
130 int irq1;
131 int irq2;
132 };
133
134 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
135 {
136 return container_of(chip, struct rcar_msi, chip);
137 }
138
139 /* Structure representing the PCIe interface */
140 struct rcar_pcie {
141 struct device *dev;
142 void __iomem *base;
143 struct list_head resources;
144 int root_bus_nr;
145 struct clk *clk;
146 struct clk *bus_clk;
147 struct rcar_msi msi;
148 };
149
150 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
151 unsigned long reg)
152 {
153 writel(val, pcie->base + reg);
154 }
155
156 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
157 unsigned long reg)
158 {
159 return readl(pcie->base + reg);
160 }
161
162 enum {
163 RCAR_PCI_ACCESS_READ,
164 RCAR_PCI_ACCESS_WRITE,
165 };
166
167 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
168 {
169 int shift = 8 * (where & 3);
170 u32 val = rcar_pci_read_reg(pcie, where & ~3);
171
172 val &= ~(mask << shift);
173 val |= data << shift;
174 rcar_pci_write_reg(pcie, val, where & ~3);
175 }
176
177 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
178 {
179 int shift = 8 * (where & 3);
180 u32 val = rcar_pci_read_reg(pcie, where & ~3);
181
182 return val >> shift;
183 }
184
185 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
186 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
187 unsigned char access_type, struct pci_bus *bus,
188 unsigned int devfn, int where, u32 *data)
189 {
190 int dev, func, reg, index;
191
192 dev = PCI_SLOT(devfn);
193 func = PCI_FUNC(devfn);
194 reg = where & ~3;
195 index = reg / 4;
196
197 /*
198 * While each channel has its own memory-mapped extended config
199 * space, it's generally only accessible when in endpoint mode.
200 * When in root complex mode, the controller is unable to target
201 * itself with either type 0 or type 1 accesses, and indeed, any
202 * controller initiated target transfer to its own config space
203 * result in a completer abort.
204 *
205 * Each channel effectively only supports a single device, but as
206 * the same channel <-> device access works for any PCI_SLOT()
207 * value, we cheat a bit here and bind the controller's config
208 * space to devfn 0 in order to enable self-enumeration. In this
209 * case the regular ECAR/ECDR path is sidelined and the mangled
210 * config access itself is initiated as an internal bus transaction.
211 */
212 if (pci_is_root_bus(bus)) {
213 if (dev != 0)
214 return PCIBIOS_DEVICE_NOT_FOUND;
215
216 if (access_type == RCAR_PCI_ACCESS_READ) {
217 *data = rcar_pci_read_reg(pcie, PCICONF(index));
218 } else {
219 /* Keep an eye out for changes to the root bus number */
220 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
221 pcie->root_bus_nr = *data & 0xff;
222
223 rcar_pci_write_reg(pcie, *data, PCICONF(index));
224 }
225
226 return PCIBIOS_SUCCESSFUL;
227 }
228
229 if (pcie->root_bus_nr < 0)
230 return PCIBIOS_DEVICE_NOT_FOUND;
231
232 /* Clear errors */
233 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
234
235 /* Set the PIO address */
236 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
237 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
238
239 /* Enable the configuration access */
240 if (bus->parent->number == pcie->root_bus_nr)
241 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
242 else
243 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
244
245 /* Check for errors */
246 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
247 return PCIBIOS_DEVICE_NOT_FOUND;
248
249 /* Check for master and target aborts */
250 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
251 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
252 return PCIBIOS_DEVICE_NOT_FOUND;
253
254 if (access_type == RCAR_PCI_ACCESS_READ)
255 *data = rcar_pci_read_reg(pcie, PCIECDR);
256 else
257 rcar_pci_write_reg(pcie, *data, PCIECDR);
258
259 /* Disable the configuration access */
260 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
261
262 return PCIBIOS_SUCCESSFUL;
263 }
264
265 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
266 int where, int size, u32 *val)
267 {
268 struct rcar_pcie *pcie = bus->sysdata;
269 int ret;
270
271 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
272 bus, devfn, where, val);
273 if (ret != PCIBIOS_SUCCESSFUL) {
274 *val = 0xffffffff;
275 return ret;
276 }
277
278 if (size == 1)
279 *val = (*val >> (8 * (where & 3))) & 0xff;
280 else if (size == 2)
281 *val = (*val >> (8 * (where & 2))) & 0xffff;
282
283 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
284 bus->number, devfn, where, size, (unsigned long)*val);
285
286 return ret;
287 }
288
289 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
290 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
291 int where, int size, u32 val)
292 {
293 struct rcar_pcie *pcie = bus->sysdata;
294 int shift, ret;
295 u32 data;
296
297 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
298 bus, devfn, where, &data);
299 if (ret != PCIBIOS_SUCCESSFUL)
300 return ret;
301
302 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
303 bus->number, devfn, where, size, (unsigned long)val);
304
305 if (size == 1) {
306 shift = 8 * (where & 3);
307 data &= ~(0xff << shift);
308 data |= ((val & 0xff) << shift);
309 } else if (size == 2) {
310 shift = 8 * (where & 2);
311 data &= ~(0xffff << shift);
312 data |= ((val & 0xffff) << shift);
313 } else
314 data = val;
315
316 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
317 bus, devfn, where, &data);
318
319 return ret;
320 }
321
322 static struct pci_ops rcar_pcie_ops = {
323 .read = rcar_pcie_read_conf,
324 .write = rcar_pcie_write_conf,
325 };
326
327 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie,
328 struct resource *res)
329 {
330 /* Setup PCIe address space mappings for each resource */
331 resource_size_t size;
332 resource_size_t res_start;
333 u32 mask;
334
335 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
336
337 /*
338 * The PAMR mask is calculated in units of 128Bytes, which
339 * keeps things pretty simple.
340 */
341 size = resource_size(res);
342 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
343 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
344
345 if (res->flags & IORESOURCE_IO)
346 res_start = pci_pio_to_address(res->start);
347 else
348 res_start = res->start;
349
350 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
351 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
352 PCIEPALR(win));
353
354 /* First resource is for IO */
355 mask = PAR_ENABLE;
356 if (res->flags & IORESOURCE_IO)
357 mask |= IO_SPACE;
358
359 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
360 }
361
362 static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci)
363 {
364 struct resource_entry *win;
365 int i = 0;
366
367 /* Setup PCI resources */
368 resource_list_for_each_entry(win, &pci->resources) {
369 struct resource *res = win->res;
370
371 if (!res->flags)
372 continue;
373
374 switch (resource_type(res)) {
375 case IORESOURCE_IO:
376 case IORESOURCE_MEM:
377 rcar_pcie_setup_window(i, pci, res);
378 i++;
379 break;
380 case IORESOURCE_BUS:
381 pci->root_bus_nr = res->start;
382 break;
383 default:
384 continue;
385 }
386
387 pci_add_resource(resource, res);
388 }
389
390 return 1;
391 }
392
393 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
394 {
395 struct device *dev = pcie->dev;
396 unsigned int timeout = 1000;
397 u32 macsr;
398
399 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
400 return;
401
402 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
403 dev_err(dev, "Speed change already in progress\n");
404 return;
405 }
406
407 macsr = rcar_pci_read_reg(pcie, MACSR);
408 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
409 goto done;
410
411 /* Set target link speed to 5.0 GT/s */
412 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
413 PCI_EXP_LNKSTA_CLS_5_0GB);
414
415 /* Set speed change reason as intentional factor */
416 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
417
418 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
419 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
420 rcar_pci_write_reg(pcie, macsr, MACSR);
421
422 /* Start link speed change */
423 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
424
425 while (timeout--) {
426 macsr = rcar_pci_read_reg(pcie, MACSR);
427 if (macsr & SPCHGFIN) {
428 /* Clear the interrupt bits */
429 rcar_pci_write_reg(pcie, macsr, MACSR);
430
431 if (macsr & SPCHGFAIL)
432 dev_err(dev, "Speed change failed\n");
433
434 goto done;
435 }
436
437 msleep(1);
438 };
439
440 dev_err(dev, "Speed change timed out\n");
441
442 done:
443 dev_info(dev, "Current link speed is %s GT/s\n",
444 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
445 }
446
447 static int rcar_pcie_enable(struct rcar_pcie *pcie)
448 {
449 struct device *dev = pcie->dev;
450 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
451 struct pci_bus *bus, *child;
452 int ret;
453
454 /* Try setting 5 GT/s link speed */
455 rcar_pcie_force_speedup(pcie);
456
457 rcar_pcie_setup(&bridge->windows, pcie);
458
459 pci_add_flags(PCI_REASSIGN_ALL_BUS);
460
461 bridge->dev.parent = dev;
462 bridge->sysdata = pcie;
463 bridge->busnr = pcie->root_bus_nr;
464 bridge->ops = &rcar_pcie_ops;
465 bridge->map_irq = of_irq_parse_and_map_pci;
466 bridge->swizzle_irq = pci_common_swizzle;
467 if (IS_ENABLED(CONFIG_PCI_MSI))
468 bridge->msi = &pcie->msi.chip;
469
470 ret = pci_scan_root_bus_bridge(bridge);
471 if (ret < 0)
472 return ret;
473
474 bus = bridge->bus;
475
476 pci_bus_size_bridges(bus);
477 pci_bus_assign_resources(bus);
478
479 list_for_each_entry(child, &bus->children, node)
480 pcie_bus_configure_settings(child);
481
482 pci_bus_add_devices(bus);
483
484 return 0;
485 }
486
487 static int phy_wait_for_ack(struct rcar_pcie *pcie)
488 {
489 struct device *dev = pcie->dev;
490 unsigned int timeout = 100;
491
492 while (timeout--) {
493 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
494 return 0;
495
496 udelay(100);
497 }
498
499 dev_err(dev, "Access to PCIe phy timed out\n");
500
501 return -ETIMEDOUT;
502 }
503
504 static void phy_write_reg(struct rcar_pcie *pcie,
505 unsigned int rate, unsigned int addr,
506 unsigned int lane, unsigned int data)
507 {
508 unsigned long phyaddr;
509
510 phyaddr = WRITE_CMD |
511 ((rate & 1) << RATE_POS) |
512 ((lane & 0xf) << LANE_POS) |
513 ((addr & 0xff) << ADR_POS);
514
515 /* Set write data */
516 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
517 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
518
519 /* Ignore errors as they will be dealt with if the data link is down */
520 phy_wait_for_ack(pcie);
521
522 /* Clear command */
523 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
524 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
525
526 /* Ignore errors as they will be dealt with if the data link is down */
527 phy_wait_for_ack(pcie);
528 }
529
530 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
531 {
532 unsigned int timeout = 10;
533
534 while (timeout--) {
535 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
536 return 0;
537
538 msleep(5);
539 }
540
541 return -ETIMEDOUT;
542 }
543
544 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
545 {
546 int err;
547
548 /* Begin initialization */
549 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
550
551 /* Set mode */
552 rcar_pci_write_reg(pcie, 1, PCIEMSR);
553
554 /*
555 * Initial header for port config space is type 1, set the device
556 * class to match. Hardware takes care of propagating the IDSETR
557 * settings, so there is no need to bother with a quirk.
558 */
559 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
560
561 /*
562 * Setup Secondary Bus Number & Subordinate Bus Number, even though
563 * they aren't used, to avoid bridge being detected as broken.
564 */
565 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
566 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
567
568 /* Initialize default capabilities. */
569 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
570 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
571 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
572 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
573 PCI_HEADER_TYPE_BRIDGE);
574
575 /* Enable data link layer active state reporting */
576 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
577 PCI_EXP_LNKCAP_DLLLARC);
578
579 /* Write out the physical slot number = 0 */
580 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
581
582 /* Set the completion timer timeout to the maximum 50ms. */
583 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
584
585 /* Terminate list of capabilities (Next Capability Offset=0) */
586 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
587
588 /* Enable MSI */
589 if (IS_ENABLED(CONFIG_PCI_MSI))
590 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
591
592 /* Finish initialization - establish a PCI Express link */
593 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
594
595 /* This will timeout if we don't have a link. */
596 err = rcar_pcie_wait_for_dl(pcie);
597 if (err)
598 return err;
599
600 /* Enable INTx interrupts */
601 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
602
603 wmb();
604
605 return 0;
606 }
607
608 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
609 {
610 unsigned int timeout = 10;
611
612 /* Initialize the phy */
613 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
614 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
615 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
616 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
617 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
618 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
619 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
620 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
621 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
622 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
623 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
624 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
625
626 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
627 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
628 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
629
630 while (timeout--) {
631 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
632 return rcar_pcie_hw_init(pcie);
633
634 msleep(5);
635 }
636
637 return -ETIMEDOUT;
638 }
639
640 static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
641 {
642 /*
643 * These settings come from the R-Car Series, 2nd Generation User's
644 * Manual, section 50.3.1 (2) Initialization of the physical layer.
645 */
646 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
647 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
648 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
649 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
650
651 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
652 /* The following value is for DC connection, no termination resistor */
653 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
654 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
655 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
656
657 return rcar_pcie_hw_init(pcie);
658 }
659
660 static int rcar_msi_alloc(struct rcar_msi *chip)
661 {
662 int msi;
663
664 mutex_lock(&chip->lock);
665
666 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
667 if (msi < INT_PCI_MSI_NR)
668 set_bit(msi, chip->used);
669 else
670 msi = -ENOSPC;
671
672 mutex_unlock(&chip->lock);
673
674 return msi;
675 }
676
677 static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs)
678 {
679 int msi;
680
681 mutex_lock(&chip->lock);
682 msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR,
683 order_base_2(no_irqs));
684 mutex_unlock(&chip->lock);
685
686 return msi;
687 }
688
689 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
690 {
691 mutex_lock(&chip->lock);
692 clear_bit(irq, chip->used);
693 mutex_unlock(&chip->lock);
694 }
695
696 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
697 {
698 struct rcar_pcie *pcie = data;
699 struct rcar_msi *msi = &pcie->msi;
700 struct device *dev = pcie->dev;
701 unsigned long reg;
702
703 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
704
705 /* MSI & INTx share an interrupt - we only handle MSI here */
706 if (!reg)
707 return IRQ_NONE;
708
709 while (reg) {
710 unsigned int index = find_first_bit(&reg, 32);
711 unsigned int irq;
712
713 /* clear the interrupt */
714 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
715
716 irq = irq_find_mapping(msi->domain, index);
717 if (irq) {
718 if (test_bit(index, msi->used))
719 generic_handle_irq(irq);
720 else
721 dev_info(dev, "unhandled MSI\n");
722 } else {
723 /* Unknown MSI, just clear it */
724 dev_dbg(dev, "unexpected MSI\n");
725 }
726
727 /* see if there's any more pending in this vector */
728 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
729 }
730
731 return IRQ_HANDLED;
732 }
733
734 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
735 struct msi_desc *desc)
736 {
737 struct rcar_msi *msi = to_rcar_msi(chip);
738 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
739 struct msi_msg msg;
740 unsigned int irq;
741 int hwirq;
742
743 hwirq = rcar_msi_alloc(msi);
744 if (hwirq < 0)
745 return hwirq;
746
747 irq = irq_find_mapping(msi->domain, hwirq);
748 if (!irq) {
749 rcar_msi_free(msi, hwirq);
750 return -EINVAL;
751 }
752
753 irq_set_msi_desc(irq, desc);
754
755 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
756 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
757 msg.data = hwirq;
758
759 pci_write_msi_msg(irq, &msg);
760
761 return 0;
762 }
763
764 static int rcar_msi_setup_irqs(struct msi_controller *chip,
765 struct pci_dev *pdev, int nvec, int type)
766 {
767 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
768 struct rcar_msi *msi = to_rcar_msi(chip);
769 struct msi_desc *desc;
770 struct msi_msg msg;
771 unsigned int irq;
772 int hwirq;
773 int i;
774
775 /* MSI-X interrupts are not supported */
776 if (type == PCI_CAP_ID_MSIX)
777 return -EINVAL;
778
779 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
780 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
781
782 hwirq = rcar_msi_alloc_region(msi, nvec);
783 if (hwirq < 0)
784 return -ENOSPC;
785
786 irq = irq_find_mapping(msi->domain, hwirq);
787 if (!irq)
788 return -ENOSPC;
789
790 for (i = 0; i < nvec; i++) {
791 /*
792 * irq_create_mapping() called from rcar_pcie_probe() pre-
793 * allocates descs, so there is no need to allocate descs here.
794 * We can therefore assume that if irq_find_mapping() above
795 * returns non-zero, then the descs are also successfully
796 * allocated.
797 */
798 if (irq_set_msi_desc_off(irq, i, desc)) {
799 /* TODO: clear */
800 return -EINVAL;
801 }
802 }
803
804 desc->nvec_used = nvec;
805 desc->msi_attrib.multiple = order_base_2(nvec);
806
807 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
808 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
809 msg.data = hwirq;
810
811 pci_write_msi_msg(irq, &msg);
812
813 return 0;
814 }
815
816 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
817 {
818 struct rcar_msi *msi = to_rcar_msi(chip);
819 struct irq_data *d = irq_get_irq_data(irq);
820
821 rcar_msi_free(msi, d->hwirq);
822 }
823
824 static struct irq_chip rcar_msi_irq_chip = {
825 .name = "R-Car PCIe MSI",
826 .irq_enable = pci_msi_unmask_irq,
827 .irq_disable = pci_msi_mask_irq,
828 .irq_mask = pci_msi_mask_irq,
829 .irq_unmask = pci_msi_unmask_irq,
830 };
831
832 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
833 irq_hw_number_t hwirq)
834 {
835 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
836 irq_set_chip_data(irq, domain->host_data);
837
838 return 0;
839 }
840
841 static const struct irq_domain_ops msi_domain_ops = {
842 .map = rcar_msi_map,
843 };
844
845 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
846 {
847 struct device *dev = pcie->dev;
848 struct rcar_msi *msi = &pcie->msi;
849 unsigned long base;
850 int err, i;
851
852 mutex_init(&msi->lock);
853
854 msi->chip.dev = dev;
855 msi->chip.setup_irq = rcar_msi_setup_irq;
856 msi->chip.setup_irqs = rcar_msi_setup_irqs;
857 msi->chip.teardown_irq = rcar_msi_teardown_irq;
858
859 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR,
860 &msi_domain_ops, &msi->chip);
861 if (!msi->domain) {
862 dev_err(dev, "failed to create IRQ domain\n");
863 return -ENOMEM;
864 }
865
866 for (i = 0; i < INT_PCI_MSI_NR; i++)
867 irq_create_mapping(msi->domain, i);
868
869 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
870 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
871 IRQF_SHARED | IRQF_NO_THREAD,
872 rcar_msi_irq_chip.name, pcie);
873 if (err < 0) {
874 dev_err(dev, "failed to request IRQ: %d\n", err);
875 goto err;
876 }
877
878 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
879 IRQF_SHARED | IRQF_NO_THREAD,
880 rcar_msi_irq_chip.name, pcie);
881 if (err < 0) {
882 dev_err(dev, "failed to request IRQ: %d\n", err);
883 goto err;
884 }
885
886 /* setup MSI data target */
887 msi->pages = __get_free_pages(GFP_KERNEL, 0);
888 base = virt_to_phys((void *)msi->pages);
889
890 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
891 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
892
893 /* enable all MSI interrupts */
894 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
895
896 return 0;
897
898 err:
899 irq_domain_remove(msi->domain);
900 return err;
901 }
902
903 static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
904 {
905 struct device *dev = pcie->dev;
906 struct resource res;
907 int err, i;
908
909 err = of_address_to_resource(dev->of_node, 0, &res);
910 if (err)
911 return err;
912
913 pcie->base = devm_ioremap_resource(dev, &res);
914 if (IS_ERR(pcie->base))
915 return PTR_ERR(pcie->base);
916
917 pcie->clk = devm_clk_get(dev, "pcie");
918 if (IS_ERR(pcie->clk)) {
919 dev_err(dev, "cannot get platform clock\n");
920 return PTR_ERR(pcie->clk);
921 }
922 err = clk_prepare_enable(pcie->clk);
923 if (err)
924 return err;
925
926 pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
927 if (IS_ERR(pcie->bus_clk)) {
928 dev_err(dev, "cannot get pcie bus clock\n");
929 err = PTR_ERR(pcie->bus_clk);
930 goto fail_clk;
931 }
932 err = clk_prepare_enable(pcie->bus_clk);
933 if (err)
934 goto fail_clk;
935
936 i = irq_of_parse_and_map(dev->of_node, 0);
937 if (!i) {
938 dev_err(dev, "cannot get platform resources for msi interrupt\n");
939 err = -ENOENT;
940 goto err_map_reg;
941 }
942 pcie->msi.irq1 = i;
943
944 i = irq_of_parse_and_map(dev->of_node, 1);
945 if (!i) {
946 dev_err(dev, "cannot get platform resources for msi interrupt\n");
947 err = -ENOENT;
948 goto err_map_reg;
949 }
950 pcie->msi.irq2 = i;
951
952 return 0;
953
954 err_map_reg:
955 clk_disable_unprepare(pcie->bus_clk);
956 fail_clk:
957 clk_disable_unprepare(pcie->clk);
958
959 return err;
960 }
961
962 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
963 struct of_pci_range *range,
964 int *index)
965 {
966 u64 restype = range->flags;
967 u64 cpu_addr = range->cpu_addr;
968 u64 cpu_end = range->cpu_addr + range->size;
969 u64 pci_addr = range->pci_addr;
970 u32 flags = LAM_64BIT | LAR_ENABLE;
971 u64 mask;
972 u64 size;
973 int idx = *index;
974
975 if (restype & IORESOURCE_PREFETCH)
976 flags |= LAM_PREFETCH;
977
978 /*
979 * If the size of the range is larger than the alignment of the start
980 * address, we have to use multiple entries to perform the mapping.
981 */
982 if (cpu_addr > 0) {
983 unsigned long nr_zeros = __ffs64(cpu_addr);
984 u64 alignment = 1ULL << nr_zeros;
985
986 size = min(range->size, alignment);
987 } else {
988 size = range->size;
989 }
990 /* Hardware supports max 4GiB inbound region */
991 size = min(size, 1ULL << 32);
992
993 mask = roundup_pow_of_two(size) - 1;
994 mask &= ~0xf;
995
996 while (cpu_addr < cpu_end) {
997 /*
998 * Set up 64-bit inbound regions as the range parser doesn't
999 * distinguish between 32 and 64-bit types.
1000 */
1001 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
1002 PCIEPRAR(idx));
1003 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
1004 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags,
1005 PCIELAMR(idx));
1006
1007 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
1008 PCIEPRAR(idx + 1));
1009 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr),
1010 PCIELAR(idx + 1));
1011 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
1012
1013 pci_addr += size;
1014 cpu_addr += size;
1015 idx += 2;
1016
1017 if (idx > MAX_NR_INBOUND_MAPS) {
1018 dev_err(pcie->dev, "Failed to map inbound regions!\n");
1019 return -EINVAL;
1020 }
1021 }
1022 *index = idx;
1023
1024 return 0;
1025 }
1026
1027 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
1028 struct device_node *np)
1029 {
1030 struct of_pci_range range;
1031 struct of_pci_range_parser parser;
1032 int index = 0;
1033 int err;
1034
1035 if (of_pci_dma_range_parser_init(&parser, np))
1036 return -EINVAL;
1037
1038 /* Get the dma-ranges from DT */
1039 for_each_of_pci_range(&parser, &range) {
1040 u64 end = range.cpu_addr + range.size - 1;
1041
1042 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
1043 range.flags, range.cpu_addr, end, range.pci_addr);
1044
1045 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
1046 if (err)
1047 return err;
1048 }
1049
1050 return 0;
1051 }
1052
1053 static const struct of_device_id rcar_pcie_of_match[] = {
1054 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
1055 { .compatible = "renesas,pcie-r8a7790",
1056 .data = rcar_pcie_hw_init_gen2 },
1057 { .compatible = "renesas,pcie-r8a7791",
1058 .data = rcar_pcie_hw_init_gen2 },
1059 { .compatible = "renesas,pcie-rcar-gen2",
1060 .data = rcar_pcie_hw_init_gen2 },
1061 { .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init },
1062 { .compatible = "renesas,pcie-rcar-gen3", .data = rcar_pcie_hw_init },
1063 {},
1064 };
1065
1066 static int rcar_pcie_parse_request_of_pci_ranges(struct rcar_pcie *pci)
1067 {
1068 int err;
1069 struct device *dev = pci->dev;
1070 struct device_node *np = dev->of_node;
1071 resource_size_t iobase;
1072 struct resource_entry *win, *tmp;
1073
1074 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources,
1075 &iobase);
1076 if (err)
1077 return err;
1078
1079 err = devm_request_pci_bus_resources(dev, &pci->resources);
1080 if (err)
1081 goto out_release_res;
1082
1083 resource_list_for_each_entry_safe(win, tmp, &pci->resources) {
1084 struct resource *res = win->res;
1085
1086 if (resource_type(res) == IORESOURCE_IO) {
1087 err = pci_remap_iospace(res, iobase);
1088 if (err) {
1089 dev_warn(dev, "error %d: failed to map resource %pR\n",
1090 err, res);
1091
1092 resource_list_destroy_entry(win);
1093 }
1094 }
1095 }
1096
1097 return 0;
1098
1099 out_release_res:
1100 pci_free_resource_list(&pci->resources);
1101 return err;
1102 }
1103
1104 static int rcar_pcie_probe(struct platform_device *pdev)
1105 {
1106 struct device *dev = &pdev->dev;
1107 struct rcar_pcie *pcie;
1108 unsigned int data;
1109 int err;
1110 int (*hw_init_fn)(struct rcar_pcie *);
1111 struct pci_host_bridge *bridge;
1112
1113 bridge = pci_alloc_host_bridge(sizeof(*pcie));
1114 if (!bridge)
1115 return -ENOMEM;
1116
1117 pcie = pci_host_bridge_priv(bridge);
1118
1119 pcie->dev = dev;
1120
1121 INIT_LIST_HEAD(&pcie->resources);
1122
1123 err = rcar_pcie_parse_request_of_pci_ranges(pcie);
1124 if (err)
1125 goto err_free_bridge;
1126
1127 err = rcar_pcie_get_resources(pcie);
1128 if (err < 0) {
1129 dev_err(dev, "failed to request resources: %d\n", err);
1130 goto err_free_resource_list;
1131 }
1132
1133 err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node);
1134 if (err)
1135 goto err_free_resource_list;
1136
1137 pm_runtime_enable(dev);
1138 err = pm_runtime_get_sync(dev);
1139 if (err < 0) {
1140 dev_err(dev, "pm_runtime_get_sync failed\n");
1141 goto err_pm_disable;
1142 }
1143
1144 /* Failure to get a link might just be that no cards are inserted */
1145 hw_init_fn = of_device_get_match_data(dev);
1146 err = hw_init_fn(pcie);
1147 if (err) {
1148 dev_info(dev, "PCIe link down\n");
1149 err = -ENODEV;
1150 goto err_pm_put;
1151 }
1152
1153 data = rcar_pci_read_reg(pcie, MACSR);
1154 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1155
1156 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1157 err = rcar_pcie_enable_msi(pcie);
1158 if (err < 0) {
1159 dev_err(dev,
1160 "failed to enable MSI support: %d\n",
1161 err);
1162 goto err_pm_put;
1163 }
1164 }
1165
1166 err = rcar_pcie_enable(pcie);
1167 if (err)
1168 goto err_pm_put;
1169
1170 return 0;
1171
1172 err_pm_put:
1173 pm_runtime_put(dev);
1174
1175 err_pm_disable:
1176 pm_runtime_disable(dev);
1177
1178 err_free_resource_list:
1179 pci_free_resource_list(&pcie->resources);
1180 err_free_bridge:
1181 pci_free_host_bridge(bridge);
1182
1183 return err;
1184 }
1185
1186 static struct platform_driver rcar_pcie_driver = {
1187 .driver = {
1188 .name = "rcar-pcie",
1189 .of_match_table = rcar_pcie_of_match,
1190 .suppress_bind_attrs = true,
1191 },
1192 .probe = rcar_pcie_probe,
1193 };
1194 builtin_platform_driver(rcar_pcie_driver);
Linux with added FPC-III support