1 // SPDX-License-Identifier: GPL-2.0
3 * Procfs interface for the PCI bus.
5 * Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
8 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <linux/proc_fs.h>
13 #include <linux/seq_file.h>
14 #include <linux/capability.h>
15 #include <linux/uaccess.h>
16 #include <asm/byteorder.h>
19 static int proc_initialized
; /* = 0 */
21 static loff_t
proc_bus_pci_lseek(struct file
*file
, loff_t off
, int whence
)
23 struct pci_dev
*dev
= PDE_DATA(file_inode(file
));
24 return fixed_size_llseek(file
, off
, whence
, dev
->cfg_size
);
27 static ssize_t
proc_bus_pci_read(struct file
*file
, char __user
*buf
,
28 size_t nbytes
, loff_t
*ppos
)
30 struct pci_dev
*dev
= PDE_DATA(file_inode(file
));
31 unsigned int pos
= *ppos
;
32 unsigned int cnt
, size
;
35 * Normal users can read only the standardized portion of the
36 * configuration space as several chips lock up when trying to read
37 * undefined locations (think of Intel PIIX4 as a typical example).
40 if (capable(CAP_SYS_ADMIN
))
42 else if (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
51 if (pos
+ nbytes
> size
)
55 if (!access_ok(VERIFY_WRITE
, buf
, cnt
))
58 pci_config_pm_runtime_get(dev
);
60 if ((pos
& 1) && cnt
) {
62 pci_user_read_config_byte(dev
, pos
, &val
);
69 if ((pos
& 3) && cnt
> 2) {
71 pci_user_read_config_word(dev
, pos
, &val
);
72 __put_user(cpu_to_le16(val
), (__le16 __user
*) buf
);
80 pci_user_read_config_dword(dev
, pos
, &val
);
81 __put_user(cpu_to_le32(val
), (__le32 __user
*) buf
);
89 pci_user_read_config_word(dev
, pos
, &val
);
90 __put_user(cpu_to_le16(val
), (__le16 __user
*) buf
);
98 pci_user_read_config_byte(dev
, pos
, &val
);
105 pci_config_pm_runtime_put(dev
);
111 static ssize_t
proc_bus_pci_write(struct file
*file
, const char __user
*buf
,
112 size_t nbytes
, loff_t
*ppos
)
114 struct inode
*ino
= file_inode(file
);
115 struct pci_dev
*dev
= PDE_DATA(ino
);
117 int size
= dev
->cfg_size
;
124 if (pos
+ nbytes
> size
)
128 if (!access_ok(VERIFY_READ
, buf
, cnt
))
131 pci_config_pm_runtime_get(dev
);
133 if ((pos
& 1) && cnt
) {
135 __get_user(val
, buf
);
136 pci_user_write_config_byte(dev
, pos
, val
);
142 if ((pos
& 3) && cnt
> 2) {
144 __get_user(val
, (__le16 __user
*) buf
);
145 pci_user_write_config_word(dev
, pos
, le16_to_cpu(val
));
153 __get_user(val
, (__le32 __user
*) buf
);
154 pci_user_write_config_dword(dev
, pos
, le32_to_cpu(val
));
162 __get_user(val
, (__le16 __user
*) buf
);
163 pci_user_write_config_word(dev
, pos
, le16_to_cpu(val
));
171 __get_user(val
, buf
);
172 pci_user_write_config_byte(dev
, pos
, val
);
178 pci_config_pm_runtime_put(dev
);
181 i_size_write(ino
, dev
->cfg_size
);
185 struct pci_filp_private
{
186 enum pci_mmap_state mmap_state
;
190 static long proc_bus_pci_ioctl(struct file
*file
, unsigned int cmd
,
193 struct pci_dev
*dev
= PDE_DATA(file_inode(file
));
195 struct pci_filp_private
*fpriv
= file
->private_data
;
196 #endif /* HAVE_PCI_MMAP */
200 case PCIIOC_CONTROLLER
:
201 ret
= pci_domain_nr(dev
->bus
);
205 case PCIIOC_MMAP_IS_IO
:
206 if (!arch_can_pci_mmap_io())
208 fpriv
->mmap_state
= pci_mmap_io
;
211 case PCIIOC_MMAP_IS_MEM
:
212 fpriv
->mmap_state
= pci_mmap_mem
;
215 case PCIIOC_WRITE_COMBINE
:
216 if (arch_can_pci_mmap_wc()) {
218 fpriv
->write_combine
= 1;
220 fpriv
->write_combine
= 0;
223 /* If arch decided it can't, fall through... */
224 #endif /* HAVE_PCI_MMAP */
234 static int proc_bus_pci_mmap(struct file
*file
, struct vm_area_struct
*vma
)
236 struct pci_dev
*dev
= PDE_DATA(file_inode(file
));
237 struct pci_filp_private
*fpriv
= file
->private_data
;
238 int i
, ret
, write_combine
= 0, res_bit
= IORESOURCE_MEM
;
240 if (!capable(CAP_SYS_RAWIO
))
243 if (fpriv
->mmap_state
== pci_mmap_io
) {
244 if (!arch_can_pci_mmap_io())
246 res_bit
= IORESOURCE_IO
;
249 /* Make sure the caller is mapping a real resource for this device */
250 for (i
= 0; i
< PCI_ROM_RESOURCE
; i
++) {
251 if (dev
->resource
[i
].flags
& res_bit
&&
252 pci_mmap_fits(dev
, i
, vma
, PCI_MMAP_PROCFS
))
256 if (i
>= PCI_ROM_RESOURCE
)
259 if (fpriv
->mmap_state
== pci_mmap_mem
&&
260 fpriv
->write_combine
) {
261 if (dev
->resource
[i
].flags
& IORESOURCE_PREFETCH
)
266 ret
= pci_mmap_page_range(dev
, i
, vma
,
267 fpriv
->mmap_state
, write_combine
);
274 static int proc_bus_pci_open(struct inode
*inode
, struct file
*file
)
276 struct pci_filp_private
*fpriv
= kmalloc(sizeof(*fpriv
), GFP_KERNEL
);
281 fpriv
->mmap_state
= pci_mmap_io
;
282 fpriv
->write_combine
= 0;
284 file
->private_data
= fpriv
;
289 static int proc_bus_pci_release(struct inode
*inode
, struct file
*file
)
291 kfree(file
->private_data
);
292 file
->private_data
= NULL
;
296 #endif /* HAVE_PCI_MMAP */
298 static const struct file_operations proc_bus_pci_operations
= {
299 .owner
= THIS_MODULE
,
300 .llseek
= proc_bus_pci_lseek
,
301 .read
= proc_bus_pci_read
,
302 .write
= proc_bus_pci_write
,
303 .unlocked_ioctl
= proc_bus_pci_ioctl
,
304 .compat_ioctl
= proc_bus_pci_ioctl
,
306 .open
= proc_bus_pci_open
,
307 .release
= proc_bus_pci_release
,
308 .mmap
= proc_bus_pci_mmap
,
309 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
310 .get_unmapped_area
= get_pci_unmapped_area
,
311 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
312 #endif /* HAVE_PCI_MMAP */
316 static void *pci_seq_start(struct seq_file
*m
, loff_t
*pos
)
318 struct pci_dev
*dev
= NULL
;
321 for_each_pci_dev(dev
) {
328 static void *pci_seq_next(struct seq_file
*m
, void *v
, loff_t
*pos
)
330 struct pci_dev
*dev
= v
;
333 dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
);
337 static void pci_seq_stop(struct seq_file
*m
, void *v
)
340 struct pci_dev
*dev
= v
;
345 static int show_device(struct seq_file
*m
, void *v
)
347 const struct pci_dev
*dev
= v
;
348 const struct pci_driver
*drv
;
354 drv
= pci_dev_driver(dev
);
355 seq_printf(m
, "%02x%02x\t%04x%04x\t%x",
362 /* only print standard and ROM resources to preserve compatibility */
363 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
364 resource_size_t start
, end
;
365 pci_resource_to_user(dev
, i
, &dev
->resource
[i
], &start
, &end
);
366 seq_printf(m
, "\t%16llx",
367 (unsigned long long)(start
|
368 (dev
->resource
[i
].flags
& PCI_REGION_FLAG_MASK
)));
370 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
371 resource_size_t start
, end
;
372 pci_resource_to_user(dev
, i
, &dev
->resource
[i
], &start
, &end
);
373 seq_printf(m
, "\t%16llx",
374 dev
->resource
[i
].start
< dev
->resource
[i
].end
?
375 (unsigned long long)(end
- start
) + 1 : 0);
379 seq_printf(m
, "%s", drv
->name
);
384 static const struct seq_operations proc_bus_pci_devices_op
= {
385 .start
= pci_seq_start
,
386 .next
= pci_seq_next
,
387 .stop
= pci_seq_stop
,
391 static struct proc_dir_entry
*proc_bus_pci_dir
;
393 int pci_proc_attach_device(struct pci_dev
*dev
)
395 struct pci_bus
*bus
= dev
->bus
;
396 struct proc_dir_entry
*e
;
399 if (!proc_initialized
)
403 if (pci_proc_domain(bus
)) {
404 sprintf(name
, "%04x:%02x", pci_domain_nr(bus
),
407 sprintf(name
, "%02x", bus
->number
);
409 bus
->procdir
= proc_mkdir(name
, proc_bus_pci_dir
);
414 sprintf(name
, "%02x.%x", PCI_SLOT(dev
->devfn
), PCI_FUNC(dev
->devfn
));
415 e
= proc_create_data(name
, S_IFREG
| S_IRUGO
| S_IWUSR
, bus
->procdir
,
416 &proc_bus_pci_operations
, dev
);
419 proc_set_size(e
, dev
->cfg_size
);
425 int pci_proc_detach_device(struct pci_dev
*dev
)
427 proc_remove(dev
->procent
);
432 int pci_proc_detach_bus(struct pci_bus
*bus
)
434 proc_remove(bus
->procdir
);
438 static int proc_bus_pci_dev_open(struct inode
*inode
, struct file
*file
)
440 return seq_open(file
, &proc_bus_pci_devices_op
);
443 static const struct file_operations proc_bus_pci_dev_operations
= {
444 .owner
= THIS_MODULE
,
445 .open
= proc_bus_pci_dev_open
,
448 .release
= seq_release
,
451 static int __init
pci_proc_init(void)
453 struct pci_dev
*dev
= NULL
;
454 proc_bus_pci_dir
= proc_mkdir("bus/pci", NULL
);
455 proc_create("devices", 0, proc_bus_pci_dir
,
456 &proc_bus_pci_dev_operations
);
457 proc_initialized
= 1;
458 for_each_pci_dev(dev
)
459 pci_proc_attach_device(dev
);
463 device_initcall(pci_proc_init
);