2 * Copyright (C) 2014-2017 Broadcom
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that
16 * supports the chipCommonA GPIO controller. Basic PINCONF such as bias,
17 * pull up/down, slew and drive strength are also supported in this driver.
19 * Pins from the chipCommonA GPIO can be individually muxed to GPIO function,
20 * through the interaction with the NSP IOMUX controller.
23 #include <linux/gpio/driver.h>
24 #include <linux/interrupt.h>
26 #include <linux/ioport.h>
27 #include <linux/kernel.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_irq.h>
31 #include <linux/pinctrl/pinconf.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/pinctrl/pinctrl.h>
34 #include <linux/slab.h>
36 #include "../pinctrl-utils.h"
38 #define NSP_CHIP_A_INT_STATUS 0x00
39 #define NSP_CHIP_A_INT_MASK 0x04
40 #define NSP_GPIO_DATA_IN 0x40
41 #define NSP_GPIO_DATA_OUT 0x44
42 #define NSP_GPIO_OUT_EN 0x48
43 #define NSP_GPIO_INT_POLARITY 0x50
44 #define NSP_GPIO_INT_MASK 0x54
45 #define NSP_GPIO_EVENT 0x58
46 #define NSP_GPIO_EVENT_INT_MASK 0x5c
47 #define NSP_GPIO_EVENT_INT_POLARITY 0x64
48 #define NSP_CHIP_A_GPIO_INT_BIT 0x01
50 /* I/O parameters offset for chipcommon A GPIO */
51 #define NSP_GPIO_DRV_CTRL 0x00
52 #define NSP_GPIO_HYSTERESIS_EN 0x10
53 #define NSP_GPIO_SLEW_RATE_EN 0x14
54 #define NSP_PULL_UP_EN 0x18
55 #define NSP_PULL_DOWN_EN 0x1c
56 #define GPIO_DRV_STRENGTH_BITS 0x03
61 * @dev: pointer to device
62 * @base: I/O register base for nsp GPIO controller
63 * @io_ctrl: I/O register base for PINCONF support outside the GPIO block
65 * @pctl: pointer to pinctrl_dev
66 * @pctldesc: pinctrl descriptor
67 * @irq_domain: pointer to irq domain
68 * @lock: lock to protect access to I/O registers
73 void __iomem
*io_ctrl
;
75 struct pinctrl_dev
*pctl
;
76 struct pinctrl_desc pctldesc
;
77 struct irq_domain
*irq_domain
;
87 * Mapping from PINCONF pins to GPIO pins is 1-to-1
89 static inline unsigned nsp_pin_to_gpio(unsigned pin
)
95 * nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
98 * @nsp_gpio: nsp GPIO device
99 * @base_type: reg base to modify
100 * @reg: register offset
104 static inline void nsp_set_bit(struct nsp_gpio
*chip
, enum base_type address
,
105 unsigned int reg
, unsigned gpio
, bool set
)
108 void __iomem
*base_address
;
110 if (address
== IO_CTRL
)
111 base_address
= chip
->io_ctrl
;
113 base_address
= chip
->base
;
115 val
= readl(base_address
+ reg
);
121 writel(val
, base_address
+ reg
);
125 * nsp_get_bit - get one bit (corresponding to the GPIO pin) in a
128 static inline bool nsp_get_bit(struct nsp_gpio
*chip
, enum base_type address
,
129 unsigned int reg
, unsigned gpio
)
131 if (address
== IO_CTRL
)
132 return !!(readl(chip
->io_ctrl
+ reg
) & BIT(gpio
));
134 return !!(readl(chip
->base
+ reg
) & BIT(gpio
));
137 static irqreturn_t
nsp_gpio_irq_handler(int irq
, void *data
)
139 struct nsp_gpio
*chip
= (struct nsp_gpio
*)data
;
140 struct gpio_chip gc
= chip
->gc
;
142 unsigned long int_bits
= 0;
145 /* go through the entire GPIOs and handle all interrupts */
146 int_status
= readl(chip
->base
+ NSP_CHIP_A_INT_STATUS
);
147 if (int_status
& NSP_CHIP_A_GPIO_INT_BIT
) {
148 unsigned int event
, level
;
150 /* Get level and edge interrupts */
151 event
= readl(chip
->base
+ NSP_GPIO_EVENT_INT_MASK
) &
152 readl(chip
->base
+ NSP_GPIO_EVENT
);
153 level
= readl(chip
->base
+ NSP_GPIO_DATA_IN
) ^
154 readl(chip
->base
+ NSP_GPIO_INT_POLARITY
);
155 level
&= readl(chip
->base
+ NSP_GPIO_INT_MASK
);
156 int_bits
= level
| event
;
158 for_each_set_bit(bit
, &int_bits
, gc
.ngpio
) {
160 * Clear the interrupt before invoking the
161 * handler, so we do not leave any window
163 writel(BIT(bit
), chip
->base
+ NSP_GPIO_EVENT
);
165 irq_linear_revmap(chip
->irq_domain
, bit
));
169 return int_bits
? IRQ_HANDLED
: IRQ_NONE
;
172 static void nsp_gpio_irq_ack(struct irq_data
*d
)
174 struct nsp_gpio
*chip
= irq_data_get_irq_chip_data(d
);
175 unsigned gpio
= d
->hwirq
;
179 trigger_type
= irq_get_trigger_type(d
->irq
);
180 if (trigger_type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
181 nsp_set_bit(chip
, REG
, NSP_GPIO_EVENT
, gpio
, val
);
185 * nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt
188 * @unmask: mask/unmask GPIO interrupt
190 static void nsp_gpio_irq_set_mask(struct irq_data
*d
, bool unmask
)
192 struct nsp_gpio
*chip
= irq_data_get_irq_chip_data(d
);
193 unsigned gpio
= d
->hwirq
;
196 trigger_type
= irq_get_trigger_type(d
->irq
);
197 if (trigger_type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
198 nsp_set_bit(chip
, REG
, NSP_GPIO_EVENT_INT_MASK
, gpio
, unmask
);
200 nsp_set_bit(chip
, REG
, NSP_GPIO_INT_MASK
, gpio
, unmask
);
203 static void nsp_gpio_irq_mask(struct irq_data
*d
)
205 struct nsp_gpio
*chip
= irq_data_get_irq_chip_data(d
);
208 raw_spin_lock_irqsave(&chip
->lock
, flags
);
209 nsp_gpio_irq_set_mask(d
, false);
210 raw_spin_unlock_irqrestore(&chip
->lock
, flags
);
213 static void nsp_gpio_irq_unmask(struct irq_data
*d
)
215 struct nsp_gpio
*chip
= irq_data_get_irq_chip_data(d
);
218 raw_spin_lock_irqsave(&chip
->lock
, flags
);
219 nsp_gpio_irq_set_mask(d
, true);
220 raw_spin_unlock_irqrestore(&chip
->lock
, flags
);
223 static int nsp_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
225 struct nsp_gpio
*chip
= irq_data_get_irq_chip_data(d
);
226 unsigned gpio
= d
->hwirq
;
231 raw_spin_lock_irqsave(&chip
->lock
, flags
);
232 falling
= nsp_get_bit(chip
, REG
, NSP_GPIO_EVENT_INT_POLARITY
, gpio
);
233 level_low
= nsp_get_bit(chip
, REG
, NSP_GPIO_INT_POLARITY
, gpio
);
235 switch (type
& IRQ_TYPE_SENSE_MASK
) {
236 case IRQ_TYPE_EDGE_RISING
:
240 case IRQ_TYPE_EDGE_FALLING
:
244 case IRQ_TYPE_LEVEL_HIGH
:
248 case IRQ_TYPE_LEVEL_LOW
:
253 dev_err(chip
->dev
, "invalid GPIO IRQ type 0x%x\n",
255 raw_spin_unlock_irqrestore(&chip
->lock
, flags
);
259 nsp_set_bit(chip
, REG
, NSP_GPIO_EVENT_INT_POLARITY
, gpio
, falling
);
260 nsp_set_bit(chip
, REG
, NSP_GPIO_INT_POLARITY
, gpio
, level_low
);
261 raw_spin_unlock_irqrestore(&chip
->lock
, flags
);
263 dev_dbg(chip
->dev
, "gpio:%u level_low:%s falling:%s\n", gpio
,
264 level_low
? "true" : "false", falling
? "true" : "false");
268 static struct irq_chip nsp_gpio_irq_chip
= {
270 .irq_enable
= nsp_gpio_irq_unmask
,
271 .irq_disable
= nsp_gpio_irq_mask
,
272 .irq_ack
= nsp_gpio_irq_ack
,
273 .irq_mask
= nsp_gpio_irq_mask
,
274 .irq_unmask
= nsp_gpio_irq_unmask
,
275 .irq_set_type
= nsp_gpio_irq_set_type
,
278 static int nsp_gpio_direction_input(struct gpio_chip
*gc
, unsigned gpio
)
280 struct nsp_gpio
*chip
= gpiochip_get_data(gc
);
283 raw_spin_lock_irqsave(&chip
->lock
, flags
);
284 nsp_set_bit(chip
, REG
, NSP_GPIO_OUT_EN
, gpio
, false);
285 raw_spin_unlock_irqrestore(&chip
->lock
, flags
);
287 dev_dbg(chip
->dev
, "gpio:%u set input\n", gpio
);
291 static int nsp_gpio_direction_output(struct gpio_chip
*gc
, unsigned gpio
,
294 struct nsp_gpio
*chip
= gpiochip_get_data(gc
);
297 raw_spin_lock_irqsave(&chip
->lock
, flags
);
298 nsp_set_bit(chip
, REG
, NSP_GPIO_OUT_EN
, gpio
, true);
299 nsp_set_bit(chip
, REG
, NSP_GPIO_DATA_OUT
, gpio
, !!(val
));
300 raw_spin_unlock_irqrestore(&chip
->lock
, flags
);
302 dev_dbg(chip
->dev
, "gpio:%u set output, value:%d\n", gpio
, val
);
306 static void nsp_gpio_set(struct gpio_chip
*gc
, unsigned gpio
, int val
)
308 struct nsp_gpio
*chip
= gpiochip_get_data(gc
);
311 raw_spin_lock_irqsave(&chip
->lock
, flags
);
312 nsp_set_bit(chip
, REG
, NSP_GPIO_DATA_OUT
, gpio
, !!(val
));
313 raw_spin_unlock_irqrestore(&chip
->lock
, flags
);
315 dev_dbg(chip
->dev
, "gpio:%u set, value:%d\n", gpio
, val
);
318 static int nsp_gpio_get(struct gpio_chip
*gc
, unsigned gpio
)
320 struct nsp_gpio
*chip
= gpiochip_get_data(gc
);
322 return !!(readl(chip
->base
+ NSP_GPIO_DATA_IN
) & BIT(gpio
));
325 static int nsp_gpio_to_irq(struct gpio_chip
*gc
, unsigned offset
)
327 struct nsp_gpio
*chip
= gpiochip_get_data(gc
);
329 return irq_linear_revmap(chip
->irq_domain
, offset
);
332 static int nsp_get_groups_count(struct pinctrl_dev
*pctldev
)
338 * Only one group: "gpio_grp", since this local pinctrl device only performs
339 * GPIO specific PINCONF configurations
341 static const char *nsp_get_group_name(struct pinctrl_dev
*pctldev
,
347 static const struct pinctrl_ops nsp_pctrl_ops
= {
348 .get_groups_count
= nsp_get_groups_count
,
349 .get_group_name
= nsp_get_group_name
,
350 .dt_node_to_map
= pinconf_generic_dt_node_to_map_pin
,
351 .dt_free_map
= pinctrl_utils_free_map
,
354 static int nsp_gpio_set_slew(struct nsp_gpio
*chip
, unsigned gpio
, u32 slew
)
357 nsp_set_bit(chip
, IO_CTRL
, NSP_GPIO_SLEW_RATE_EN
, gpio
, true);
359 nsp_set_bit(chip
, IO_CTRL
, NSP_GPIO_SLEW_RATE_EN
, gpio
, false);
364 static int nsp_gpio_set_pull(struct nsp_gpio
*chip
, unsigned gpio
,
365 bool pull_up
, bool pull_down
)
369 raw_spin_lock_irqsave(&chip
->lock
, flags
);
370 nsp_set_bit(chip
, IO_CTRL
, NSP_PULL_DOWN_EN
, gpio
, pull_down
);
371 nsp_set_bit(chip
, IO_CTRL
, NSP_PULL_UP_EN
, gpio
, pull_up
);
372 raw_spin_unlock_irqrestore(&chip
->lock
, flags
);
374 dev_dbg(chip
->dev
, "gpio:%u set pullup:%d pulldown: %d\n",
375 gpio
, pull_up
, pull_down
);
379 static void nsp_gpio_get_pull(struct nsp_gpio
*chip
, unsigned gpio
,
380 bool *pull_up
, bool *pull_down
)
384 raw_spin_lock_irqsave(&chip
->lock
, flags
);
385 *pull_up
= nsp_get_bit(chip
, IO_CTRL
, NSP_PULL_UP_EN
, gpio
);
386 *pull_down
= nsp_get_bit(chip
, IO_CTRL
, NSP_PULL_DOWN_EN
, gpio
);
387 raw_spin_unlock_irqrestore(&chip
->lock
, flags
);
390 static int nsp_gpio_set_strength(struct nsp_gpio
*chip
, unsigned gpio
,
393 u32 offset
, shift
, i
;
397 /* make sure drive strength is supported */
398 if (strength
< 2 || strength
> 16 || (strength
% 2))
402 offset
= NSP_GPIO_DRV_CTRL
;
403 dev_dbg(chip
->dev
, "gpio:%u set drive strength:%d mA\n", gpio
,
405 raw_spin_lock_irqsave(&chip
->lock
, flags
);
406 strength
= (strength
/ 2) - 1;
407 for (i
= GPIO_DRV_STRENGTH_BITS
; i
> 0; i
--) {
408 val
= readl(chip
->io_ctrl
+ offset
);
410 val
|= ((strength
>> (i
-1)) & 0x1) << shift
;
411 writel(val
, chip
->io_ctrl
+ offset
);
414 raw_spin_unlock_irqrestore(&chip
->lock
, flags
);
419 static int nsp_gpio_get_strength(struct nsp_gpio
*chip
, unsigned gpio
,
422 unsigned int offset
, shift
;
427 offset
= NSP_GPIO_DRV_CTRL
;
430 raw_spin_lock_irqsave(&chip
->lock
, flags
);
432 for (i
= (GPIO_DRV_STRENGTH_BITS
- 1); i
>= 0; i
--) {
433 val
= readl(chip
->io_ctrl
+ offset
) & BIT(shift
);
435 *strength
+= (val
<< i
);
440 *strength
= (*strength
+ 1) * 2;
441 raw_spin_unlock_irqrestore(&chip
->lock
, flags
);
446 static int nsp_pin_config_group_get(struct pinctrl_dev
*pctldev
,
448 unsigned long *config
)
453 static int nsp_pin_config_group_set(struct pinctrl_dev
*pctldev
,
455 unsigned long *configs
, unsigned num_configs
)
460 static int nsp_pin_config_get(struct pinctrl_dev
*pctldev
, unsigned pin
,
461 unsigned long *config
)
463 struct nsp_gpio
*chip
= pinctrl_dev_get_drvdata(pctldev
);
464 enum pin_config_param param
= pinconf_to_config_param(*config
);
467 bool pull_up
, pull_down
;
470 gpio
= nsp_pin_to_gpio(pin
);
472 case PIN_CONFIG_BIAS_DISABLE
:
473 nsp_gpio_get_pull(chip
, gpio
, &pull_up
, &pull_down
);
474 if ((pull_up
== false) && (pull_down
== false))
479 case PIN_CONFIG_BIAS_PULL_UP
:
480 nsp_gpio_get_pull(chip
, gpio
, &pull_up
, &pull_down
);
486 case PIN_CONFIG_BIAS_PULL_DOWN
:
487 nsp_gpio_get_pull(chip
, gpio
, &pull_up
, &pull_down
);
493 case PIN_CONFIG_DRIVE_STRENGTH
:
494 ret
= nsp_gpio_get_strength(chip
, gpio
, &arg
);
497 *config
= pinconf_to_config_packed(param
, arg
);
505 static int nsp_pin_config_set(struct pinctrl_dev
*pctldev
, unsigned pin
,
506 unsigned long *configs
, unsigned num_configs
)
508 struct nsp_gpio
*chip
= pinctrl_dev_get_drvdata(pctldev
);
509 enum pin_config_param param
;
511 unsigned int i
, gpio
;
514 gpio
= nsp_pin_to_gpio(pin
);
515 for (i
= 0; i
< num_configs
; i
++) {
516 param
= pinconf_to_config_param(configs
[i
]);
517 arg
= pinconf_to_config_argument(configs
[i
]);
520 case PIN_CONFIG_BIAS_DISABLE
:
521 ret
= nsp_gpio_set_pull(chip
, gpio
, false, false);
526 case PIN_CONFIG_BIAS_PULL_UP
:
527 ret
= nsp_gpio_set_pull(chip
, gpio
, true, false);
532 case PIN_CONFIG_BIAS_PULL_DOWN
:
533 ret
= nsp_gpio_set_pull(chip
, gpio
, false, true);
538 case PIN_CONFIG_DRIVE_STRENGTH
:
539 ret
= nsp_gpio_set_strength(chip
, gpio
, arg
);
544 case PIN_CONFIG_SLEW_RATE
:
545 ret
= nsp_gpio_set_slew(chip
, gpio
, arg
);
551 dev_err(chip
->dev
, "invalid configuration\n");
560 static const struct pinconf_ops nsp_pconf_ops
= {
562 .pin_config_get
= nsp_pin_config_get
,
563 .pin_config_set
= nsp_pin_config_set
,
564 .pin_config_group_get
= nsp_pin_config_group_get
,
565 .pin_config_group_set
= nsp_pin_config_group_set
,
569 * NSP GPIO controller supports some PINCONF related configurations such as
570 * pull up, pull down, slew and drive strength, when the pin is configured
573 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
576 static int nsp_gpio_register_pinconf(struct nsp_gpio
*chip
)
578 struct pinctrl_desc
*pctldesc
= &chip
->pctldesc
;
579 struct pinctrl_pin_desc
*pins
;
580 struct gpio_chip
*gc
= &chip
->gc
;
583 pins
= devm_kcalloc(chip
->dev
, gc
->ngpio
, sizeof(*pins
), GFP_KERNEL
);
586 for (i
= 0; i
< gc
->ngpio
; i
++) {
588 pins
[i
].name
= devm_kasprintf(chip
->dev
, GFP_KERNEL
,
593 pctldesc
->name
= dev_name(chip
->dev
);
594 pctldesc
->pctlops
= &nsp_pctrl_ops
;
595 pctldesc
->pins
= pins
;
596 pctldesc
->npins
= gc
->ngpio
;
597 pctldesc
->confops
= &nsp_pconf_ops
;
599 chip
->pctl
= devm_pinctrl_register(chip
->dev
, pctldesc
, chip
);
600 if (IS_ERR(chip
->pctl
)) {
601 dev_err(chip
->dev
, "unable to register pinctrl device\n");
602 return PTR_ERR(chip
->pctl
);
608 static const struct of_device_id nsp_gpio_of_match
[] = {
609 {.compatible
= "brcm,nsp-gpio-a",},
613 static int nsp_gpio_probe(struct platform_device
*pdev
)
615 struct device
*dev
= &pdev
->dev
;
616 struct resource
*res
;
617 struct nsp_gpio
*chip
;
618 struct gpio_chip
*gc
;
622 if (of_property_read_u32(pdev
->dev
.of_node
, "ngpios", &val
)) {
623 dev_err(&pdev
->dev
, "Missing ngpios OF property\n");
627 chip
= devm_kzalloc(dev
, sizeof(*chip
), GFP_KERNEL
);
632 platform_set_drvdata(pdev
, chip
);
634 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
635 chip
->base
= devm_ioremap_resource(dev
, res
);
636 if (IS_ERR(chip
->base
)) {
637 dev_err(dev
, "unable to map I/O memory\n");
638 return PTR_ERR(chip
->base
);
641 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
642 chip
->io_ctrl
= devm_ioremap_resource(dev
, res
);
643 if (IS_ERR(chip
->io_ctrl
)) {
644 dev_err(dev
, "unable to map I/O memory\n");
645 return PTR_ERR(chip
->io_ctrl
);
648 raw_spin_lock_init(&chip
->lock
);
651 gc
->can_sleep
= false;
653 gc
->label
= dev_name(dev
);
655 gc
->of_node
= dev
->of_node
;
656 gc
->request
= gpiochip_generic_request
;
657 gc
->free
= gpiochip_generic_free
;
658 gc
->direction_input
= nsp_gpio_direction_input
;
659 gc
->direction_output
= nsp_gpio_direction_output
;
660 gc
->set
= nsp_gpio_set
;
661 gc
->get
= nsp_gpio_get
;
662 gc
->to_irq
= nsp_gpio_to_irq
;
664 /* optional GPIO interrupt support */
665 irq
= platform_get_irq(pdev
, 0);
667 /* Create irq domain so that each pin can be assigned an IRQ.*/
668 chip
->irq_domain
= irq_domain_add_linear(gc
->of_node
, gc
->ngpio
,
669 &irq_domain_simple_ops
,
671 if (!chip
->irq_domain
) {
672 dev_err(&pdev
->dev
, "Couldn't allocate IRQ domain\n");
676 /* Map each gpio to an IRQ and set the handler for gpiolib. */
677 for (count
= 0; count
< gc
->ngpio
; count
++) {
678 int irq
= irq_create_mapping(chip
->irq_domain
, count
);
680 irq_set_chip_and_handler(irq
, &nsp_gpio_irq_chip
,
682 irq_set_chip_data(irq
, chip
);
685 /* Install ISR for this GPIO controller. */
686 ret
= devm_request_irq(&pdev
->dev
, irq
, nsp_gpio_irq_handler
,
687 IRQF_SHARED
, "gpio-a", chip
);
689 dev_err(&pdev
->dev
, "Unable to request IRQ%d: %d\n",
691 goto err_rm_gpiochip
;
694 val
= readl(chip
->base
+ NSP_CHIP_A_INT_MASK
);
695 val
= val
| NSP_CHIP_A_GPIO_INT_BIT
;
696 writel(val
, (chip
->base
+ NSP_CHIP_A_INT_MASK
));
699 ret
= gpiochip_add_data(gc
, chip
);
701 dev_err(dev
, "unable to add GPIO chip\n");
705 ret
= nsp_gpio_register_pinconf(chip
);
707 dev_err(dev
, "unable to register pinconf\n");
708 goto err_rm_gpiochip
;
719 static struct platform_driver nsp_gpio_driver
= {
721 .name
= "nsp-gpio-a",
722 .of_match_table
= nsp_gpio_of_match
,
724 .probe
= nsp_gpio_probe
,
727 static int __init
nsp_gpio_init(void)
729 return platform_driver_register(&nsp_gpio_driver
);
731 arch_initcall_sync(nsp_gpio_init
);