2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/gpio/driver.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30 #include <linux/bitops.h>
31 #include <linux/regmap.h>
32 #include <linux/mfd/syscon.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
36 #include <dt-bindings/pinctrl/mt65xx.h>
39 #include "../pinconf.h"
40 #include "../pinctrl-utils.h"
41 #include "pinctrl-mtk-common.h"
43 #define MAX_GPIO_MODE_PER_REG 5
44 #define GPIO_MODE_BITS 3
45 #define GPIO_MODE_PREFIX "GPIO"
47 static const char * const mtk_gpio_functions
[] = {
48 "func0", "func1", "func2", "func3",
49 "func4", "func5", "func6", "func7",
50 "func8", "func9", "func10", "func11",
51 "func12", "func13", "func14", "func15",
55 * There are two base address for pull related configuration
56 * in mt8135, and different GPIO pins use different base address.
57 * When pin number greater than type1_start and less than type1_end,
58 * should use the second base address.
60 static struct regmap
*mtk_get_regmap(struct mtk_pinctrl
*pctl
,
63 if (pin
>= pctl
->devdata
->type1_start
&& pin
< pctl
->devdata
->type1_end
)
68 static unsigned int mtk_get_port(struct mtk_pinctrl
*pctl
, unsigned long pin
)
70 /* Different SoC has different mask and port shift. */
71 return ((pin
>> 4) & pctl
->devdata
->port_mask
)
72 << pctl
->devdata
->port_shf
;
75 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev
,
76 struct pinctrl_gpio_range
*range
, unsigned offset
,
79 unsigned int reg_addr
;
81 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
83 reg_addr
= mtk_get_port(pctl
, offset
) + pctl
->devdata
->dir_offset
;
84 bit
= BIT(offset
& 0xf);
86 if (pctl
->devdata
->spec_dir_set
)
87 pctl
->devdata
->spec_dir_set(®_addr
, offset
);
90 /* Different SoC has different alignment offset. */
91 reg_addr
= CLR_ADDR(reg_addr
, pctl
);
93 reg_addr
= SET_ADDR(reg_addr
, pctl
);
95 regmap_write(mtk_get_regmap(pctl
, offset
), reg_addr
, bit
);
99 static void mtk_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
101 unsigned int reg_addr
;
103 struct mtk_pinctrl
*pctl
= gpiochip_get_data(chip
);
105 reg_addr
= mtk_get_port(pctl
, offset
) + pctl
->devdata
->dout_offset
;
106 bit
= BIT(offset
& 0xf);
109 reg_addr
= SET_ADDR(reg_addr
, pctl
);
111 reg_addr
= CLR_ADDR(reg_addr
, pctl
);
113 regmap_write(mtk_get_regmap(pctl
, offset
), reg_addr
, bit
);
116 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl
*pctl
, unsigned pin
,
117 int value
, enum pin_config_param arg
)
119 unsigned int reg_addr
, offset
;
123 * Due to some soc are not support ies/smt config, add this special
124 * control to handle it.
126 if (!pctl
->devdata
->spec_ies_smt_set
&&
127 pctl
->devdata
->ies_offset
== MTK_PINCTRL_NOT_SUPPORT
&&
128 arg
== PIN_CONFIG_INPUT_ENABLE
)
131 if (!pctl
->devdata
->spec_ies_smt_set
&&
132 pctl
->devdata
->smt_offset
== MTK_PINCTRL_NOT_SUPPORT
&&
133 arg
== PIN_CONFIG_INPUT_SCHMITT_ENABLE
)
137 * Due to some pins are irregular, their input enable and smt
138 * control register are discontinuous, so we need this special handle.
140 if (pctl
->devdata
->spec_ies_smt_set
) {
141 return pctl
->devdata
->spec_ies_smt_set(mtk_get_regmap(pctl
, pin
),
142 pin
, pctl
->devdata
->port_align
, value
, arg
);
145 bit
= BIT(pin
& 0xf);
147 if (arg
== PIN_CONFIG_INPUT_ENABLE
)
148 offset
= pctl
->devdata
->ies_offset
;
150 offset
= pctl
->devdata
->smt_offset
;
153 reg_addr
= SET_ADDR(mtk_get_port(pctl
, pin
) + offset
, pctl
);
155 reg_addr
= CLR_ADDR(mtk_get_port(pctl
, pin
) + offset
, pctl
);
157 regmap_write(mtk_get_regmap(pctl
, pin
), reg_addr
, bit
);
161 int mtk_pconf_spec_set_ies_smt_range(struct regmap
*regmap
,
162 const struct mtk_pin_ies_smt_set
*ies_smt_infos
, unsigned int info_num
,
163 unsigned int pin
, unsigned char align
, int value
)
165 unsigned int i
, reg_addr
, bit
;
167 for (i
= 0; i
< info_num
; i
++) {
168 if (pin
>= ies_smt_infos
[i
].start
&&
169 pin
<= ies_smt_infos
[i
].end
) {
178 reg_addr
= ies_smt_infos
[i
].offset
+ align
;
180 reg_addr
= ies_smt_infos
[i
].offset
+ (align
<< 1);
182 bit
= BIT(ies_smt_infos
[i
].bit
);
183 regmap_write(regmap
, reg_addr
, bit
);
187 static const struct mtk_pin_drv_grp
*mtk_find_pin_drv_grp_by_pin(
188 struct mtk_pinctrl
*pctl
, unsigned long pin
) {
191 for (i
= 0; i
< pctl
->devdata
->n_pin_drv_grps
; i
++) {
192 const struct mtk_pin_drv_grp
*pin_drv
=
193 pctl
->devdata
->pin_drv_grp
+ i
;
194 if (pin
== pin_drv
->pin
)
201 static int mtk_pconf_set_driving(struct mtk_pinctrl
*pctl
,
202 unsigned int pin
, unsigned char driving
)
204 const struct mtk_pin_drv_grp
*pin_drv
;
206 unsigned int bits
, mask
, shift
;
207 const struct mtk_drv_group_desc
*drv_grp
;
209 if (pin
>= pctl
->devdata
->npins
)
212 pin_drv
= mtk_find_pin_drv_grp_by_pin(pctl
, pin
);
213 if (!pin_drv
|| pin_drv
->grp
> pctl
->devdata
->n_grp_cls
)
216 drv_grp
= pctl
->devdata
->grp_desc
+ pin_drv
->grp
;
217 if (driving
>= drv_grp
->min_drv
&& driving
<= drv_grp
->max_drv
218 && !(driving
% drv_grp
->step
)) {
219 val
= driving
/ drv_grp
->step
- 1;
220 bits
= drv_grp
->high_bit
- drv_grp
->low_bit
+ 1;
221 mask
= BIT(bits
) - 1;
222 shift
= pin_drv
->bit
+ drv_grp
->low_bit
;
225 return regmap_update_bits(mtk_get_regmap(pctl
, pin
),
226 pin_drv
->offset
, mask
, val
);
232 int mtk_pctrl_spec_pull_set_samereg(struct regmap
*regmap
,
233 const struct mtk_pin_spec_pupd_set_samereg
*pupd_infos
,
234 unsigned int info_num
, unsigned int pin
,
235 unsigned char align
, bool isup
, unsigned int r1r0
)
238 unsigned int reg_pupd
, reg_set
, reg_rst
;
239 unsigned int bit_pupd
, bit_r0
, bit_r1
;
240 const struct mtk_pin_spec_pupd_set_samereg
*spec_pupd_pin
;
243 for (i
= 0; i
< info_num
; i
++) {
244 if (pin
== pupd_infos
[i
].pin
) {
253 spec_pupd_pin
= pupd_infos
+ i
;
254 reg_set
= spec_pupd_pin
->offset
+ align
;
255 reg_rst
= spec_pupd_pin
->offset
+ (align
<< 1);
262 bit_pupd
= BIT(spec_pupd_pin
->pupd_bit
);
263 regmap_write(regmap
, reg_pupd
, bit_pupd
);
265 bit_r0
= BIT(spec_pupd_pin
->r0_bit
);
266 bit_r1
= BIT(spec_pupd_pin
->r1_bit
);
269 case MTK_PUPD_SET_R1R0_00
:
270 regmap_write(regmap
, reg_rst
, bit_r0
);
271 regmap_write(regmap
, reg_rst
, bit_r1
);
273 case MTK_PUPD_SET_R1R0_01
:
274 regmap_write(regmap
, reg_set
, bit_r0
);
275 regmap_write(regmap
, reg_rst
, bit_r1
);
277 case MTK_PUPD_SET_R1R0_10
:
278 regmap_write(regmap
, reg_rst
, bit_r0
);
279 regmap_write(regmap
, reg_set
, bit_r1
);
281 case MTK_PUPD_SET_R1R0_11
:
282 regmap_write(regmap
, reg_set
, bit_r0
);
283 regmap_write(regmap
, reg_set
, bit_r1
);
292 static int mtk_pconf_set_pull_select(struct mtk_pinctrl
*pctl
,
293 unsigned int pin
, bool enable
, bool isup
, unsigned int arg
)
296 unsigned int reg_pullen
, reg_pullsel
;
299 /* Some pins' pull setting are very different,
300 * they have separate pull up/down bit, R0 and R1
301 * resistor bit, so we need this special handle.
303 if (pctl
->devdata
->spec_pull_set
) {
304 ret
= pctl
->devdata
->spec_pull_set(mtk_get_regmap(pctl
, pin
),
305 pin
, pctl
->devdata
->port_align
, isup
, arg
);
310 /* For generic pull config, default arg value should be 0 or 1. */
311 if (arg
!= 0 && arg
!= 1) {
312 dev_err(pctl
->dev
, "invalid pull-up argument %d on pin %d .\n",
317 bit
= BIT(pin
& 0xf);
319 reg_pullen
= SET_ADDR(mtk_get_port(pctl
, pin
) +
320 pctl
->devdata
->pullen_offset
, pctl
);
322 reg_pullen
= CLR_ADDR(mtk_get_port(pctl
, pin
) +
323 pctl
->devdata
->pullen_offset
, pctl
);
326 reg_pullsel
= SET_ADDR(mtk_get_port(pctl
, pin
) +
327 pctl
->devdata
->pullsel_offset
, pctl
);
329 reg_pullsel
= CLR_ADDR(mtk_get_port(pctl
, pin
) +
330 pctl
->devdata
->pullsel_offset
, pctl
);
332 regmap_write(mtk_get_regmap(pctl
, pin
), reg_pullen
, bit
);
333 regmap_write(mtk_get_regmap(pctl
, pin
), reg_pullsel
, bit
);
337 static int mtk_pconf_parse_conf(struct pinctrl_dev
*pctldev
,
338 unsigned int pin
, enum pin_config_param param
,
339 enum pin_config_param arg
)
342 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
345 case PIN_CONFIG_BIAS_DISABLE
:
346 ret
= mtk_pconf_set_pull_select(pctl
, pin
, false, false, arg
);
348 case PIN_CONFIG_BIAS_PULL_UP
:
349 ret
= mtk_pconf_set_pull_select(pctl
, pin
, true, true, arg
);
351 case PIN_CONFIG_BIAS_PULL_DOWN
:
352 ret
= mtk_pconf_set_pull_select(pctl
, pin
, true, false, arg
);
354 case PIN_CONFIG_INPUT_ENABLE
:
355 mtk_pmx_gpio_set_direction(pctldev
, NULL
, pin
, true);
356 ret
= mtk_pconf_set_ies_smt(pctl
, pin
, arg
, param
);
358 case PIN_CONFIG_OUTPUT
:
359 mtk_gpio_set(pctl
->chip
, pin
, arg
);
360 ret
= mtk_pmx_gpio_set_direction(pctldev
, NULL
, pin
, false);
362 case PIN_CONFIG_INPUT_SCHMITT_ENABLE
:
363 mtk_pmx_gpio_set_direction(pctldev
, NULL
, pin
, true);
364 ret
= mtk_pconf_set_ies_smt(pctl
, pin
, arg
, param
);
366 case PIN_CONFIG_DRIVE_STRENGTH
:
367 ret
= mtk_pconf_set_driving(pctl
, pin
, arg
);
376 static int mtk_pconf_group_get(struct pinctrl_dev
*pctldev
,
378 unsigned long *config
)
380 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
382 *config
= pctl
->groups
[group
].config
;
387 static int mtk_pconf_group_set(struct pinctrl_dev
*pctldev
, unsigned group
,
388 unsigned long *configs
, unsigned num_configs
)
390 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
391 struct mtk_pinctrl_group
*g
= &pctl
->groups
[group
];
394 for (i
= 0; i
< num_configs
; i
++) {
395 ret
= mtk_pconf_parse_conf(pctldev
, g
->pin
,
396 pinconf_to_config_param(configs
[i
]),
397 pinconf_to_config_argument(configs
[i
]));
401 g
->config
= configs
[i
];
407 static const struct pinconf_ops mtk_pconf_ops
= {
408 .pin_config_group_get
= mtk_pconf_group_get
,
409 .pin_config_group_set
= mtk_pconf_group_set
,
412 static struct mtk_pinctrl_group
*
413 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl
*pctl
, u32 pin
)
417 for (i
= 0; i
< pctl
->ngroups
; i
++) {
418 struct mtk_pinctrl_group
*grp
= pctl
->groups
+ i
;
427 static const struct mtk_desc_function
*mtk_pctrl_find_function_by_pin(
428 struct mtk_pinctrl
*pctl
, u32 pin_num
, u32 fnum
)
430 const struct mtk_desc_pin
*pin
= pctl
->devdata
->pins
+ pin_num
;
431 const struct mtk_desc_function
*func
= pin
->functions
;
433 while (func
&& func
->name
) {
434 if (func
->muxval
== fnum
)
442 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl
*pctl
,
443 u32 pin_num
, u32 fnum
)
447 for (i
= 0; i
< pctl
->devdata
->npins
; i
++) {
448 const struct mtk_desc_pin
*pin
= pctl
->devdata
->pins
+ i
;
450 if (pin
->pin
.number
== pin_num
) {
451 const struct mtk_desc_function
*func
=
454 while (func
&& func
->name
) {
455 if (func
->muxval
== fnum
)
467 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl
*pctl
,
468 u32 pin
, u32 fnum
, struct mtk_pinctrl_group
*grp
,
469 struct pinctrl_map
**map
, unsigned *reserved_maps
,
474 if (*num_maps
== *reserved_maps
)
477 (*map
)[*num_maps
].type
= PIN_MAP_TYPE_MUX_GROUP
;
478 (*map
)[*num_maps
].data
.mux
.group
= grp
->name
;
480 ret
= mtk_pctrl_is_function_valid(pctl
, pin
, fnum
);
482 dev_err(pctl
->dev
, "invalid function %d on pin %d .\n",
487 (*map
)[*num_maps
].data
.mux
.function
= mtk_gpio_functions
[fnum
];
493 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev
*pctldev
,
494 struct device_node
*node
,
495 struct pinctrl_map
**map
,
496 unsigned *reserved_maps
,
499 struct property
*pins
;
500 u32 pinfunc
, pin
, func
;
501 int num_pins
, num_funcs
, maps_per_pin
;
502 unsigned long *configs
;
503 unsigned int num_configs
;
506 unsigned reserve
= 0;
507 struct mtk_pinctrl_group
*grp
;
508 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
510 pins
= of_find_property(node
, "pinmux", NULL
);
512 dev_err(pctl
->dev
, "missing pins property in node %s .\n",
517 err
= pinconf_generic_parse_dt_config(node
, pctldev
, &configs
,
525 num_pins
= pins
->length
/ sizeof(u32
);
526 num_funcs
= num_pins
;
530 if (has_config
&& num_pins
>= 1)
533 if (!num_pins
|| !maps_per_pin
) {
538 reserve
= num_pins
* maps_per_pin
;
540 err
= pinctrl_utils_reserve_map(pctldev
, map
,
541 reserved_maps
, num_maps
, reserve
);
545 for (i
= 0; i
< num_pins
; i
++) {
546 err
= of_property_read_u32_index(node
, "pinmux",
551 pin
= MTK_GET_PIN_NO(pinfunc
);
552 func
= MTK_GET_PIN_FUNC(pinfunc
);
554 if (pin
>= pctl
->devdata
->npins
||
555 func
>= ARRAY_SIZE(mtk_gpio_functions
)) {
556 dev_err(pctl
->dev
, "invalid pins value.\n");
561 grp
= mtk_pctrl_find_group_by_pin(pctl
, pin
);
563 dev_err(pctl
->dev
, "unable to match pin %d to group\n",
569 err
= mtk_pctrl_dt_node_to_map_func(pctl
, pin
, func
, grp
, map
,
570 reserved_maps
, num_maps
);
575 err
= pinctrl_utils_add_map_configs(pctldev
, map
,
576 reserved_maps
, num_maps
, grp
->name
,
577 configs
, num_configs
,
578 PIN_MAP_TYPE_CONFIGS_GROUP
);
591 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev
*pctldev
,
592 struct device_node
*np_config
,
593 struct pinctrl_map
**map
, unsigned *num_maps
)
595 struct device_node
*np
;
596 unsigned reserved_maps
;
603 for_each_child_of_node(np_config
, np
) {
604 ret
= mtk_pctrl_dt_subnode_to_map(pctldev
, np
, map
,
605 &reserved_maps
, num_maps
);
607 pinctrl_utils_free_map(pctldev
, *map
, *num_maps
);
616 static int mtk_pctrl_get_groups_count(struct pinctrl_dev
*pctldev
)
618 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
620 return pctl
->ngroups
;
623 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev
*pctldev
,
626 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
628 return pctl
->groups
[group
].name
;
631 static int mtk_pctrl_get_group_pins(struct pinctrl_dev
*pctldev
,
633 const unsigned **pins
,
636 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
638 *pins
= (unsigned *)&pctl
->groups
[group
].pin
;
644 static const struct pinctrl_ops mtk_pctrl_ops
= {
645 .dt_node_to_map
= mtk_pctrl_dt_node_to_map
,
646 .dt_free_map
= pinctrl_utils_free_map
,
647 .get_groups_count
= mtk_pctrl_get_groups_count
,
648 .get_group_name
= mtk_pctrl_get_group_name
,
649 .get_group_pins
= mtk_pctrl_get_group_pins
,
652 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev
*pctldev
)
654 return ARRAY_SIZE(mtk_gpio_functions
);
657 static const char *mtk_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
660 return mtk_gpio_functions
[selector
];
663 static int mtk_pmx_get_func_groups(struct pinctrl_dev
*pctldev
,
665 const char * const **groups
,
666 unsigned * const num_groups
)
668 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
670 *groups
= pctl
->grp_names
;
671 *num_groups
= pctl
->ngroups
;
676 static int mtk_pmx_set_mode(struct pinctrl_dev
*pctldev
,
677 unsigned long pin
, unsigned long mode
)
679 unsigned int reg_addr
;
682 unsigned int mask
= (1L << GPIO_MODE_BITS
) - 1;
683 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
685 if (pctl
->devdata
->spec_pinmux_set
)
686 pctl
->devdata
->spec_pinmux_set(mtk_get_regmap(pctl
, pin
),
689 reg_addr
= ((pin
/ MAX_GPIO_MODE_PER_REG
) << pctl
->devdata
->port_shf
)
690 + pctl
->devdata
->pinmux_offset
;
693 bit
= pin
% MAX_GPIO_MODE_PER_REG
;
694 mask
<<= (GPIO_MODE_BITS
* bit
);
695 val
= (mode
<< (GPIO_MODE_BITS
* bit
));
696 return regmap_update_bits(mtk_get_regmap(pctl
, pin
),
697 reg_addr
, mask
, val
);
700 static const struct mtk_desc_pin
*
701 mtk_find_pin_by_eint_num(struct mtk_pinctrl
*pctl
, unsigned int eint_num
)
704 const struct mtk_desc_pin
*pin
;
706 for (i
= 0; i
< pctl
->devdata
->npins
; i
++) {
707 pin
= pctl
->devdata
->pins
+ i
;
708 if (pin
->eint
.eintnum
== eint_num
)
715 static int mtk_pmx_set_mux(struct pinctrl_dev
*pctldev
,
720 const struct mtk_desc_function
*desc
;
721 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
722 struct mtk_pinctrl_group
*g
= pctl
->groups
+ group
;
724 ret
= mtk_pctrl_is_function_valid(pctl
, g
->pin
, function
);
726 dev_err(pctl
->dev
, "invalid function %d on group %d .\n",
731 desc
= mtk_pctrl_find_function_by_pin(pctl
, g
->pin
, function
);
734 mtk_pmx_set_mode(pctldev
, g
->pin
, desc
->muxval
);
738 static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl
*pctl
,
741 const struct mtk_desc_pin
*pin
= pctl
->devdata
->pins
+ offset
;
742 const struct mtk_desc_function
*func
= pin
->functions
;
744 while (func
&& func
->name
) {
745 if (!strncmp(func
->name
, GPIO_MODE_PREFIX
,
746 sizeof(GPIO_MODE_PREFIX
)-1))
753 static int mtk_pmx_gpio_request_enable(struct pinctrl_dev
*pctldev
,
754 struct pinctrl_gpio_range
*range
,
758 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
760 muxval
= mtk_pmx_find_gpio_mode(pctl
, offset
);
763 dev_err(pctl
->dev
, "invalid gpio pin %d.\n", offset
);
767 mtk_pmx_set_mode(pctldev
, offset
, muxval
);
768 mtk_pconf_set_ies_smt(pctl
, offset
, 1, PIN_CONFIG_INPUT_ENABLE
);
773 static const struct pinmux_ops mtk_pmx_ops
= {
774 .get_functions_count
= mtk_pmx_get_funcs_cnt
,
775 .get_function_name
= mtk_pmx_get_func_name
,
776 .get_function_groups
= mtk_pmx_get_func_groups
,
777 .set_mux
= mtk_pmx_set_mux
,
778 .gpio_set_direction
= mtk_pmx_gpio_set_direction
,
779 .gpio_request_enable
= mtk_pmx_gpio_request_enable
,
782 static int mtk_gpio_direction_input(struct gpio_chip
*chip
,
785 return pinctrl_gpio_direction_input(chip
->base
+ offset
);
788 static int mtk_gpio_direction_output(struct gpio_chip
*chip
,
789 unsigned offset
, int value
)
791 mtk_gpio_set(chip
, offset
, value
);
792 return pinctrl_gpio_direction_output(chip
->base
+ offset
);
795 static int mtk_gpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
797 unsigned int reg_addr
;
799 unsigned int read_val
= 0;
801 struct mtk_pinctrl
*pctl
= gpiochip_get_data(chip
);
803 reg_addr
= mtk_get_port(pctl
, offset
) + pctl
->devdata
->dir_offset
;
804 bit
= BIT(offset
& 0xf);
806 if (pctl
->devdata
->spec_dir_set
)
807 pctl
->devdata
->spec_dir_set(®_addr
, offset
);
809 regmap_read(pctl
->regmap1
, reg_addr
, &read_val
);
810 return !(read_val
& bit
);
813 static int mtk_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
815 unsigned int reg_addr
;
817 unsigned int read_val
= 0;
818 struct mtk_pinctrl
*pctl
= gpiochip_get_data(chip
);
820 reg_addr
= mtk_get_port(pctl
, offset
) +
821 pctl
->devdata
->din_offset
;
823 bit
= BIT(offset
& 0xf);
824 regmap_read(pctl
->regmap1
, reg_addr
, &read_val
);
825 return !!(read_val
& bit
);
828 static int mtk_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
830 const struct mtk_desc_pin
*pin
;
831 struct mtk_pinctrl
*pctl
= gpiochip_get_data(chip
);
834 pin
= pctl
->devdata
->pins
+ offset
;
835 if (pin
->eint
.eintnum
== NO_EINT_SUPPORT
)
838 irq
= irq_find_mapping(pctl
->domain
, pin
->eint
.eintnum
);
845 static int mtk_pinctrl_irq_request_resources(struct irq_data
*d
)
847 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
848 const struct mtk_desc_pin
*pin
;
851 pin
= mtk_find_pin_by_eint_num(pctl
, d
->hwirq
);
854 dev_err(pctl
->dev
, "Can not find pin\n");
858 ret
= gpiochip_lock_as_irq(pctl
->chip
, pin
->pin
.number
);
860 dev_err(pctl
->dev
, "unable to lock HW IRQ %lu for IRQ\n",
865 /* set mux to INT mode */
866 mtk_pmx_set_mode(pctl
->pctl_dev
, pin
->pin
.number
, pin
->eint
.eintmux
);
867 /* set gpio direction to input */
868 mtk_pmx_gpio_set_direction(pctl
->pctl_dev
, NULL
, pin
->pin
.number
, true);
869 /* set input-enable */
870 mtk_pconf_set_ies_smt(pctl
, pin
->pin
.number
, 1, PIN_CONFIG_INPUT_ENABLE
);
875 static void mtk_pinctrl_irq_release_resources(struct irq_data
*d
)
877 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
878 const struct mtk_desc_pin
*pin
;
880 pin
= mtk_find_pin_by_eint_num(pctl
, d
->hwirq
);
883 dev_err(pctl
->dev
, "Can not find pin\n");
887 gpiochip_unlock_as_irq(pctl
->chip
, pin
->pin
.number
);
890 static void __iomem
*mtk_eint_get_offset(struct mtk_pinctrl
*pctl
,
891 unsigned int eint_num
, unsigned int offset
)
893 unsigned int eint_base
= 0;
896 if (eint_num
>= pctl
->devdata
->ap_num
)
897 eint_base
= pctl
->devdata
->ap_num
;
899 reg
= pctl
->eint_reg_base
+ offset
+ ((eint_num
- eint_base
) / 32) * 4;
905 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
906 * @eint_num: the EINT number to setmtk_pinctrl
908 static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl
*pctl
,
909 unsigned int eint_num
)
912 unsigned int bit
= BIT(eint_num
% 32);
913 const struct mtk_eint_offsets
*eint_offsets
=
914 &pctl
->devdata
->eint_offsets
;
916 void __iomem
*reg
= mtk_eint_get_offset(pctl
, eint_num
,
919 if (readl(reg
) & bit
)
920 sens
= MT_LEVEL_SENSITIVE
;
922 sens
= MT_EDGE_SENSITIVE
;
924 if ((eint_num
< pctl
->devdata
->db_cnt
) && (sens
!= MT_EDGE_SENSITIVE
))
931 * mtk_eint_get_mask: To get the eint mask
932 * @eint_num: the EINT number to get
934 static unsigned int mtk_eint_get_mask(struct mtk_pinctrl
*pctl
,
935 unsigned int eint_num
)
937 unsigned int bit
= BIT(eint_num
% 32);
938 const struct mtk_eint_offsets
*eint_offsets
=
939 &pctl
->devdata
->eint_offsets
;
941 void __iomem
*reg
= mtk_eint_get_offset(pctl
, eint_num
,
944 return !!(readl(reg
) & bit
);
947 static int mtk_eint_flip_edge(struct mtk_pinctrl
*pctl
, int hwirq
)
949 int start_level
, curr_level
;
950 unsigned int reg_offset
;
951 const struct mtk_eint_offsets
*eint_offsets
= &(pctl
->devdata
->eint_offsets
);
952 u32 mask
= BIT(hwirq
& 0x1f);
953 u32 port
= (hwirq
>> 5) & eint_offsets
->port_mask
;
954 void __iomem
*reg
= pctl
->eint_reg_base
+ (port
<< 2);
955 const struct mtk_desc_pin
*pin
;
957 pin
= mtk_find_pin_by_eint_num(pctl
, hwirq
);
958 curr_level
= mtk_gpio_get(pctl
->chip
, pin
->pin
.number
);
960 start_level
= curr_level
;
962 reg_offset
= eint_offsets
->pol_clr
;
964 reg_offset
= eint_offsets
->pol_set
;
965 writel(mask
, reg
+ reg_offset
);
967 curr_level
= mtk_gpio_get(pctl
->chip
, pin
->pin
.number
);
968 } while (start_level
!= curr_level
);
973 static void mtk_eint_mask(struct irq_data
*d
)
975 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
976 const struct mtk_eint_offsets
*eint_offsets
=
977 &pctl
->devdata
->eint_offsets
;
978 u32 mask
= BIT(d
->hwirq
& 0x1f);
979 void __iomem
*reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
980 eint_offsets
->mask_set
);
985 static void mtk_eint_unmask(struct irq_data
*d
)
987 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
988 const struct mtk_eint_offsets
*eint_offsets
=
989 &pctl
->devdata
->eint_offsets
;
990 u32 mask
= BIT(d
->hwirq
& 0x1f);
991 void __iomem
*reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
992 eint_offsets
->mask_clr
);
996 if (pctl
->eint_dual_edges
[d
->hwirq
])
997 mtk_eint_flip_edge(pctl
, d
->hwirq
);
1000 static int mtk_gpio_set_debounce(struct gpio_chip
*chip
, unsigned offset
,
1003 struct mtk_pinctrl
*pctl
= dev_get_drvdata(chip
->parent
);
1004 int eint_num
, virq
, eint_offset
;
1005 unsigned int set_offset
, bit
, clr_bit
, clr_offset
, rst
, i
, unmask
, dbnc
;
1006 static const unsigned int debounce_time
[] = {500, 1000, 16000, 32000, 64000,
1008 const struct mtk_desc_pin
*pin
;
1011 pin
= pctl
->devdata
->pins
+ offset
;
1012 if (pin
->eint
.eintnum
== NO_EINT_SUPPORT
)
1015 eint_num
= pin
->eint
.eintnum
;
1016 virq
= irq_find_mapping(pctl
->domain
, eint_num
);
1017 eint_offset
= (eint_num
% 4) * 8;
1018 d
= irq_get_irq_data(virq
);
1020 set_offset
= (eint_num
/ 4) * 4 + pctl
->devdata
->eint_offsets
.dbnc_set
;
1021 clr_offset
= (eint_num
/ 4) * 4 + pctl
->devdata
->eint_offsets
.dbnc_clr
;
1022 if (!mtk_eint_can_en_debounce(pctl
, eint_num
))
1025 dbnc
= ARRAY_SIZE(debounce_time
);
1026 for (i
= 0; i
< ARRAY_SIZE(debounce_time
); i
++) {
1027 if (debounce
<= debounce_time
[i
]) {
1033 if (!mtk_eint_get_mask(pctl
, eint_num
)) {
1040 clr_bit
= 0xff << eint_offset
;
1041 writel(clr_bit
, pctl
->eint_reg_base
+ clr_offset
);
1043 bit
= ((dbnc
<< EINT_DBNC_SET_DBNC_BITS
) | EINT_DBNC_SET_EN
) <<
1045 rst
= EINT_DBNC_RST_BIT
<< eint_offset
;
1046 writel(rst
| bit
, pctl
->eint_reg_base
+ set_offset
);
1048 /* Delay a while (more than 2T) to wait for hw debounce counter reset
1057 static int mtk_gpio_set_config(struct gpio_chip
*chip
, unsigned offset
,
1058 unsigned long config
)
1062 if (pinconf_to_config_param(config
) != PIN_CONFIG_INPUT_DEBOUNCE
)
1065 debounce
= pinconf_to_config_argument(config
);
1066 return mtk_gpio_set_debounce(chip
, offset
, debounce
);
1069 static const struct gpio_chip mtk_gpio_chip
= {
1070 .owner
= THIS_MODULE
,
1071 .request
= gpiochip_generic_request
,
1072 .free
= gpiochip_generic_free
,
1073 .get_direction
= mtk_gpio_get_direction
,
1074 .direction_input
= mtk_gpio_direction_input
,
1075 .direction_output
= mtk_gpio_direction_output
,
1076 .get
= mtk_gpio_get
,
1077 .set
= mtk_gpio_set
,
1078 .to_irq
= mtk_gpio_to_irq
,
1079 .set_config
= mtk_gpio_set_config
,
1080 .of_gpio_n_cells
= 2,
1083 static int mtk_eint_set_type(struct irq_data
*d
,
1086 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
1087 const struct mtk_eint_offsets
*eint_offsets
=
1088 &pctl
->devdata
->eint_offsets
;
1089 u32 mask
= BIT(d
->hwirq
& 0x1f);
1092 if (((type
& IRQ_TYPE_EDGE_BOTH
) && (type
& IRQ_TYPE_LEVEL_MASK
)) ||
1093 ((type
& IRQ_TYPE_LEVEL_MASK
) == IRQ_TYPE_LEVEL_MASK
)) {
1094 dev_err(pctl
->dev
, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
1095 d
->irq
, d
->hwirq
, type
);
1099 if ((type
& IRQ_TYPE_EDGE_BOTH
) == IRQ_TYPE_EDGE_BOTH
)
1100 pctl
->eint_dual_edges
[d
->hwirq
] = 1;
1102 pctl
->eint_dual_edges
[d
->hwirq
] = 0;
1104 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_EDGE_FALLING
)) {
1105 reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
1106 eint_offsets
->pol_clr
);
1109 reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
1110 eint_offsets
->pol_set
);
1114 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
)) {
1115 reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
1116 eint_offsets
->sens_clr
);
1119 reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
1120 eint_offsets
->sens_set
);
1124 if (pctl
->eint_dual_edges
[d
->hwirq
])
1125 mtk_eint_flip_edge(pctl
, d
->hwirq
);
1130 static int mtk_eint_irq_set_wake(struct irq_data
*d
, unsigned int on
)
1132 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
1133 int shift
= d
->hwirq
& 0x1f;
1134 int reg
= d
->hwirq
>> 5;
1137 pctl
->wake_mask
[reg
] |= BIT(shift
);
1139 pctl
->wake_mask
[reg
] &= ~BIT(shift
);
1144 static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets
*chip
,
1145 void __iomem
*eint_reg_base
, u32
*buf
)
1150 for (port
= 0; port
< chip
->ports
; port
++) {
1151 reg
= eint_reg_base
+ (port
<< 2);
1152 writel_relaxed(~buf
[port
], reg
+ chip
->mask_set
);
1153 writel_relaxed(buf
[port
], reg
+ chip
->mask_clr
);
1157 static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets
*chip
,
1158 void __iomem
*eint_reg_base
, u32
*buf
)
1163 for (port
= 0; port
< chip
->ports
; port
++) {
1164 reg
= eint_reg_base
+ chip
->mask
+ (port
<< 2);
1165 buf
[port
] = ~readl_relaxed(reg
);
1166 /* Mask is 0 when irq is enabled, and 1 when disabled. */
1170 static int mtk_eint_suspend(struct device
*device
)
1173 struct mtk_pinctrl
*pctl
= dev_get_drvdata(device
);
1174 const struct mtk_eint_offsets
*eint_offsets
=
1175 &pctl
->devdata
->eint_offsets
;
1177 reg
= pctl
->eint_reg_base
;
1178 mtk_eint_chip_read_mask(eint_offsets
, reg
, pctl
->cur_mask
);
1179 mtk_eint_chip_write_mask(eint_offsets
, reg
, pctl
->wake_mask
);
1184 static int mtk_eint_resume(struct device
*device
)
1186 struct mtk_pinctrl
*pctl
= dev_get_drvdata(device
);
1187 const struct mtk_eint_offsets
*eint_offsets
=
1188 &pctl
->devdata
->eint_offsets
;
1190 mtk_eint_chip_write_mask(eint_offsets
,
1191 pctl
->eint_reg_base
, pctl
->cur_mask
);
1196 const struct dev_pm_ops mtk_eint_pm_ops
= {
1197 .suspend_noirq
= mtk_eint_suspend
,
1198 .resume_noirq
= mtk_eint_resume
,
1201 static void mtk_eint_ack(struct irq_data
*d
)
1203 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
1204 const struct mtk_eint_offsets
*eint_offsets
=
1205 &pctl
->devdata
->eint_offsets
;
1206 u32 mask
= BIT(d
->hwirq
& 0x1f);
1207 void __iomem
*reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
1213 static struct irq_chip mtk_pinctrl_irq_chip
= {
1215 .irq_disable
= mtk_eint_mask
,
1216 .irq_mask
= mtk_eint_mask
,
1217 .irq_unmask
= mtk_eint_unmask
,
1218 .irq_ack
= mtk_eint_ack
,
1219 .irq_set_type
= mtk_eint_set_type
,
1220 .irq_set_wake
= mtk_eint_irq_set_wake
,
1221 .irq_request_resources
= mtk_pinctrl_irq_request_resources
,
1222 .irq_release_resources
= mtk_pinctrl_irq_release_resources
,
1225 static unsigned int mtk_eint_init(struct mtk_pinctrl
*pctl
)
1227 const struct mtk_eint_offsets
*eint_offsets
=
1228 &pctl
->devdata
->eint_offsets
;
1229 void __iomem
*reg
= pctl
->eint_reg_base
+ eint_offsets
->dom_en
;
1232 for (i
= 0; i
< pctl
->devdata
->ap_num
; i
+= 32) {
1233 writel(0xffffffff, reg
);
1240 mtk_eint_debounce_process(struct mtk_pinctrl
*pctl
, int index
)
1242 unsigned int rst
, ctrl_offset
;
1243 unsigned int bit
, dbnc
;
1244 const struct mtk_eint_offsets
*eint_offsets
=
1245 &pctl
->devdata
->eint_offsets
;
1247 ctrl_offset
= (index
/ 4) * 4 + eint_offsets
->dbnc_ctrl
;
1248 dbnc
= readl(pctl
->eint_reg_base
+ ctrl_offset
);
1249 bit
= EINT_DBNC_SET_EN
<< ((index
% 4) * 8);
1250 if ((bit
& dbnc
) > 0) {
1251 ctrl_offset
= (index
/ 4) * 4 + eint_offsets
->dbnc_set
;
1252 rst
= EINT_DBNC_RST_BIT
<< ((index
% 4) * 8);
1253 writel(rst
, pctl
->eint_reg_base
+ ctrl_offset
);
1257 static void mtk_eint_irq_handler(struct irq_desc
*desc
)
1259 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1260 struct mtk_pinctrl
*pctl
= irq_desc_get_handler_data(desc
);
1261 unsigned int status
, eint_num
;
1262 int offset
, index
, virq
;
1263 const struct mtk_eint_offsets
*eint_offsets
=
1264 &pctl
->devdata
->eint_offsets
;
1265 void __iomem
*reg
= mtk_eint_get_offset(pctl
, 0, eint_offsets
->stat
);
1266 int dual_edges
, start_level
, curr_level
;
1267 const struct mtk_desc_pin
*pin
;
1269 chained_irq_enter(chip
, desc
);
1271 eint_num
< pctl
->devdata
->ap_num
;
1272 eint_num
+= 32, reg
+= 4) {
1273 status
= readl(reg
);
1275 offset
= __ffs(status
);
1276 index
= eint_num
+ offset
;
1277 virq
= irq_find_mapping(pctl
->domain
, index
);
1278 status
&= ~BIT(offset
);
1280 dual_edges
= pctl
->eint_dual_edges
[index
];
1282 /* Clear soft-irq in case we raised it
1284 writel(BIT(offset
), reg
- eint_offsets
->stat
+
1285 eint_offsets
->soft_clr
);
1287 pin
= mtk_find_pin_by_eint_num(pctl
, index
);
1288 start_level
= mtk_gpio_get(pctl
->chip
,
1292 generic_handle_irq(virq
);
1295 curr_level
= mtk_eint_flip_edge(pctl
, index
);
1297 /* If level changed, we might lost one edge
1298 interrupt, raised it through soft-irq */
1299 if (start_level
!= curr_level
)
1300 writel(BIT(offset
), reg
-
1301 eint_offsets
->stat
+
1302 eint_offsets
->soft_set
);
1305 if (index
< pctl
->devdata
->db_cnt
)
1306 mtk_eint_debounce_process(pctl
, index
);
1309 chained_irq_exit(chip
, desc
);
1312 static int mtk_pctrl_build_state(struct platform_device
*pdev
)
1314 struct mtk_pinctrl
*pctl
= platform_get_drvdata(pdev
);
1317 pctl
->ngroups
= pctl
->devdata
->npins
;
1319 /* Allocate groups */
1320 pctl
->groups
= devm_kcalloc(&pdev
->dev
, pctl
->ngroups
,
1321 sizeof(*pctl
->groups
), GFP_KERNEL
);
1325 /* We assume that one pin is one group, use pin name as group name. */
1326 pctl
->grp_names
= devm_kcalloc(&pdev
->dev
, pctl
->ngroups
,
1327 sizeof(*pctl
->grp_names
), GFP_KERNEL
);
1328 if (!pctl
->grp_names
)
1331 for (i
= 0; i
< pctl
->devdata
->npins
; i
++) {
1332 const struct mtk_desc_pin
*pin
= pctl
->devdata
->pins
+ i
;
1333 struct mtk_pinctrl_group
*group
= pctl
->groups
+ i
;
1335 group
->name
= pin
->pin
.name
;
1336 group
->pin
= pin
->pin
.number
;
1338 pctl
->grp_names
[i
] = pin
->pin
.name
;
1344 int mtk_pctrl_init(struct platform_device
*pdev
,
1345 const struct mtk_pinctrl_devdata
*data
,
1346 struct regmap
*regmap
)
1348 struct pinctrl_pin_desc
*pins
;
1349 struct mtk_pinctrl
*pctl
;
1350 struct device_node
*np
= pdev
->dev
.of_node
, *node
;
1351 struct property
*prop
;
1352 struct resource
*res
;
1353 int i
, ret
, irq
, ports_buf
;
1355 pctl
= devm_kzalloc(&pdev
->dev
, sizeof(*pctl
), GFP_KERNEL
);
1359 platform_set_drvdata(pdev
, pctl
);
1361 prop
= of_find_property(np
, "pins-are-numbered", NULL
);
1363 dev_err(&pdev
->dev
, "only support pins-are-numbered format\n");
1367 node
= of_parse_phandle(np
, "mediatek,pctl-regmap", 0);
1369 pctl
->regmap1
= syscon_node_to_regmap(node
);
1370 if (IS_ERR(pctl
->regmap1
))
1371 return PTR_ERR(pctl
->regmap1
);
1372 } else if (regmap
) {
1373 pctl
->regmap1
= regmap
;
1375 dev_err(&pdev
->dev
, "Pinctrl node has not register regmap.\n");
1379 /* Only 8135 has two base addr, other SoCs have only one. */
1380 node
= of_parse_phandle(np
, "mediatek,pctl-regmap", 1);
1382 pctl
->regmap2
= syscon_node_to_regmap(node
);
1383 if (IS_ERR(pctl
->regmap2
))
1384 return PTR_ERR(pctl
->regmap2
);
1387 pctl
->devdata
= data
;
1388 ret
= mtk_pctrl_build_state(pdev
);
1390 dev_err(&pdev
->dev
, "build state failed: %d\n", ret
);
1394 pins
= devm_kcalloc(&pdev
->dev
, pctl
->devdata
->npins
, sizeof(*pins
),
1399 for (i
= 0; i
< pctl
->devdata
->npins
; i
++)
1400 pins
[i
] = pctl
->devdata
->pins
[i
].pin
;
1402 pctl
->pctl_desc
.name
= dev_name(&pdev
->dev
);
1403 pctl
->pctl_desc
.owner
= THIS_MODULE
;
1404 pctl
->pctl_desc
.pins
= pins
;
1405 pctl
->pctl_desc
.npins
= pctl
->devdata
->npins
;
1406 pctl
->pctl_desc
.confops
= &mtk_pconf_ops
;
1407 pctl
->pctl_desc
.pctlops
= &mtk_pctrl_ops
;
1408 pctl
->pctl_desc
.pmxops
= &mtk_pmx_ops
;
1409 pctl
->dev
= &pdev
->dev
;
1411 pctl
->pctl_dev
= devm_pinctrl_register(&pdev
->dev
, &pctl
->pctl_desc
,
1413 if (IS_ERR(pctl
->pctl_dev
)) {
1414 dev_err(&pdev
->dev
, "couldn't register pinctrl driver\n");
1415 return PTR_ERR(pctl
->pctl_dev
);
1418 pctl
->chip
= devm_kzalloc(&pdev
->dev
, sizeof(*pctl
->chip
), GFP_KERNEL
);
1422 *pctl
->chip
= mtk_gpio_chip
;
1423 pctl
->chip
->ngpio
= pctl
->devdata
->npins
;
1424 pctl
->chip
->label
= dev_name(&pdev
->dev
);
1425 pctl
->chip
->parent
= &pdev
->dev
;
1426 pctl
->chip
->base
= -1;
1428 ret
= gpiochip_add_data(pctl
->chip
, pctl
);
1432 /* Register the GPIO to pin mappings. */
1433 ret
= gpiochip_add_pin_range(pctl
->chip
, dev_name(&pdev
->dev
),
1434 0, 0, pctl
->devdata
->npins
);
1440 if (!of_property_read_bool(np
, "interrupt-controller"))
1443 /* Get EINT register base from dts. */
1444 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1446 dev_err(&pdev
->dev
, "Unable to get Pinctrl resource\n");
1451 pctl
->eint_reg_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1452 if (IS_ERR(pctl
->eint_reg_base
)) {
1457 ports_buf
= pctl
->devdata
->eint_offsets
.ports
;
1458 pctl
->wake_mask
= devm_kcalloc(&pdev
->dev
, ports_buf
,
1459 sizeof(*pctl
->wake_mask
), GFP_KERNEL
);
1460 if (!pctl
->wake_mask
) {
1465 pctl
->cur_mask
= devm_kcalloc(&pdev
->dev
, ports_buf
,
1466 sizeof(*pctl
->cur_mask
), GFP_KERNEL
);
1467 if (!pctl
->cur_mask
) {
1472 pctl
->eint_dual_edges
= devm_kcalloc(&pdev
->dev
, pctl
->devdata
->ap_num
,
1473 sizeof(int), GFP_KERNEL
);
1474 if (!pctl
->eint_dual_edges
) {
1479 irq
= irq_of_parse_and_map(np
, 0);
1481 dev_err(&pdev
->dev
, "couldn't parse and map irq\n");
1486 pctl
->domain
= irq_domain_add_linear(np
,
1487 pctl
->devdata
->ap_num
, &irq_domain_simple_ops
, NULL
);
1488 if (!pctl
->domain
) {
1489 dev_err(&pdev
->dev
, "Couldn't register IRQ domain\n");
1494 mtk_eint_init(pctl
);
1495 for (i
= 0; i
< pctl
->devdata
->ap_num
; i
++) {
1496 int virq
= irq_create_mapping(pctl
->domain
, i
);
1498 irq_set_chip_and_handler(virq
, &mtk_pinctrl_irq_chip
,
1500 irq_set_chip_data(virq
, pctl
);
1503 irq_set_chained_handler_and_data(irq
, mtk_eint_irq_handler
, pctl
);
1507 gpiochip_remove(pctl
->chip
);