?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.16.11
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-at91-pio4.c
blob4b57a13758a43b49020e8d728662f1dbd5cbf7a3
1 /*
2 * Driver for the Atmel PIO4 controller
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/clk.h>
18 #include <linux/gpio/driver.h>
19 /* FIXME: needed for gpio_to_irq(), get rid of this */
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/init.h>
24 #include <linux/of.h>
25 #include <linux/platform_device.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/slab.h>
31 #include "core.h"
32 #include "pinconf.h"
33 #include "pinctrl-utils.h"
34
35 /*
36 * Warning:
37 * In order to not introduce confusion between Atmel PIO groups and pinctrl
38 * framework groups, Atmel PIO groups will be called banks, line is kept to
39 * designed the pin id into this bank.
40 */
41
42 #define ATMEL_PIO_MSKR 0x0000
43 #define ATMEL_PIO_CFGR 0x0004
44 #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
45 #define ATMEL_PIO_DIR_MASK BIT(8)
46 #define ATMEL_PIO_PUEN_MASK BIT(9)
47 #define ATMEL_PIO_PDEN_MASK BIT(10)
48 #define ATMEL_PIO_IFEN_MASK BIT(12)
49 #define ATMEL_PIO_IFSCEN_MASK BIT(13)
50 #define ATMEL_PIO_OPD_MASK BIT(14)
51 #define ATMEL_PIO_SCHMITT_MASK BIT(15)
52 #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
53 #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
54 #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
55 #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
56 #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
57 #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
58 #define ATMEL_PIO_PDSR 0x0008
59 #define ATMEL_PIO_LOCKSR 0x000C
60 #define ATMEL_PIO_SODR 0x0010
61 #define ATMEL_PIO_CODR 0x0014
62 #define ATMEL_PIO_ODSR 0x0018
63 #define ATMEL_PIO_IER 0x0020
64 #define ATMEL_PIO_IDR 0x0024
65 #define ATMEL_PIO_IMR 0x0028
66 #define ATMEL_PIO_ISR 0x002C
67 #define ATMEL_PIO_IOFR 0x003C
68
69 #define ATMEL_PIO_NPINS_PER_BANK 32
70 #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
71 #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
72 #define ATMEL_PIO_BANK_OFFSET 0x40
73
74 #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
75 #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
76 #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
77
78 struct atmel_pioctrl_data {
79 unsigned nbanks;
80 };
81
82 struct atmel_group {
83 const char *name;
84 u32 pin;
85 };
86
87 struct atmel_pin {
88 unsigned pin_id;
89 unsigned mux;
90 unsigned ioset;
91 unsigned bank;
92 unsigned line;
93 const char *device;
94 };
95
96 /**
97 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
98 * @reg_base: base address of the controller.
99 * @clk: clock of the controller.
100 * @nbanks: number of PIO groups, it can vary depending on the SoC.
101 * @pinctrl_dev: pinctrl device registered.
102 * @groups: groups table to provide group name and pin in the group to pinctrl.
103 * @group_names: group names table to provide all the group/pin names to
104 * pinctrl or gpio.
105 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
106 * fields are set at probe time. Other ones are set when parsing dt
107 * pinctrl.
108 * @npins: number of pins.
109 * @gpio_chip: gpio chip registered.
110 * @irq_domain: irq domain for the gpio controller.
111 * @irqs: table containing the hw irq number of the bank. The index of the
112 * table is the bank id.
113 * @dev: device entry for the Atmel PIO controller.
114 * @node: node of the Atmel PIO controller.
115 */
116 struct atmel_pioctrl {
117 void __iomem *reg_base;
118 struct clk *clk;
119 unsigned nbanks;
120 struct pinctrl_dev *pinctrl_dev;
121 struct atmel_group *groups;
122 const char * const *group_names;
123 struct atmel_pin **pins;
124 unsigned npins;
125 struct gpio_chip *gpio_chip;
126 struct irq_domain *irq_domain;
127 int *irqs;
128 unsigned *pm_wakeup_sources;
129 struct {
130 u32 imr;
131 u32 odsr;
132 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK];
133 } *pm_suspend_backup;
134 struct device *dev;
135 struct device_node *node;
136 };
137
138 static const char * const atmel_functions[] = {
139 "GPIO", "A", "B", "C", "D", "E", "F", "G"
140 };
141
142 /* --- GPIO --- */
143 static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
144 unsigned int bank, unsigned int reg)
145 {
146 return readl_relaxed(atmel_pioctrl->reg_base
147 + ATMEL_PIO_BANK_OFFSET * bank + reg);
148 }
149
150 static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
151 unsigned int bank, unsigned int reg,
152 unsigned int val)
153 {
154 writel_relaxed(val, atmel_pioctrl->reg_base
155 + ATMEL_PIO_BANK_OFFSET * bank + reg);
156 }
157
158 static void atmel_gpio_irq_ack(struct irq_data *d)
159 {
160 /*
161 * Nothing to do, interrupt is cleared when reading the status
162 * register.
163 */
164 }
165
166 static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
167 {
168 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
169 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
170 unsigned reg;
171
172 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
173 BIT(pin->line));
174 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
175 reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
176
177 switch (type) {
178 case IRQ_TYPE_EDGE_RISING:
179 irq_set_handler_locked(d, handle_edge_irq);
180 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
181 break;
182 case IRQ_TYPE_EDGE_FALLING:
183 irq_set_handler_locked(d, handle_edge_irq);
184 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
185 break;
186 case IRQ_TYPE_EDGE_BOTH:
187 irq_set_handler_locked(d, handle_edge_irq);
188 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
189 break;
190 case IRQ_TYPE_LEVEL_LOW:
191 irq_set_handler_locked(d, handle_level_irq);
192 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
193 break;
194 case IRQ_TYPE_LEVEL_HIGH:
195 irq_set_handler_locked(d, handle_level_irq);
196 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
197 break;
198 case IRQ_TYPE_NONE:
199 default:
200 return -EINVAL;
201 }
202
203 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
204
205 return 0;
206 }
207
208 static void atmel_gpio_irq_mask(struct irq_data *d)
209 {
210 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
211 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
212
213 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
214 BIT(pin->line));
215 }
216
217 static void atmel_gpio_irq_unmask(struct irq_data *d)
218 {
219 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
220 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
221
222 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
223 BIT(pin->line));
224 }
225
226 #ifdef CONFIG_PM_SLEEP
227
228 static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
229 {
230 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
231 int bank = ATMEL_PIO_BANK(d->hwirq);
232 int line = ATMEL_PIO_LINE(d->hwirq);
233
234 /* The gpio controller has one interrupt line per bank. */
235 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
236
237 if (on)
238 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
239 else
240 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
241
242 return 0;
243 }
244 #else
245 #define atmel_gpio_irq_set_wake NULL
246 #endif /* CONFIG_PM_SLEEP */
247
248 static struct irq_chip atmel_gpio_irq_chip = {
249 .name = "GPIO",
250 .irq_ack = atmel_gpio_irq_ack,
251 .irq_mask = atmel_gpio_irq_mask,
252 .irq_unmask = atmel_gpio_irq_unmask,
253 .irq_set_type = atmel_gpio_irq_set_type,
254 .irq_set_wake = atmel_gpio_irq_set_wake,
255 };
256
257 static void atmel_gpio_irq_handler(struct irq_desc *desc)
258 {
259 unsigned int irq = irq_desc_get_irq(desc);
260 struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
261 struct irq_chip *chip = irq_desc_get_chip(desc);
262 unsigned long isr;
263 int n, bank = -1;
264
265 /* Find from which bank is the irq received. */
266 for (n = 0; n < atmel_pioctrl->nbanks; n++) {
267 if (atmel_pioctrl->irqs[n] == irq) {
268 bank = n;
269 break;
270 }
271 }
272
273 if (bank < 0) {
274 dev_err(atmel_pioctrl->dev,
275 "no bank associated to irq %u\n", irq);
276 return;
277 }
278
279 chained_irq_enter(chip, desc);
280
281 for (;;) {
282 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
283 ATMEL_PIO_ISR);
284 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
285 ATMEL_PIO_IMR);
286 if (!isr)
287 break;
288
289 for_each_set_bit(n, &isr, BITS_PER_LONG)
290 generic_handle_irq(gpio_to_irq(bank *
291 ATMEL_PIO_NPINS_PER_BANK + n));
292 }
293
294 chained_irq_exit(chip, desc);
295 }
296
297 static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
298 {
299 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
300 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
301 unsigned reg;
302
303 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
304 BIT(pin->line));
305 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
306 reg &= ~ATMEL_PIO_DIR_MASK;
307 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
308
309 return 0;
310 }
311
312 static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
313 {
314 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
315 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
316 unsigned reg;
317
318 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
319
320 return !!(reg & BIT(pin->line));
321 }
322
323 static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
324 int value)
325 {
326 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
327 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
328 unsigned reg;
329
330 atmel_gpio_write(atmel_pioctrl, pin->bank,
331 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
332 BIT(pin->line));
333
334 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
335 BIT(pin->line));
336 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
337 reg |= ATMEL_PIO_DIR_MASK;
338 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
339
340 return 0;
341 }
342
343 static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
344 {
345 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
346 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
347
348 atmel_gpio_write(atmel_pioctrl, pin->bank,
349 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
350 BIT(pin->line));
351 }
352
353 static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
354 {
355 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
356
357 return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
358 }
359
360 static struct gpio_chip atmel_gpio_chip = {
361 .direction_input = atmel_gpio_direction_input,
362 .get = atmel_gpio_get,
363 .direction_output = atmel_gpio_direction_output,
364 .set = atmel_gpio_set,
365 .to_irq = atmel_gpio_to_irq,
366 .base = 0,
367 };
368
369 /* --- PINCTRL --- */
370 static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
371 unsigned pin_id)
372 {
373 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
374 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
375 unsigned line = atmel_pioctrl->pins[pin_id]->line;
376 void __iomem *addr = atmel_pioctrl->reg_base
377 + bank * ATMEL_PIO_BANK_OFFSET;
378
379 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
380 /* Have to set MSKR first, to access the right pin CFGR. */
381 wmb();
382
383 return readl_relaxed(addr + ATMEL_PIO_CFGR);
384 }
385
386 static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
387 unsigned pin_id, u32 conf)
388 {
389 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
390 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
391 unsigned line = atmel_pioctrl->pins[pin_id]->line;
392 void __iomem *addr = atmel_pioctrl->reg_base
393 + bank * ATMEL_PIO_BANK_OFFSET;
394
395 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
396 /* Have to set MSKR first, to access the right pin CFGR. */
397 wmb();
398 writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
399 }
400
401 static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
402 {
403 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
404
405 return atmel_pioctrl->npins;
406 }
407
408 static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
409 unsigned selector)
410 {
411 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
412
413 return atmel_pioctrl->groups[selector].name;
414 }
415
416 static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
417 unsigned selector, const unsigned **pins,
418 unsigned *num_pins)
419 {
420 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
421
422 *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
423 *num_pins = 1;
424
425 return 0;
426 }
427
428 static struct atmel_group *
429 atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
430 {
431 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
432 int i;
433
434 for (i = 0; i < atmel_pioctrl->npins; i++) {
435 struct atmel_group *grp = atmel_pioctrl->groups + i;
436
437 if (grp->pin == pin)
438 return grp;
439 }
440
441 return NULL;
442 }
443
444 static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
445 struct device_node *np,
446 u32 pinfunc, const char **grp_name,
447 const char **func_name)
448 {
449 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
450 unsigned pin_id, func_id;
451 struct atmel_group *grp;
452
453 pin_id = ATMEL_GET_PIN_NO(pinfunc);
454 func_id = ATMEL_GET_PIN_FUNC(pinfunc);
455
456 if (func_id >= ARRAY_SIZE(atmel_functions))
457 return -EINVAL;
458
459 *func_name = atmel_functions[func_id];
460
461 grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
462 if (!grp)
463 return -EINVAL;
464 *grp_name = grp->name;
465
466 atmel_pioctrl->pins[pin_id]->mux = func_id;
467 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
468 /* Want the device name not the group one. */
469 if (np->parent == atmel_pioctrl->node)
470 atmel_pioctrl->pins[pin_id]->device = np->name;
471 else
472 atmel_pioctrl->pins[pin_id]->device = np->parent->name;
473
474 return 0;
475 }
476
477 static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
478 struct device_node *np,
479 struct pinctrl_map **map,
480 unsigned *reserved_maps,
481 unsigned *num_maps)
482 {
483 unsigned num_pins, num_configs, reserve;
484 unsigned long *configs;
485 struct property *pins;
486 bool has_config;
487 u32 pinfunc;
488 int ret, i;
489
490 pins = of_find_property(np, "pinmux", NULL);
491 if (!pins)
492 return -EINVAL;
493
494 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
495 &num_configs);
496 if (ret < 0) {
497 dev_err(pctldev->dev, "%pOF: could not parse node property\n",
498 np);
499 return ret;
500 }
501
502 if (num_configs)
503 has_config = true;
504
505 num_pins = pins->length / sizeof(u32);
506 if (!num_pins) {
507 dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
508 ret = -EINVAL;
509 goto exit;
510 }
511
512 /*
513 * Reserve maps, at least there is a mux map and an optional conf
514 * map for each pin.
515 */
516 reserve = 1;
517 if (has_config && num_pins >= 1)
518 reserve++;
519 reserve *= num_pins;
520 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
521 reserve);
522 if (ret < 0)
523 goto exit;
524
525 for (i = 0; i < num_pins; i++) {
526 const char *group, *func;
527
528 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
529 if (ret)
530 goto exit;
531
532 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
533 &func);
534 if (ret)
535 goto exit;
536
537 pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
538 group, func);
539
540 if (has_config) {
541 ret = pinctrl_utils_add_map_configs(pctldev, map,
542 reserved_maps, num_maps, group,
543 configs, num_configs,
544 PIN_MAP_TYPE_CONFIGS_GROUP);
545 if (ret < 0)
546 goto exit;
547 }
548 }
549
550 exit:
551 kfree(configs);
552 return ret;
553 }
554
555 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
556 struct device_node *np_config,
557 struct pinctrl_map **map,
558 unsigned *num_maps)
559 {
560 struct device_node *np;
561 unsigned reserved_maps;
562 int ret;
563
564 *map = NULL;
565 *num_maps = 0;
566 reserved_maps = 0;
567
568 /*
569 * If all the pins of a device have the same configuration (or no one),
570 * it is useless to add a subnode, so directly parse node referenced by
571 * phandle.
572 */
573 ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
574 &reserved_maps, num_maps);
575 if (ret) {
576 for_each_child_of_node(np_config, np) {
577 ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
578 &reserved_maps, num_maps);
579 if (ret < 0)
580 break;
581 }
582 }
583
584 if (ret < 0) {
585 pinctrl_utils_free_map(pctldev, *map, *num_maps);
586 dev_err(pctldev->dev, "can't create maps for node %pOF\n",
587 np_config);
588 }
589
590 return ret;
591 }
592
593 static const struct pinctrl_ops atmel_pctlops = {
594 .get_groups_count = atmel_pctl_get_groups_count,
595 .get_group_name = atmel_pctl_get_group_name,
596 .get_group_pins = atmel_pctl_get_group_pins,
597 .dt_node_to_map = atmel_pctl_dt_node_to_map,
598 .dt_free_map = pinctrl_utils_free_map,
599 };
600
601 static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
602 {
603 return ARRAY_SIZE(atmel_functions);
604 }
605
606 static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
607 unsigned selector)
608 {
609 return atmel_functions[selector];
610 }
611
612 static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
613 unsigned selector,
614 const char * const **groups,
615 unsigned * const num_groups)
616 {
617 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
618
619 *groups = atmel_pioctrl->group_names;
620 *num_groups = atmel_pioctrl->npins;
621
622 return 0;
623 }
624
625 static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
626 unsigned function,
627 unsigned group)
628 {
629 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
630 unsigned pin;
631 u32 conf;
632
633 dev_dbg(pctldev->dev, "enable function %s group %s\n",
634 atmel_functions[function], atmel_pioctrl->groups[group].name);
635
636 pin = atmel_pioctrl->groups[group].pin;
637 conf = atmel_pin_config_read(pctldev, pin);
638 conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
639 conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
640 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
641 atmel_pin_config_write(pctldev, pin, conf);
642
643 return 0;
644 }
645
646 static const struct pinmux_ops atmel_pmxops = {
647 .get_functions_count = atmel_pmx_get_functions_count,
648 .get_function_name = atmel_pmx_get_function_name,
649 .get_function_groups = atmel_pmx_get_function_groups,
650 .set_mux = atmel_pmx_set_mux,
651 };
652
653 static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
654 unsigned group,
655 unsigned long *config)
656 {
657 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
658 unsigned param = pinconf_to_config_param(*config), arg = 0;
659 struct atmel_group *grp = atmel_pioctrl->groups + group;
660 unsigned pin_id = grp->pin;
661 u32 res;
662
663 res = atmel_pin_config_read(pctldev, pin_id);
664
665 switch (param) {
666 case PIN_CONFIG_BIAS_PULL_UP:
667 if (!(res & ATMEL_PIO_PUEN_MASK))
668 return -EINVAL;
669 arg = 1;
670 break;
671 case PIN_CONFIG_BIAS_PULL_DOWN:
672 if ((res & ATMEL_PIO_PUEN_MASK) ||
673 (!(res & ATMEL_PIO_PDEN_MASK)))
674 return -EINVAL;
675 arg = 1;
676 break;
677 case PIN_CONFIG_BIAS_DISABLE:
678 if ((res & ATMEL_PIO_PUEN_MASK) ||
679 ((res & ATMEL_PIO_PDEN_MASK)))
680 return -EINVAL;
681 arg = 1;
682 break;
683 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
684 if (!(res & ATMEL_PIO_OPD_MASK))
685 return -EINVAL;
686 arg = 1;
687 break;
688 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
689 if (!(res & ATMEL_PIO_SCHMITT_MASK))
690 return -EINVAL;
691 arg = 1;
692 break;
693 default:
694 return -ENOTSUPP;
695 }
696
697 *config = pinconf_to_config_packed(param, arg);
698 return 0;
699 }
700
701 static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
702 unsigned group,
703 unsigned long *configs,
704 unsigned num_configs)
705 {
706 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
707 struct atmel_group *grp = atmel_pioctrl->groups + group;
708 unsigned bank, pin, pin_id = grp->pin;
709 u32 mask, conf = 0;
710 int i;
711
712 conf = atmel_pin_config_read(pctldev, pin_id);
713
714 for (i = 0; i < num_configs; i++) {
715 unsigned param = pinconf_to_config_param(configs[i]);
716 unsigned arg = pinconf_to_config_argument(configs[i]);
717
718 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
719 __func__, pin_id, configs[i]);
720
721 switch (param) {
722 case PIN_CONFIG_BIAS_DISABLE:
723 conf &= (~ATMEL_PIO_PUEN_MASK);
724 conf &= (~ATMEL_PIO_PDEN_MASK);
725 break;
726 case PIN_CONFIG_BIAS_PULL_UP:
727 conf |= ATMEL_PIO_PUEN_MASK;
728 conf &= (~ATMEL_PIO_PDEN_MASK);
729 break;
730 case PIN_CONFIG_BIAS_PULL_DOWN:
731 conf |= ATMEL_PIO_PDEN_MASK;
732 conf &= (~ATMEL_PIO_PUEN_MASK);
733 break;
734 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
735 if (arg == 0)
736 conf &= (~ATMEL_PIO_OPD_MASK);
737 else
738 conf |= ATMEL_PIO_OPD_MASK;
739 break;
740 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
741 if (arg == 0)
742 conf |= ATMEL_PIO_SCHMITT_MASK;
743 else
744 conf &= (~ATMEL_PIO_SCHMITT_MASK);
745 break;
746 case PIN_CONFIG_INPUT_DEBOUNCE:
747 if (arg == 0) {
748 conf &= (~ATMEL_PIO_IFEN_MASK);
749 conf &= (~ATMEL_PIO_IFSCEN_MASK);
750 } else {
751 /*
752 * We don't care about the debounce value for several reasons:
753 * - can't have different debounce periods inside a same group,
754 * - the register to configure this period is a secure register.
755 * The debouncing filter can filter a pulse with a duration of less
756 * than 1/2 slow clock period.
757 */
758 conf |= ATMEL_PIO_IFEN_MASK;
759 conf |= ATMEL_PIO_IFSCEN_MASK;
760 }
761 break;
762 case PIN_CONFIG_OUTPUT:
763 conf |= ATMEL_PIO_DIR_MASK;
764 bank = ATMEL_PIO_BANK(pin_id);
765 pin = ATMEL_PIO_LINE(pin_id);
766 mask = 1 << pin;
767
768 if (arg == 0) {
769 writel_relaxed(mask, atmel_pioctrl->reg_base +
770 bank * ATMEL_PIO_BANK_OFFSET +
771 ATMEL_PIO_CODR);
772 } else {
773 writel_relaxed(mask, atmel_pioctrl->reg_base +
774 bank * ATMEL_PIO_BANK_OFFSET +
775 ATMEL_PIO_SODR);
776 }
777 break;
778 default:
779 dev_warn(pctldev->dev,
780 "unsupported configuration parameter: %u\n",
781 param);
782 continue;
783 }
784 }
785
786 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
787 atmel_pin_config_write(pctldev, pin_id, conf);
788
789 return 0;
790 }
791
792 static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
793 struct seq_file *s, unsigned pin_id)
794 {
795 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
796 u32 conf;
797
798 if (!atmel_pioctrl->pins[pin_id]->device)
799 return;
800
801 if (atmel_pioctrl->pins[pin_id])
802 seq_printf(s, " (%s, ioset %u) ",
803 atmel_pioctrl->pins[pin_id]->device,
804 atmel_pioctrl->pins[pin_id]->ioset);
805
806 conf = atmel_pin_config_read(pctldev, pin_id);
807 if (conf & ATMEL_PIO_PUEN_MASK)
808 seq_printf(s, "%s ", "pull-up");
809 if (conf & ATMEL_PIO_PDEN_MASK)
810 seq_printf(s, "%s ", "pull-down");
811 if (conf & ATMEL_PIO_IFEN_MASK)
812 seq_printf(s, "%s ", "debounce");
813 if (conf & ATMEL_PIO_OPD_MASK)
814 seq_printf(s, "%s ", "open-drain");
815 if (conf & ATMEL_PIO_SCHMITT_MASK)
816 seq_printf(s, "%s ", "schmitt");
817 }
818
819 static const struct pinconf_ops atmel_confops = {
820 .pin_config_group_get = atmel_conf_pin_config_group_get,
821 .pin_config_group_set = atmel_conf_pin_config_group_set,
822 .pin_config_dbg_show = atmel_conf_pin_config_dbg_show,
823 };
824
825 static struct pinctrl_desc atmel_pinctrl_desc = {
826 .name = "atmel_pinctrl",
827 .confops = &atmel_confops,
828 .pctlops = &atmel_pctlops,
829 .pmxops = &atmel_pmxops,
830 };
831
832 static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
833 {
834 struct platform_device *pdev = to_platform_device(dev);
835 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
836 int i, j;
837
838 /*
839 * For each bank, save IMR to restore it later and disable all GPIO
840 * interrupts excepting the ones marked as wakeup sources.
841 */
842 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
843 atmel_pioctrl->pm_suspend_backup[i].imr =
844 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
845 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
846 ~atmel_pioctrl->pm_wakeup_sources[i]);
847 atmel_pioctrl->pm_suspend_backup[i].odsr =
848 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
849 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
850 atmel_gpio_write(atmel_pioctrl, i,
851 ATMEL_PIO_MSKR, BIT(j));
852 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
853 atmel_gpio_read(atmel_pioctrl, i,
854 ATMEL_PIO_CFGR);
855 }
856 }
857
858 return 0;
859 }
860
861 static int __maybe_unused atmel_pctrl_resume(struct device *dev)
862 {
863 struct platform_device *pdev = to_platform_device(dev);
864 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
865 int i, j;
866
867 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
868 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
869 atmel_pioctrl->pm_suspend_backup[i].imr);
870 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
871 atmel_pioctrl->pm_suspend_backup[i].odsr);
872 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
873 atmel_gpio_write(atmel_pioctrl, i,
874 ATMEL_PIO_MSKR, BIT(j));
875 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
876 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
877 }
878 }
879
880 return 0;
881 }
882
883 static const struct dev_pm_ops atmel_pctrl_pm_ops = {
884 SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
885 };
886
887 /*
888 * The number of banks can be different from a SoC to another one.
889 * We can have up to 16 banks.
890 */
891 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
892 .nbanks = 4,
893 };
894
895 static const struct of_device_id atmel_pctrl_of_match[] = {
896 {
897 .compatible = "atmel,sama5d2-pinctrl",
898 .data = &atmel_sama5d2_pioctrl_data,
899 }, {
900 /* sentinel */
901 }
902 };
903
904 static int atmel_pinctrl_probe(struct platform_device *pdev)
905 {
906 struct device *dev = &pdev->dev;
907 struct pinctrl_pin_desc *pin_desc;
908 const char **group_names;
909 const struct of_device_id *match;
910 int i, ret;
911 struct resource *res;
912 struct atmel_pioctrl *atmel_pioctrl;
913 const struct atmel_pioctrl_data *atmel_pioctrl_data;
914
915 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
916 if (!atmel_pioctrl)
917 return -ENOMEM;
918 atmel_pioctrl->dev = dev;
919 atmel_pioctrl->node = dev->of_node;
920 platform_set_drvdata(pdev, atmel_pioctrl);
921
922 match = of_match_node(atmel_pctrl_of_match, dev->of_node);
923 if (!match) {
924 dev_err(dev, "unknown compatible string\n");
925 return -ENODEV;
926 }
927 atmel_pioctrl_data = match->data;
928 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
929 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
930
931 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
932 if (!res) {
933 dev_err(dev, "unable to get atmel pinctrl resource\n");
934 return -EINVAL;
935 }
936 atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res);
937 if (IS_ERR(atmel_pioctrl->reg_base))
938 return -EINVAL;
939
940 atmel_pioctrl->clk = devm_clk_get(dev, NULL);
941 if (IS_ERR(atmel_pioctrl->clk)) {
942 dev_err(dev, "failed to get clock\n");
943 return PTR_ERR(atmel_pioctrl->clk);
944 }
945
946 atmel_pioctrl->pins = devm_kzalloc(dev, sizeof(*atmel_pioctrl->pins)
947 * atmel_pioctrl->npins, GFP_KERNEL);
948 if (!atmel_pioctrl->pins)
949 return -ENOMEM;
950
951 pin_desc = devm_kzalloc(dev, sizeof(*pin_desc)
952 * atmel_pioctrl->npins, GFP_KERNEL);
953 if (!pin_desc)
954 return -ENOMEM;
955 atmel_pinctrl_desc.pins = pin_desc;
956 atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
957
958 /* One pin is one group since a pin can achieve all functions. */
959 group_names = devm_kzalloc(dev, sizeof(*group_names)
960 * atmel_pioctrl->npins, GFP_KERNEL);
961 if (!group_names)
962 return -ENOMEM;
963 atmel_pioctrl->group_names = group_names;
964
965 atmel_pioctrl->groups = devm_kzalloc(&pdev->dev,
966 sizeof(*atmel_pioctrl->groups) * atmel_pioctrl->npins,
967 GFP_KERNEL);
968 if (!atmel_pioctrl->groups)
969 return -ENOMEM;
970 for (i = 0 ; i < atmel_pioctrl->npins; i++) {
971 struct atmel_group *group = atmel_pioctrl->groups + i;
972 unsigned bank = ATMEL_PIO_BANK(i);
973 unsigned line = ATMEL_PIO_LINE(i);
974
975 atmel_pioctrl->pins[i] = devm_kzalloc(dev,
976 sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
977 if (!atmel_pioctrl->pins[i])
978 return -ENOMEM;
979
980 atmel_pioctrl->pins[i]->pin_id = i;
981 atmel_pioctrl->pins[i]->bank = bank;
982 atmel_pioctrl->pins[i]->line = line;
983
984 pin_desc[i].number = i;
985 /* Pin naming convention: P(bank_name)(bank_pin_number). */
986 pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
987 bank + 'A', line);
988
989 group->name = group_names[i] = pin_desc[i].name;
990 group->pin = pin_desc[i].number;
991
992 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
993 }
994
995 atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
996 atmel_pioctrl->gpio_chip->of_node = dev->of_node;
997 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
998 atmel_pioctrl->gpio_chip->label = dev_name(dev);
999 atmel_pioctrl->gpio_chip->parent = dev;
1000 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
1001
1002 atmel_pioctrl->pm_wakeup_sources = devm_kzalloc(dev,
1003 sizeof(*atmel_pioctrl->pm_wakeup_sources)
1004 * atmel_pioctrl->nbanks, GFP_KERNEL);
1005 if (!atmel_pioctrl->pm_wakeup_sources)
1006 return -ENOMEM;
1007
1008 atmel_pioctrl->pm_suspend_backup = devm_kzalloc(dev,
1009 sizeof(*atmel_pioctrl->pm_suspend_backup)
1010 * atmel_pioctrl->nbanks, GFP_KERNEL);
1011 if (!atmel_pioctrl->pm_suspend_backup)
1012 return -ENOMEM;
1013
1014 atmel_pioctrl->irqs = devm_kzalloc(dev, sizeof(*atmel_pioctrl->irqs)
1015 * atmel_pioctrl->nbanks, GFP_KERNEL);
1016 if (!atmel_pioctrl->irqs)
1017 return -ENOMEM;
1018
1019 /* There is one controller but each bank has its own irq line. */
1020 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
1021 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1022 if (!res) {
1023 dev_err(dev, "missing irq resource for group %c\n",
1024 'A' + i);
1025 return -EINVAL;
1026 }
1027 atmel_pioctrl->irqs[i] = res->start;
1028 irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
1029 irq_set_handler_data(res->start, atmel_pioctrl);
1030 dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
1031 }
1032
1033 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
1034 atmel_pioctrl->gpio_chip->ngpio,
1035 &irq_domain_simple_ops, NULL);
1036 if (!atmel_pioctrl->irq_domain) {
1037 dev_err(dev, "can't add the irq domain\n");
1038 return -ENODEV;
1039 }
1040 atmel_pioctrl->irq_domain->name = "atmel gpio";
1041
1042 for (i = 0; i < atmel_pioctrl->npins; i++) {
1043 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
1044
1045 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
1046 handle_simple_irq);
1047 irq_set_chip_data(irq, atmel_pioctrl);
1048 dev_dbg(dev,
1049 "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
1050 i, irq);
1051 }
1052
1053 ret = clk_prepare_enable(atmel_pioctrl->clk);
1054 if (ret) {
1055 dev_err(dev, "failed to prepare and enable clock\n");
1056 goto clk_prepare_enable_error;
1057 }
1058
1059 atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
1060 &atmel_pinctrl_desc,
1061 atmel_pioctrl);
1062 if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
1063 ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
1064 dev_err(dev, "pinctrl registration failed\n");
1065 goto clk_unprep;
1066 }
1067
1068 ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
1069 if (ret) {
1070 dev_err(dev, "failed to add gpiochip\n");
1071 goto clk_unprep;
1072 }
1073
1074 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
1075 0, 0, atmel_pioctrl->gpio_chip->ngpio);
1076 if (ret) {
1077 dev_err(dev, "failed to add gpio pin range\n");
1078 goto gpiochip_add_pin_range_error;
1079 }
1080
1081 dev_info(&pdev->dev, "atmel pinctrl initialized\n");
1082
1083 return 0;
1084
1085 gpiochip_add_pin_range_error:
1086 gpiochip_remove(atmel_pioctrl->gpio_chip);
1087
1088 clk_unprep:
1089 clk_disable_unprepare(atmel_pioctrl->clk);
1090
1091 clk_prepare_enable_error:
1092 irq_domain_remove(atmel_pioctrl->irq_domain);
1093
1094 return ret;
1095 }
1096
1097 static struct platform_driver atmel_pinctrl_driver = {
1098 .driver = {
1099 .name = "pinctrl-at91-pio4",
1100 .of_match_table = atmel_pctrl_of_match,
1101 .pm = &atmel_pctrl_pm_ops,
1102 .suppress_bind_attrs = true,
1103 },
1104 .probe = atmel_pinctrl_probe,
1105 };
1106 builtin_platform_driver(atmel_pinctrl_driver);
Linux with added FPC-III support