| blob | 35951e7b89d2fae33377dd56529811f8c0c3ad06 |
1 /*
2 * R8A7795 ES2.0+ processor support - PFC hardware block.
3 *
4 * Copyright (C) 2015-2016 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
11 #include <linux/kernel.h>
12 #include <linux/sys_soc.h>
17 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
21 #define CPU_ALL_PORT(fn, sfx) \
22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
34 /*
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
37 */
39 /* GPSR0 */
40 #define GPSR0_15 F_(D15, IP7_11_8)
41 #define GPSR0_14 F_(D14, IP7_7_4)
42 #define GPSR0_13 F_(D13, IP7_3_0)
43 #define GPSR0_12 F_(D12, IP6_31_28)
44 #define GPSR0_11 F_(D11, IP6_27_24)
45 #define GPSR0_10 F_(D10, IP6_23_20)
46 #define GPSR0_9 F_(D9, IP6_19_16)
47 #define GPSR0_8 F_(D8, IP6_15_12)
48 #define GPSR0_7 F_(D7, IP6_11_8)
49 #define GPSR0_6 F_(D6, IP6_7_4)
50 #define GPSR0_5 F_(D5, IP6_3_0)
51 #define GPSR0_4 F_(D4, IP5_31_28)
52 #define GPSR0_3 F_(D3, IP5_27_24)
53 #define GPSR0_2 F_(D2, IP5_23_20)
54 #define GPSR0_1 F_(D1, IP5_19_16)
55 #define GPSR0_0 F_(D0, IP5_15_12)
57 /* GPSR1 */
58 #define GPSR1_28 FM(CLKOUT)
59 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
60 #define GPSR1_26 F_(WE1_N, IP5_7_4)
61 #define GPSR1_25 F_(WE0_N, IP5_3_0)
62 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
63 #define GPSR1_23 F_(RD_N, IP4_27_24)
64 #define GPSR1_22 F_(BS_N, IP4_23_20)
65 #define GPSR1_21 F_(CS1_N, IP4_19_16)
66 #define GPSR1_20 F_(CS0_N, IP4_15_12)
67 #define GPSR1_19 F_(A19, IP4_11_8)
68 #define GPSR1_18 F_(A18, IP4_7_4)
69 #define GPSR1_17 F_(A17, IP4_3_0)
70 #define GPSR1_16 F_(A16, IP3_31_28)
71 #define GPSR1_15 F_(A15, IP3_27_24)
72 #define GPSR1_14 F_(A14, IP3_23_20)
73 #define GPSR1_13 F_(A13, IP3_19_16)
74 #define GPSR1_12 F_(A12, IP3_15_12)
75 #define GPSR1_11 F_(A11, IP3_11_8)
76 #define GPSR1_10 F_(A10, IP3_7_4)
77 #define GPSR1_9 F_(A9, IP3_3_0)
78 #define GPSR1_8 F_(A8, IP2_31_28)
79 #define GPSR1_7 F_(A7, IP2_27_24)
80 #define GPSR1_6 F_(A6, IP2_23_20)
81 #define GPSR1_5 F_(A5, IP2_19_16)
82 #define GPSR1_4 F_(A4, IP2_15_12)
83 #define GPSR1_3 F_(A3, IP2_11_8)
84 #define GPSR1_2 F_(A2, IP2_7_4)
85 #define GPSR1_1 F_(A1, IP2_3_0)
86 #define GPSR1_0 F_(A0, IP1_31_28)
88 /* GPSR2 */
89 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
90 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
91 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
92 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
93 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
94 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
95 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
96 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
97 #define GPSR2_6 F_(PWM0, IP1_19_16)
98 #define GPSR2_5 F_(IRQ5, IP1_15_12)
99 #define GPSR2_4 F_(IRQ4, IP1_11_8)
100 #define GPSR2_3 F_(IRQ3, IP1_7_4)
101 #define GPSR2_2 F_(IRQ2, IP1_3_0)
102 #define GPSR2_1 F_(IRQ1, IP0_31_28)
103 #define GPSR2_0 F_(IRQ0, IP0_27_24)
105 /* GPSR3 */
106 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
107 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
108 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
109 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
110 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
111 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
112 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
113 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
114 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
115 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
116 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
117 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
118 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
119 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
120 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
121 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
123 /* GPSR4 */
124 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
125 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
126 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
127 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
128 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
129 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
130 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
131 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
132 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
133 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
134 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
135 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
136 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
137 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
138 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
139 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
140 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
141 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
143 /* GPSR5 */
144 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
145 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
146 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
147 #define GPSR5_22 FM(MSIOF0_RXD)
148 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
149 #define GPSR5_20 FM(MSIOF0_TXD)
150 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
151 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
152 #define GPSR5_17 FM(MSIOF0_SCK)
153 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
154 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
155 #define GPSR5_14 F_(HTX0, IP13_19_16)
156 #define GPSR5_13 F_(HRX0, IP13_15_12)
157 #define GPSR5_12 F_(HSCK0, IP13_11_8)
158 #define GPSR5_11 F_(RX2_A, IP13_7_4)
159 #define GPSR5_10 F_(TX2_A, IP13_3_0)
160 #define GPSR5_9 F_(SCK2, IP12_31_28)
161 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
162 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
163 #define GPSR5_6 F_(TX1_A, IP12_19_16)
164 #define GPSR5_5 F_(RX1_A, IP12_15_12)
165 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
166 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
167 #define GPSR5_2 F_(TX0, IP12_3_0)
168 #define GPSR5_1 F_(RX0, IP11_31_28)
169 #define GPSR5_0 F_(SCK0, IP11_27_24)
171 /* GPSR6 */
172 #define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
173 #define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
174 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
175 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
176 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
177 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
178 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
179 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
180 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
181 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
182 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
183 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
184 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
185 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
186 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
187 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
188 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
189 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
190 #define GPSR6_13 FM(SSI_SDATA5)
191 #define GPSR6_12 FM(SSI_WS5)
192 #define GPSR6_11 FM(SSI_SCK5)
193 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
194 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
195 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
196 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
197 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
198 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
199 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
200 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
201 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
202 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
203 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
205 /* GPSR7 */
206 #define GPSR7_3 FM(HDMI1_CEC)
207 #define GPSR7_2 FM(HDMI0_CEC)
208 #define GPSR7_1 FM(AVS2)
209 #define GPSR7_0 FM(AVS1)
212 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
213 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
234 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
277 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
309 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
330 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
339 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
359 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
360 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
361 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
362 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
363 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
365 #define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
367 #define PINMUX_GPSR \
368 \
369 GPSR6_31 \
370 GPSR6_30 \
371 GPSR6_29 \
372 GPSR1_28 GPSR6_28 \
373 GPSR1_27 GPSR6_27 \
374 GPSR1_26 GPSR6_26 \
375 GPSR1_25 GPSR5_25 GPSR6_25 \
376 GPSR1_24 GPSR5_24 GPSR6_24 \
377 GPSR1_23 GPSR5_23 GPSR6_23 \
378 GPSR1_22 GPSR5_22 GPSR6_22 \
379 GPSR1_21 GPSR5_21 GPSR6_21 \
380 GPSR1_20 GPSR5_20 GPSR6_20 \
381 GPSR1_19 GPSR5_19 GPSR6_19 \
382 GPSR1_18 GPSR5_18 GPSR6_18 \
383 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
384 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
385 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
386 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
387 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
388 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
389 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
390 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
391 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
392 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
393 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
394 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
395 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
396 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
397 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
398 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
399 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
400 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
402 #define PINMUX_IPSR \
403 \
404 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
405 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
406 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
407 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
408 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
409 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
410 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
411 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
412 \
413 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
414 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
415 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
416 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
417 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
418 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
419 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
420 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
421 \
422 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
423 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
424 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
425 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
426 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
427 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
428 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
429 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
430 \
431 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
432 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
433 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
434 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
435 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
436 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
437 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
438 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
439 \
440 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
441 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
442 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
443 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
444 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
445 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
446 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
447 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
450 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
451 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
452 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
453 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
454 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
455 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
456 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
457 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
458 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
459 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
460 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
461 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
462 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
463 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
464 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
465 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
466 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
467 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
470 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
471 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
472 #define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
473 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
474 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
476 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
477 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
478 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
479 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
480 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
481 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
482 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
483 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
484 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
485 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
486 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
487 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
488 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
489 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
490 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
491 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
494 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
495 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
496 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
497 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
498 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
499 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
501 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
502 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
503 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
504 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
505 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
507 #define PINMUX_MOD_SELS \
508 \
509 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
510 MOD_SEL2_30 \
511 MOD_SEL1_29_28_27 MOD_SEL2_29 \
512 MOD_SEL0_28_27 MOD_SEL2_28_27 \
513 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
514 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
515 MOD_SEL0_23 MOD_SEL1_23_22_21 \
516 MOD_SEL0_22 \
517 MOD_SEL0_21 MOD_SEL2_21 \
518 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
519 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
520 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
521 MOD_SEL2_17 \
522 MOD_SEL0_16 MOD_SEL1_16 \
523 MOD_SEL1_15_14 \
524 MOD_SEL0_14_13 \
525 MOD_SEL1_13 \
526 MOD_SEL0_12 MOD_SEL1_12 \
527 MOD_SEL0_11 MOD_SEL1_11 \
528 MOD_SEL0_10 MOD_SEL1_10 \
529 MOD_SEL0_9_8 MOD_SEL1_9 \
530 MOD_SEL0_7_6 \
531 MOD_SEL1_6 \
532 MOD_SEL0_5 MOD_SEL1_5 \
533 MOD_SEL0_4_3 MOD_SEL1_4 \
534 MOD_SEL1_3 \
535 MOD_SEL1_2 \
536 MOD_SEL1_1 \
537 MOD_SEL1_0 MOD_SEL2_0
539 /*
540 * These pins are not able to be muxed but have other properties
541 * that can be set, such as drive-strength or pull-up/pull-down enable.
542 */
543 #define PINMUX_STATIC \
544 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
545 FM(QSPI0_IO2) FM(QSPI0_IO3) \
546 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
547 FM(QSPI1_IO2) FM(QSPI1_IO3) \
548 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
549 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
550 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
551 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
552 FM(PRESETOUT) \
553 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
554 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
559 PINMUX_DATA_BEGIN,
561 PINMUX_DATA_END,
563 #define F_(x, y)
564 #define FM(x) FN_##x,
565 PINMUX_FUNCTION_BEGIN,
567 PINMUX_GPSR
568 PINMUX_IPSR
569 PINMUX_MOD_SELS
570 PINMUX_FUNCTION_END,
571 #undef F_
572 #undef FM
574 #define F_(x, y)
575 #define FM(x) x##_MARK,
576 PINMUX_MARK_BEGIN,
577 PINMUX_GPSR
578 PINMUX_IPSR
579 PINMUX_MOD_SELS
580 PINMUX_STATIC
581 PINMUX_MARK_END,
582 #undef F_
583 #undef FM
584 };
604 /* IPSR0 */
645 /* IPSR1 */
696 /* IPSR2 */
757 /* IPSR3 */
811 /* IPSR4 */
857 /* IPSR5 */
907 /* IPSR6 */
959 /* IPSR7 */
1001 /* IPSR8 */
1050 /* IPSR9 */
1076 /* IPSR10 */
1104 /* IPSR11 */
1142 /* IPSR12 */
1203 /* IPSR13 */
1263 /* IPSR14 */
1304 /* IPSR15 */
1351 /* IPSR16 */
1406 /* IPSR17 */
1473 /* IPSR18 */
1494 /*
1495 * Static pins can not be muxed between different functions but
1496 * still needs a mark entry in the pinmux list. Add each static
1497 * pin to the list without an associated function. The sh-pfc
1498 * core will do the right thing and skip trying to mux then pin
1499 * while still applying configuration to it
1500 */
1501 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1502 PINMUX_STATIC
1503 #undef FM
1504 };
1506 /*
1507 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1508 * Physical layout rows: A - AW, cols: 1 - 39.
1509 */
1512 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1513 #define PIN_NONE U16_MAX
1518 /*
1519 * Pins not associated with a GPIO port.
1520 *
1521 * The pin positions are different between different r8a7795
1522 * packages, all that is needed for the pfc driver is a unique
1523 * number for each pin. To this end use the pin layout from
1524 * R-Car H3SiP to calculate a unique number for each pin.
1525 */
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569 };
1571 /* - AUDIO CLOCK ------------------------------------------------------------ */
1573 /* CLK A */
1575 };
1577 AUDIO_CLKA_A_MARK,
1578 };
1580 /* CLK A */
1582 };
1584 AUDIO_CLKA_B_MARK,
1585 };
1587 /* CLK A */
1589 };
1591 AUDIO_CLKA_C_MARK,
1592 };
1594 /* CLK B */
1596 };
1598 AUDIO_CLKB_A_MARK,
1599 };
1601 /* CLK B */
1603 };
1605 AUDIO_CLKB_B_MARK,
1606 };
1608 /* CLK C */
1610 };
1612 AUDIO_CLKC_A_MARK,
1613 };
1615 /* CLK C */
1617 };
1619 AUDIO_CLKC_B_MARK,
1620 };
1622 /* CLKOUT */
1624 };
1626 AUDIO_CLKOUT_A_MARK,
1627 };
1629 /* CLKOUT */
1631 };
1633 AUDIO_CLKOUT_B_MARK,
1634 };
1636 /* CLKOUT */
1638 };
1640 AUDIO_CLKOUT_C_MARK,
1641 };
1643 /* CLKOUT */
1645 };
1647 AUDIO_CLKOUT_D_MARK,
1648 };
1650 /* CLKOUT1 */
1652 };
1654 AUDIO_CLKOUT1_A_MARK,
1655 };
1657 /* CLKOUT1 */
1659 };
1661 AUDIO_CLKOUT1_B_MARK,
1662 };
1664 /* CLKOUT2 */
1666 };
1668 AUDIO_CLKOUT2_A_MARK,
1669 };
1671 /* CLKOUT2 */
1673 };
1675 AUDIO_CLKOUT2_B_MARK,
1676 };
1678 /* CLKOUT3 */
1680 };
1682 AUDIO_CLKOUT3_A_MARK,
1683 };
1685 /* CLKOUT3 */
1687 };
1689 AUDIO_CLKOUT3_B_MARK,
1690 };
1692 /* - EtherAVB --------------------------------------------------------------- */
1694 /* AVB_LINK */
1696 };
1698 AVB_LINK_MARK,
1699 };
1701 /* AVB_MAGIC_ */
1703 };
1705 AVB_MAGIC_MARK,
1706 };
1708 /* AVB_PHY_INT */
1710 };
1712 AVB_PHY_INT_MARK,
1713 };
1715 /* AVB_MDC, AVB_MDIO */
1717 };
1720 };
1722 /*
1723 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1724 * AVB_TD1, AVB_TD2, AVB_TD3,
1725 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1726 * AVB_RD1, AVB_RD2, AVB_RD3,
1727 * AVB_TXCREFCLK
1728 */
1735 };
1741 AVB_TXCREFCLK_MARK,
1742 };
1744 /* AVB_AVTP_PPS */
1746 };
1748 AVB_AVTP_PPS_MARK,
1749 };
1751 /* AVB_AVTP_MATCH_A */
1753 };
1755 AVB_AVTP_MATCH_A_MARK,
1756 };
1758 /* AVB_AVTP_CAPTURE_A */
1760 };
1762 AVB_AVTP_CAPTURE_A_MARK,
1763 };
1765 /* AVB_AVTP_MATCH_B */
1767 };
1769 AVB_AVTP_MATCH_B_MARK,
1770 };
1772 /* AVB_AVTP_CAPTURE_B */
1774 };
1776 AVB_AVTP_CAPTURE_B_MARK,
1777 };
1779 /* - CAN ------------------------------------------------------------------ */
1781 /* TX, RX */
1783 };
1786 };
1788 /* TX, RX */
1790 };
1793 };
1795 /* TX, RX */
1797 };
1800 };
1802 /* - CAN Clock -------------------------------------------------------------- */
1804 /* CLK */
1806 };
1808 CAN_CLK_MARK,
1809 };
1811 /* - CAN FD --------------------------------------------------------------- */
1813 /* TX, RX */
1815 };
1818 };
1820 /* TX, RX */
1822 };
1825 };
1827 /* TX, RX */
1829 };
1832 };
1834 /* - DRIF0 --------------------------------------------------------------- */
1836 /* CLK, SYNC */
1838 };
1841 };
1843 /* D0 */
1845 };
1847 RIF0_D0_A_MARK,
1848 };
1850 /* D1 */
1852 };
1854 RIF0_D1_A_MARK,
1855 };
1857 /* CLK, SYNC */
1859 };
1862 };
1864 /* D0 */
1866 };
1868 RIF0_D0_B_MARK,
1869 };
1871 /* D1 */
1873 };
1875 RIF0_D1_B_MARK,
1876 };
1878 /* CLK, SYNC */
1880 };
1883 };
1885 /* D0 */
1887 };
1889 RIF0_D0_C_MARK,
1890 };
1892 /* D1 */
1894 };
1896 RIF0_D1_C_MARK,
1897 };
1898 /* - DRIF1 --------------------------------------------------------------- */
1900 /* CLK, SYNC */
1902 };
1905 };
1907 /* D0 */
1909 };
1911 RIF1_D0_A_MARK,
1912 };
1914 /* D1 */
1916 };
1918 RIF1_D1_A_MARK,
1919 };
1921 /* CLK, SYNC */
1923 };
1926 };
1928 /* D0 */
1930 };
1932 RIF1_D0_B_MARK,
1933 };
1935 /* D1 */
1937 };
1939 RIF1_D1_B_MARK,
1940 };
1942 /* CLK, SYNC */
1944 };
1947 };
1949 /* D0 */
1951 };
1953 RIF1_D0_C_MARK,
1954 };
1956 /* D1 */
1958 };
1960 RIF1_D1_C_MARK,
1961 };
1962 /* - DRIF2 --------------------------------------------------------------- */
1964 /* CLK, SYNC */
1966 };
1969 };
1971 /* D0 */
1973 };
1975 RIF2_D0_A_MARK,
1976 };
1978 /* D1 */
1980 };
1982 RIF2_D1_A_MARK,
1983 };
1985 /* CLK, SYNC */
1987 };
1990 };
1992 /* D0 */
1994 };
1996 RIF2_D0_B_MARK,
1997 };
1999 /* D1 */
2001 };
2003 RIF2_D1_B_MARK,
2004 };
2005 /* - DRIF3 --------------------------------------------------------------- */
2007 /* CLK, SYNC */
2009 };
2012 };
2014 /* D0 */
2016 };
2018 RIF3_D0_A_MARK,
2019 };
2021 /* D1 */
2023 };
2025 RIF3_D1_A_MARK,
2026 };
2028 /* CLK, SYNC */
2030 };
2033 };
2035 /* D0 */
2037 };
2039 RIF3_D0_B_MARK,
2040 };
2042 /* D1 */
2044 };
2046 RIF3_D1_B_MARK,
2047 };
2049 /* - DU --------------------------------------------------------------------- */
2051 /* R[7:2], G[7:2], B[7:2] */
2058 };
2066 };
2068 /* R[7:0], G[7:0], B[7:0] */
2078 };
2086 };
2088 /* CLKOUT */
2090 };
2092 DU_DOTCLKOUT0_MARK
2093 };
2095 /* CLKOUT */
2097 };
2099 DU_DOTCLKOUT1_MARK
2100 };
2102 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2104 };
2106 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2107 };
2109 /* EXDISP/EXODDF/EXCDE */
2111 };
2113 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2114 };
2116 /* CDE */
2118 };
2120 DU_CDE_MARK,
2121 };
2123 /* DISP */
2125 };
2127 DU_DISP_MARK,
2128 };
2130 /* - HSCIF0 ----------------------------------------------------------------- */
2132 /* RX, TX */
2134 };
2137 };
2139 /* SCK */
2141 };
2143 HSCK0_MARK,
2144 };
2146 /* RTS, CTS */
2148 };
2151 };
2152 /* - HSCIF1 ----------------------------------------------------------------- */
2154 /* RX, TX */
2156 };
2159 };
2161 /* SCK */
2163 };
2165 HSCK1_A_MARK,
2166 };
2168 /* RTS, CTS */
2170 };
2173 };
2176 /* RX, TX */
2178 };
2181 };
2183 /* SCK */
2185 };
2187 HSCK1_B_MARK,
2188 };
2190 /* RTS, CTS */
2192 };
2195 };
2196 /* - HSCIF2 ----------------------------------------------------------------- */
2198 /* RX, TX */
2200 };
2203 };
2205 /* SCK */
2207 };
2209 HSCK2_A_MARK,
2210 };
2212 /* RTS, CTS */
2214 };
2217 };
2220 /* RX, TX */
2222 };
2225 };
2227 /* SCK */
2229 };
2231 HSCK2_B_MARK,
2232 };
2234 /* RTS, CTS */
2236 };
2239 };
2242 /* RX, TX */
2244 };
2247 };
2249 /* SCK */
2251 };
2253 HSCK2_C_MARK,
2254 };
2256 /* RTS, CTS */
2258 };
2261 };
2262 /* - HSCIF3 ----------------------------------------------------------------- */
2264 /* RX, TX */
2266 };
2269 };
2271 /* SCK */
2273 };
2275 HSCK3_MARK,
2276 };
2278 /* RTS, CTS */
2280 };
2283 };
2286 /* RX, TX */
2288 };
2291 };
2293 /* RX, TX */
2295 };
2298 };
2300 /* RX, TX */
2302 };
2305 };
2306 /* - HSCIF4 ----------------------------------------------------------------- */
2308 /* RX, TX */
2310 };
2313 };
2315 /* SCK */
2317 };
2319 HSCK4_MARK,
2320 };
2322 /* RTS, CTS */
2324 };
2327 };
2330 /* RX, TX */
2332 };
2335 };
2337 /* - I2C -------------------------------------------------------------------- */
2339 /* SDA, SCL */
2341 };
2344 };
2346 /* SDA, SCL */
2348 };
2351 };
2353 /* SDA, SCL */
2355 };
2358 };
2360 /* SDA, SCL */
2362 };
2365 };
2367 /* SDA, SCL */
2369 };
2372 };
2374 /* SDA, SCL */
2376 };
2379 };
2381 /* SDA, SCL */
2383 };
2386 };
2388 /* - INTC-EX ---------------------------------------------------------------- */
2390 /* IRQ0 */
2392 };
2394 IRQ0_MARK,
2395 };
2397 /* IRQ1 */
2399 };
2401 IRQ1_MARK,
2402 };
2404 /* IRQ2 */
2406 };
2408 IRQ2_MARK,
2409 };
2411 /* IRQ3 */
2413 };
2415 IRQ3_MARK,
2416 };
2418 /* IRQ4 */
2420 };
2422 IRQ4_MARK,
2423 };
2425 /* IRQ5 */
2427 };
2429 IRQ5_MARK,
2430 };
2432 /* - MSIOF0 ----------------------------------------------------------------- */
2434 /* SCK */
2436 };
2438 MSIOF0_SCK_MARK,
2439 };
2441 /* SYNC */
2443 };
2445 MSIOF0_SYNC_MARK,
2446 };
2448 /* SS1 */
2450 };
2452 MSIOF0_SS1_MARK,
2453 };
2455 /* SS2 */
2457 };
2459 MSIOF0_SS2_MARK,
2460 };
2462 /* TXD */
2464 };
2466 MSIOF0_TXD_MARK,
2467 };
2469 /* RXD */
2471 };
2473 MSIOF0_RXD_MARK,
2474 };
2475 /* - MSIOF1 ----------------------------------------------------------------- */
2477 /* SCK */
2479 };
2481 MSIOF1_SCK_A_MARK,
2482 };
2484 /* SYNC */
2486 };
2488 MSIOF1_SYNC_A_MARK,
2489 };
2491 /* SS1 */
2493 };
2495 MSIOF1_SS1_A_MARK,
2496 };
2498 /* SS2 */
2500 };
2502 MSIOF1_SS2_A_MARK,
2503 };
2505 /* TXD */
2507 };
2509 MSIOF1_TXD_A_MARK,
2510 };
2512 /* RXD */
2514 };
2516 MSIOF1_RXD_A_MARK,
2517 };
2519 /* SCK */
2521 };
2523 MSIOF1_SCK_B_MARK,
2524 };
2526 /* SYNC */
2528 };
2530 MSIOF1_SYNC_B_MARK,
2531 };
2533 /* SS1 */
2535 };
2537 MSIOF1_SS1_B_MARK,
2538 };
2540 /* SS2 */
2542 };
2544 MSIOF1_SS2_B_MARK,
2545 };
2547 /* TXD */
2549 };
2551 MSIOF1_TXD_B_MARK,
2552 };
2554 /* RXD */
2556 };
2558 MSIOF1_RXD_B_MARK,
2559 };
2561 /* SCK */
2563 };
2565 MSIOF1_SCK_C_MARK,
2566 };
2568 /* SYNC */
2570 };
2572 MSIOF1_SYNC_C_MARK,
2573 };
2575 /* SS1 */
2577 };
2579 MSIOF1_SS1_C_MARK,
2580 };
2582 /* SS2 */
2584 };
2586 MSIOF1_SS2_C_MARK,
2587 };
2589 /* TXD */
2591 };
2593 MSIOF1_TXD_C_MARK,
2594 };
2596 /* RXD */
2598 };
2600 MSIOF1_RXD_C_MARK,
2601 };
2603 /* SCK */
2605 };
2607 MSIOF1_SCK_D_MARK,
2608 };
2610 /* SYNC */
2612 };
2614 MSIOF1_SYNC_D_MARK,
2615 };
2617 /* SS1 */
2619 };
2621 MSIOF1_SS1_D_MARK,
2622 };
2624 /* SS2 */
2626 };
2628 MSIOF1_SS2_D_MARK,
2629 };
2631 /* TXD */
2633 };
2635 MSIOF1_TXD_D_MARK,
2636 };
2638 /* RXD */
2640 };
2642 MSIOF1_RXD_D_MARK,
2643 };
2645 /* SCK */
2647 };
2649 MSIOF1_SCK_E_MARK,
2650 };
2652 /* SYNC */
2654 };
2656 MSIOF1_SYNC_E_MARK,
2657 };
2659 /* SS1 */
2661 };
2663 MSIOF1_SS1_E_MARK,
2664 };
2666 /* SS2 */
2668 };
2670 MSIOF1_SS2_E_MARK,
2671 };
2673 /* TXD */
2675 };
2677 MSIOF1_TXD_E_MARK,
2678 };
2680 /* RXD */
2682 };
2684 MSIOF1_RXD_E_MARK,
2685 };
2687 /* SCK */
2689 };
2691 MSIOF1_SCK_F_MARK,
2692 };
2694 /* SYNC */
2696 };
2698 MSIOF1_SYNC_F_MARK,
2699 };
2701 /* SS1 */
2703 };
2705 MSIOF1_SS1_F_MARK,
2706 };
2708 /* SS2 */
2710 };
2712 MSIOF1_SS2_F_MARK,
2713 };
2715 /* TXD */
2717 };
2719 MSIOF1_TXD_F_MARK,
2720 };
2722 /* RXD */
2724 };
2726 MSIOF1_RXD_F_MARK,
2727 };
2729 /* SCK */
2731 };
2733 MSIOF1_SCK_G_MARK,
2734 };
2736 /* SYNC */
2738 };
2740 MSIOF1_SYNC_G_MARK,
2741 };
2743 /* SS1 */
2745 };
2747 MSIOF1_SS1_G_MARK,
2748 };
2750 /* SS2 */
2752 };
2754 MSIOF1_SS2_G_MARK,
2755 };
2757 /* TXD */
2759 };
2761 MSIOF1_TXD_G_MARK,
2762 };
2764 /* RXD */
2766 };
2768 MSIOF1_RXD_G_MARK,
2769 };
2770 /* - MSIOF2 ----------------------------------------------------------------- */
2772 /* SCK */
2774 };
2776 MSIOF2_SCK_A_MARK,
2777 };
2779 /* SYNC */
2781 };
2783 MSIOF2_SYNC_A_MARK,
2784 };
2786 /* SS1 */
2788 };
2790 MSIOF2_SS1_A_MARK,
2791 };
2793 /* SS2 */
2795 };
2797 MSIOF2_SS2_A_MARK,
2798 };
2800 /* TXD */
2802 };
2804 MSIOF2_TXD_A_MARK,
2805 };
2807 /* RXD */
2809 };
2811 MSIOF2_RXD_A_MARK,
2812 };
2814 /* SCK */
2816 };
2818 MSIOF2_SCK_B_MARK,
2819 };
2821 /* SYNC */
2823 };
2825 MSIOF2_SYNC_B_MARK,
2826 };
2828 /* SS1 */
2830 };
2832 MSIOF2_SS1_B_MARK,
2833 };
2835 /* SS2 */
2837 };
2839 MSIOF2_SS2_B_MARK,
2840 };
2842 /* TXD */
2844 };
2846 MSIOF2_TXD_B_MARK,
2847 };
2849 /* RXD */
2851 };
2853 MSIOF2_RXD_B_MARK,
2854 };
2856 /* SCK */
2858 };
2860 MSIOF2_SCK_C_MARK,
2861 };
2863 /* SYNC */
2865 };
2867 MSIOF2_SYNC_C_MARK,
2868 };
2870 /* SS1 */
2872 };
2874 MSIOF2_SS1_C_MARK,
2875 };
2877 /* SS2 */
2879 };
2881 MSIOF2_SS2_C_MARK,
2882 };
2884 /* TXD */
2886 };
2888 MSIOF2_TXD_C_MARK,
2889 };
2891 /* RXD */
2893 };
2895 MSIOF2_RXD_C_MARK,
2896 };
2898 /* SCK */
2900 };
2902 MSIOF2_SCK_D_MARK,
2903 };
2905 /* SYNC */
2907 };
2909 MSIOF2_SYNC_D_MARK,
2910 };
2912 /* SS1 */
2914 };
2916 MSIOF2_SS1_D_MARK,
2917 };
2919 /* SS2 */
2921 };
2923 MSIOF2_SS2_D_MARK,
2924 };
2926 /* TXD */
2928 };
2930 MSIOF2_TXD_D_MARK,
2931 };
2933 /* RXD */
2935 };
2937 MSIOF2_RXD_D_MARK,
2938 };
2939 /* - MSIOF3 ----------------------------------------------------------------- */
2941 /* SCK */
2943 };
2945 MSIOF3_SCK_A_MARK,
2946 };
2948 /* SYNC */
2950 };
2952 MSIOF3_SYNC_A_MARK,
2953 };
2955 /* SS1 */
2957 };
2959 MSIOF3_SS1_A_MARK,
2960 };
2962 /* SS2 */
2964 };
2966 MSIOF3_SS2_A_MARK,
2967 };
2969 /* TXD */
2971 };
2973 MSIOF3_TXD_A_MARK,
2974 };
2976 /* RXD */
2978 };
2980 MSIOF3_RXD_A_MARK,
2981 };
2983 /* SCK */
2985 };
2987 MSIOF3_SCK_B_MARK,
2988 };
2990 /* SYNC */
2992 };
2994 MSIOF3_SYNC_B_MARK,
2995 };
2997 /* SS1 */
2999 };
3001 MSIOF3_SS1_B_MARK,
3002 };
3004 /* SS2 */
3006 };
3008 MSIOF3_SS2_B_MARK,
3009 };
3011 /* TXD */
3013 };
3015 MSIOF3_TXD_B_MARK,
3016 };
3018 /* RXD */
3020 };
3022 MSIOF3_RXD_B_MARK,
3023 };
3025 /* SCK */
3027 };
3029 MSIOF3_SCK_C_MARK,
3030 };
3032 /* SYNC */
3034 };
3036 MSIOF3_SYNC_C_MARK,
3037 };
3039 /* TXD */
3041 };
3043 MSIOF3_TXD_C_MARK,
3044 };
3046 /* RXD */
3048 };
3050 MSIOF3_RXD_C_MARK,
3051 };
3053 /* SCK */
3055 };
3057 MSIOF3_SCK_D_MARK,
3058 };
3060 /* SYNC */
3062 };
3064 MSIOF3_SYNC_D_MARK,
3065 };
3067 /* SS1 */
3069 };
3071 MSIOF3_SS1_D_MARK,
3072 };
3074 /* TXD */
3076 };
3078 MSIOF3_TXD_D_MARK,
3079 };
3081 /* RXD */
3083 };
3085 MSIOF3_RXD_D_MARK,
3086 };
3088 /* SCK */
3090 };
3092 MSIOF3_SCK_E_MARK,
3093 };
3095 /* SYNC */
3097 };
3099 MSIOF3_SYNC_E_MARK,
3100 };
3102 /* SS1 */
3104 };
3106 MSIOF3_SS1_E_MARK,
3107 };
3109 /* SS1 */
3111 };
3113 MSIOF3_SS2_E_MARK,
3114 };
3116 /* TXD */
3118 };
3120 MSIOF3_TXD_E_MARK,
3121 };
3123 /* RXD */
3125 };
3127 MSIOF3_RXD_E_MARK,
3128 };
3130 /* - PWM0 --------------------------------------------------------------------*/
3132 /* PWM */
3134 };
3136 PWM0_MARK,
3137 };
3138 /* - PWM1 --------------------------------------------------------------------*/
3140 /* PWM */
3142 };
3144 PWM1_A_MARK,
3145 };
3147 /* PWM */
3149 };
3151 PWM1_B_MARK,
3152 };
3153 /* - PWM2 --------------------------------------------------------------------*/
3155 /* PWM */
3157 };
3159 PWM2_A_MARK,
3160 };
3162 /* PWM */
3164 };
3166 PWM2_B_MARK,
3167 };
3168 /* - PWM3 --------------------------------------------------------------------*/
3170 /* PWM */
3172 };
3174 PWM3_A_MARK,
3175 };
3177 /* PWM */
3179 };
3181 PWM3_B_MARK,
3182 };
3183 /* - PWM4 --------------------------------------------------------------------*/
3185 /* PWM */
3187 };
3189 PWM4_A_MARK,
3190 };
3192 /* PWM */
3194 };
3196 PWM4_B_MARK,
3197 };
3198 /* - PWM5 --------------------------------------------------------------------*/
3200 /* PWM */
3202 };
3204 PWM5_A_MARK,
3205 };
3207 /* PWM */
3209 };
3211 PWM5_B_MARK,
3212 };
3213 /* - PWM6 --------------------------------------------------------------------*/
3215 /* PWM */
3217 };
3219 PWM6_A_MARK,
3220 };
3222 /* PWM */
3224 };
3226 PWM6_B_MARK,
3227 };
3229 /* - SATA --------------------------------------------------------------------*/
3231 /* DEVSLP */
3233 };
3235 SATA_DEVSLP_A_MARK,
3236 };
3238 /* DEVSLP */
3240 };
3242 SATA_DEVSLP_B_MARK,
3243 };
3245 /* - SCIF0 ------------------------------------------------------------------ */
3247 /* RX, TX */
3249 };
3252 };
3254 /* SCK */
3256 };
3258 SCK0_MARK,
3259 };
3261 /* RTS, CTS */
3263 };
3266 };
3267 /* - SCIF1 ------------------------------------------------------------------ */
3269 /* RX, TX */
3271 };
3274 };
3276 /* SCK */
3278 };
3280 SCK1_MARK,
3281 };
3283 /* RTS, CTS */
3285 };
3288 };
3291 /* RX, TX */
3293 };
3296 };
3297 /* - SCIF2 ------------------------------------------------------------------ */
3299 /* RX, TX */
3301 };
3304 };
3306 /* SCK */
3308 };
3310 SCK2_MARK,
3311 };
3313 /* RX, TX */
3315 };
3318 };
3319 /* - SCIF3 ------------------------------------------------------------------ */
3321 /* RX, TX */
3323 };
3326 };
3328 /* SCK */
3330 };
3332 SCK3_MARK,
3333 };
3335 /* RTS, CTS */
3337 };
3340 };
3342 /* RX, TX */
3344 };
3347 };
3348 /* - SCIF4 ------------------------------------------------------------------ */
3350 /* RX, TX */
3352 };
3355 };
3357 /* SCK */
3359 };
3361 SCK4_A_MARK,
3362 };
3364 /* RTS, CTS */
3366 };
3369 };
3371 /* RX, TX */
3373 };
3376 };
3378 /* SCK */
3380 };
3382 SCK4_B_MARK,
3383 };
3385 /* RTS, CTS */
3387 };
3390 };
3392 /* RX, TX */
3394 };
3397 };
3399 /* SCK */
3401 };
3403 SCK4_C_MARK,
3404 };
3406 /* RTS, CTS */
3408 };
3411 };
3412 /* - SCIF5 ------------------------------------------------------------------ */
3414 /* RX, TX */
3416 };
3419 };
3421 /* SCK */
3423 };
3425 SCK5_A_MARK,
3426 };
3428 /* RX, TX */
3430 };
3433 };
3435 /* SCK */
3437 };
3439 SCK5_B_MARK,
3440 };
3442 /* - SCIF Clock ------------------------------------------------------------- */
3444 /* SCIF_CLK */
3446 };
3448 SCIF_CLK_A_MARK,
3449 };
3451 /* SCIF_CLK */
3453 };
3455 SCIF_CLK_B_MARK,
3456 };
3458 /* - SDHI0 ------------------------------------------------------------------ */
3460 /* D0 */
3462 };
3464 SD0_DAT0_MARK,
3465 };
3467 /* D[0:3] */
3470 };
3474 };
3476 /* CLK, CMD */
3478 };
3481 };
3483 /* CD */
3485 };
3487 SD0_CD_MARK,
3488 };
3490 /* WP */
3492 };
3494 SD0_WP_MARK,
3495 };
3496 /* - SDHI1 ------------------------------------------------------------------ */
3498 /* D0 */
3500 };
3502 SD1_DAT0_MARK,
3503 };
3505 /* D[0:3] */
3508 };
3512 };
3514 /* CLK, CMD */
3516 };
3519 };
3521 /* CD */
3523 };
3525 SD1_CD_MARK,
3526 };
3528 /* WP */
3530 };
3532 SD1_WP_MARK,
3533 };
3534 /* - SDHI2 ------------------------------------------------------------------ */
3536 /* D0 */
3538 };
3540 SD2_DAT0_MARK,
3541 };
3543 /* D[0:3] */
3546 };
3550 };
3552 /* D[0:7] */
3557 };
3563 };
3565 /* CLK, CMD */
3567 };
3570 };
3572 /* CD */
3574 };
3576 SD2_CD_A_MARK,
3577 };
3579 /* CD */
3581 };
3583 SD2_CD_B_MARK,
3584 };
3586 /* WP */
3588 };
3590 SD2_WP_A_MARK,
3591 };
3593 /* WP */
3595 };
3597 SD2_WP_B_MARK,
3598 };
3600 /* DS */
3602 };
3604 SD2_DS_MARK,
3605 };
3606 /* - SDHI3 ------------------------------------------------------------------ */
3608 /* D0 */
3610 };
3612 SD3_DAT0_MARK,
3613 };
3615 /* D[0:3] */
3618 };
3622 };
3624 /* D[0:7] */
3629 };
3635 };
3637 /* CLK, CMD */
3639 };
3642 };
3644 /* CD */
3646 };
3648 SD3_CD_MARK,
3649 };
3651 /* WP */
3653 };
3655 SD3_WP_MARK,
3656 };
3658 /* DS */
3660 };
3662 SD3_DS_MARK,
3663 };
3665 /* - SSI -------------------------------------------------------------------- */
3667 /* SDATA */
3669 };
3671 SSI_SDATA0_MARK,
3672 };
3674 /* SCK, WS */
3676 };
3679 };
3681 /* SDATA */
3683 };
3685 SSI_SDATA1_A_MARK,
3686 };
3688 /* SDATA */
3690 };
3692 SSI_SDATA1_B_MARK,
3693 };
3695 /* SCK, WS */
3697 };
3700 };
3702 /* SCK, WS */
3704 };
3707 };
3709 /* SDATA */
3711 };
3713 SSI_SDATA2_A_MARK,
3714 };
3716 /* SDATA */
3718 };
3720 SSI_SDATA2_B_MARK,
3721 };
3723 /* SCK, WS */
3725 };
3728 };
3730 /* SCK, WS */
3732 };
3735 };
3737 /* SDATA */
3739 };
3741 SSI_SDATA3_MARK,
3742 };
3744 /* SCK, WS */
3746 };
3749 };
3751 /* SDATA */
3753 };
3755 SSI_SDATA4_MARK,
3756 };
3758 /* SCK, WS */
3760 };
3763 };
3765 /* SDATA */
3767 };
3769 SSI_SDATA5_MARK,
3770 };
3772 /* SCK, WS */
3774 };
3777 };
3779 /* SDATA */
3781 };
3783 SSI_SDATA6_MARK,
3784 };
3786 /* SCK, WS */
3788 };
3791 };
3793 /* SDATA */
3795 };
3797 SSI_SDATA7_MARK,
3798 };
3800 /* SCK, WS */
3802 };
3805 };
3807 /* SDATA */
3809 };
3811 SSI_SDATA8_MARK,
3812 };
3814 /* SDATA */
3816 };
3818 SSI_SDATA9_A_MARK,
3819 };
3821 /* SDATA */
3823 };
3825 SSI_SDATA9_B_MARK,
3826 };
3828 /* SCK, WS */
3830 };
3833 };
3835 /* SCK, WS */
3837 };
3840 };
3842 /* - USB0 ------------------------------------------------------------------- */
3844 /* PWEN, OVC */
3846 };
3849 };
3850 /* - USB1 ------------------------------------------------------------------- */
3852 /* PWEN, OVC */
3854 };
3857 };
3858 /* - USB2 ------------------------------------------------------------------- */
3860 /* PWEN, OVC */
3862 };
3865 };
3866 /* - USB2_CH3 --------------------------------------------------------------- */
3868 /* PWEN, OVC */
3870 };
3873 };
3875 /* - USB30 ------------------------------------------------------------------ */
3877 /* PWEN, OVC */
3879 };
3882 };
4197 };
4217 };
4230 };
4235 };
4239 };
4243 };
4248 };
4252 };
4264 };
4276 };
4285 };
4294 };
4305 };
4311 };
4320 };
4332 };
4341 };
4348 };
4353 };
4358 };
4364 };
4373 };
4382 };
4427 };
4454 };
4484 };
4488 };
4493 };
4498 };
4503 };
4508 };
4513 };
4518 };
4523 };
4529 };
4536 };
4542 };
4549 };
4561 };
4568 };
4573 };
4581 };
4589 };
4601 };
4611 };
4639 };
4643 };
4647 };
4651 };
4655 };
4659 };
4712 };
4715 #define F_(x, y) FN_##y
4716 #define FM(x) FN_##x
4750 },
4784 },
4818 },
4852 },
4886 },
4920 },
4954 },
4988 },
4989 #undef F_
4990 #undef FM
4992 #define F_(x, y) x,
4993 #define FM(x) FN_##x,
4995 IP0_31_28
4996 IP0_27_24
4997 IP0_23_20
4998 IP0_19_16
4999 IP0_15_12
5000 IP0_11_8
5001 IP0_7_4
5002 IP0_3_0 }
5003 },
5005 IP1_31_28
5006 IP1_27_24
5007 IP1_23_20
5008 IP1_19_16
5009 IP1_15_12
5010 IP1_11_8
5011 IP1_7_4
5012 IP1_3_0 }
5013 },
5015 IP2_31_28
5016 IP2_27_24
5017 IP2_23_20
5018 IP2_19_16
5019 IP2_15_12
5020 IP2_11_8
5021 IP2_7_4
5022 IP2_3_0 }
5023 },
5025 IP3_31_28
5026 IP3_27_24
5027 IP3_23_20
5028 IP3_19_16
5029 IP3_15_12
5030 IP3_11_8
5031 IP3_7_4
5032 IP3_3_0 }
5033 },
5035 IP4_31_28
5036 IP4_27_24
5037 IP4_23_20
5038 IP4_19_16
5039 IP4_15_12
5040 IP4_11_8
5041 IP4_7_4
5042 IP4_3_0 }
5043 },
5045 IP5_31_28
5046 IP5_27_24
5047 IP5_23_20
5048 IP5_19_16
5049 IP5_15_12
5050 IP5_11_8
5051 IP5_7_4
5052 IP5_3_0 }
5053 },
5055 IP6_31_28
5056 IP6_27_24
5057 IP6_23_20
5058 IP6_19_16
5059 IP6_15_12
5060 IP6_11_8
5061 IP6_7_4
5062 IP6_3_0 }
5063 },
5065 IP7_31_28
5066 IP7_27_24
5067 IP7_23_20
5068 IP7_19_16
5070 IP7_11_8
5071 IP7_7_4
5072 IP7_3_0 }
5073 },
5075 IP8_31_28
5076 IP8_27_24
5077 IP8_23_20
5078 IP8_19_16
5079 IP8_15_12
5080 IP8_11_8
5081 IP8_7_4
5082 IP8_3_0 }
5083 },
5085 IP9_31_28
5086 IP9_27_24
5087 IP9_23_20
5088 IP9_19_16
5089 IP9_15_12
5090 IP9_11_8
5091 IP9_7_4
5092 IP9_3_0 }
5093 },
5095 IP10_31_28
5096 IP10_27_24
5097 IP10_23_20
5098 IP10_19_16
5099 IP10_15_12
5100 IP10_11_8
5101 IP10_7_4
5102 IP10_3_0 }
5103 },
5105 IP11_31_28
5106 IP11_27_24
5107 IP11_23_20
5108 IP11_19_16
5109 IP11_15_12
5110 IP11_11_8
5111 IP11_7_4
5112 IP11_3_0 }
5113 },
5115 IP12_31_28
5116 IP12_27_24
5117 IP12_23_20
5118 IP12_19_16
5119 IP12_15_12
5120 IP12_11_8
5121 IP12_7_4
5122 IP12_3_0 }
5123 },
5125 IP13_31_28
5126 IP13_27_24
5127 IP13_23_20
5128 IP13_19_16
5129 IP13_15_12
5130 IP13_11_8
5131 IP13_7_4
5132 IP13_3_0 }
5133 },
5135 IP14_31_28
5136 IP14_27_24
5137 IP14_23_20
5138 IP14_19_16
5139 IP14_15_12
5140 IP14_11_8
5141 IP14_7_4
5142 IP14_3_0 }
5143 },
5145 IP15_31_28
5146 IP15_27_24
5147 IP15_23_20
5148 IP15_19_16
5149 IP15_15_12
5150 IP15_11_8
5151 IP15_7_4
5152 IP15_3_0 }
5153 },
5155 IP16_31_28
5156 IP16_27_24
5157 IP16_23_20
5158 IP16_19_16
5159 IP16_15_12
5160 IP16_11_8
5161 IP16_7_4
5162 IP16_3_0 }
5163 },
5165 IP17_31_28
5166 IP17_27_24
5167 IP17_23_20
5168 IP17_19_16
5169 IP17_15_12
5170 IP17_11_8
5171 IP17_7_4
5172 IP17_3_0 }
5173 },
5181 IP18_7_4
5182 IP18_3_0 }
5183 },
5184 #undef F_
5185 #undef FM
5187 #define F_(x, y) x,
5188 #define FM(x) FN_##x,
5192 MOD_SEL0_31_30_29
5193 MOD_SEL0_28_27
5194 MOD_SEL0_26_25_24
5195 MOD_SEL0_23
5196 MOD_SEL0_22
5197 MOD_SEL0_21
5198 MOD_SEL0_20
5199 MOD_SEL0_19
5200 MOD_SEL0_18_17
5201 MOD_SEL0_16
5203 MOD_SEL0_14_13
5204 MOD_SEL0_12
5205 MOD_SEL0_11
5206 MOD_SEL0_10
5207 MOD_SEL0_9_8
5208 MOD_SEL0_7_6
5209 MOD_SEL0_5
5210 MOD_SEL0_4_3
5211 /* RESERVED 2, 1, 0 */
5213 },
5217 MOD_SEL1_31_30
5218 MOD_SEL1_29_28_27
5219 MOD_SEL1_26
5220 MOD_SEL1_25_24
5221 MOD_SEL1_23_22_21
5222 MOD_SEL1_20
5223 MOD_SEL1_19
5224 MOD_SEL1_18_17
5225 MOD_SEL1_16
5226 MOD_SEL1_15_14
5227 MOD_SEL1_13
5228 MOD_SEL1_12
5229 MOD_SEL1_11
5230 MOD_SEL1_10
5231 MOD_SEL1_9
5233 MOD_SEL1_6
5234 MOD_SEL1_5
5235 MOD_SEL1_4
5236 MOD_SEL1_3
5237 MOD_SEL1_2
5238 MOD_SEL1_1
5239 MOD_SEL1_0 }
5240 },
5244 MOD_SEL2_31
5245 MOD_SEL2_30
5246 MOD_SEL2_29
5247 MOD_SEL2_28_27
5248 MOD_SEL2_26
5249 MOD_SEL2_25_24_23
5250 /* RESERVED 22 */
5252 MOD_SEL2_21
5253 MOD_SEL2_20
5254 MOD_SEL2_19
5255 MOD_SEL2_18
5256 MOD_SEL2_17
5257 /* RESERVED 16 */
5259 /* RESERVED 15, 14, 13, 12 */
5262 /* RESERVED 11, 10, 9, 8 */
5265 /* RESERVED 7, 6, 5, 4 */
5268 /* RESERVED 3, 2, 1 */
5270 MOD_SEL2_0 }
5271 },
5272 { },
5273 };
5285 } },
5295 } },
5305 } },
5315 } },
5325 } },
5335 } },
5345 } },
5355 } },
5365 } },
5375 } },
5385 } },
5395 } },
5401 } },
5411 } },
5421 } },
5431 } },
5441 } },
5451 } },
5461 } },
5471 } },
5481 } },
5491 } },
5501 } },
5511 } },
5520 } },
5521 { },
5522 };
5525 POCCTRL,
5526 };
5531 };
5534 {
5546 }
5582 } },
5616 } },
5650 } },
5684 } },
5718 } },
5752 } },
5786 } },
5788 };
5792 {
5804 else
5806 }
5810 {
5829 }
5834 };
5837 {
5842 }
5849 };
5872 };