| blob | e5807d1ce0dccbb660bcc81f6e80f7c126061d4c |
1 /*
2 * R8A7796 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 *
6 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
7 *
8 * R-Car Gen3 processor support - PFC hardware block.
9 *
10 * Copyright (C) 2015 Renesas Electronics Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 */
17 #include <linux/kernel.h>
22 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
23 SH_PFC_PIN_CFG_PULL_UP | \
24 SH_PFC_PIN_CFG_PULL_DOWN)
26 #define CPU_ALL_PORT(fn, sfx) \
27 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
36 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
39 /*
40 * F_() : just information
41 * FM() : macro for FN_xxx / xxx_MARK
42 */
44 /* GPSR0 */
45 #define GPSR0_15 F_(D15, IP7_11_8)
46 #define GPSR0_14 F_(D14, IP7_7_4)
47 #define GPSR0_13 F_(D13, IP7_3_0)
48 #define GPSR0_12 F_(D12, IP6_31_28)
49 #define GPSR0_11 F_(D11, IP6_27_24)
50 #define GPSR0_10 F_(D10, IP6_23_20)
51 #define GPSR0_9 F_(D9, IP6_19_16)
52 #define GPSR0_8 F_(D8, IP6_15_12)
53 #define GPSR0_7 F_(D7, IP6_11_8)
54 #define GPSR0_6 F_(D6, IP6_7_4)
55 #define GPSR0_5 F_(D5, IP6_3_0)
56 #define GPSR0_4 F_(D4, IP5_31_28)
57 #define GPSR0_3 F_(D3, IP5_27_24)
58 #define GPSR0_2 F_(D2, IP5_23_20)
59 #define GPSR0_1 F_(D1, IP5_19_16)
60 #define GPSR0_0 F_(D0, IP5_15_12)
62 /* GPSR1 */
63 #define GPSR1_28 FM(CLKOUT)
64 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
65 #define GPSR1_26 F_(WE1_N, IP5_7_4)
66 #define GPSR1_25 F_(WE0_N, IP5_3_0)
67 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
68 #define GPSR1_23 F_(RD_N, IP4_27_24)
69 #define GPSR1_22 F_(BS_N, IP4_23_20)
70 #define GPSR1_21 F_(CS1_N, IP4_19_16)
71 #define GPSR1_20 F_(CS0_N, IP4_15_12)
72 #define GPSR1_19 F_(A19, IP4_11_8)
73 #define GPSR1_18 F_(A18, IP4_7_4)
74 #define GPSR1_17 F_(A17, IP4_3_0)
75 #define GPSR1_16 F_(A16, IP3_31_28)
76 #define GPSR1_15 F_(A15, IP3_27_24)
77 #define GPSR1_14 F_(A14, IP3_23_20)
78 #define GPSR1_13 F_(A13, IP3_19_16)
79 #define GPSR1_12 F_(A12, IP3_15_12)
80 #define GPSR1_11 F_(A11, IP3_11_8)
81 #define GPSR1_10 F_(A10, IP3_7_4)
82 #define GPSR1_9 F_(A9, IP3_3_0)
83 #define GPSR1_8 F_(A8, IP2_31_28)
84 #define GPSR1_7 F_(A7, IP2_27_24)
85 #define GPSR1_6 F_(A6, IP2_23_20)
86 #define GPSR1_5 F_(A5, IP2_19_16)
87 #define GPSR1_4 F_(A4, IP2_15_12)
88 #define GPSR1_3 F_(A3, IP2_11_8)
89 #define GPSR1_2 F_(A2, IP2_7_4)
90 #define GPSR1_1 F_(A1, IP2_3_0)
91 #define GPSR1_0 F_(A0, IP1_31_28)
93 /* GPSR2 */
94 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
95 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
96 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
97 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
98 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
99 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
100 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
101 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
102 #define GPSR2_6 F_(PWM0, IP1_19_16)
103 #define GPSR2_5 F_(IRQ5, IP1_15_12)
104 #define GPSR2_4 F_(IRQ4, IP1_11_8)
105 #define GPSR2_3 F_(IRQ3, IP1_7_4)
106 #define GPSR2_2 F_(IRQ2, IP1_3_0)
107 #define GPSR2_1 F_(IRQ1, IP0_31_28)
108 #define GPSR2_0 F_(IRQ0, IP0_27_24)
110 /* GPSR3 */
111 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
112 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
113 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
114 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
115 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
116 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
117 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
118 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
119 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
120 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
121 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
122 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
123 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
124 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
125 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
126 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
128 /* GPSR4 */
129 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
130 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
131 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
132 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
133 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
134 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
135 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
136 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
137 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
138 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
139 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
140 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
141 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
142 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
143 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
144 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
145 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
146 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
148 /* GPSR5 */
149 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
150 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
151 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
152 #define GPSR5_22 FM(MSIOF0_RXD)
153 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
154 #define GPSR5_20 FM(MSIOF0_TXD)
155 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
156 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
157 #define GPSR5_17 FM(MSIOF0_SCK)
158 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
159 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
160 #define GPSR5_14 F_(HTX0, IP13_19_16)
161 #define GPSR5_13 F_(HRX0, IP13_15_12)
162 #define GPSR5_12 F_(HSCK0, IP13_11_8)
163 #define GPSR5_11 F_(RX2_A, IP13_7_4)
164 #define GPSR5_10 F_(TX2_A, IP13_3_0)
165 #define GPSR5_9 F_(SCK2, IP12_31_28)
166 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
167 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
168 #define GPSR5_6 F_(TX1_A, IP12_19_16)
169 #define GPSR5_5 F_(RX1_A, IP12_15_12)
170 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
171 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
172 #define GPSR5_2 F_(TX0, IP12_3_0)
173 #define GPSR5_1 F_(RX0, IP11_31_28)
174 #define GPSR5_0 F_(SCK0, IP11_27_24)
176 /* GPSR6 */
177 #define GPSR6_31 F_(GP6_31, IP18_7_4)
178 #define GPSR6_30 F_(GP6_30, IP18_3_0)
179 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
180 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
181 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
182 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
183 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
184 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
185 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
186 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
187 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
188 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
189 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
190 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
191 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
192 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
193 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
194 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
195 #define GPSR6_13 FM(SSI_SDATA5)
196 #define GPSR6_12 FM(SSI_WS5)
197 #define GPSR6_11 FM(SSI_SCK5)
198 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
199 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
200 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
201 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
202 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
203 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
204 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
205 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
206 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
207 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
208 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
210 /* GPSR7 */
211 #define GPSR7_3 FM(GP7_03)
212 #define GPSR7_2 FM(HDMI0_CEC)
213 #define GPSR7_1 FM(AVS2)
214 #define GPSR7_0 FM(AVS1)
217 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
218 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
247 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
278 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
314 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
335 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
344 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
364 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
365 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
366 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
367 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
368 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
370 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
372 #define PINMUX_GPSR \
373 \
374 GPSR6_31 \
375 GPSR6_30 \
376 GPSR6_29 \
377 GPSR1_28 GPSR6_28 \
378 GPSR1_27 GPSR6_27 \
379 GPSR1_26 GPSR6_26 \
380 GPSR1_25 GPSR5_25 GPSR6_25 \
381 GPSR1_24 GPSR5_24 GPSR6_24 \
382 GPSR1_23 GPSR5_23 GPSR6_23 \
383 GPSR1_22 GPSR5_22 GPSR6_22 \
384 GPSR1_21 GPSR5_21 GPSR6_21 \
385 GPSR1_20 GPSR5_20 GPSR6_20 \
386 GPSR1_19 GPSR5_19 GPSR6_19 \
387 GPSR1_18 GPSR5_18 GPSR6_18 \
388 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
389 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
390 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
391 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
392 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
393 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
394 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
395 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
396 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
397 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
398 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
399 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
400 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
401 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
402 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
403 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
404 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
405 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
407 #define PINMUX_IPSR \
408 \
409 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
410 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
411 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
412 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
413 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
414 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
415 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
416 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
417 \
418 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
419 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
420 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
421 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
422 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
423 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
424 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
425 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
426 \
427 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
428 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
429 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
430 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
431 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
432 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
433 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
434 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
435 \
436 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
437 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
438 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
439 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
440 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
441 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
442 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
443 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
444 \
445 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
446 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
447 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
448 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
449 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
450 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
451 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
452 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
455 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
456 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
457 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
458 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
459 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
460 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
461 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
462 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
463 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
464 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
465 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
466 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
467 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
468 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
469 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
470 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
471 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
472 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
475 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
476 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
477 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
478 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
479 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
480 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
481 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
482 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
483 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
484 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
485 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
486 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
487 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
488 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
489 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
490 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
491 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
492 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
493 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
494 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
495 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
496 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
499 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
500 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
501 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
502 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
503 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
504 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
505 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
506 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
507 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
508 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
509 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
510 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
511 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
513 #define PINMUX_MOD_SELS \
514 \
515 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
516 MOD_SEL2_30 \
517 MOD_SEL1_29_28_27 MOD_SEL2_29 \
518 MOD_SEL0_28_27 MOD_SEL2_28_27 \
519 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
520 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
521 MOD_SEL0_23 MOD_SEL1_23_22_21 \
522 MOD_SEL0_22 MOD_SEL2_22 \
523 MOD_SEL0_21 MOD_SEL2_21 \
524 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
525 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
526 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
527 MOD_SEL2_17 \
528 MOD_SEL0_16 MOD_SEL1_16 \
529 MOD_SEL1_15_14 \
530 MOD_SEL0_14_13 \
531 MOD_SEL1_13 \
532 MOD_SEL0_12 MOD_SEL1_12 \
533 MOD_SEL0_11 MOD_SEL1_11 \
534 MOD_SEL0_10 MOD_SEL1_10 \
535 MOD_SEL0_9_8 MOD_SEL1_9 \
536 MOD_SEL0_7_6 \
537 MOD_SEL1_6 \
538 MOD_SEL0_5 MOD_SEL1_5 \
539 MOD_SEL0_4_3 MOD_SEL1_4 \
540 MOD_SEL1_3 \
541 MOD_SEL1_2 \
542 MOD_SEL1_1 \
543 MOD_SEL1_0 MOD_SEL2_0
545 /*
546 * These pins are not able to be muxed but have other properties
547 * that can be set, such as drive-strength or pull-up/pull-down enable.
548 */
549 #define PINMUX_STATIC \
550 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
551 FM(QSPI0_IO2) FM(QSPI0_IO3) \
552 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
553 FM(QSPI1_IO2) FM(QSPI1_IO3) \
554 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
555 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
556 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
557 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
558 FM(PRESETOUT) \
559 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
560 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
565 PINMUX_DATA_BEGIN,
567 PINMUX_DATA_END,
569 #define F_(x, y)
570 #define FM(x) FN_##x,
571 PINMUX_FUNCTION_BEGIN,
573 PINMUX_GPSR
574 PINMUX_IPSR
575 PINMUX_MOD_SELS
576 PINMUX_FUNCTION_END,
577 #undef F_
578 #undef FM
580 #define F_(x, y)
581 #define FM(x) x##_MARK,
582 PINMUX_MARK_BEGIN,
583 PINMUX_GPSR
584 PINMUX_IPSR
585 PINMUX_MOD_SELS
586 PINMUX_STATIC
587 PINMUX_MARK_END,
588 #undef F_
589 #undef FM
590 };
607 /* IPSR0 */
647 /* IPSR1 */
697 /* IPSR2 */
758 /* IPSR3 */
812 /* IPSR4 */
858 /* IPSR5 */
908 /* IPSR6 */
960 /* IPSR7 */
1002 /* IPSR8 */
1051 /* IPSR9 */
1076 /* IPSR10 */
1104 /* IPSR11 */
1142 /* IPSR12 */
1203 /* IPSR13 */
1263 /* IPSR14 */
1304 /* IPSR15 */
1351 /* IPSR16 */
1403 /* IPSR17 */
1470 /* IPSR18 */
1491 /* I2C */
1496 /*
1497 * Static pins can not be muxed between different functions but
1498 * still needs a mark entry in the pinmux list. Add each static
1499 * pin to the list without an associated function. The sh-pfc
1500 * core will do the right thing and skip trying to mux then pin
1501 * while still applying configuration to it
1502 */
1503 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1504 PINMUX_STATIC
1505 #undef FM
1506 };
1508 /*
1509 * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1510 * Physical layout rows: A - AW, cols: 1 - 39.
1511 */
1514 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1515 #define PIN_NONE U16_MAX
1520 /*
1521 * Pins not associated with a GPIO port.
1522 *
1523 * The pin positions are different between different r8a7796
1524 * packages, all that is needed for the pfc driver is a unique
1525 * number for each pin. To this end use the pin layout from
1526 * R-Car M3SiP to calculate a unique number for each pin.
1527 */
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1570 };
1572 /* - AUDIO CLOCK ------------------------------------------------------------ */
1574 /* CLK A */
1576 };
1578 AUDIO_CLKA_A_MARK,
1579 };
1581 /* CLK A */
1583 };
1585 AUDIO_CLKA_B_MARK,
1586 };
1588 /* CLK A */
1590 };
1592 AUDIO_CLKA_C_MARK,
1593 };
1595 /* CLK B */
1597 };
1599 AUDIO_CLKB_A_MARK,
1600 };
1602 /* CLK B */
1604 };
1606 AUDIO_CLKB_B_MARK,
1607 };
1609 /* CLK C */
1611 };
1613 AUDIO_CLKC_A_MARK,
1614 };
1616 /* CLK C */
1618 };
1620 AUDIO_CLKC_B_MARK,
1621 };
1623 /* CLKOUT */
1625 };
1627 AUDIO_CLKOUT_A_MARK,
1628 };
1630 /* CLKOUT */
1632 };
1634 AUDIO_CLKOUT_B_MARK,
1635 };
1637 /* CLKOUT */
1639 };
1641 AUDIO_CLKOUT_C_MARK,
1642 };
1644 /* CLKOUT */
1646 };
1648 AUDIO_CLKOUT_D_MARK,
1649 };
1651 /* CLKOUT1 */
1653 };
1655 AUDIO_CLKOUT1_A_MARK,
1656 };
1658 /* CLKOUT1 */
1660 };
1662 AUDIO_CLKOUT1_B_MARK,
1663 };
1665 /* CLKOUT2 */
1667 };
1669 AUDIO_CLKOUT2_A_MARK,
1670 };
1672 /* CLKOUT2 */
1674 };
1676 AUDIO_CLKOUT2_B_MARK,
1677 };
1680 /* CLKOUT3 */
1682 };
1684 AUDIO_CLKOUT3_A_MARK,
1685 };
1687 /* CLKOUT3 */
1689 };
1691 AUDIO_CLKOUT3_B_MARK,
1692 };
1694 /* - EtherAVB --------------------------------------------------------------- */
1696 /* AVB_LINK */
1698 };
1700 AVB_LINK_MARK,
1701 };
1703 /* AVB_MAGIC_ */
1705 };
1707 AVB_MAGIC_MARK,
1708 };
1710 /* AVB_PHY_INT */
1712 };
1714 AVB_PHY_INT_MARK,
1715 };
1717 /* AVB_MDC, AVB_MDIO */
1719 };
1722 };
1724 /*
1725 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1726 * AVB_TD1, AVB_TD2, AVB_TD3,
1727 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1728 * AVB_RD1, AVB_RD2, AVB_RD3,
1729 * AVB_TXCREFCLK
1730 */
1737 };
1743 AVB_TXCREFCLK_MARK,
1744 };
1746 /* AVB_AVTP_PPS */
1748 };
1750 AVB_AVTP_PPS_MARK,
1751 };
1753 /* AVB_AVTP_MATCH_A */
1755 };
1757 AVB_AVTP_MATCH_A_MARK,
1758 };
1760 /* AVB_AVTP_CAPTURE_A */
1762 };
1764 AVB_AVTP_CAPTURE_A_MARK,
1765 };
1767 /* AVB_AVTP_MATCH_B */
1769 };
1771 AVB_AVTP_MATCH_B_MARK,
1772 };
1774 /* AVB_AVTP_CAPTURE_B */
1776 };
1778 AVB_AVTP_CAPTURE_B_MARK,
1779 };
1781 /* - CAN ------------------------------------------------------------------ */
1783 /* TX, RX */
1785 };
1788 };
1790 /* TX, RX */
1792 };
1795 };
1797 /* TX, RX */
1799 };
1802 };
1804 /* - CAN Clock -------------------------------------------------------------- */
1806 /* CLK */
1808 };
1810 CAN_CLK_MARK,
1811 };
1813 /* - CAN FD --------------------------------------------------------------- */
1815 /* TX, RX */
1817 };
1820 };
1822 /* TX, RX */
1824 };
1827 };
1829 /* TX, RX */
1831 };
1834 };
1836 /* - DRIF0 --------------------------------------------------------------- */
1838 /* CLK, SYNC */
1840 };
1843 };
1845 /* D0 */
1847 };
1849 RIF0_D0_A_MARK,
1850 };
1852 /* D1 */
1854 };
1856 RIF0_D1_A_MARK,
1857 };
1859 /* CLK, SYNC */
1861 };
1864 };
1866 /* D0 */
1868 };
1870 RIF0_D0_B_MARK,
1871 };
1873 /* D1 */
1875 };
1877 RIF0_D1_B_MARK,
1878 };
1880 /* CLK, SYNC */
1882 };
1885 };
1887 /* D0 */
1889 };
1891 RIF0_D0_C_MARK,
1892 };
1894 /* D1 */
1896 };
1898 RIF0_D1_C_MARK,
1899 };
1900 /* - DRIF1 --------------------------------------------------------------- */
1902 /* CLK, SYNC */
1904 };
1907 };
1909 /* D0 */
1911 };
1913 RIF1_D0_A_MARK,
1914 };
1916 /* D1 */
1918 };
1920 RIF1_D1_A_MARK,
1921 };
1923 /* CLK, SYNC */
1925 };
1928 };
1930 /* D0 */
1932 };
1934 RIF1_D0_B_MARK,
1935 };
1937 /* D1 */
1939 };
1941 RIF1_D1_B_MARK,
1942 };
1944 /* CLK, SYNC */
1946 };
1949 };
1951 /* D0 */
1953 };
1955 RIF1_D0_C_MARK,
1956 };
1958 /* D1 */
1960 };
1962 RIF1_D1_C_MARK,
1963 };
1964 /* - DRIF2 --------------------------------------------------------------- */
1966 /* CLK, SYNC */
1968 };
1971 };
1973 /* D0 */
1975 };
1977 RIF2_D0_A_MARK,
1978 };
1980 /* D1 */
1982 };
1984 RIF2_D1_A_MARK,
1985 };
1987 /* CLK, SYNC */
1989 };
1992 };
1994 /* D0 */
1996 };
1998 RIF2_D0_B_MARK,
1999 };
2001 /* D1 */
2003 };
2005 RIF2_D1_B_MARK,
2006 };
2007 /* - DRIF3 --------------------------------------------------------------- */
2009 /* CLK, SYNC */
2011 };
2014 };
2016 /* D0 */
2018 };
2020 RIF3_D0_A_MARK,
2021 };
2023 /* D1 */
2025 };
2027 RIF3_D1_A_MARK,
2028 };
2030 /* CLK, SYNC */
2032 };
2035 };
2037 /* D0 */
2039 };
2041 RIF3_D0_B_MARK,
2042 };
2044 /* D1 */
2046 };
2048 RIF3_D1_B_MARK,
2049 };
2051 /* - DU --------------------------------------------------------------------- */
2053 /* R[7:2], G[7:2], B[7:2] */
2060 };
2068 };
2070 /* R[7:0], G[7:0], B[7:0] */
2080 };
2088 };
2090 /* CLKOUT */
2092 };
2094 DU_DOTCLKOUT0_MARK
2095 };
2097 /* CLKOUT */
2099 };
2101 DU_DOTCLKOUT1_MARK
2102 };
2104 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2106 };
2108 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2109 };
2111 /* EXDISP/EXODDF/EXCDE */
2113 };
2115 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2116 };
2118 /* CDE */
2120 };
2122 DU_CDE_MARK,
2123 };
2125 /* DISP */
2127 };
2129 DU_DISP_MARK,
2130 };
2132 /* - HSCIF0 ----------------------------------------------------------------- */
2134 /* RX, TX */
2136 };
2139 };
2141 /* SCK */
2143 };
2145 HSCK0_MARK,
2146 };
2148 /* RTS, CTS */
2150 };
2153 };
2154 /* - HSCIF1 ----------------------------------------------------------------- */
2156 /* RX, TX */
2158 };
2161 };
2163 /* SCK */
2165 };
2167 HSCK1_A_MARK,
2168 };
2170 /* RTS, CTS */
2172 };
2175 };
2178 /* RX, TX */
2180 };
2183 };
2185 /* SCK */
2187 };
2189 HSCK1_B_MARK,
2190 };
2192 /* RTS, CTS */
2194 };
2197 };
2198 /* - HSCIF2 ----------------------------------------------------------------- */
2200 /* RX, TX */
2202 };
2205 };
2207 /* SCK */
2209 };
2211 HSCK2_A_MARK,
2212 };
2214 /* RTS, CTS */
2216 };
2219 };
2222 /* RX, TX */
2224 };
2227 };
2229 /* SCK */
2231 };
2233 HSCK2_B_MARK,
2234 };
2236 /* RTS, CTS */
2238 };
2241 };
2244 /* RX, TX */
2246 };
2249 };
2251 /* SCK */
2253 };
2255 HSCK2_C_MARK,
2256 };
2258 /* RTS, CTS */
2260 };
2263 };
2264 /* - HSCIF3 ----------------------------------------------------------------- */
2266 /* RX, TX */
2268 };
2271 };
2273 /* SCK */
2275 };
2277 HSCK3_MARK,
2278 };
2280 /* RTS, CTS */
2282 };
2285 };
2288 /* RX, TX */
2290 };
2293 };
2295 /* RX, TX */
2297 };
2300 };
2302 /* RX, TX */
2304 };
2307 };
2308 /* - HSCIF4 ----------------------------------------------------------------- */
2310 /* RX, TX */
2312 };
2315 };
2317 /* SCK */
2319 };
2321 HSCK4_MARK,
2322 };
2324 /* RTS, CTS */
2326 };
2329 };
2332 /* RX, TX */
2334 };
2337 };
2339 /* - I2C -------------------------------------------------------------------- */
2341 /* SDA, SCL */
2343 };
2346 };
2348 /* SDA, SCL */
2350 };
2353 };
2355 /* SDA, SCL */
2357 };
2360 };
2362 /* SDA, SCL */
2364 };
2367 };
2369 /* SDA, SCL */
2371 };
2374 };
2376 /* SDA, SCL */
2378 };
2381 };
2383 /* SDA, SCL */
2385 };
2388 };
2390 /* - INTC-EX ---------------------------------------------------------------- */
2392 /* IRQ0 */
2394 };
2396 IRQ0_MARK,
2397 };
2399 /* IRQ1 */
2401 };
2403 IRQ1_MARK,
2404 };
2406 /* IRQ2 */
2408 };
2410 IRQ2_MARK,
2411 };
2413 /* IRQ3 */
2415 };
2417 IRQ3_MARK,
2418 };
2420 /* IRQ4 */
2422 };
2424 IRQ4_MARK,
2425 };
2427 /* IRQ5 */
2429 };
2431 IRQ5_MARK,
2432 };
2434 /* - MSIOF0 ----------------------------------------------------------------- */
2436 /* SCK */
2438 };
2440 MSIOF0_SCK_MARK,
2441 };
2443 /* SYNC */
2445 };
2447 MSIOF0_SYNC_MARK,
2448 };
2450 /* SS1 */
2452 };
2454 MSIOF0_SS1_MARK,
2455 };
2457 /* SS2 */
2459 };
2461 MSIOF0_SS2_MARK,
2462 };
2464 /* TXD */
2466 };
2468 MSIOF0_TXD_MARK,
2469 };
2471 /* RXD */
2473 };
2475 MSIOF0_RXD_MARK,
2476 };
2477 /* - MSIOF1 ----------------------------------------------------------------- */
2479 /* SCK */
2481 };
2483 MSIOF1_SCK_A_MARK,
2484 };
2486 /* SYNC */
2488 };
2490 MSIOF1_SYNC_A_MARK,
2491 };
2493 /* SS1 */
2495 };
2497 MSIOF1_SS1_A_MARK,
2498 };
2500 /* SS2 */
2502 };
2504 MSIOF1_SS2_A_MARK,
2505 };
2507 /* TXD */
2509 };
2511 MSIOF1_TXD_A_MARK,
2512 };
2514 /* RXD */
2516 };
2518 MSIOF1_RXD_A_MARK,
2519 };
2521 /* SCK */
2523 };
2525 MSIOF1_SCK_B_MARK,
2526 };
2528 /* SYNC */
2530 };
2532 MSIOF1_SYNC_B_MARK,
2533 };
2535 /* SS1 */
2537 };
2539 MSIOF1_SS1_B_MARK,
2540 };
2542 /* SS2 */
2544 };
2546 MSIOF1_SS2_B_MARK,
2547 };
2549 /* TXD */
2551 };
2553 MSIOF1_TXD_B_MARK,
2554 };
2556 /* RXD */
2558 };
2560 MSIOF1_RXD_B_MARK,
2561 };
2563 /* SCK */
2565 };
2567 MSIOF1_SCK_C_MARK,
2568 };
2570 /* SYNC */
2572 };
2574 MSIOF1_SYNC_C_MARK,
2575 };
2577 /* SS1 */
2579 };
2581 MSIOF1_SS1_C_MARK,
2582 };
2584 /* SS2 */
2586 };
2588 MSIOF1_SS2_C_MARK,
2589 };
2591 /* TXD */
2593 };
2595 MSIOF1_TXD_C_MARK,
2596 };
2598 /* RXD */
2600 };
2602 MSIOF1_RXD_C_MARK,
2603 };
2605 /* SCK */
2607 };
2609 MSIOF1_SCK_D_MARK,
2610 };
2612 /* SYNC */
2614 };
2616 MSIOF1_SYNC_D_MARK,
2617 };
2619 /* SS1 */
2621 };
2623 MSIOF1_SS1_D_MARK,
2624 };
2626 /* SS2 */
2628 };
2630 MSIOF1_SS2_D_MARK,
2631 };
2633 /* TXD */
2635 };
2637 MSIOF1_TXD_D_MARK,
2638 };
2640 /* RXD */
2642 };
2644 MSIOF1_RXD_D_MARK,
2645 };
2647 /* SCK */
2649 };
2651 MSIOF1_SCK_E_MARK,
2652 };
2654 /* SYNC */
2656 };
2658 MSIOF1_SYNC_E_MARK,
2659 };
2661 /* SS1 */
2663 };
2665 MSIOF1_SS1_E_MARK,
2666 };
2668 /* SS2 */
2670 };
2672 MSIOF1_SS2_E_MARK,
2673 };
2675 /* TXD */
2677 };
2679 MSIOF1_TXD_E_MARK,
2680 };
2682 /* RXD */
2684 };
2686 MSIOF1_RXD_E_MARK,
2687 };
2689 /* SCK */
2691 };
2693 MSIOF1_SCK_F_MARK,
2694 };
2696 /* SYNC */
2698 };
2700 MSIOF1_SYNC_F_MARK,
2701 };
2703 /* SS1 */
2705 };
2707 MSIOF1_SS1_F_MARK,
2708 };
2710 /* SS2 */
2712 };
2714 MSIOF1_SS2_F_MARK,
2715 };
2717 /* TXD */
2719 };
2721 MSIOF1_TXD_F_MARK,
2722 };
2724 /* RXD */
2726 };
2728 MSIOF1_RXD_F_MARK,
2729 };
2731 /* SCK */
2733 };
2735 MSIOF1_SCK_G_MARK,
2736 };
2738 /* SYNC */
2740 };
2742 MSIOF1_SYNC_G_MARK,
2743 };
2745 /* SS1 */
2747 };
2749 MSIOF1_SS1_G_MARK,
2750 };
2752 /* SS2 */
2754 };
2756 MSIOF1_SS2_G_MARK,
2757 };
2759 /* TXD */
2761 };
2763 MSIOF1_TXD_G_MARK,
2764 };
2766 /* RXD */
2768 };
2770 MSIOF1_RXD_G_MARK,
2771 };
2772 /* - MSIOF2 ----------------------------------------------------------------- */
2774 /* SCK */
2776 };
2778 MSIOF2_SCK_A_MARK,
2779 };
2781 /* SYNC */
2783 };
2785 MSIOF2_SYNC_A_MARK,
2786 };
2788 /* SS1 */
2790 };
2792 MSIOF2_SS1_A_MARK,
2793 };
2795 /* SS2 */
2797 };
2799 MSIOF2_SS2_A_MARK,
2800 };
2802 /* TXD */
2804 };
2806 MSIOF2_TXD_A_MARK,
2807 };
2809 /* RXD */
2811 };
2813 MSIOF2_RXD_A_MARK,
2814 };
2816 /* SCK */
2818 };
2820 MSIOF2_SCK_B_MARK,
2821 };
2823 /* SYNC */
2825 };
2827 MSIOF2_SYNC_B_MARK,
2828 };
2830 /* SS1 */
2832 };
2834 MSIOF2_SS1_B_MARK,
2835 };
2837 /* SS2 */
2839 };
2841 MSIOF2_SS2_B_MARK,
2842 };
2844 /* TXD */
2846 };
2848 MSIOF2_TXD_B_MARK,
2849 };
2851 /* RXD */
2853 };
2855 MSIOF2_RXD_B_MARK,
2856 };
2858 /* SCK */
2860 };
2862 MSIOF2_SCK_C_MARK,
2863 };
2865 /* SYNC */
2867 };
2869 MSIOF2_SYNC_C_MARK,
2870 };
2872 /* SS1 */
2874 };
2876 MSIOF2_SS1_C_MARK,
2877 };
2879 /* SS2 */
2881 };
2883 MSIOF2_SS2_C_MARK,
2884 };
2886 /* TXD */
2888 };
2890 MSIOF2_TXD_C_MARK,
2891 };
2893 /* RXD */
2895 };
2897 MSIOF2_RXD_C_MARK,
2898 };
2900 /* SCK */
2902 };
2904 MSIOF2_SCK_D_MARK,
2905 };
2907 /* SYNC */
2909 };
2911 MSIOF2_SYNC_D_MARK,
2912 };
2914 /* SS1 */
2916 };
2918 MSIOF2_SS1_D_MARK,
2919 };
2921 /* SS2 */
2923 };
2925 MSIOF2_SS2_D_MARK,
2926 };
2928 /* TXD */
2930 };
2932 MSIOF2_TXD_D_MARK,
2933 };
2935 /* RXD */
2937 };
2939 MSIOF2_RXD_D_MARK,
2940 };
2941 /* - MSIOF3 ----------------------------------------------------------------- */
2943 /* SCK */
2945 };
2947 MSIOF3_SCK_A_MARK,
2948 };
2950 /* SYNC */
2952 };
2954 MSIOF3_SYNC_A_MARK,
2955 };
2957 /* SS1 */
2959 };
2961 MSIOF3_SS1_A_MARK,
2962 };
2964 /* SS2 */
2966 };
2968 MSIOF3_SS2_A_MARK,
2969 };
2971 /* TXD */
2973 };
2975 MSIOF3_TXD_A_MARK,
2976 };
2978 /* RXD */
2980 };
2982 MSIOF3_RXD_A_MARK,
2983 };
2985 /* SCK */
2987 };
2989 MSIOF3_SCK_B_MARK,
2990 };
2992 /* SYNC */
2994 };
2996 MSIOF3_SYNC_B_MARK,
2997 };
2999 /* SS1 */
3001 };
3003 MSIOF3_SS1_B_MARK,
3004 };
3006 /* SS2 */
3008 };
3010 MSIOF3_SS2_B_MARK,
3011 };
3013 /* TXD */
3015 };
3017 MSIOF3_TXD_B_MARK,
3018 };
3020 /* RXD */
3022 };
3024 MSIOF3_RXD_B_MARK,
3025 };
3027 /* SCK */
3029 };
3031 MSIOF3_SCK_C_MARK,
3032 };
3034 /* SYNC */
3036 };
3038 MSIOF3_SYNC_C_MARK,
3039 };
3041 /* TXD */
3043 };
3045 MSIOF3_TXD_C_MARK,
3046 };
3048 /* RXD */
3050 };
3052 MSIOF3_RXD_C_MARK,
3053 };
3055 /* SCK */
3057 };
3059 MSIOF3_SCK_D_MARK,
3060 };
3062 /* SYNC */
3064 };
3066 MSIOF3_SYNC_D_MARK,
3067 };
3069 /* SS1 */
3071 };
3073 MSIOF3_SS1_D_MARK,
3074 };
3076 /* TXD */
3078 };
3080 MSIOF3_TXD_D_MARK,
3081 };
3083 /* RXD */
3085 };
3087 MSIOF3_RXD_D_MARK,
3088 };
3091 /* SCK */
3093 };
3095 MSIOF3_SCK_E_MARK,
3096 };
3098 /* SYNC */
3100 };
3102 MSIOF3_SYNC_E_MARK,
3103 };
3105 /* SS1 */
3107 };
3109 MSIOF3_SS1_E_MARK,
3110 };
3112 /* SS1 */
3114 };
3116 MSIOF3_SS2_E_MARK,
3117 };
3119 /* TXD */
3121 };
3123 MSIOF3_TXD_E_MARK,
3124 };
3126 /* RXD */
3128 };
3130 MSIOF3_RXD_E_MARK,
3131 };
3133 /* - PWM0 --------------------------------------------------------------------*/
3135 /* PWM */
3137 };
3139 PWM0_MARK,
3140 };
3141 /* - PWM1 --------------------------------------------------------------------*/
3143 /* PWM */
3145 };
3147 PWM1_A_MARK,
3148 };
3150 /* PWM */
3152 };
3154 PWM1_B_MARK,
3155 };
3156 /* - PWM2 --------------------------------------------------------------------*/
3158 /* PWM */
3160 };
3162 PWM2_A_MARK,
3163 };
3165 /* PWM */
3167 };
3169 PWM2_B_MARK,
3170 };
3171 /* - PWM3 --------------------------------------------------------------------*/
3173 /* PWM */
3175 };
3177 PWM3_A_MARK,
3178 };
3180 /* PWM */
3182 };
3184 PWM3_B_MARK,
3185 };
3186 /* - PWM4 --------------------------------------------------------------------*/
3188 /* PWM */
3190 };
3192 PWM4_A_MARK,
3193 };
3195 /* PWM */
3197 };
3199 PWM4_B_MARK,
3200 };
3201 /* - PWM5 --------------------------------------------------------------------*/
3203 /* PWM */
3205 };
3207 PWM5_A_MARK,
3208 };
3210 /* PWM */
3212 };
3214 PWM5_B_MARK,
3215 };
3216 /* - PWM6 --------------------------------------------------------------------*/
3218 /* PWM */
3220 };
3222 PWM6_A_MARK,
3223 };
3225 /* PWM */
3227 };
3229 PWM6_B_MARK,
3230 };
3232 /* - SCIF0 ------------------------------------------------------------------ */
3234 /* RX, TX */
3236 };
3239 };
3241 /* SCK */
3243 };
3245 SCK0_MARK,
3246 };
3248 /* RTS, CTS */
3250 };
3253 };
3254 /* - SCIF1 ------------------------------------------------------------------ */
3256 /* RX, TX */
3258 };
3261 };
3263 /* SCK */
3265 };
3267 SCK1_MARK,
3268 };
3270 /* RTS, CTS */
3272 };
3275 };
3278 /* RX, TX */
3280 };
3283 };
3284 /* - SCIF2 ------------------------------------------------------------------ */
3286 /* RX, TX */
3288 };
3291 };
3293 /* SCK */
3295 };
3297 SCK2_MARK,
3298 };
3300 /* RX, TX */
3302 };
3305 };
3306 /* - SCIF3 ------------------------------------------------------------------ */
3308 /* RX, TX */
3310 };
3313 };
3315 /* SCK */
3317 };
3319 SCK3_MARK,
3320 };
3322 /* RTS, CTS */
3324 };
3327 };
3329 /* RX, TX */
3331 };
3334 };
3335 /* - SCIF4 ------------------------------------------------------------------ */
3337 /* RX, TX */
3339 };
3342 };
3344 /* SCK */
3346 };
3348 SCK4_A_MARK,
3349 };
3351 /* RTS, CTS */
3353 };
3356 };
3358 /* RX, TX */
3360 };
3363 };
3365 /* SCK */
3367 };
3369 SCK4_B_MARK,
3370 };
3372 /* RTS, CTS */
3374 };
3377 };
3379 /* RX, TX */
3381 };
3384 };
3386 /* SCK */
3388 };
3390 SCK4_C_MARK,
3391 };
3393 /* RTS, CTS */
3395 };
3398 };
3399 /* - SCIF5 ------------------------------------------------------------------ */
3401 /* RX, TX */
3403 };
3406 };
3408 /* SCK */
3410 };
3412 SCK5_A_MARK,
3413 };
3416 /* RX, TX */
3418 };
3421 };
3423 /* SCK */
3425 };
3427 SCK5_B_MARK,
3428 };
3430 /* - SCIF Clock ------------------------------------------------------------- */
3432 /* SCIF_CLK */
3434 };
3436 SCIF_CLK_A_MARK,
3437 };
3439 /* SCIF_CLK */
3441 };
3443 SCIF_CLK_B_MARK,
3444 };
3446 /* - SDHI0 ------------------------------------------------------------------ */
3448 /* D0 */
3450 };
3452 SD0_DAT0_MARK,
3453 };
3455 /* D[0:3] */
3458 };
3462 };
3464 /* CLK, CMD */
3466 };
3469 };
3471 /* CD */
3473 };
3475 SD0_CD_MARK,
3476 };
3478 /* WP */
3480 };
3482 SD0_WP_MARK,
3483 };
3484 /* - SDHI1 ------------------------------------------------------------------ */
3486 /* D0 */
3488 };
3490 SD1_DAT0_MARK,
3491 };
3493 /* D[0:3] */
3496 };
3500 };
3502 /* CLK, CMD */
3504 };
3507 };
3509 /* CD */
3511 };
3513 SD1_CD_MARK,
3514 };
3516 /* WP */
3518 };
3520 SD1_WP_MARK,
3521 };
3522 /* - SDHI2 ------------------------------------------------------------------ */
3524 /* D0 */
3526 };
3528 SD2_DAT0_MARK,
3529 };
3531 /* D[0:3] */
3534 };
3538 };
3540 /* D[0:7] */
3545 };
3551 };
3553 /* CLK, CMD */
3555 };
3558 };
3560 /* CD */
3562 };
3564 SD2_CD_A_MARK,
3565 };
3567 /* CD */
3569 };
3571 SD2_CD_B_MARK,
3572 };
3574 /* WP */
3576 };
3578 SD2_WP_A_MARK,
3579 };
3581 /* WP */
3583 };
3585 SD2_WP_B_MARK,
3586 };
3588 /* DS */
3590 };
3592 SD2_DS_MARK,
3593 };
3594 /* - SDHI3 ------------------------------------------------------------------ */
3596 /* D0 */
3598 };
3600 SD3_DAT0_MARK,
3601 };
3603 /* D[0:3] */
3606 };
3610 };
3612 /* D[0:7] */
3617 };
3623 };
3625 /* CLK, CMD */
3627 };
3630 };
3632 /* CD */
3634 };
3636 SD3_CD_MARK,
3637 };
3639 /* WP */
3641 };
3643 SD3_WP_MARK,
3644 };
3646 /* DS */
3648 };
3650 SD3_DS_MARK,
3651 };
3653 /* - SSI -------------------------------------------------------------------- */
3655 /* SDATA */
3657 };
3659 SSI_SDATA0_MARK,
3660 };
3662 /* SCK, WS */
3664 };
3667 };
3669 /* SDATA */
3671 };
3673 SSI_SDATA1_A_MARK,
3674 };
3676 /* SDATA */
3678 };
3680 SSI_SDATA1_B_MARK,
3681 };
3683 /* SCK, WS */
3685 };
3688 };
3690 /* SCK, WS */
3692 };
3695 };
3697 /* SDATA */
3699 };
3701 SSI_SDATA2_A_MARK,
3702 };
3704 /* SDATA */
3706 };
3708 SSI_SDATA2_B_MARK,
3709 };
3711 /* SCK, WS */
3713 };
3716 };
3718 /* SCK, WS */
3720 };
3723 };
3725 /* SDATA */
3727 };
3729 SSI_SDATA3_MARK,
3730 };
3732 /* SCK, WS */
3734 };
3737 };
3739 /* SDATA */
3741 };
3743 SSI_SDATA4_MARK,
3744 };
3746 /* SCK, WS */
3748 };
3751 };
3753 /* SDATA */
3755 };
3757 SSI_SDATA5_MARK,
3758 };
3760 /* SCK, WS */
3762 };
3765 };
3767 /* SDATA */
3769 };
3771 SSI_SDATA6_MARK,
3772 };
3774 /* SCK, WS */
3776 };
3779 };
3781 /* SDATA */
3783 };
3785 SSI_SDATA7_MARK,
3786 };
3788 /* SCK, WS */
3790 };
3793 };
3795 /* SDATA */
3797 };
3799 SSI_SDATA8_MARK,
3800 };
3802 /* SDATA */
3804 };
3806 SSI_SDATA9_A_MARK,
3807 };
3809 /* SDATA */
3811 };
3813 SSI_SDATA9_B_MARK,
3814 };
3816 /* SCK, WS */
3818 };
3821 };
3823 /* SCK, WS */
3825 };
3828 };
3830 /* - USB0 ------------------------------------------------------------------- */
3832 /* PWEN, OVC */
3834 };
3837 };
3838 /* - USB1 ------------------------------------------------------------------- */
3840 /* PWEN, OVC */
3842 };
3845 };
3847 /* - USB30 ------------------------------------------------------------------ */
3849 /* PWEN, OVC */
3851 };
3854 };
4165 };
4185 };
4198 };
4203 };
4207 };
4211 };
4216 };
4220 };
4232 };
4244 };
4253 };
4262 };
4273 };
4279 };
4288 };
4300 };
4309 };
4316 };
4321 };
4326 };
4332 };
4341 };
4350 };
4395 };
4422 };
4452 };
4456 };
4461 };
4466 };
4471 };
4476 };
4481 };
4486 };
4492 };
4499 };
4505 };
4512 };
4524 };
4531 };
4536 };
4544 };
4552 };
4564 };
4574 };
4602 };
4606 };
4610 };
4614 };
4664 };
4667 #define F_(x, y) FN_##y
4668 #define FM(x) FN_##x
4702 },
4736 },
4770 },
4804 },
4838 },
4872 },
4906 },
4940 },
4941 #undef F_
4942 #undef FM
4944 #define F_(x, y) x,
4945 #define FM(x) FN_##x,
4947 IP0_31_28
4948 IP0_27_24
4949 IP0_23_20
4950 IP0_19_16
4951 IP0_15_12
4952 IP0_11_8
4953 IP0_7_4
4954 IP0_3_0 }
4955 },
4957 IP1_31_28
4958 IP1_27_24
4959 IP1_23_20
4960 IP1_19_16
4961 IP1_15_12
4962 IP1_11_8
4963 IP1_7_4
4964 IP1_3_0 }
4965 },
4967 IP2_31_28
4968 IP2_27_24
4969 IP2_23_20
4970 IP2_19_16
4971 IP2_15_12
4972 IP2_11_8
4973 IP2_7_4
4974 IP2_3_0 }
4975 },
4977 IP3_31_28
4978 IP3_27_24
4979 IP3_23_20
4980 IP3_19_16
4981 IP3_15_12
4982 IP3_11_8
4983 IP3_7_4
4984 IP3_3_0 }
4985 },
4987 IP4_31_28
4988 IP4_27_24
4989 IP4_23_20
4990 IP4_19_16
4991 IP4_15_12
4992 IP4_11_8
4993 IP4_7_4
4994 IP4_3_0 }
4995 },
4997 IP5_31_28
4998 IP5_27_24
4999 IP5_23_20
5000 IP5_19_16
5001 IP5_15_12
5002 IP5_11_8
5003 IP5_7_4
5004 IP5_3_0 }
5005 },
5007 IP6_31_28
5008 IP6_27_24
5009 IP6_23_20
5010 IP6_19_16
5011 IP6_15_12
5012 IP6_11_8
5013 IP6_7_4
5014 IP6_3_0 }
5015 },
5017 IP7_31_28
5018 IP7_27_24
5019 IP7_23_20
5020 IP7_19_16
5022 IP7_11_8
5023 IP7_7_4
5024 IP7_3_0 }
5025 },
5027 IP8_31_28
5028 IP8_27_24
5029 IP8_23_20
5030 IP8_19_16
5031 IP8_15_12
5032 IP8_11_8
5033 IP8_7_4
5034 IP8_3_0 }
5035 },
5037 IP9_31_28
5038 IP9_27_24
5039 IP9_23_20
5040 IP9_19_16
5041 IP9_15_12
5042 IP9_11_8
5043 IP9_7_4
5044 IP9_3_0 }
5045 },
5047 IP10_31_28
5048 IP10_27_24
5049 IP10_23_20
5050 IP10_19_16
5051 IP10_15_12
5052 IP10_11_8
5053 IP10_7_4
5054 IP10_3_0 }
5055 },
5057 IP11_31_28
5058 IP11_27_24
5059 IP11_23_20
5060 IP11_19_16
5061 IP11_15_12
5062 IP11_11_8
5063 IP11_7_4
5064 IP11_3_0 }
5065 },
5067 IP12_31_28
5068 IP12_27_24
5069 IP12_23_20
5070 IP12_19_16
5071 IP12_15_12
5072 IP12_11_8
5073 IP12_7_4
5074 IP12_3_0 }
5075 },
5077 IP13_31_28
5078 IP13_27_24
5079 IP13_23_20
5080 IP13_19_16
5081 IP13_15_12
5082 IP13_11_8
5083 IP13_7_4
5084 IP13_3_0 }
5085 },
5087 IP14_31_28
5088 IP14_27_24
5089 IP14_23_20
5090 IP14_19_16
5091 IP14_15_12
5092 IP14_11_8
5093 IP14_7_4
5094 IP14_3_0 }
5095 },
5097 IP15_31_28
5098 IP15_27_24
5099 IP15_23_20
5100 IP15_19_16
5101 IP15_15_12
5102 IP15_11_8
5103 IP15_7_4
5104 IP15_3_0 }
5105 },
5107 IP16_31_28
5108 IP16_27_24
5109 IP16_23_20
5110 IP16_19_16
5111 IP16_15_12
5112 IP16_11_8
5113 IP16_7_4
5114 IP16_3_0 }
5115 },
5117 IP17_31_28
5118 IP17_27_24
5119 IP17_23_20
5120 IP17_19_16
5121 IP17_15_12
5122 IP17_11_8
5123 IP17_7_4
5124 IP17_3_0 }
5125 },
5133 IP18_7_4
5134 IP18_3_0 }
5135 },
5136 #undef F_
5137 #undef FM
5139 #define F_(x, y) x,
5140 #define FM(x) FN_##x,
5144 MOD_SEL0_31_30_29
5145 MOD_SEL0_28_27
5146 MOD_SEL0_26_25_24
5147 MOD_SEL0_23
5148 MOD_SEL0_22
5149 MOD_SEL0_21
5150 MOD_SEL0_20
5151 MOD_SEL0_19
5152 MOD_SEL0_18_17
5153 MOD_SEL0_16
5155 MOD_SEL0_14_13
5156 MOD_SEL0_12
5157 MOD_SEL0_11
5158 MOD_SEL0_10
5159 MOD_SEL0_9_8
5160 MOD_SEL0_7_6
5161 MOD_SEL0_5
5162 MOD_SEL0_4_3
5163 /* RESERVED 2, 1, 0 */
5165 },
5169 MOD_SEL1_31_30
5170 MOD_SEL1_29_28_27
5171 MOD_SEL1_26
5172 MOD_SEL1_25_24
5173 MOD_SEL1_23_22_21
5174 MOD_SEL1_20
5175 MOD_SEL1_19
5176 MOD_SEL1_18_17
5177 MOD_SEL1_16
5178 MOD_SEL1_15_14
5179 MOD_SEL1_13
5180 MOD_SEL1_12
5181 MOD_SEL1_11
5182 MOD_SEL1_10
5183 MOD_SEL1_9
5185 MOD_SEL1_6
5186 MOD_SEL1_5
5187 MOD_SEL1_4
5188 MOD_SEL1_3
5189 MOD_SEL1_2
5190 MOD_SEL1_1
5191 MOD_SEL1_0 }
5192 },
5196 MOD_SEL2_31
5197 MOD_SEL2_30
5198 MOD_SEL2_29
5199 MOD_SEL2_28_27
5200 MOD_SEL2_26
5201 MOD_SEL2_25_24_23
5202 MOD_SEL2_22
5203 MOD_SEL2_21
5204 MOD_SEL2_20
5205 MOD_SEL2_19
5206 MOD_SEL2_18
5207 MOD_SEL2_17
5208 /* RESERVED 16 */
5210 /* RESERVED 15, 14, 13, 12 */
5213 /* RESERVED 11, 10, 9, 8 */
5216 /* RESERVED 7, 6, 5, 4 */
5219 /* RESERVED 3, 2, 1 */
5221 MOD_SEL2_0 }
5222 },
5223 { },
5224 };
5236 } },
5246 } },
5256 } },
5266 } },
5276 } },
5286 } },
5296 } },
5306 } },
5316 } },
5326 } },
5336 } },
5346 } },
5351 } },
5361 } },
5371 } },
5381 } },
5391 } },
5401 } },
5411 } },
5421 } },
5431 } },
5441 } },
5451 } },
5461 } },
5470 } },
5471 { },
5472 };
5475 POCCTRL,
5476 };
5481 };
5484 {
5496 }
5532 } },
5566 } },
5600 } },
5634 } },
5668 } },
5702 } },
5736 } },
5738 };
5742 {
5754 else
5756 }
5760 {
5779 }
5785 };
5808 };