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Linux 4.16.11
[linux/fpc-iii.git] / drivers / pinctrl / sh-pfc / pfc-r8a77970.c
blob794f12d7444903b45b49339092742492b9f433d5
1 /*
2 * R8A77970 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 */
17
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20
21 #include "core.h"
22 #include "sh_pfc.h"
23
24 #define CPU_ALL_PORT(fn, sfx) \
25 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
26 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
27 PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
28 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
29 PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
30 PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
31 /*
32 * F_() : just information
33 * FM() : macro for FN_xxx / xxx_MARK
34 */
35
36 /* GPSR0 */
37 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
38 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
39 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
40 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
41 #define GPSR0_17 F_(DU_DB7, IP2_7_4)
42 #define GPSR0_16 F_(DU_DB6, IP2_3_0)
43 #define GPSR0_15 F_(DU_DB5, IP1_31_28)
44 #define GPSR0_14 F_(DU_DB4, IP1_27_24)
45 #define GPSR0_13 F_(DU_DB3, IP1_23_20)
46 #define GPSR0_12 F_(DU_DB2, IP1_19_16)
47 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
48 #define GPSR0_10 F_(DU_DG6, IP1_11_8)
49 #define GPSR0_9 F_(DU_DG5, IP1_7_4)
50 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
51 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
52 #define GPSR0_6 F_(DU_DG2, IP0_27_24)
53 #define GPSR0_5 F_(DU_DR7, IP0_23_20)
54 #define GPSR0_4 F_(DU_DR6, IP0_19_16)
55 #define GPSR0_3 F_(DU_DR5, IP0_15_12)
56 #define GPSR0_2 F_(DU_DR4, IP0_11_8)
57 #define GPSR0_1 F_(DU_DR3, IP0_7_4)
58 #define GPSR0_0 F_(DU_DR2, IP0_3_0)
59
60 /* GPSR1 */
61 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24)
62 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20)
63 #define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16)
64 #define GPSR1_24 F_(CANFD1_RX, IP8_15_12)
65 #define GPSR1_23 F_(CANFD1_TX, IP8_11_8)
66 #define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4)
67 #define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0)
68 #define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28)
69 #define GPSR1_19 FM(AVB0_AVTP_MATCH)
70 #define GPSR1_18 FM(AVB0_LINK)
71 #define GPSR1_17 FM(AVB0_PHY_INT)
72 #define GPSR1_16 FM(AVB0_MAGIC)
73 #define GPSR1_15 FM(AVB0_MDC)
74 #define GPSR1_14 FM(AVB0_MDIO)
75 #define GPSR1_13 FM(AVB0_TXCREFCLK)
76 #define GPSR1_12 FM(AVB0_TD3)
77 #define GPSR1_11 FM(AVB0_TD2)
78 #define GPSR1_10 FM(AVB0_TD1)
79 #define GPSR1_9 FM(AVB0_TD0)
80 #define GPSR1_8 FM(AVB0_TXC)
81 #define GPSR1_7 FM(AVB0_TX_CTL)
82 #define GPSR1_6 FM(AVB0_RD3)
83 #define GPSR1_5 FM(AVB0_RD2)
84 #define GPSR1_4 FM(AVB0_RD1)
85 #define GPSR1_3 FM(AVB0_RD0)
86 #define GPSR1_2 FM(AVB0_RXC)
87 #define GPSR1_1 FM(AVB0_RX_CTL)
88 #define GPSR1_0 F_(IRQ0, IP2_27_24)
89
90 /* GPSR2 */
91 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
92 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
93 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
94 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
95 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
96 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
97 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
98 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
99 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
100 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
101 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
102 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
103 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
104 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
105 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
106 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
107 #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
108
109 /* GPSR3 */
110 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
111 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
112 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
113 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
114 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
115 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
116 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
117 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
118 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
119 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
120 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
121 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
122 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
123 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
124 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
125 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
126 #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
127
128 /* GPSR4 */
129 #define GPSR4_5 F_(SDA2, IP7_27_24)
130 #define GPSR4_4 F_(SCL2, IP7_23_20)
131 #define GPSR4_3 F_(SDA1, IP7_19_16)
132 #define GPSR4_2 F_(SCL1, IP7_15_12)
133 #define GPSR4_1 F_(SDA0, IP7_11_8)
134 #define GPSR4_0 F_(SCL0, IP7_7_4)
135
136 /* GPSR5 */
137 #define GPSR5_14 FM(RPC_INT_N)
138 #define GPSR5_13 FM(RPC_WP_N)
139 #define GPSR5_12 FM(RPC_RESET_N)
140 #define GPSR5_11 FM(QSPI1_SSL)
141 #define GPSR5_10 FM(QSPI1_IO3)
142 #define GPSR5_9 FM(QSPI1_IO2)
143 #define GPSR5_8 FM(QSPI1_MISO_IO1)
144 #define GPSR5_7 FM(QSPI1_MOSI_IO0)
145 #define GPSR5_6 FM(QSPI1_SPCLK)
146 #define GPSR5_5 FM(QSPI0_SSL)
147 #define GPSR5_4 FM(QSPI0_IO3)
148 #define GPSR5_3 FM(QSPI0_IO2)
149 #define GPSR5_2 FM(QSPI0_MISO_IO1)
150 #define GPSR5_1 FM(QSPI0_MOSI_IO0)
151 #define GPSR5_0 FM(QSPI0_SPCLK)
152
153
154 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
155 #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
156 #define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
157 #define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
158 #define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
159 #define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
160 #define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
161 #define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
162 #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
163 #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
164 #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
165 #define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
166 #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
167 #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
168 #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
169 #define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
170 #define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
171 #define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
172 #define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
173 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
174 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
175 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
176 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
177 #define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
178 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
179 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
180 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
181 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
182 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
183 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
184 #define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
185 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
186 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
187 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227
228 #define PINMUX_GPSR \
229 \
230 GPSR1_27 \
231 GPSR1_26 \
232 GPSR1_25 \
233 GPSR1_24 \
234 GPSR1_23 \
235 GPSR1_22 \
236 GPSR0_21 GPSR1_21 \
237 GPSR0_20 GPSR1_20 \
238 GPSR0_19 GPSR1_19 \
239 GPSR0_18 GPSR1_18 \
240 GPSR0_17 GPSR1_17 \
241 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \
242 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \
243 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 \
244 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 \
245 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 \
246 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 \
247 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR5_10 \
248 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR5_9 \
249 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR5_8 \
250 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR5_7 \
251 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR5_6 \
252 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
253 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
254 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
255 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
256 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
257 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
258
259 #define PINMUX_IPSR \
260 \
261 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
262 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
263 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
264 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
265 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
266 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
267 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
268 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
269 \
270 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
271 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
272 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
273 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
274 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
275 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
276 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
277 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
278 \
279 FM(IP8_3_0) IP8_3_0 \
280 FM(IP8_7_4) IP8_7_4 \
281 FM(IP8_11_8) IP8_11_8 \
282 FM(IP8_15_12) IP8_15_12 \
283 FM(IP8_19_16) IP8_19_16 \
284 FM(IP8_23_20) IP8_23_20 \
285 FM(IP8_27_24) IP8_27_24 \
286 FM(IP8_31_28) IP8_31_28
287
288 /* MOD_SEL0 */ /* 0 */ /* 1 */
289 #define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
290 #define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
291 #define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
292 #define MOD_SEL0_8 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
293 #define MOD_SEL0_7 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
294 #define MOD_SEL0_6 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
295 #define MOD_SEL0_5 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
296 #define MOD_SEL0_4 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
297 #define MOD_SEL0_3 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
298 #define MOD_SEL0_2 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
299 #define MOD_SEL0_1 FM(SEL_RSP_0) FM(SEL_RSP_1)
300 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
301
302 #define PINMUX_MOD_SELS \
303 \
304 MOD_SEL0_11 \
305 MOD_SEL0_10 \
306 MOD_SEL0_9 \
307 MOD_SEL0_8 \
308 MOD_SEL0_7 \
309 MOD_SEL0_6 \
310 MOD_SEL0_5 \
311 MOD_SEL0_4 \
312 MOD_SEL0_3 \
313 MOD_SEL0_2 \
314 MOD_SEL0_1 \
315 MOD_SEL0_0
316
317 enum {
318 PINMUX_RESERVED = 0,
319
320 PINMUX_DATA_BEGIN,
321 GP_ALL(DATA),
322 PINMUX_DATA_END,
323
324 #define F_(x, y)
325 #define FM(x) FN_##x,
326 PINMUX_FUNCTION_BEGIN,
327 GP_ALL(FN),
328 PINMUX_GPSR
329 PINMUX_IPSR
330 PINMUX_MOD_SELS
331 PINMUX_FUNCTION_END,
332 #undef F_
333 #undef FM
334
335 #define F_(x, y)
336 #define FM(x) x##_MARK,
337 PINMUX_MARK_BEGIN,
338 PINMUX_GPSR
339 PINMUX_IPSR
340 PINMUX_MOD_SELS
341 PINMUX_MARK_END,
342 #undef F_
343 #undef FM
344 };
345
346 static const u16 pinmux_data[] = {
347 PINMUX_DATA_GP_ALL(),
348
349 PINMUX_SINGLE(AVB0_RX_CTL),
350 PINMUX_SINGLE(AVB0_RXC),
351 PINMUX_SINGLE(AVB0_RD0),
352 PINMUX_SINGLE(AVB0_RD1),
353 PINMUX_SINGLE(AVB0_RD2),
354 PINMUX_SINGLE(AVB0_RD3),
355 PINMUX_SINGLE(AVB0_TX_CTL),
356 PINMUX_SINGLE(AVB0_TXC),
357 PINMUX_SINGLE(AVB0_TD0),
358 PINMUX_SINGLE(AVB0_TD1),
359 PINMUX_SINGLE(AVB0_TD2),
360 PINMUX_SINGLE(AVB0_TD3),
361 PINMUX_SINGLE(AVB0_TXCREFCLK),
362 PINMUX_SINGLE(AVB0_MDIO),
363 PINMUX_SINGLE(AVB0_MDC),
364 PINMUX_SINGLE(AVB0_MAGIC),
365 PINMUX_SINGLE(AVB0_PHY_INT),
366 PINMUX_SINGLE(AVB0_LINK),
367 PINMUX_SINGLE(AVB0_AVTP_MATCH),
368
369 PINMUX_SINGLE(QSPI0_SPCLK),
370 PINMUX_SINGLE(QSPI0_MOSI_IO0),
371 PINMUX_SINGLE(QSPI0_MISO_IO1),
372 PINMUX_SINGLE(QSPI0_IO2),
373 PINMUX_SINGLE(QSPI0_IO3),
374 PINMUX_SINGLE(QSPI0_SSL),
375 PINMUX_SINGLE(QSPI1_SPCLK),
376 PINMUX_SINGLE(QSPI1_MOSI_IO0),
377 PINMUX_SINGLE(QSPI1_MISO_IO1),
378 PINMUX_SINGLE(QSPI1_IO2),
379 PINMUX_SINGLE(QSPI1_IO3),
380 PINMUX_SINGLE(QSPI1_SSL),
381 PINMUX_SINGLE(RPC_RESET_N),
382 PINMUX_SINGLE(RPC_WP_N),
383 PINMUX_SINGLE(RPC_INT_N),
384
385 /* IPSR0 */
386 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
387 PINMUX_IPSR_GPSR(IP0_3_0, HSCK0),
388 PINMUX_IPSR_GPSR(IP0_3_0, A0),
389
390 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
391 PINMUX_IPSR_GPSR(IP0_7_4, HRTS0_N),
392 PINMUX_IPSR_GPSR(IP0_7_4, A1),
393
394 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
395 PINMUX_IPSR_GPSR(IP0_11_8, HCTS0_N),
396 PINMUX_IPSR_GPSR(IP0_11_8, A2),
397
398 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
399 PINMUX_IPSR_GPSR(IP0_15_12, HTX0),
400 PINMUX_IPSR_GPSR(IP0_15_12, A3),
401
402 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
403 PINMUX_IPSR_GPSR(IP0_19_16, MSIOF3_RXD),
404 PINMUX_IPSR_GPSR(IP0_19_16, A4),
405
406 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
407 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF3_TXD),
408 PINMUX_IPSR_GPSR(IP0_23_20, A5),
409
410 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
411 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1),
412 PINMUX_IPSR_GPSR(IP0_27_24, A6),
413
414 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
415 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
416 PINMUX_IPSR_GPSR(IP0_31_28, A7),
417 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
418
419 /* IPSR1 */
420 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
421 PINMUX_IPSR_GPSR(IP1_3_0, A8),
422 PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
423
424 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
425 PINMUX_IPSR_GPSR(IP1_7_4, A9),
426 PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0),
427
428 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
429 PINMUX_IPSR_GPSR(IP1_11_8, A10),
430 PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0),
431
432 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
433 PINMUX_IPSR_GPSR(IP1_15_12, A11),
434 PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
435
436 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
437 PINMUX_IPSR_GPSR(IP1_19_16, A12),
438 PINMUX_IPSR_GPSR(IP1_19_16, IRQ2),
439
440 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
441 PINMUX_IPSR_GPSR(IP1_23_20, A13),
442 PINMUX_IPSR_GPSR(IP1_23_20, FXR_CLKOUT1),
443
444 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
445 PINMUX_IPSR_GPSR(IP1_27_24, A14),
446 PINMUX_IPSR_GPSR(IP1_27_24, FXR_CLKOUT2),
447
448 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
449 PINMUX_IPSR_GPSR(IP1_31_28, A15),
450 PINMUX_IPSR_GPSR(IP1_31_28, FXR_TXENA_N),
451
452 /* IPSR2 */
453 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
454 PINMUX_IPSR_GPSR(IP2_3_0, A16),
455 PINMUX_IPSR_GPSR(IP2_3_0, FXR_TXENB_N),
456
457 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
458 PINMUX_IPSR_GPSR(IP2_7_4, A17),
459
460 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
461 PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
462 PINMUX_IPSR_GPSR(IP2_11_8, A18),
463
464 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
465 PINMUX_IPSR_GPSR(IP2_15_12, HRX0),
466 PINMUX_IPSR_GPSR(IP2_15_12, A19),
467 PINMUX_IPSR_GPSR(IP2_15_12, IRQ3),
468
469 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
470 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
471
472 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
473 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
474
475 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
476 PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),
477
478 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
479 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
480 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
481 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
482
483 /* IPSR3 */
484 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
485 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
486 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
487 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
488 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
489
490 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
491 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
492 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
493 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
494
495 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
496 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
497 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
498 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
499
500 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
501 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
502 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS),
503 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
504
505 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
506 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
507 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
508 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
509
510 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
511 PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS),
512 PINMUX_IPSR_MSEL(IP3_23_20, SDA3_A, SEL_I2C3_0),
513
514 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
515 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
516 PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0),
517
518 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
519 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
520 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
521
522 /* IPSR4 */
523 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
524 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
525 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
526
527 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
528 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
529 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
530
531 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
532 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
533 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS),
534
535 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
536 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
537 PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0),
538
539 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
540 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
541 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
542 PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
543
544 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
545 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
546 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
547 PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
548
549 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
550 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
551 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
552 PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1),
553
554 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
555 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
556 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
557 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
558 PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A),
559
560 /* IPSR5 */
561 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
562 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
563 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
564
565 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
566 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
567 PINMUX_IPSR_GPSR(IP5_7_4, D0),
568
569 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
570 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
571 PINMUX_IPSR_GPSR(IP5_11_8, D1),
572
573 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
574 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
575 PINMUX_IPSR_GPSR(IP5_15_12, D2),
576
577 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
578 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
579 PINMUX_IPSR_GPSR(IP5_19_16, D3),
580
581 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
582 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
583 PINMUX_IPSR_GPSR(IP5_23_20, D4),
584 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CMD),
585
586 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
587 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
588 PINMUX_IPSR_GPSR(IP5_27_24, D5),
589 PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
590
591 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
592 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
593 PINMUX_IPSR_GPSR(IP5_31_28, D6),
594 PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1),
595
596 /* IPSR6 */
597 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
598 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
599 PINMUX_IPSR_GPSR(IP6_3_0, D7),
600 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D2),
601
602 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
603 PINMUX_IPSR_GPSR(IP6_7_4, SCK4),
604 PINMUX_IPSR_GPSR(IP6_7_4, D8),
605 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D3),
606
607 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
608 PINMUX_IPSR_GPSR(IP6_11_8, RX4),
609 PINMUX_IPSR_GPSR(IP6_11_8, D9),
610 PINMUX_IPSR_GPSR(IP6_11_8, MMC_CLK),
611
612 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
613 PINMUX_IPSR_GPSR(IP6_15_12, TX4),
614 PINMUX_IPSR_GPSR(IP6_15_12, D10),
615 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D4),
616
617 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
618 PINMUX_IPSR_GPSR(IP6_19_16, CTS4_N),
619 PINMUX_IPSR_GPSR(IP6_19_16, D11),
620 PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
621
622 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
623 PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS),
624 PINMUX_IPSR_GPSR(IP6_23_20, D12),
625 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
626 PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1),
627
628 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
629 PINMUX_IPSR_GPSR(IP6_27_24, D13),
630 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7),
631 PINMUX_IPSR_MSEL(IP6_27_24, SDA3_B, SEL_I2C3_1),
632
633 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
634 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
635 PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
636 PINMUX_IPSR_GPSR(IP6_31_28, D14),
637 PINMUX_IPSR_GPSR(IP6_31_28, MMC_WP),
638
639 /* IPSR7 */
640 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
641 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
642 PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
643 PINMUX_IPSR_GPSR(IP7_3_0, D15),
644 PINMUX_IPSR_GPSR(IP7_3_0, MMC_CD),
645
646 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
647 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
648 PINMUX_IPSR_GPSR(IP7_7_4, TPU0TO0),
649 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
650 PINMUX_IPSR_GPSR(IP7_7_4, MSIOF0_RXD),
651
652 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
653 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR1),
654 PINMUX_IPSR_GPSR(IP7_11_8, TPU0TO1),
655 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
656 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
657 PINMUX_IPSR_GPSR(IP7_11_8, MSIOF0_TXD),
658
659 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
660 PINMUX_IPSR_GPSR(IP7_15_12, DU_DG0),
661 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
662 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
663 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
664 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF0_SCK),
665
666 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
667 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
668 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
669 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
670 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS),
671 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
672
673 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
674 PINMUX_IPSR_GPSR(IP7_23_20, DU_DB0),
675 PINMUX_IPSR_MSEL(IP7_23_20, TCLK1_A, SEL_TMU_0),
676 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
677 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
678 PINMUX_IPSR_GPSR(IP7_23_20, MSIOF0_SS1),
679
680 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
681 PINMUX_IPSR_GPSR(IP7_27_24, DU_DB1),
682 PINMUX_IPSR_MSEL(IP7_27_24, TCLK2_A, SEL_TMU_0),
683 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
684 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
685 PINMUX_IPSR_GPSR(IP7_27_24, MSIOF0_SS2),
686
687 PINMUX_IPSR_GPSR(IP7_31_28, AVB0_AVTP_CAPTURE),
688 PINMUX_IPSR_GPSR(IP7_31_28, FSCLKST2_N_B),
689
690 /* IPSR8 */
691 PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0),
692 PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA),
693 PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1),
694 PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP),
695 PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C),
696
697 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0),
698 PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR),
699 PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1),
700 PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE),
701
702 PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX),
703 PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB),
704 PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1),
705 PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1),
706 PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1),
707
708 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX),
709 PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR),
710 PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1),
711 PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1),
712 PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1),
713
714 PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0),
715 PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR),
716 PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1),
717 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_1),
718 PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1),
719
720 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN),
721 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKEN_IN),
722
723 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKOUT),
724 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
725 };
726
727 static const struct sh_pfc_pin pinmux_pins[] = {
728 PINMUX_GPIO_GP_ALL(),
729 };
730
731 /* - CANFD Clock ------------------------------------------------------------ */
732 static const unsigned int canfd_clk_a_pins[] = {
733 /* CANFD_CLK */
734 RCAR_GP_PIN(1, 25),
735 };
736 static const unsigned int canfd_clk_a_mux[] = {
737 CANFD_CLK_A_MARK,
738 };
739 static const unsigned int canfd_clk_b_pins[] = {
740 /* CANFD_CLK */
741 RCAR_GP_PIN(3, 8),
742 };
743 static const unsigned int canfd_clk_b_mux[] = {
744 CANFD_CLK_B_MARK,
745 };
746
747 /* - CANFD0 ----------------------------------------------------------------- */
748 static const unsigned int canfd0_data_a_pins[] = {
749 /* TX, RX */
750 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
751 };
752 static const unsigned int canfd0_data_a_mux[] = {
753 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
754 };
755 static const unsigned int canfd0_data_b_pins[] = {
756 /* TX, RX */
757 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
758 };
759 static const unsigned int canfd0_data_b_mux[] = {
760 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
761 };
762
763 /* - CANFD1 ----------------------------------------------------------------- */
764 static const unsigned int canfd1_data_pins[] = {
765 /* TX, RX */
766 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
767 };
768 static const unsigned int canfd1_data_mux[] = {
769 CANFD1_TX_MARK, CANFD1_RX_MARK,
770 };
771
772 /* - DU --------------------------------------------------------------------- */
773 static const unsigned int du_rgb666_pins[] = {
774 /* R[7:2], G[7:2], B[7:2] */
775 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
776 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
777 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
778 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
779 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
780 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
781 };
782 static const unsigned int du_rgb666_mux[] = {
783 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
784 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
785 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
786 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
787 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
788 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
789 };
790 static const unsigned int du_clk_out_pins[] = {
791 /* DOTCLKOUT */
792 RCAR_GP_PIN(0, 18),
793 };
794 static const unsigned int du_clk_out_mux[] = {
795 DU_DOTCLKOUT_MARK,
796 };
797 static const unsigned int du_sync_pins[] = {
798 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
799 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
800 };
801 static const unsigned int du_sync_mux[] = {
802 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
803 };
804 static const unsigned int du_oddf_pins[] = {
805 /* EXODDF/ODDF/DISP/CDE */
806 RCAR_GP_PIN(0, 21),
807 };
808 static const unsigned int du_oddf_mux[] = {
809 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
810 };
811 static const unsigned int du_cde_pins[] = {
812 /* CDE */
813 RCAR_GP_PIN(1, 22),
814 };
815 static const unsigned int du_cde_mux[] = {
816 DU_CDE_MARK,
817 };
818 static const unsigned int du_disp_pins[] = {
819 /* DISP */
820 RCAR_GP_PIN(1, 21),
821 };
822 static const unsigned int du_disp_mux[] = {
823 DU_DISP_MARK,
824 };
825
826 /* - HSCIF0 ----------------------------------------------------------------- */
827 static const unsigned int hscif0_data_pins[] = {
828 /* HRX, HTX */
829 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
830 };
831 static const unsigned int hscif0_data_mux[] = {
832 HRX0_MARK, HTX0_MARK,
833 };
834 static const unsigned int hscif0_clk_pins[] = {
835 /* HSCK */
836 RCAR_GP_PIN(0, 0),
837 };
838 static const unsigned int hscif0_clk_mux[] = {
839 HSCK0_MARK,
840 };
841 static const unsigned int hscif0_ctrl_pins[] = {
842 /* HRTS#, HCTS# */
843 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
844 };
845 static const unsigned int hscif0_ctrl_mux[] = {
846 HRTS0_N_MARK, HCTS0_N_MARK,
847 };
848
849 /* - HSCIF1 ----------------------------------------------------------------- */
850 static const unsigned int hscif1_data_pins[] = {
851 /* HRX, HTX */
852 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
853 };
854 static const unsigned int hscif1_data_mux[] = {
855 HRX1_MARK, HTX1_MARK,
856 };
857 static const unsigned int hscif1_clk_pins[] = {
858 /* HSCK */
859 RCAR_GP_PIN(2, 7),
860 };
861 static const unsigned int hscif1_clk_mux[] = {
862 HSCK1_MARK,
863 };
864 static const unsigned int hscif1_ctrl_pins[] = {
865 /* HRTS#, HCTS# */
866 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
867 };
868 static const unsigned int hscif1_ctrl_mux[] = {
869 HRTS1_N_MARK, HCTS1_N_MARK,
870 };
871
872 /* - HSCIF2 ----------------------------------------------------------------- */
873 static const unsigned int hscif2_data_pins[] = {
874 /* HRX, HTX */
875 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
876 };
877 static const unsigned int hscif2_data_mux[] = {
878 HRX2_MARK, HTX2_MARK,
879 };
880 static const unsigned int hscif2_clk_pins[] = {
881 /* HSCK */
882 RCAR_GP_PIN(2, 12),
883 };
884 static const unsigned int hscif2_clk_mux[] = {
885 HSCK2_MARK,
886 };
887 static const unsigned int hscif2_ctrl_pins[] = {
888 /* HRTS#, HCTS# */
889 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
890 };
891 static const unsigned int hscif2_ctrl_mux[] = {
892 HRTS2_N_MARK, HCTS2_N_MARK,
893 };
894
895 /* - HSCIF3 ----------------------------------------------------------------- */
896 static const unsigned int hscif3_data_pins[] = {
897 /* HRX, HTX */
898 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
899 };
900 static const unsigned int hscif3_data_mux[] = {
901 HRX3_MARK, HTX3_MARK,
902 };
903 static const unsigned int hscif3_clk_pins[] = {
904 /* HSCK */
905 RCAR_GP_PIN(2, 0),
906 };
907 static const unsigned int hscif3_clk_mux[] = {
908 HSCK3_MARK,
909 };
910 static const unsigned int hscif3_ctrl_pins[] = {
911 /* HRTS#, HCTS# */
912 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
913 };
914 static const unsigned int hscif3_ctrl_mux[] = {
915 HRTS3_N_MARK, HCTS3_N_MARK,
916 };
917
918 /* - I2C0 ------------------------------------------------------------------- */
919 static const unsigned int i2c0_pins[] = {
920 /* SDA, SCL */
921 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
922 };
923 static const unsigned int i2c0_mux[] = {
924 SDA0_MARK, SCL0_MARK,
925 };
926
927 /* - I2C1 ------------------------------------------------------------------- */
928 static const unsigned int i2c1_pins[] = {
929 /* SDA, SCL */
930 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
931 };
932 static const unsigned int i2c1_mux[] = {
933 SDA1_MARK, SCL1_MARK,
934 };
935
936 /* - I2C2 ------------------------------------------------------------------- */
937 static const unsigned int i2c2_pins[] = {
938 /* SDA, SCL */
939 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
940 };
941 static const unsigned int i2c2_mux[] = {
942 SDA2_MARK, SCL2_MARK,
943 };
944
945 /* - I2C3 ------------------------------------------------------------------- */
946 static const unsigned int i2c3_a_pins[] = {
947 /* SDA, SCL */
948 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
949 };
950 static const unsigned int i2c3_a_mux[] = {
951 SDA3_A_MARK, SCL3_A_MARK,
952 };
953 static const unsigned int i2c3_b_pins[] = {
954 /* SDA, SCL */
955 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
956 };
957 static const unsigned int i2c3_b_mux[] = {
958 SDA3_B_MARK, SCL3_B_MARK,
959 };
960
961 /* - I2C4 ------------------------------------------------------------------- */
962 static const unsigned int i2c4_pins[] = {
963 /* SDA, SCL */
964 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
965 };
966 static const unsigned int i2c4_mux[] = {
967 SDA4_MARK, SCL4_MARK,
968 };
969
970 /* - INTC-EX ---------------------------------------------------------------- */
971 static const unsigned int intc_ex_irq0_pins[] = {
972 /* IRQ0 */
973 RCAR_GP_PIN(1, 0),
974 };
975 static const unsigned int intc_ex_irq0_mux[] = {
976 IRQ0_MARK,
977 };
978 static const unsigned int intc_ex_irq1_pins[] = {
979 /* IRQ1 */
980 RCAR_GP_PIN(0, 11),
981 };
982 static const unsigned int intc_ex_irq1_mux[] = {
983 IRQ1_MARK,
984 };
985 static const unsigned int intc_ex_irq2_pins[] = {
986 /* IRQ2 */
987 RCAR_GP_PIN(0, 12),
988 };
989 static const unsigned int intc_ex_irq2_mux[] = {
990 IRQ2_MARK,
991 };
992 static const unsigned int intc_ex_irq3_pins[] = {
993 /* IRQ3 */
994 RCAR_GP_PIN(0, 19),
995 };
996 static const unsigned int intc_ex_irq3_mux[] = {
997 IRQ3_MARK,
998 };
999 static const unsigned int intc_ex_irq4_pins[] = {
1000 /* IRQ4 */
1001 RCAR_GP_PIN(3, 15),
1002 };
1003 static const unsigned int intc_ex_irq4_mux[] = {
1004 IRQ4_MARK,
1005 };
1006 static const unsigned int intc_ex_irq5_pins[] = {
1007 /* IRQ5 */
1008 RCAR_GP_PIN(3, 16),
1009 };
1010 static const unsigned int intc_ex_irq5_mux[] = {
1011 IRQ5_MARK,
1012 };
1013
1014 /* - MMC -------------------------------------------------------------------- */
1015 static const unsigned int mmc_data1_pins[] = {
1016 /* D0 */
1017 RCAR_GP_PIN(3, 6),
1018 };
1019 static const unsigned int mmc_data1_mux[] = {
1020 MMC_D0_MARK,
1021 };
1022 static const unsigned int mmc_data4_pins[] = {
1023 /* D[0:3] */
1024 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1025 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1026 };
1027 static const unsigned int mmc_data4_mux[] = {
1028 MMC_D0_MARK, MMC_D1_MARK,
1029 MMC_D2_MARK, MMC_D3_MARK,
1030 };
1031 static const unsigned int mmc_data8_pins[] = {
1032 /* D[0:7] */
1033 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1034 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1035 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1036 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1037 };
1038 static const unsigned int mmc_data8_mux[] = {
1039 MMC_D0_MARK, MMC_D1_MARK,
1040 MMC_D2_MARK, MMC_D3_MARK,
1041 MMC_D4_MARK, MMC_D5_MARK,
1042 MMC_D6_MARK, MMC_D7_MARK,
1043 };
1044 static const unsigned int mmc_ctrl_pins[] = {
1045 /* CLK, CMD */
1046 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
1047 };
1048 static const unsigned int mmc_ctrl_mux[] = {
1049 MMC_CLK_MARK, MMC_CMD_MARK,
1050 };
1051 static const unsigned int mmc_cd_pins[] = {
1052 /* CD */
1053 RCAR_GP_PIN(3, 16),
1054 };
1055 static const unsigned int mmc_cd_mux[] = {
1056 MMC_CD_MARK,
1057 };
1058 static const unsigned int mmc_wp_pins[] = {
1059 /* WP */
1060 RCAR_GP_PIN(3, 15),
1061 };
1062 static const unsigned int mmc_wp_mux[] = {
1063 MMC_WP_MARK,
1064 };
1065
1066 /* - MSIOF0 ----------------------------------------------------------------- */
1067 static const unsigned int msiof0_clk_pins[] = {
1068 /* SCK */
1069 RCAR_GP_PIN(4, 2),
1070 };
1071 static const unsigned int msiof0_clk_mux[] = {
1072 MSIOF0_SCK_MARK,
1073 };
1074 static const unsigned int msiof0_sync_pins[] = {
1075 /* SYNC */
1076 RCAR_GP_PIN(4, 3),
1077 };
1078 static const unsigned int msiof0_sync_mux[] = {
1079 MSIOF0_SYNC_MARK,
1080 };
1081 static const unsigned int msiof0_ss1_pins[] = {
1082 /* SS1 */
1083 RCAR_GP_PIN(4, 4),
1084 };
1085 static const unsigned int msiof0_ss1_mux[] = {
1086 MSIOF0_SS1_MARK,
1087 };
1088 static const unsigned int msiof0_ss2_pins[] = {
1089 /* SS2 */
1090 RCAR_GP_PIN(4, 5),
1091 };
1092 static const unsigned int msiof0_ss2_mux[] = {
1093 MSIOF0_SS2_MARK,
1094 };
1095 static const unsigned int msiof0_txd_pins[] = {
1096 /* TXD */
1097 RCAR_GP_PIN(4, 1),
1098 };
1099 static const unsigned int msiof0_txd_mux[] = {
1100 MSIOF0_TXD_MARK,
1101 };
1102 static const unsigned int msiof0_rxd_pins[] = {
1103 /* RXD */
1104 RCAR_GP_PIN(4, 0),
1105 };
1106 static const unsigned int msiof0_rxd_mux[] = {
1107 MSIOF0_RXD_MARK,
1108 };
1109
1110 /* - MSIOF1 ----------------------------------------------------------------- */
1111 static const unsigned int msiof1_clk_pins[] = {
1112 /* SCK */
1113 RCAR_GP_PIN(3, 2),
1114 };
1115 static const unsigned int msiof1_clk_mux[] = {
1116 MSIOF1_SCK_MARK,
1117 };
1118 static const unsigned int msiof1_sync_pins[] = {
1119 /* SYNC */
1120 RCAR_GP_PIN(3, 3),
1121 };
1122 static const unsigned int msiof1_sync_mux[] = {
1123 MSIOF1_SYNC_MARK,
1124 };
1125 static const unsigned int msiof1_ss1_pins[] = {
1126 /* SS1 */
1127 RCAR_GP_PIN(3, 4),
1128 };
1129 static const unsigned int msiof1_ss1_mux[] = {
1130 MSIOF1_SS1_MARK,
1131 };
1132 static const unsigned int msiof1_ss2_pins[] = {
1133 /* SS2 */
1134 RCAR_GP_PIN(3, 5),
1135 };
1136 static const unsigned int msiof1_ss2_mux[] = {
1137 MSIOF1_SS2_MARK,
1138 };
1139 static const unsigned int msiof1_txd_pins[] = {
1140 /* TXD */
1141 RCAR_GP_PIN(3, 1),
1142 };
1143 static const unsigned int msiof1_txd_mux[] = {
1144 MSIOF1_TXD_MARK,
1145 };
1146 static const unsigned int msiof1_rxd_pins[] = {
1147 /* RXD */
1148 RCAR_GP_PIN(3, 0),
1149 };
1150 static const unsigned int msiof1_rxd_mux[] = {
1151 MSIOF1_RXD_MARK,
1152 };
1153
1154 /* - MSIOF2 ----------------------------------------------------------------- */
1155 static const unsigned int msiof2_clk_pins[] = {
1156 /* SCK */
1157 RCAR_GP_PIN(2, 0),
1158 };
1159 static const unsigned int msiof2_clk_mux[] = {
1160 MSIOF2_SCK_MARK,
1161 };
1162 static const unsigned int msiof2_sync_pins[] = {
1163 /* SYNC */
1164 RCAR_GP_PIN(2, 3),
1165 };
1166 static const unsigned int msiof2_sync_mux[] = {
1167 MSIOF2_SYNC_MARK,
1168 };
1169 static const unsigned int msiof2_ss1_pins[] = {
1170 /* SS1 */
1171 RCAR_GP_PIN(2, 4),
1172 };
1173 static const unsigned int msiof2_ss1_mux[] = {
1174 MSIOF2_SS1_MARK,
1175 };
1176 static const unsigned int msiof2_ss2_pins[] = {
1177 /* SS2 */
1178 RCAR_GP_PIN(2, 5),
1179 };
1180 static const unsigned int msiof2_ss2_mux[] = {
1181 MSIOF2_SS2_MARK,
1182 };
1183 static const unsigned int msiof2_txd_pins[] = {
1184 /* TXD */
1185 RCAR_GP_PIN(2, 2),
1186 };
1187 static const unsigned int msiof2_txd_mux[] = {
1188 MSIOF2_TXD_MARK,
1189 };
1190 static const unsigned int msiof2_rxd_pins[] = {
1191 /* RXD */
1192 RCAR_GP_PIN(2, 1),
1193 };
1194 static const unsigned int msiof2_rxd_mux[] = {
1195 MSIOF2_RXD_MARK,
1196 };
1197
1198 /* - MSIOF3 ----------------------------------------------------------------- */
1199 static const unsigned int msiof3_clk_pins[] = {
1200 /* SCK */
1201 RCAR_GP_PIN(0, 20),
1202 };
1203 static const unsigned int msiof3_clk_mux[] = {
1204 MSIOF3_SCK_MARK,
1205 };
1206 static const unsigned int msiof3_sync_pins[] = {
1207 /* SYNC */
1208 RCAR_GP_PIN(0, 21),
1209 };
1210 static const unsigned int msiof3_sync_mux[] = {
1211 MSIOF3_SYNC_MARK,
1212 };
1213 static const unsigned int msiof3_ss1_pins[] = {
1214 /* SS1 */
1215 RCAR_GP_PIN(0, 6),
1216 };
1217 static const unsigned int msiof3_ss1_mux[] = {
1218 MSIOF3_SS1_MARK,
1219 };
1220 static const unsigned int msiof3_ss2_pins[] = {
1221 /* SS2 */
1222 RCAR_GP_PIN(0, 7),
1223 };
1224 static const unsigned int msiof3_ss2_mux[] = {
1225 MSIOF3_SS2_MARK,
1226 };
1227 static const unsigned int msiof3_txd_pins[] = {
1228 /* TXD */
1229 RCAR_GP_PIN(0, 5),
1230 };
1231 static const unsigned int msiof3_txd_mux[] = {
1232 MSIOF3_TXD_MARK,
1233 };
1234 static const unsigned int msiof3_rxd_pins[] = {
1235 /* RXD */
1236 RCAR_GP_PIN(0, 4),
1237 };
1238 static const unsigned int msiof3_rxd_mux[] = {
1239 MSIOF3_RXD_MARK,
1240 };
1241
1242 /* - PWM0 ------------------------------------------------------------------- */
1243 static const unsigned int pwm0_a_pins[] = {
1244 RCAR_GP_PIN(2, 12),
1245 };
1246 static const unsigned int pwm0_a_mux[] = {
1247 PWM0_A_MARK,
1248 };
1249 static const unsigned int pwm0_b_pins[] = {
1250 RCAR_GP_PIN(1, 21),
1251 };
1252 static const unsigned int pwm0_b_mux[] = {
1253 PWM0_B_MARK,
1254 };
1255
1256 /* - PWM1 ------------------------------------------------------------------- */
1257 static const unsigned int pwm1_a_pins[] = {
1258 RCAR_GP_PIN(2, 13),
1259 };
1260 static const unsigned int pwm1_a_mux[] = {
1261 PWM1_A_MARK,
1262 };
1263 static const unsigned int pwm1_b_pins[] = {
1264 RCAR_GP_PIN(1, 22),
1265 };
1266 static const unsigned int pwm1_b_mux[] = {
1267 PWM1_B_MARK,
1268 };
1269
1270 /* - PWM2 ------------------------------------------------------------------- */
1271 static const unsigned int pwm2_a_pins[] = {
1272 RCAR_GP_PIN(2, 14),
1273 };
1274 static const unsigned int pwm2_a_mux[] = {
1275 PWM2_A_MARK,
1276 };
1277 static const unsigned int pwm2_b_pins[] = {
1278 RCAR_GP_PIN(1, 23),
1279 };
1280 static const unsigned int pwm2_b_mux[] = {
1281 PWM2_B_MARK,
1282 };
1283
1284 /* - PWM3 ------------------------------------------------------------------- */
1285 static const unsigned int pwm3_a_pins[] = {
1286 RCAR_GP_PIN(2, 15),
1287 };
1288 static const unsigned int pwm3_a_mux[] = {
1289 PWM3_A_MARK,
1290 };
1291 static const unsigned int pwm3_b_pins[] = {
1292 RCAR_GP_PIN(1, 24),
1293 };
1294 static const unsigned int pwm3_b_mux[] = {
1295 PWM3_B_MARK,
1296 };
1297
1298 /* - PWM4 ------------------------------------------------------------------- */
1299 static const unsigned int pwm4_a_pins[] = {
1300 RCAR_GP_PIN(2, 16),
1301 };
1302 static const unsigned int pwm4_a_mux[] = {
1303 PWM4_A_MARK,
1304 };
1305 static const unsigned int pwm4_b_pins[] = {
1306 RCAR_GP_PIN(1, 25),
1307 };
1308 static const unsigned int pwm4_b_mux[] = {
1309 PWM4_B_MARK,
1310 };
1311
1312 /* - SCIF Clock ------------------------------------------------------------- */
1313 static const unsigned int scif_clk_a_pins[] = {
1314 /* SCIF_CLK */
1315 RCAR_GP_PIN(0, 18),
1316 };
1317 static const unsigned int scif_clk_a_mux[] = {
1318 SCIF_CLK_A_MARK,
1319 };
1320 static const unsigned int scif_clk_b_pins[] = {
1321 /* SCIF_CLK */
1322 RCAR_GP_PIN(1, 25),
1323 };
1324 static const unsigned int scif_clk_b_mux[] = {
1325 SCIF_CLK_B_MARK,
1326 };
1327
1328 /* - SCIF0 ------------------------------------------------------------------ */
1329 static const unsigned int scif0_data_pins[] = {
1330 /* RX, TX */
1331 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1332 };
1333 static const unsigned int scif0_data_mux[] = {
1334 RX0_MARK, TX0_MARK,
1335 };
1336 static const unsigned int scif0_clk_pins[] = {
1337 /* SCK */
1338 RCAR_GP_PIN(4, 1),
1339 };
1340 static const unsigned int scif0_clk_mux[] = {
1341 SCK0_MARK,
1342 };
1343 static const unsigned int scif0_ctrl_pins[] = {
1344 /* RTS#, CTS# */
1345 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1346 };
1347 static const unsigned int scif0_ctrl_mux[] = {
1348 RTS0_N_TANS_MARK, CTS0_N_MARK,
1349 };
1350
1351 /* - SCIF1 ------------------------------------------------------------------ */
1352 static const unsigned int scif1_data_a_pins[] = {
1353 /* RX, TX */
1354 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1355 };
1356 static const unsigned int scif1_data_a_mux[] = {
1357 RX1_A_MARK, TX1_A_MARK,
1358 };
1359 static const unsigned int scif1_clk_pins[] = {
1360 /* SCK */
1361 RCAR_GP_PIN(2, 5),
1362 };
1363 static const unsigned int scif1_clk_mux[] = {
1364 SCK1_MARK,
1365 };
1366 static const unsigned int scif1_ctrl_pins[] = {
1367 /* RTS#, CTS# */
1368 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1369 };
1370 static const unsigned int scif1_ctrl_mux[] = {
1371 RTS1_N_TANS_MARK, CTS1_N_MARK,
1372 };
1373 static const unsigned int scif1_data_b_pins[] = {
1374 /* RX, TX */
1375 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1376 };
1377 static const unsigned int scif1_data_b_mux[] = {
1378 RX1_B_MARK, TX1_B_MARK,
1379 };
1380
1381 /* - SCIF3 ------------------------------------------------------------------ */
1382 static const unsigned int scif3_data_pins[] = {
1383 /* RX, TX */
1384 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1385 };
1386 static const unsigned int scif3_data_mux[] = {
1387 RX3_MARK, TX3_MARK,
1388 };
1389 static const unsigned int scif3_clk_pins[] = {
1390 /* SCK */
1391 RCAR_GP_PIN(2, 0),
1392 };
1393 static const unsigned int scif3_clk_mux[] = {
1394 SCK3_MARK,
1395 };
1396 static const unsigned int scif3_ctrl_pins[] = {
1397 /* RTS#, CTS# */
1398 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1399 };
1400 static const unsigned int scif3_ctrl_mux[] = {
1401 RTS3_N_TANS_MARK, CTS3_N_MARK,
1402 };
1403
1404 /* - SCIF4 ------------------------------------------------------------------ */
1405 static const unsigned int scif4_data_pins[] = {
1406 /* RX, TX */
1407 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1408 };
1409 static const unsigned int scif4_data_mux[] = {
1410 RX4_MARK, TX4_MARK,
1411 };
1412 static const unsigned int scif4_clk_pins[] = {
1413 /* SCK */
1414 RCAR_GP_PIN(3, 9),
1415 };
1416 static const unsigned int scif4_clk_mux[] = {
1417 SCK4_MARK,
1418 };
1419 static const unsigned int scif4_ctrl_pins[] = {
1420 /* RTS#, CTS# */
1421 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1422 };
1423 static const unsigned int scif4_ctrl_mux[] = {
1424 RTS4_N_TANS_MARK, CTS4_N_MARK,
1425 };
1426
1427 /* - TMU -------------------------------------------------------------------- */
1428 static const unsigned int tmu_tclk1_a_pins[] = {
1429 /* TCLK1 */
1430 RCAR_GP_PIN(4, 4),
1431 };
1432 static const unsigned int tmu_tclk1_a_mux[] = {
1433 TCLK1_A_MARK,
1434 };
1435 static const unsigned int tmu_tclk1_b_pins[] = {
1436 /* TCLK1 */
1437 RCAR_GP_PIN(1, 23),
1438 };
1439 static const unsigned int tmu_tclk1_b_mux[] = {
1440 TCLK1_B_MARK,
1441 };
1442 static const unsigned int tmu_tclk2_a_pins[] = {
1443 /* TCLK2 */
1444 RCAR_GP_PIN(4, 5),
1445 };
1446 static const unsigned int tmu_tclk2_a_mux[] = {
1447 TCLK2_A_MARK,
1448 };
1449 static const unsigned int tmu_tclk2_b_pins[] = {
1450 /* TCLK2 */
1451 RCAR_GP_PIN(1, 24),
1452 };
1453 static const unsigned int tmu_tclk2_b_mux[] = {
1454 TCLK2_B_MARK,
1455 };
1456
1457 /* - VIN0 ------------------------------------------------------------------- */
1458 static const unsigned int vin0_data8_pins[] = {
1459 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1460 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1461 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1462 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1463 };
1464 static const unsigned int vin0_data8_mux[] = {
1465 VI0_DATA0_MARK, VI0_DATA1_MARK,
1466 VI0_DATA2_MARK, VI0_DATA3_MARK,
1467 VI0_DATA4_MARK, VI0_DATA5_MARK,
1468 VI0_DATA6_MARK, VI0_DATA7_MARK,
1469 };
1470 static const unsigned int vin0_data10_pins[] = {
1471 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1472 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1473 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1474 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1475 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1476 };
1477 static const unsigned int vin0_data10_mux[] = {
1478 VI0_DATA0_MARK, VI0_DATA1_MARK,
1479 VI0_DATA2_MARK, VI0_DATA3_MARK,
1480 VI0_DATA4_MARK, VI0_DATA5_MARK,
1481 VI0_DATA6_MARK, VI0_DATA7_MARK,
1482 VI0_DATA8_MARK, VI0_DATA9_MARK,
1483 };
1484 static const unsigned int vin0_data12_pins[] = {
1485 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1486 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1487 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1488 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1489 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1490 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1491 };
1492 static const unsigned int vin0_data12_mux[] = {
1493 VI0_DATA0_MARK, VI0_DATA1_MARK,
1494 VI0_DATA2_MARK, VI0_DATA3_MARK,
1495 VI0_DATA4_MARK, VI0_DATA5_MARK,
1496 VI0_DATA6_MARK, VI0_DATA7_MARK,
1497 VI0_DATA8_MARK, VI0_DATA9_MARK,
1498 VI0_DATA10_MARK, VI0_DATA11_MARK,
1499 };
1500 static const unsigned int vin0_sync_pins[] = {
1501 /* HSYNC#, VSYNC# */
1502 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1503 };
1504 static const unsigned int vin0_sync_mux[] = {
1505 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1506 };
1507 static const unsigned int vin0_field_pins[] = {
1508 /* FIELD */
1509 RCAR_GP_PIN(2, 16),
1510 };
1511 static const unsigned int vin0_field_mux[] = {
1512 VI0_FIELD_MARK,
1513 };
1514 static const unsigned int vin0_clkenb_pins[] = {
1515 /* CLKENB */
1516 RCAR_GP_PIN(2, 1),
1517 };
1518 static const unsigned int vin0_clkenb_mux[] = {
1519 VI0_CLKENB_MARK,
1520 };
1521 static const unsigned int vin0_clk_pins[] = {
1522 /* CLK */
1523 RCAR_GP_PIN(2, 0),
1524 };
1525 static const unsigned int vin0_clk_mux[] = {
1526 VI0_CLK_MARK,
1527 };
1528
1529 /* - VIN1 ------------------------------------------------------------------- */
1530 static const unsigned int vin1_data8_pins[] = {
1531 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1532 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1533 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1534 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1535 };
1536 static const unsigned int vin1_data8_mux[] = {
1537 VI1_DATA0_MARK, VI1_DATA1_MARK,
1538 VI1_DATA2_MARK, VI1_DATA3_MARK,
1539 VI1_DATA4_MARK, VI1_DATA5_MARK,
1540 VI1_DATA6_MARK, VI1_DATA7_MARK,
1541 };
1542 static const unsigned int vin1_data10_pins[] = {
1543 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1544 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1545 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1546 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1547 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1548 };
1549 static const unsigned int vin1_data10_mux[] = {
1550 VI1_DATA0_MARK, VI1_DATA1_MARK,
1551 VI1_DATA2_MARK, VI1_DATA3_MARK,
1552 VI1_DATA4_MARK, VI1_DATA5_MARK,
1553 VI1_DATA6_MARK, VI1_DATA7_MARK,
1554 VI1_DATA8_MARK, VI1_DATA9_MARK,
1555 };
1556 static const unsigned int vin1_data12_pins[] = {
1557 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1558 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1559 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1560 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1561 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1562 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1563 };
1564 static const unsigned int vin1_data12_mux[] = {
1565 VI1_DATA0_MARK, VI1_DATA1_MARK,
1566 VI1_DATA2_MARK, VI1_DATA3_MARK,
1567 VI1_DATA4_MARK, VI1_DATA5_MARK,
1568 VI1_DATA6_MARK, VI1_DATA7_MARK,
1569 VI1_DATA8_MARK, VI1_DATA9_MARK,
1570 VI1_DATA10_MARK, VI1_DATA11_MARK,
1571 };
1572 static const unsigned int vin1_sync_pins[] = {
1573 /* HSYNC#, VSYNC# */
1574 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1575 };
1576 static const unsigned int vin1_sync_mux[] = {
1577 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1578 };
1579 static const unsigned int vin1_field_pins[] = {
1580 RCAR_GP_PIN(3, 16),
1581 };
1582 static const unsigned int vin1_field_mux[] = {
1583 /* FIELD */
1584 VI1_FIELD_MARK,
1585 };
1586 static const unsigned int vin1_clkenb_pins[] = {
1587 RCAR_GP_PIN(3, 1),
1588 };
1589 static const unsigned int vin1_clkenb_mux[] = {
1590 /* CLKENB */
1591 VI1_CLKENB_MARK,
1592 };
1593 static const unsigned int vin1_clk_pins[] = {
1594 RCAR_GP_PIN(3, 0),
1595 };
1596 static const unsigned int vin1_clk_mux[] = {
1597 /* CLK */
1598 VI1_CLK_MARK,
1599 };
1600
1601 static const struct sh_pfc_pin_group pinmux_groups[] = {
1602 SH_PFC_PIN_GROUP(canfd_clk_a),
1603 SH_PFC_PIN_GROUP(canfd_clk_b),
1604 SH_PFC_PIN_GROUP(canfd0_data_a),
1605 SH_PFC_PIN_GROUP(canfd0_data_b),
1606 SH_PFC_PIN_GROUP(canfd1_data),
1607 SH_PFC_PIN_GROUP(du_rgb666),
1608 SH_PFC_PIN_GROUP(du_clk_out),
1609 SH_PFC_PIN_GROUP(du_sync),
1610 SH_PFC_PIN_GROUP(du_oddf),
1611 SH_PFC_PIN_GROUP(du_cde),
1612 SH_PFC_PIN_GROUP(du_disp),
1613 SH_PFC_PIN_GROUP(hscif0_data),
1614 SH_PFC_PIN_GROUP(hscif0_clk),
1615 SH_PFC_PIN_GROUP(hscif0_ctrl),
1616 SH_PFC_PIN_GROUP(hscif1_data),
1617 SH_PFC_PIN_GROUP(hscif1_clk),
1618 SH_PFC_PIN_GROUP(hscif1_ctrl),
1619 SH_PFC_PIN_GROUP(hscif2_data),
1620 SH_PFC_PIN_GROUP(hscif2_clk),
1621 SH_PFC_PIN_GROUP(hscif2_ctrl),
1622 SH_PFC_PIN_GROUP(hscif3_data),
1623 SH_PFC_PIN_GROUP(hscif3_clk),
1624 SH_PFC_PIN_GROUP(hscif3_ctrl),
1625 SH_PFC_PIN_GROUP(i2c0),
1626 SH_PFC_PIN_GROUP(i2c1),
1627 SH_PFC_PIN_GROUP(i2c2),
1628 SH_PFC_PIN_GROUP(i2c3_a),
1629 SH_PFC_PIN_GROUP(i2c3_b),
1630 SH_PFC_PIN_GROUP(i2c4),
1631 SH_PFC_PIN_GROUP(intc_ex_irq0),
1632 SH_PFC_PIN_GROUP(intc_ex_irq1),
1633 SH_PFC_PIN_GROUP(intc_ex_irq2),
1634 SH_PFC_PIN_GROUP(intc_ex_irq3),
1635 SH_PFC_PIN_GROUP(intc_ex_irq4),
1636 SH_PFC_PIN_GROUP(intc_ex_irq5),
1637 SH_PFC_PIN_GROUP(mmc_data1),
1638 SH_PFC_PIN_GROUP(mmc_data4),
1639 SH_PFC_PIN_GROUP(mmc_data8),
1640 SH_PFC_PIN_GROUP(mmc_ctrl),
1641 SH_PFC_PIN_GROUP(mmc_cd),
1642 SH_PFC_PIN_GROUP(mmc_wp),
1643 SH_PFC_PIN_GROUP(msiof0_clk),
1644 SH_PFC_PIN_GROUP(msiof0_sync),
1645 SH_PFC_PIN_GROUP(msiof0_ss1),
1646 SH_PFC_PIN_GROUP(msiof0_ss2),
1647 SH_PFC_PIN_GROUP(msiof0_txd),
1648 SH_PFC_PIN_GROUP(msiof0_rxd),
1649 SH_PFC_PIN_GROUP(msiof1_clk),
1650 SH_PFC_PIN_GROUP(msiof1_sync),
1651 SH_PFC_PIN_GROUP(msiof1_ss1),
1652 SH_PFC_PIN_GROUP(msiof1_ss2),
1653 SH_PFC_PIN_GROUP(msiof1_txd),
1654 SH_PFC_PIN_GROUP(msiof1_rxd),
1655 SH_PFC_PIN_GROUP(msiof2_clk),
1656 SH_PFC_PIN_GROUP(msiof2_sync),
1657 SH_PFC_PIN_GROUP(msiof2_ss1),
1658 SH_PFC_PIN_GROUP(msiof2_ss2),
1659 SH_PFC_PIN_GROUP(msiof2_txd),
1660 SH_PFC_PIN_GROUP(msiof2_rxd),
1661 SH_PFC_PIN_GROUP(msiof3_clk),
1662 SH_PFC_PIN_GROUP(msiof3_sync),
1663 SH_PFC_PIN_GROUP(msiof3_ss1),
1664 SH_PFC_PIN_GROUP(msiof3_ss2),
1665 SH_PFC_PIN_GROUP(msiof3_txd),
1666 SH_PFC_PIN_GROUP(msiof3_rxd),
1667 SH_PFC_PIN_GROUP(pwm0_a),
1668 SH_PFC_PIN_GROUP(pwm0_b),
1669 SH_PFC_PIN_GROUP(pwm1_a),
1670 SH_PFC_PIN_GROUP(pwm1_b),
1671 SH_PFC_PIN_GROUP(pwm2_a),
1672 SH_PFC_PIN_GROUP(pwm2_b),
1673 SH_PFC_PIN_GROUP(pwm3_a),
1674 SH_PFC_PIN_GROUP(pwm3_b),
1675 SH_PFC_PIN_GROUP(pwm4_a),
1676 SH_PFC_PIN_GROUP(pwm4_b),
1677 SH_PFC_PIN_GROUP(scif_clk_a),
1678 SH_PFC_PIN_GROUP(scif_clk_b),
1679 SH_PFC_PIN_GROUP(scif0_data),
1680 SH_PFC_PIN_GROUP(scif0_clk),
1681 SH_PFC_PIN_GROUP(scif0_ctrl),
1682 SH_PFC_PIN_GROUP(scif1_data_a),
1683 SH_PFC_PIN_GROUP(scif1_clk),
1684 SH_PFC_PIN_GROUP(scif1_ctrl),
1685 SH_PFC_PIN_GROUP(scif1_data_b),
1686 SH_PFC_PIN_GROUP(scif3_data),
1687 SH_PFC_PIN_GROUP(scif3_clk),
1688 SH_PFC_PIN_GROUP(scif3_ctrl),
1689 SH_PFC_PIN_GROUP(scif4_data),
1690 SH_PFC_PIN_GROUP(scif4_clk),
1691 SH_PFC_PIN_GROUP(scif4_ctrl),
1692 SH_PFC_PIN_GROUP(tmu_tclk1_a),
1693 SH_PFC_PIN_GROUP(tmu_tclk1_b),
1694 SH_PFC_PIN_GROUP(tmu_tclk2_a),
1695 SH_PFC_PIN_GROUP(tmu_tclk2_b),
1696 SH_PFC_PIN_GROUP(vin0_data8),
1697 SH_PFC_PIN_GROUP(vin0_data10),
1698 SH_PFC_PIN_GROUP(vin0_data12),
1699 SH_PFC_PIN_GROUP(vin0_sync),
1700 SH_PFC_PIN_GROUP(vin0_field),
1701 SH_PFC_PIN_GROUP(vin0_clkenb),
1702 SH_PFC_PIN_GROUP(vin0_clk),
1703 SH_PFC_PIN_GROUP(vin1_data8),
1704 SH_PFC_PIN_GROUP(vin1_data10),
1705 SH_PFC_PIN_GROUP(vin1_data12),
1706 SH_PFC_PIN_GROUP(vin1_sync),
1707 SH_PFC_PIN_GROUP(vin1_field),
1708 SH_PFC_PIN_GROUP(vin1_clkenb),
1709 SH_PFC_PIN_GROUP(vin1_clk),
1710 };
1711
1712 static const char * const canfd_clk_groups[] = {
1713 "canfd_clk_a",
1714 "canfd_clk_b",
1715 };
1716
1717 static const char * const canfd0_groups[] = {
1718 "canfd0_data_a",
1719 "canfd0_data_b",
1720 };
1721
1722 static const char * const canfd1_groups[] = {
1723 "canfd1_data",
1724 };
1725
1726 static const char * const du_groups[] = {
1727 "du_rgb666",
1728 "du_clk_out",
1729 "du_sync",
1730 "du_oddf",
1731 "du_cde",
1732 "du_disp",
1733 };
1734
1735 static const char * const hscif0_groups[] = {
1736 "hscif0_data",
1737 "hscif0_clk",
1738 "hscif0_ctrl",
1739 };
1740
1741 static const char * const hscif1_groups[] = {
1742 "hscif1_data",
1743 "hscif1_clk",
1744 "hscif1_ctrl",
1745 };
1746
1747 static const char * const hscif2_groups[] = {
1748 "hscif2_data",
1749 "hscif2_clk",
1750 "hscif2_ctrl",
1751 };
1752
1753 static const char * const hscif3_groups[] = {
1754 "hscif3_data",
1755 "hscif3_clk",
1756 "hscif3_ctrl",
1757 };
1758
1759 static const char * const i2c0_groups[] = {
1760 "i2c0",
1761 };
1762
1763 static const char * const i2c1_groups[] = {
1764 "i2c1",
1765 };
1766
1767 static const char * const i2c2_groups[] = {
1768 "i2c2",
1769 };
1770
1771 static const char * const i2c3_groups[] = {
1772 "i2c3_a",
1773 "i2c3_b",
1774 };
1775
1776 static const char * const i2c4_groups[] = {
1777 "i2c4",
1778 };
1779
1780 static const char * const intc_ex_groups[] = {
1781 "intc_ex_irq0",
1782 "intc_ex_irq1",
1783 "intc_ex_irq2",
1784 "intc_ex_irq3",
1785 "intc_ex_irq4",
1786 "intc_ex_irq5",
1787 };
1788
1789 static const char * const mmc_groups[] = {
1790 "mmc_data1",
1791 "mmc_data4",
1792 "mmc_data8",
1793 "mmc_ctrl",
1794 "mmc_cd",
1795 "mmc_wp",
1796 };
1797
1798 static const char * const msiof0_groups[] = {
1799 "msiof0_clk",
1800 "msiof0_sync",
1801 "msiof0_ss1",
1802 "msiof0_ss2",
1803 "msiof0_txd",
1804 "msiof0_rxd",
1805 };
1806
1807 static const char * const msiof1_groups[] = {
1808 "msiof1_clk",
1809 "msiof1_sync",
1810 "msiof1_ss1",
1811 "msiof1_ss2",
1812 "msiof1_txd",
1813 "msiof1_rxd",
1814 };
1815
1816 static const char * const msiof2_groups[] = {
1817 "msiof2_clk",
1818 "msiof2_sync",
1819 "msiof2_ss1",
1820 "msiof2_ss2",
1821 "msiof2_txd",
1822 "msiof2_rxd",
1823 };
1824
1825 static const char * const msiof3_groups[] = {
1826 "msiof3_clk",
1827 "msiof3_sync",
1828 "msiof3_ss1",
1829 "msiof3_ss2",
1830 "msiof3_txd",
1831 "msiof3_rxd",
1832 };
1833
1834 static const char * const pwm0_groups[] = {
1835 "pwm0_a",
1836 "pwm0_b",
1837 };
1838
1839 static const char * const pwm1_groups[] = {
1840 "pwm1_a",
1841 "pwm1_b",
1842 };
1843
1844 static const char * const pwm2_groups[] = {
1845 "pwm2_a",
1846 "pwm2_b",
1847 };
1848
1849 static const char * const pwm3_groups[] = {
1850 "pwm3_a",
1851 "pwm3_b",
1852 };
1853
1854 static const char * const pwm4_groups[] = {
1855 "pwm4_a",
1856 "pwm4_b",
1857 };
1858
1859 static const char * const scif_clk_groups[] = {
1860 "scif_clk_a",
1861 "scif_clk_b",
1862 };
1863
1864 static const char * const scif0_groups[] = {
1865 "scif0_data",
1866 "scif0_clk",
1867 "scif0_ctrl",
1868 };
1869
1870 static const char * const scif1_groups[] = {
1871 "scif1_data_a",
1872 "scif1_clk",
1873 "scif1_ctrl",
1874 "scif1_data_b",
1875 };
1876
1877 static const char * const scif3_groups[] = {
1878 "scif3_data",
1879 "scif3_clk",
1880 "scif3_ctrl",
1881 };
1882
1883 static const char * const scif4_groups[] = {
1884 "scif4_data",
1885 "scif4_clk",
1886 "scif4_ctrl",
1887 };
1888
1889 static const char * const tmu_groups[] = {
1890 "tmu_tclk1_a",
1891 "tmu_tclk1_b",
1892 "tmu_tclk2_a",
1893 "tmu_tclk2_b",
1894 };
1895
1896 static const char * const vin0_groups[] = {
1897 "vin0_data8",
1898 "vin0_data10",
1899 "vin0_data12",
1900 "vin0_sync",
1901 "vin0_field",
1902 "vin0_clkenb",
1903 "vin0_clk",
1904 };
1905
1906 static const char * const vin1_groups[] = {
1907 "vin1_data8",
1908 "vin1_data10",
1909 "vin1_data12",
1910 "vin1_sync",
1911 "vin1_field",
1912 "vin1_clkenb",
1913 "vin1_clk",
1914 };
1915
1916 static const struct sh_pfc_function pinmux_functions[] = {
1917 SH_PFC_FUNCTION(canfd_clk),
1918 SH_PFC_FUNCTION(canfd0),
1919 SH_PFC_FUNCTION(canfd1),
1920 SH_PFC_FUNCTION(du),
1921 SH_PFC_FUNCTION(hscif0),
1922 SH_PFC_FUNCTION(hscif1),
1923 SH_PFC_FUNCTION(hscif2),
1924 SH_PFC_FUNCTION(hscif3),
1925 SH_PFC_FUNCTION(i2c0),
1926 SH_PFC_FUNCTION(i2c1),
1927 SH_PFC_FUNCTION(i2c2),
1928 SH_PFC_FUNCTION(i2c3),
1929 SH_PFC_FUNCTION(i2c4),
1930 SH_PFC_FUNCTION(intc_ex),
1931 SH_PFC_FUNCTION(mmc),
1932 SH_PFC_FUNCTION(msiof0),
1933 SH_PFC_FUNCTION(msiof1),
1934 SH_PFC_FUNCTION(msiof2),
1935 SH_PFC_FUNCTION(msiof3),
1936 SH_PFC_FUNCTION(pwm0),
1937 SH_PFC_FUNCTION(pwm1),
1938 SH_PFC_FUNCTION(pwm2),
1939 SH_PFC_FUNCTION(pwm3),
1940 SH_PFC_FUNCTION(pwm4),
1941 SH_PFC_FUNCTION(scif_clk),
1942 SH_PFC_FUNCTION(scif0),
1943 SH_PFC_FUNCTION(scif1),
1944 SH_PFC_FUNCTION(scif3),
1945 SH_PFC_FUNCTION(scif4),
1946 SH_PFC_FUNCTION(tmu),
1947 SH_PFC_FUNCTION(vin0),
1948 SH_PFC_FUNCTION(vin1),
1949 };
1950
1951 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1952 #define F_(x, y) FN_##y
1953 #define FM(x) FN_##x
1954 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
1955 0, 0,
1956 0, 0,
1957 0, 0,
1958 0, 0,
1959 0, 0,
1960 0, 0,
1961 0, 0,
1962 0, 0,
1963 0, 0,
1964 0, 0,
1965 GP_0_21_FN, GPSR0_21,
1966 GP_0_20_FN, GPSR0_20,
1967 GP_0_19_FN, GPSR0_19,
1968 GP_0_18_FN, GPSR0_18,
1969 GP_0_17_FN, GPSR0_17,
1970 GP_0_16_FN, GPSR0_16,
1971 GP_0_15_FN, GPSR0_15,
1972 GP_0_14_FN, GPSR0_14,
1973 GP_0_13_FN, GPSR0_13,
1974 GP_0_12_FN, GPSR0_12,
1975 GP_0_11_FN, GPSR0_11,
1976 GP_0_10_FN, GPSR0_10,
1977 GP_0_9_FN, GPSR0_9,
1978 GP_0_8_FN, GPSR0_8,
1979 GP_0_7_FN, GPSR0_7,
1980 GP_0_6_FN, GPSR0_6,
1981 GP_0_5_FN, GPSR0_5,
1982 GP_0_4_FN, GPSR0_4,
1983 GP_0_3_FN, GPSR0_3,
1984 GP_0_2_FN, GPSR0_2,
1985 GP_0_1_FN, GPSR0_1,
1986 GP_0_0_FN, GPSR0_0, }
1987 },
1988 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
1989 0, 0,
1990 0, 0,
1991 0, 0,
1992 0, 0,
1993 GP_1_27_FN, GPSR1_27,
1994 GP_1_26_FN, GPSR1_26,
1995 GP_1_25_FN, GPSR1_25,
1996 GP_1_24_FN, GPSR1_24,
1997 GP_1_23_FN, GPSR1_23,
1998 GP_1_22_FN, GPSR1_22,
1999 GP_1_21_FN, GPSR1_21,
2000 GP_1_20_FN, GPSR1_20,
2001 GP_1_19_FN, GPSR1_19,
2002 GP_1_18_FN, GPSR1_18,
2003 GP_1_17_FN, GPSR1_17,
2004 GP_1_16_FN, GPSR1_16,
2005 GP_1_15_FN, GPSR1_15,
2006 GP_1_14_FN, GPSR1_14,
2007 GP_1_13_FN, GPSR1_13,
2008 GP_1_12_FN, GPSR1_12,
2009 GP_1_11_FN, GPSR1_11,
2010 GP_1_10_FN, GPSR1_10,
2011 GP_1_9_FN, GPSR1_9,
2012 GP_1_8_FN, GPSR1_8,
2013 GP_1_7_FN, GPSR1_7,
2014 GP_1_6_FN, GPSR1_6,
2015 GP_1_5_FN, GPSR1_5,
2016 GP_1_4_FN, GPSR1_4,
2017 GP_1_3_FN, GPSR1_3,
2018 GP_1_2_FN, GPSR1_2,
2019 GP_1_1_FN, GPSR1_1,
2020 GP_1_0_FN, GPSR1_0, }
2021 },
2022 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2023 0, 0,
2024 0, 0,
2025 0, 0,
2026 0, 0,
2027 0, 0,
2028 0, 0,
2029 0, 0,
2030 0, 0,
2031 0, 0,
2032 0, 0,
2033 0, 0,
2034 0, 0,
2035 0, 0,
2036 0, 0,
2037 0, 0,
2038 GP_2_16_FN, GPSR2_16,
2039 GP_2_15_FN, GPSR2_15,
2040 GP_2_14_FN, GPSR2_14,
2041 GP_2_13_FN, GPSR2_13,
2042 GP_2_12_FN, GPSR2_12,
2043 GP_2_11_FN, GPSR2_11,
2044 GP_2_10_FN, GPSR2_10,
2045 GP_2_9_FN, GPSR2_9,
2046 GP_2_8_FN, GPSR2_8,
2047 GP_2_7_FN, GPSR2_7,
2048 GP_2_6_FN, GPSR2_6,
2049 GP_2_5_FN, GPSR2_5,
2050 GP_2_4_FN, GPSR2_4,
2051 GP_2_3_FN, GPSR2_3,
2052 GP_2_2_FN, GPSR2_2,
2053 GP_2_1_FN, GPSR2_1,
2054 GP_2_0_FN, GPSR2_0, }
2055 },
2056 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2057 0, 0,
2058 0, 0,
2059 0, 0,
2060 0, 0,
2061 0, 0,
2062 0, 0,
2063 0, 0,
2064 0, 0,
2065 0, 0,
2066 0, 0,
2067 0, 0,
2068 0, 0,
2069 0, 0,
2070 0, 0,
2071 0, 0,
2072 GP_3_16_FN, GPSR3_16,
2073 GP_3_15_FN, GPSR3_15,
2074 GP_3_14_FN, GPSR3_14,
2075 GP_3_13_FN, GPSR3_13,
2076 GP_3_12_FN, GPSR3_12,
2077 GP_3_11_FN, GPSR3_11,
2078 GP_3_10_FN, GPSR3_10,
2079 GP_3_9_FN, GPSR3_9,
2080 GP_3_8_FN, GPSR3_8,
2081 GP_3_7_FN, GPSR3_7,
2082 GP_3_6_FN, GPSR3_6,
2083 GP_3_5_FN, GPSR3_5,
2084 GP_3_4_FN, GPSR3_4,
2085 GP_3_3_FN, GPSR3_3,
2086 GP_3_2_FN, GPSR3_2,
2087 GP_3_1_FN, GPSR3_1,
2088 GP_3_0_FN, GPSR3_0, }
2089 },
2090 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2091 0, 0,
2092 0, 0,
2093 0, 0,
2094 0, 0,
2095 0, 0,
2096 0, 0,
2097 0, 0,
2098 0, 0,
2099 0, 0,
2100 0, 0,
2101 0, 0,
2102 0, 0,
2103 0, 0,
2104 0, 0,
2105 0, 0,
2106 0, 0,
2107 0, 0,
2108 0, 0,
2109 0, 0,
2110 0, 0,
2111 0, 0,
2112 0, 0,
2113 0, 0,
2114 0, 0,
2115 0, 0,
2116 0, 0,
2117 GP_4_5_FN, GPSR4_5,
2118 GP_4_4_FN, GPSR4_4,
2119 GP_4_3_FN, GPSR4_3,
2120 GP_4_2_FN, GPSR4_2,
2121 GP_4_1_FN, GPSR4_1,
2122 GP_4_0_FN, GPSR4_0, }
2123 },
2124 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2125 0, 0,
2126 0, 0,
2127 0, 0,
2128 0, 0,
2129 0, 0,
2130 0, 0,
2131 0, 0,
2132 0, 0,
2133 0, 0,
2134 0, 0,
2135 0, 0,
2136 0, 0,
2137 0, 0,
2138 0, 0,
2139 0, 0,
2140 0, 0,
2141 0, 0,
2142 GP_5_14_FN, GPSR5_14,
2143 GP_5_13_FN, GPSR5_13,
2144 GP_5_12_FN, GPSR5_12,
2145 GP_5_11_FN, GPSR5_11,
2146 GP_5_10_FN, GPSR5_10,
2147 GP_5_9_FN, GPSR5_9,
2148 GP_5_8_FN, GPSR5_8,
2149 GP_5_7_FN, GPSR5_7,
2150 GP_5_6_FN, GPSR5_6,
2151 GP_5_5_FN, GPSR5_5,
2152 GP_5_4_FN, GPSR5_4,
2153 GP_5_3_FN, GPSR5_3,
2154 GP_5_2_FN, GPSR5_2,
2155 GP_5_1_FN, GPSR5_1,
2156 GP_5_0_FN, GPSR5_0, }
2157 },
2158 #undef F_
2159 #undef FM
2160
2161 #define F_(x, y) x,
2162 #define FM(x) FN_##x,
2163 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2164 IP0_31_28
2165 IP0_27_24
2166 IP0_23_20
2167 IP0_19_16
2168 IP0_15_12
2169 IP0_11_8
2170 IP0_7_4
2171 IP0_3_0 }
2172 },
2173 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2174 IP1_31_28
2175 IP1_27_24
2176 IP1_23_20
2177 IP1_19_16
2178 IP1_15_12
2179 IP1_11_8
2180 IP1_7_4
2181 IP1_3_0 }
2182 },
2183 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2184 IP2_31_28
2185 IP2_27_24
2186 IP2_23_20
2187 IP2_19_16
2188 IP2_15_12
2189 IP2_11_8
2190 IP2_7_4
2191 IP2_3_0 }
2192 },
2193 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2194 IP3_31_28
2195 IP3_27_24
2196 IP3_23_20
2197 IP3_19_16
2198 IP3_15_12
2199 IP3_11_8
2200 IP3_7_4
2201 IP3_3_0 }
2202 },
2203 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2204 IP4_31_28
2205 IP4_27_24
2206 IP4_23_20
2207 IP4_19_16
2208 IP4_15_12
2209 IP4_11_8
2210 IP4_7_4
2211 IP4_3_0 }
2212 },
2213 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2214 IP5_31_28
2215 IP5_27_24
2216 IP5_23_20
2217 IP5_19_16
2218 IP5_15_12
2219 IP5_11_8
2220 IP5_7_4
2221 IP5_3_0 }
2222 },
2223 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2224 IP6_31_28
2225 IP6_27_24
2226 IP6_23_20
2227 IP6_19_16
2228 IP6_15_12
2229 IP6_11_8
2230 IP6_7_4
2231 IP6_3_0 }
2232 },
2233 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2234 IP7_31_28
2235 IP7_27_24
2236 IP7_23_20
2237 IP7_19_16
2238 IP7_15_12
2239 IP7_11_8
2240 IP7_7_4
2241 IP7_3_0 }
2242 },
2243 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2244 IP8_31_28
2245 IP8_27_24
2246 IP8_23_20
2247 IP8_19_16
2248 IP8_15_12
2249 IP8_11_8
2250 IP8_7_4
2251 IP8_3_0 }
2252 },
2253 #undef F_
2254 #undef FM
2255
2256 #define F_(x, y) x,
2257 #define FM(x) FN_##x,
2258 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2259 4, 4, 4, 4,
2260 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
2261 /* RESERVED 31, 30, 29, 28 */
2262 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2263 /* RESERVED 27, 26, 25, 24 */
2264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2265 /* RESERVED 23, 22, 21, 20 */
2266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2267 /* RESERVED 19, 18, 17, 16 */
2268 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2269 /* RESERVED 15, 14, 13, 12 */
2270 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2271 MOD_SEL0_11
2272 MOD_SEL0_10
2273 MOD_SEL0_9
2274 MOD_SEL0_8
2275 MOD_SEL0_7
2276 MOD_SEL0_6
2277 MOD_SEL0_5
2278 MOD_SEL0_4
2279 MOD_SEL0_3
2280 MOD_SEL0_2
2281 MOD_SEL0_1
2282 MOD_SEL0_0 }
2283 },
2284 { },
2285 };
2286
2287 static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2288 u32 *pocctrl)
2289 {
2290 int bit = pin & 0x1f;
2291
2292 *pocctrl = 0xe6060380;
2293 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2294 return bit;
2295 if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2296 return bit + 22;
2297
2298 *pocctrl += 4;
2299 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2300 return bit - 10;
2301 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
2302 return bit + 7;
2303
2304 return -EINVAL;
2305 }
2306
2307 static const struct sh_pfc_soc_operations pinmux_ops = {
2308 .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2309 };
2310
2311 const struct sh_pfc_soc_info r8a77970_pinmux_info = {
2312 .name = "r8a77970_pfc",
2313 .ops = &pinmux_ops,
2314 .unlock_reg = 0xe6060000, /* PMMR */
2315
2316 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2317
2318 .pins = pinmux_pins,
2319 .nr_pins = ARRAY_SIZE(pinmux_pins),
2320 .groups = pinmux_groups,
2321 .nr_groups = ARRAY_SIZE(pinmux_groups),
2322 .functions = pinmux_functions,
2323 .nr_functions = ARRAY_SIZE(pinmux_functions),
2324
2325 .cfg_regs = pinmux_config_regs,
2326
2327 .pinmux_data = pinmux_data,
2328 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2329 };
Linux with added FPC-III support