?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.16.11
[linux/fpc-iii.git] / drivers / pinctrl / stm32 / pinctrl-stm32.c
blob617df163067fef8cdc6b8530c91b6d3ab0ce3e9d
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 *
7 * Heavily based on Mediatek's pinctrl driver
8 */
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/io.h>
12 #include <linux/irq.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/pinctrl/machine.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinconf-generic.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 #include <linux/platform_device.h>
26 #include <linux/regmap.h>
27 #include <linux/reset.h>
28 #include <linux/slab.h>
29
30 #include "../core.h"
31 #include "../pinconf.h"
32 #include "../pinctrl-utils.h"
33 #include "pinctrl-stm32.h"
34
35 #define STM32_GPIO_MODER 0x00
36 #define STM32_GPIO_TYPER 0x04
37 #define STM32_GPIO_SPEEDR 0x08
38 #define STM32_GPIO_PUPDR 0x0c
39 #define STM32_GPIO_IDR 0x10
40 #define STM32_GPIO_ODR 0x14
41 #define STM32_GPIO_BSRR 0x18
42 #define STM32_GPIO_LCKR 0x1c
43 #define STM32_GPIO_AFRL 0x20
44 #define STM32_GPIO_AFRH 0x24
45
46 #define STM32_GPIO_PINS_PER_BANK 16
47 #define STM32_GPIO_IRQ_LINE 16
48
49 #define gpio_range_to_bank(chip) \
50 container_of(chip, struct stm32_gpio_bank, range)
51
52 static const char * const stm32_gpio_functions[] = {
53 "gpio", "af0", "af1",
54 "af2", "af3", "af4",
55 "af5", "af6", "af7",
56 "af8", "af9", "af10",
57 "af11", "af12", "af13",
58 "af14", "af15", "analog",
59 };
60
61 struct stm32_pinctrl_group {
62 const char *name;
63 unsigned long config;
64 unsigned pin;
65 };
66
67 struct stm32_gpio_bank {
68 void __iomem *base;
69 struct clk *clk;
70 spinlock_t lock;
71 struct gpio_chip gpio_chip;
72 struct pinctrl_gpio_range range;
73 struct fwnode_handle *fwnode;
74 struct irq_domain *domain;
75 u32 bank_nr;
76 };
77
78 struct stm32_pinctrl {
79 struct device *dev;
80 struct pinctrl_dev *pctl_dev;
81 struct pinctrl_desc pctl_desc;
82 struct stm32_pinctrl_group *groups;
83 unsigned ngroups;
84 const char **grp_names;
85 struct stm32_gpio_bank *banks;
86 unsigned nbanks;
87 const struct stm32_pinctrl_match_data *match_data;
88 struct irq_domain *domain;
89 struct regmap *regmap;
90 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
91 };
92
93 static inline int stm32_gpio_pin(int gpio)
94 {
95 return gpio % STM32_GPIO_PINS_PER_BANK;
96 }
97
98 static inline u32 stm32_gpio_get_mode(u32 function)
99 {
100 switch (function) {
101 case STM32_PIN_GPIO:
102 return 0;
103 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
104 return 2;
105 case STM32_PIN_ANALOG:
106 return 3;
107 }
108
109 return 0;
110 }
111
112 static inline u32 stm32_gpio_get_alt(u32 function)
113 {
114 switch (function) {
115 case STM32_PIN_GPIO:
116 return 0;
117 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
118 return function - 1;
119 case STM32_PIN_ANALOG:
120 return 0;
121 }
122
123 return 0;
124 }
125
126 /* GPIO functions */
127
128 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
129 unsigned offset, int value)
130 {
131 if (!value)
132 offset += STM32_GPIO_PINS_PER_BANK;
133
134 clk_enable(bank->clk);
135
136 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
137
138 clk_disable(bank->clk);
139 }
140
141 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
142 {
143 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
144 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
145 struct pinctrl_gpio_range *range;
146 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
147
148 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
149 if (!range) {
150 dev_err(pctl->dev, "pin %d not in range.\n", pin);
151 return -EINVAL;
152 }
153
154 return pinctrl_gpio_request(chip->base + offset);
155 }
156
157 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
158 {
159 pinctrl_gpio_free(chip->base + offset);
160 }
161
162 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
163 {
164 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
165 int ret;
166
167 clk_enable(bank->clk);
168
169 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
170
171 clk_disable(bank->clk);
172
173 return ret;
174 }
175
176 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
177 {
178 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
179
180 __stm32_gpio_set(bank, offset, value);
181 }
182
183 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
184 {
185 return pinctrl_gpio_direction_input(chip->base + offset);
186 }
187
188 static int stm32_gpio_direction_output(struct gpio_chip *chip,
189 unsigned offset, int value)
190 {
191 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
192
193 __stm32_gpio_set(bank, offset, value);
194 pinctrl_gpio_direction_output(chip->base + offset);
195
196 return 0;
197 }
198
199
200 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
201 {
202 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
203 struct irq_fwspec fwspec;
204
205 fwspec.fwnode = bank->fwnode;
206 fwspec.param_count = 2;
207 fwspec.param[0] = offset;
208 fwspec.param[1] = IRQ_TYPE_NONE;
209
210 return irq_create_fwspec_mapping(&fwspec);
211 }
212
213 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
214 {
215 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
216 int pin = stm32_gpio_pin(offset);
217 int ret;
218 u32 mode, alt;
219
220 stm32_pmx_get_mode(bank, pin, &mode, &alt);
221 if ((alt == 0) && (mode == 0))
222 ret = 1;
223 else if ((alt == 0) && (mode == 1))
224 ret = 0;
225 else
226 ret = -EINVAL;
227
228 return ret;
229 }
230
231 static const struct gpio_chip stm32_gpio_template = {
232 .request = stm32_gpio_request,
233 .free = stm32_gpio_free,
234 .get = stm32_gpio_get,
235 .set = stm32_gpio_set,
236 .direction_input = stm32_gpio_direction_input,
237 .direction_output = stm32_gpio_direction_output,
238 .to_irq = stm32_gpio_to_irq,
239 .get_direction = stm32_gpio_get_direction,
240 };
241
242 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
243 {
244 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
245 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
246 int ret;
247
248 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
249 if (ret)
250 return ret;
251
252 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
253 if (ret) {
254 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
255 irq_data->hwirq);
256 return ret;
257 }
258
259 return 0;
260 }
261
262 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
263 {
264 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
265
266 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
267 }
268
269 static struct irq_chip stm32_gpio_irq_chip = {
270 .name = "stm32gpio",
271 .irq_eoi = irq_chip_eoi_parent,
272 .irq_mask = irq_chip_mask_parent,
273 .irq_unmask = irq_chip_unmask_parent,
274 .irq_set_type = irq_chip_set_type_parent,
275 .irq_request_resources = stm32_gpio_irq_request_resources,
276 .irq_release_resources = stm32_gpio_irq_release_resources,
277 };
278
279 static int stm32_gpio_domain_translate(struct irq_domain *d,
280 struct irq_fwspec *fwspec,
281 unsigned long *hwirq,
282 unsigned int *type)
283 {
284 if ((fwspec->param_count != 2) ||
285 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
286 return -EINVAL;
287
288 *hwirq = fwspec->param[0];
289 *type = fwspec->param[1];
290 return 0;
291 }
292
293 static int stm32_gpio_domain_activate(struct irq_domain *d,
294 struct irq_data *irq_data, bool reserve)
295 {
296 struct stm32_gpio_bank *bank = d->host_data;
297 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
298
299 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr);
300 return 0;
301 }
302
303 static int stm32_gpio_domain_alloc(struct irq_domain *d,
304 unsigned int virq,
305 unsigned int nr_irqs, void *data)
306 {
307 struct stm32_gpio_bank *bank = d->host_data;
308 struct irq_fwspec *fwspec = data;
309 struct irq_fwspec parent_fwspec;
310 irq_hw_number_t hwirq;
311
312 hwirq = fwspec->param[0];
313 parent_fwspec.fwnode = d->parent->fwnode;
314 parent_fwspec.param_count = 2;
315 parent_fwspec.param[0] = fwspec->param[0];
316 parent_fwspec.param[1] = fwspec->param[1];
317
318 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
319 bank);
320
321 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
322 }
323
324 static const struct irq_domain_ops stm32_gpio_domain_ops = {
325 .translate = stm32_gpio_domain_translate,
326 .alloc = stm32_gpio_domain_alloc,
327 .free = irq_domain_free_irqs_common,
328 .activate = stm32_gpio_domain_activate,
329 };
330
331 /* Pinctrl functions */
332 static struct stm32_pinctrl_group *
333 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
334 {
335 int i;
336
337 for (i = 0; i < pctl->ngroups; i++) {
338 struct stm32_pinctrl_group *grp = pctl->groups + i;
339
340 if (grp->pin == pin)
341 return grp;
342 }
343
344 return NULL;
345 }
346
347 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
348 u32 pin_num, u32 fnum)
349 {
350 int i;
351
352 for (i = 0; i < pctl->match_data->npins; i++) {
353 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
354 const struct stm32_desc_function *func = pin->functions;
355
356 if (pin->pin.number != pin_num)
357 continue;
358
359 while (func && func->name) {
360 if (func->num == fnum)
361 return true;
362 func++;
363 }
364
365 break;
366 }
367
368 return false;
369 }
370
371 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
372 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
373 struct pinctrl_map **map, unsigned *reserved_maps,
374 unsigned *num_maps)
375 {
376 if (*num_maps == *reserved_maps)
377 return -ENOSPC;
378
379 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
380 (*map)[*num_maps].data.mux.group = grp->name;
381
382 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
383 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
384 fnum, pin);
385 return -EINVAL;
386 }
387
388 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
389 (*num_maps)++;
390
391 return 0;
392 }
393
394 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
395 struct device_node *node,
396 struct pinctrl_map **map,
397 unsigned *reserved_maps,
398 unsigned *num_maps)
399 {
400 struct stm32_pinctrl *pctl;
401 struct stm32_pinctrl_group *grp;
402 struct property *pins;
403 u32 pinfunc, pin, func;
404 unsigned long *configs;
405 unsigned int num_configs;
406 bool has_config = 0;
407 unsigned reserve = 0;
408 int num_pins, num_funcs, maps_per_pin, i, err;
409
410 pctl = pinctrl_dev_get_drvdata(pctldev);
411
412 pins = of_find_property(node, "pinmux", NULL);
413 if (!pins) {
414 dev_err(pctl->dev, "missing pins property in node %s .\n",
415 node->name);
416 return -EINVAL;
417 }
418
419 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
420 &num_configs);
421 if (err)
422 return err;
423
424 if (num_configs)
425 has_config = 1;
426
427 num_pins = pins->length / sizeof(u32);
428 num_funcs = num_pins;
429 maps_per_pin = 0;
430 if (num_funcs)
431 maps_per_pin++;
432 if (has_config && num_pins >= 1)
433 maps_per_pin++;
434
435 if (!num_pins || !maps_per_pin)
436 return -EINVAL;
437
438 reserve = num_pins * maps_per_pin;
439
440 err = pinctrl_utils_reserve_map(pctldev, map,
441 reserved_maps, num_maps, reserve);
442 if (err)
443 return err;
444
445 for (i = 0; i < num_pins; i++) {
446 err = of_property_read_u32_index(node, "pinmux",
447 i, &pinfunc);
448 if (err)
449 return err;
450
451 pin = STM32_GET_PIN_NO(pinfunc);
452 func = STM32_GET_PIN_FUNC(pinfunc);
453
454 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
455 dev_err(pctl->dev, "invalid function.\n");
456 return -EINVAL;
457 }
458
459 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
460 if (!grp) {
461 dev_err(pctl->dev, "unable to match pin %d to group\n",
462 pin);
463 return -EINVAL;
464 }
465
466 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
467 reserved_maps, num_maps);
468 if (err)
469 return err;
470
471 if (has_config) {
472 err = pinctrl_utils_add_map_configs(pctldev, map,
473 reserved_maps, num_maps, grp->name,
474 configs, num_configs,
475 PIN_MAP_TYPE_CONFIGS_GROUP);
476 if (err)
477 return err;
478 }
479 }
480
481 return 0;
482 }
483
484 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
485 struct device_node *np_config,
486 struct pinctrl_map **map, unsigned *num_maps)
487 {
488 struct device_node *np;
489 unsigned reserved_maps;
490 int ret;
491
492 *map = NULL;
493 *num_maps = 0;
494 reserved_maps = 0;
495
496 for_each_child_of_node(np_config, np) {
497 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
498 &reserved_maps, num_maps);
499 if (ret < 0) {
500 pinctrl_utils_free_map(pctldev, *map, *num_maps);
501 return ret;
502 }
503 }
504
505 return 0;
506 }
507
508 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
509 {
510 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
511
512 return pctl->ngroups;
513 }
514
515 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
516 unsigned group)
517 {
518 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
519
520 return pctl->groups[group].name;
521 }
522
523 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
524 unsigned group,
525 const unsigned **pins,
526 unsigned *num_pins)
527 {
528 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
529
530 *pins = (unsigned *)&pctl->groups[group].pin;
531 *num_pins = 1;
532
533 return 0;
534 }
535
536 static const struct pinctrl_ops stm32_pctrl_ops = {
537 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
538 .dt_free_map = pinctrl_utils_free_map,
539 .get_groups_count = stm32_pctrl_get_groups_count,
540 .get_group_name = stm32_pctrl_get_group_name,
541 .get_group_pins = stm32_pctrl_get_group_pins,
542 };
543
544
545 /* Pinmux functions */
546
547 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
548 {
549 return ARRAY_SIZE(stm32_gpio_functions);
550 }
551
552 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
553 unsigned selector)
554 {
555 return stm32_gpio_functions[selector];
556 }
557
558 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
559 unsigned function,
560 const char * const **groups,
561 unsigned * const num_groups)
562 {
563 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
564
565 *groups = pctl->grp_names;
566 *num_groups = pctl->ngroups;
567
568 return 0;
569 }
570
571 static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
572 int pin, u32 mode, u32 alt)
573 {
574 u32 val;
575 int alt_shift = (pin % 8) * 4;
576 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
577 unsigned long flags;
578
579 clk_enable(bank->clk);
580 spin_lock_irqsave(&bank->lock, flags);
581
582 val = readl_relaxed(bank->base + alt_offset);
583 val &= ~GENMASK(alt_shift + 3, alt_shift);
584 val |= (alt << alt_shift);
585 writel_relaxed(val, bank->base + alt_offset);
586
587 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
588 val &= ~GENMASK(pin * 2 + 1, pin * 2);
589 val |= mode << (pin * 2);
590 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
591
592 spin_unlock_irqrestore(&bank->lock, flags);
593 clk_disable(bank->clk);
594 }
595
596 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
597 u32 *alt)
598 {
599 u32 val;
600 int alt_shift = (pin % 8) * 4;
601 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
602 unsigned long flags;
603
604 clk_enable(bank->clk);
605 spin_lock_irqsave(&bank->lock, flags);
606
607 val = readl_relaxed(bank->base + alt_offset);
608 val &= GENMASK(alt_shift + 3, alt_shift);
609 *alt = val >> alt_shift;
610
611 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
612 val &= GENMASK(pin * 2 + 1, pin * 2);
613 *mode = val >> (pin * 2);
614
615 spin_unlock_irqrestore(&bank->lock, flags);
616 clk_disable(bank->clk);
617 }
618
619 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
620 unsigned function,
621 unsigned group)
622 {
623 bool ret;
624 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
625 struct stm32_pinctrl_group *g = pctl->groups + group;
626 struct pinctrl_gpio_range *range;
627 struct stm32_gpio_bank *bank;
628 u32 mode, alt;
629 int pin;
630
631 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
632 if (!ret) {
633 dev_err(pctl->dev, "invalid function %d on group %d .\n",
634 function, group);
635 return -EINVAL;
636 }
637
638 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
639 bank = gpiochip_get_data(range->gc);
640 pin = stm32_gpio_pin(g->pin);
641
642 mode = stm32_gpio_get_mode(function);
643 alt = stm32_gpio_get_alt(function);
644
645 stm32_pmx_set_mode(bank, pin, mode, alt);
646
647 return 0;
648 }
649
650 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
651 struct pinctrl_gpio_range *range, unsigned gpio,
652 bool input)
653 {
654 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
655 int pin = stm32_gpio_pin(gpio);
656
657 stm32_pmx_set_mode(bank, pin, !input, 0);
658
659 return 0;
660 }
661
662 static const struct pinmux_ops stm32_pmx_ops = {
663 .get_functions_count = stm32_pmx_get_funcs_cnt,
664 .get_function_name = stm32_pmx_get_func_name,
665 .get_function_groups = stm32_pmx_get_func_groups,
666 .set_mux = stm32_pmx_set_mux,
667 .gpio_set_direction = stm32_pmx_gpio_set_direction,
668 .strict = true,
669 };
670
671 /* Pinconf functions */
672
673 static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
674 unsigned offset, u32 drive)
675 {
676 unsigned long flags;
677 u32 val;
678
679 clk_enable(bank->clk);
680 spin_lock_irqsave(&bank->lock, flags);
681
682 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
683 val &= ~BIT(offset);
684 val |= drive << offset;
685 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
686
687 spin_unlock_irqrestore(&bank->lock, flags);
688 clk_disable(bank->clk);
689 }
690
691 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
692 unsigned int offset)
693 {
694 unsigned long flags;
695 u32 val;
696
697 clk_enable(bank->clk);
698 spin_lock_irqsave(&bank->lock, flags);
699
700 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
701 val &= BIT(offset);
702
703 spin_unlock_irqrestore(&bank->lock, flags);
704 clk_disable(bank->clk);
705
706 return (val >> offset);
707 }
708
709 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
710 unsigned offset, u32 speed)
711 {
712 unsigned long flags;
713 u32 val;
714
715 clk_enable(bank->clk);
716 spin_lock_irqsave(&bank->lock, flags);
717
718 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
719 val &= ~GENMASK(offset * 2 + 1, offset * 2);
720 val |= speed << (offset * 2);
721 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
722
723 spin_unlock_irqrestore(&bank->lock, flags);
724 clk_disable(bank->clk);
725 }
726
727 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
728 unsigned int offset)
729 {
730 unsigned long flags;
731 u32 val;
732
733 clk_enable(bank->clk);
734 spin_lock_irqsave(&bank->lock, flags);
735
736 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
737 val &= GENMASK(offset * 2 + 1, offset * 2);
738
739 spin_unlock_irqrestore(&bank->lock, flags);
740 clk_disable(bank->clk);
741
742 return (val >> (offset * 2));
743 }
744
745 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
746 unsigned offset, u32 bias)
747 {
748 unsigned long flags;
749 u32 val;
750
751 clk_enable(bank->clk);
752 spin_lock_irqsave(&bank->lock, flags);
753
754 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
755 val &= ~GENMASK(offset * 2 + 1, offset * 2);
756 val |= bias << (offset * 2);
757 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
758
759 spin_unlock_irqrestore(&bank->lock, flags);
760 clk_disable(bank->clk);
761 }
762
763 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
764 unsigned int offset)
765 {
766 unsigned long flags;
767 u32 val;
768
769 clk_enable(bank->clk);
770 spin_lock_irqsave(&bank->lock, flags);
771
772 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
773 val &= GENMASK(offset * 2 + 1, offset * 2);
774
775 spin_unlock_irqrestore(&bank->lock, flags);
776 clk_disable(bank->clk);
777
778 return (val >> (offset * 2));
779 }
780
781 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
782 unsigned int offset, bool dir)
783 {
784 unsigned long flags;
785 u32 val;
786
787 clk_enable(bank->clk);
788 spin_lock_irqsave(&bank->lock, flags);
789
790 if (dir)
791 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
792 BIT(offset));
793 else
794 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
795 BIT(offset));
796
797 spin_unlock_irqrestore(&bank->lock, flags);
798 clk_disable(bank->clk);
799
800 return val;
801 }
802
803 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
804 unsigned int pin, enum pin_config_param param,
805 enum pin_config_param arg)
806 {
807 struct pinctrl_gpio_range *range;
808 struct stm32_gpio_bank *bank;
809 int offset, ret = 0;
810
811 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
812 bank = gpiochip_get_data(range->gc);
813 offset = stm32_gpio_pin(pin);
814
815 switch (param) {
816 case PIN_CONFIG_DRIVE_PUSH_PULL:
817 stm32_pconf_set_driving(bank, offset, 0);
818 break;
819 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
820 stm32_pconf_set_driving(bank, offset, 1);
821 break;
822 case PIN_CONFIG_SLEW_RATE:
823 stm32_pconf_set_speed(bank, offset, arg);
824 break;
825 case PIN_CONFIG_BIAS_DISABLE:
826 stm32_pconf_set_bias(bank, offset, 0);
827 break;
828 case PIN_CONFIG_BIAS_PULL_UP:
829 stm32_pconf_set_bias(bank, offset, 1);
830 break;
831 case PIN_CONFIG_BIAS_PULL_DOWN:
832 stm32_pconf_set_bias(bank, offset, 2);
833 break;
834 case PIN_CONFIG_OUTPUT:
835 __stm32_gpio_set(bank, offset, arg);
836 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
837 break;
838 default:
839 ret = -EINVAL;
840 }
841
842 return ret;
843 }
844
845 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
846 unsigned group,
847 unsigned long *config)
848 {
849 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
850
851 *config = pctl->groups[group].config;
852
853 return 0;
854 }
855
856 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
857 unsigned long *configs, unsigned num_configs)
858 {
859 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
860 struct stm32_pinctrl_group *g = &pctl->groups[group];
861 int i, ret;
862
863 for (i = 0; i < num_configs; i++) {
864 ret = stm32_pconf_parse_conf(pctldev, g->pin,
865 pinconf_to_config_param(configs[i]),
866 pinconf_to_config_argument(configs[i]));
867 if (ret < 0)
868 return ret;
869
870 g->config = configs[i];
871 }
872
873 return 0;
874 }
875
876 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
877 struct seq_file *s,
878 unsigned int pin)
879 {
880 struct pinctrl_gpio_range *range;
881 struct stm32_gpio_bank *bank;
882 int offset;
883 u32 mode, alt, drive, speed, bias;
884 static const char * const modes[] = {
885 "input", "output", "alternate", "analog" };
886 static const char * const speeds[] = {
887 "low", "medium", "high", "very high" };
888 static const char * const biasing[] = {
889 "floating", "pull up", "pull down", "" };
890 bool val;
891
892 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
893 bank = gpiochip_get_data(range->gc);
894 offset = stm32_gpio_pin(pin);
895
896 stm32_pmx_get_mode(bank, offset, &mode, &alt);
897 bias = stm32_pconf_get_bias(bank, offset);
898
899 seq_printf(s, "%s ", modes[mode]);
900
901 switch (mode) {
902 /* input */
903 case 0:
904 val = stm32_pconf_get(bank, offset, true);
905 seq_printf(s, "- %s - %s",
906 val ? "high" : "low",
907 biasing[bias]);
908 break;
909
910 /* output */
911 case 1:
912 drive = stm32_pconf_get_driving(bank, offset);
913 speed = stm32_pconf_get_speed(bank, offset);
914 val = stm32_pconf_get(bank, offset, false);
915 seq_printf(s, "- %s - %s - %s - %s %s",
916 val ? "high" : "low",
917 drive ? "open drain" : "push pull",
918 biasing[bias],
919 speeds[speed], "speed");
920 break;
921
922 /* alternate */
923 case 2:
924 drive = stm32_pconf_get_driving(bank, offset);
925 speed = stm32_pconf_get_speed(bank, offset);
926 seq_printf(s, "%d - %s - %s - %s %s", alt,
927 drive ? "open drain" : "push pull",
928 biasing[bias],
929 speeds[speed], "speed");
930 break;
931
932 /* analog */
933 case 3:
934 break;
935 }
936 }
937
938
939 static const struct pinconf_ops stm32_pconf_ops = {
940 .pin_config_group_get = stm32_pconf_group_get,
941 .pin_config_group_set = stm32_pconf_group_set,
942 .pin_config_dbg_show = stm32_pconf_dbg_show,
943 };
944
945 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
946 struct device_node *np)
947 {
948 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
949 struct pinctrl_gpio_range *range = &bank->range;
950 struct of_phandle_args args;
951 struct device *dev = pctl->dev;
952 struct resource res;
953 struct reset_control *rstc;
954 int npins = STM32_GPIO_PINS_PER_BANK;
955 int bank_nr, err;
956
957 rstc = of_reset_control_get_exclusive(np, NULL);
958 if (!IS_ERR(rstc))
959 reset_control_deassert(rstc);
960
961 if (of_address_to_resource(np, 0, &res))
962 return -ENODEV;
963
964 bank->base = devm_ioremap_resource(dev, &res);
965 if (IS_ERR(bank->base))
966 return PTR_ERR(bank->base);
967
968 bank->clk = of_clk_get_by_name(np, NULL);
969 if (IS_ERR(bank->clk)) {
970 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
971 return PTR_ERR(bank->clk);
972 }
973
974 err = clk_prepare(bank->clk);
975 if (err) {
976 dev_err(dev, "failed to prepare clk (%d)\n", err);
977 return err;
978 }
979
980 bank->gpio_chip = stm32_gpio_template;
981
982 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
983
984 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) {
985 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
986 bank->gpio_chip.base = args.args[1];
987 } else {
988 bank_nr = pctl->nbanks;
989 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
990 range->name = bank->gpio_chip.label;
991 range->id = bank_nr;
992 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
993 range->base = range->id * STM32_GPIO_PINS_PER_BANK;
994 range->npins = npins;
995 range->gc = &bank->gpio_chip;
996 pinctrl_add_gpio_range(pctl->pctl_dev,
997 &pctl->banks[bank_nr].range);
998 }
999 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1000
1001 bank->gpio_chip.ngpio = npins;
1002 bank->gpio_chip.of_node = np;
1003 bank->gpio_chip.parent = dev;
1004 bank->bank_nr = bank_nr;
1005 spin_lock_init(&bank->lock);
1006
1007 /* create irq hierarchical domain */
1008 bank->fwnode = of_node_to_fwnode(np);
1009
1010 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
1011 STM32_GPIO_IRQ_LINE, bank->fwnode,
1012 &stm32_gpio_domain_ops, bank);
1013
1014 if (!bank->domain)
1015 return -ENODEV;
1016
1017 err = gpiochip_add_data(&bank->gpio_chip, bank);
1018 if (err) {
1019 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1020 return err;
1021 }
1022
1023 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1024 return 0;
1025 }
1026
1027 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1028 struct stm32_pinctrl *pctl)
1029 {
1030 struct device_node *np = pdev->dev.of_node, *parent;
1031 struct device *dev = &pdev->dev;
1032 struct regmap *rm;
1033 int offset, ret, i;
1034
1035 parent = of_irq_find_parent(np);
1036 if (!parent)
1037 return -ENXIO;
1038
1039 pctl->domain = irq_find_host(parent);
1040 if (!pctl->domain)
1041 return -ENXIO;
1042
1043 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1044 if (IS_ERR(pctl->regmap))
1045 return PTR_ERR(pctl->regmap);
1046
1047 rm = pctl->regmap;
1048
1049 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1050 if (ret)
1051 return ret;
1052
1053 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1054 struct reg_field mux;
1055
1056 mux.reg = offset + (i / 4) * 4;
1057 mux.lsb = (i % 4) * 4;
1058 mux.msb = mux.lsb + 3;
1059
1060 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1061 if (IS_ERR(pctl->irqmux[i]))
1062 return PTR_ERR(pctl->irqmux[i]);
1063 }
1064
1065 return 0;
1066 }
1067
1068 static int stm32_pctrl_build_state(struct platform_device *pdev)
1069 {
1070 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1071 int i;
1072
1073 pctl->ngroups = pctl->match_data->npins;
1074
1075 /* Allocate groups */
1076 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1077 sizeof(*pctl->groups), GFP_KERNEL);
1078 if (!pctl->groups)
1079 return -ENOMEM;
1080
1081 /* We assume that one pin is one group, use pin name as group name. */
1082 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1083 sizeof(*pctl->grp_names), GFP_KERNEL);
1084 if (!pctl->grp_names)
1085 return -ENOMEM;
1086
1087 for (i = 0; i < pctl->match_data->npins; i++) {
1088 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
1089 struct stm32_pinctrl_group *group = pctl->groups + i;
1090
1091 group->name = pin->pin.name;
1092 group->pin = pin->pin.number;
1093
1094 pctl->grp_names[i] = pin->pin.name;
1095 }
1096
1097 return 0;
1098 }
1099
1100 int stm32_pctl_probe(struct platform_device *pdev)
1101 {
1102 struct device_node *np = pdev->dev.of_node;
1103 struct device_node *child;
1104 const struct of_device_id *match;
1105 struct device *dev = &pdev->dev;
1106 struct stm32_pinctrl *pctl;
1107 struct pinctrl_pin_desc *pins;
1108 int i, ret, banks = 0;
1109
1110 if (!np)
1111 return -EINVAL;
1112
1113 match = of_match_device(dev->driver->of_match_table, dev);
1114 if (!match || !match->data)
1115 return -EINVAL;
1116
1117 if (!of_find_property(np, "pins-are-numbered", NULL)) {
1118 dev_err(dev, "only support pins-are-numbered format\n");
1119 return -EINVAL;
1120 }
1121
1122 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1123 if (!pctl)
1124 return -ENOMEM;
1125
1126 platform_set_drvdata(pdev, pctl);
1127
1128 pctl->dev = dev;
1129 pctl->match_data = match->data;
1130 ret = stm32_pctrl_build_state(pdev);
1131 if (ret) {
1132 dev_err(dev, "build state failed: %d\n", ret);
1133 return -EINVAL;
1134 }
1135
1136 if (of_find_property(np, "interrupt-parent", NULL)) {
1137 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1138 if (ret)
1139 return ret;
1140 }
1141
1142 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins),
1143 GFP_KERNEL);
1144 if (!pins)
1145 return -ENOMEM;
1146
1147 for (i = 0; i < pctl->match_data->npins; i++)
1148 pins[i] = pctl->match_data->pins[i].pin;
1149
1150 pctl->pctl_desc.name = dev_name(&pdev->dev);
1151 pctl->pctl_desc.owner = THIS_MODULE;
1152 pctl->pctl_desc.pins = pins;
1153 pctl->pctl_desc.npins = pctl->match_data->npins;
1154 pctl->pctl_desc.confops = &stm32_pconf_ops;
1155 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1156 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1157 pctl->dev = &pdev->dev;
1158
1159 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1160 pctl);
1161
1162 if (IS_ERR(pctl->pctl_dev)) {
1163 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1164 return PTR_ERR(pctl->pctl_dev);
1165 }
1166
1167 for_each_child_of_node(np, child)
1168 if (of_property_read_bool(child, "gpio-controller"))
1169 banks++;
1170
1171 if (!banks) {
1172 dev_err(dev, "at least one GPIO bank is required\n");
1173 return -EINVAL;
1174 }
1175 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1176 GFP_KERNEL);
1177 if (!pctl->banks)
1178 return -ENOMEM;
1179
1180 for_each_child_of_node(np, child) {
1181 if (of_property_read_bool(child, "gpio-controller")) {
1182 ret = stm32_gpiolib_register_bank(pctl, child);
1183 if (ret)
1184 return ret;
1185
1186 pctl->nbanks++;
1187 }
1188 }
1189
1190 dev_info(dev, "Pinctrl STM32 initialized\n");
1191
1192 return 0;
1193 }
1194
Linux with added FPC-III support