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Linux 4.16.11
[linux/fpc-iii.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
blob4ccb61e2ae5ccdbd778aec6c42afb1bd50a5e991
1 /*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12 #include "hisi_sas.h"
13 #define DRV_NAME "hisi_sas_v2_hw"
14
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
34 #define ITCT_CLR 0x44
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
149 #define DLVRY_Q_0_DEPTH 0x268
150 #define DLVRY_Q_0_WR_PTR 0x26c
151 #define DLVRY_Q_0_RD_PTR 0x270
152 #define HYPER_STREAM_ID_EN_CFG 0xc80
153 #define OQ0_INT_SRC_MSK 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
156 #define COMPL_Q_0_DEPTH 0x4e8
157 #define COMPL_Q_0_WR_PTR 0x4ec
158 #define COMPL_Q_0_RD_PTR 0x4f0
159 #define HGC_RXM_DFX_STATUS14 0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
162 HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15 0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
172 HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE (0x2000)
175
176 #define PHY_CFG (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF 0
179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF 2
181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF 0
184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF 0
187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
189 #define SL_CFG (PORT_BASE + 0x84)
190 #define PHY_PCN (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
192 #define SL_CONTROL (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF 0
194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF 17
196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF 1
199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
207 #define TXID_AUTO (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF 1
209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
210 #define TXID_AUTO_CTB_OFF 11
211 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
212 #define TX_HARDRST_OFF 2
213 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
214 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
215 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
216 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
217 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
218 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
219 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
220 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
221 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
222 #define CON_CONTROL (PORT_BASE + 0x118)
223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
225 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
226 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
227 #define CHL_INT0 (PORT_BASE + 0x1b4)
228 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
229 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
230 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
231 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
232 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
233 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
234 #define CHL_INT0_NOT_RDY_OFF 4
235 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
236 #define CHL_INT0_PHY_RDY_OFF 5
237 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
238 #define CHL_INT1 (PORT_BASE + 0x1b8)
239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
243 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
244 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
245 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
246 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
247 #define CHL_INT2 (PORT_BASE + 0x1bc)
248 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
249 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
250 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
251 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
252 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
253 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
254 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
255 #define DMA_TX_DFX1_IPTT_OFF 0
256 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
257 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
258 #define PORT_DFX0 (PORT_BASE + 0x258)
259 #define LINK_DFX2 (PORT_BASE + 0X264)
260 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
261 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
262 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
263 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
264 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
265 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
266 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
267 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
268 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
269 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
270 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
271 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
272 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
273 #define DMA_TX_STATUS_BUSY_OFF 0
274 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
275 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
276 #define DMA_RX_STATUS_BUSY_OFF 0
277 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
278
279 #define AXI_CFG (0x5100)
280 #define AM_CFG_MAX_TRANS (0x5010)
281 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
282
283 #define AXI_MASTER_CFG_BASE (0x5000)
284 #define AM_CTRL_GLOBAL (0x0)
285 #define AM_CURR_TRANS_RETURN (0x150)
286
287 /* HW dma structures */
288 /* Delivery queue header */
289 /* dw0 */
290 #define CMD_HDR_ABORT_FLAG_OFF 0
291 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
292 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
293 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
294 #define CMD_HDR_RESP_REPORT_OFF 5
295 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
296 #define CMD_HDR_TLR_CTRL_OFF 6
297 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
298 #define CMD_HDR_PORT_OFF 18
299 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
300 #define CMD_HDR_PRIORITY_OFF 27
301 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
302 #define CMD_HDR_CMD_OFF 29
303 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
304 /* dw1 */
305 #define CMD_HDR_DIR_OFF 5
306 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
307 #define CMD_HDR_RESET_OFF 7
308 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
309 #define CMD_HDR_VDTL_OFF 10
310 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
311 #define CMD_HDR_FRAME_TYPE_OFF 11
312 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
313 #define CMD_HDR_DEV_ID_OFF 16
314 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
315 /* dw2 */
316 #define CMD_HDR_CFL_OFF 0
317 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
318 #define CMD_HDR_NCQ_TAG_OFF 10
319 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
320 #define CMD_HDR_MRFL_OFF 15
321 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
322 #define CMD_HDR_SG_MOD_OFF 24
323 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
324 #define CMD_HDR_FIRST_BURST_OFF 26
325 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
326 /* dw3 */
327 #define CMD_HDR_IPTT_OFF 0
328 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
329 /* dw6 */
330 #define CMD_HDR_DIF_SGL_LEN_OFF 0
331 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
332 #define CMD_HDR_DATA_SGL_LEN_OFF 16
333 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
334 #define CMD_HDR_ABORT_IPTT_OFF 16
335 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
336
337 /* Completion header */
338 /* dw0 */
339 #define CMPLT_HDR_ERR_PHASE_OFF 2
340 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
341 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
342 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
343 #define CMPLT_HDR_ERX_OFF 12
344 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
345 #define CMPLT_HDR_ABORT_STAT_OFF 13
346 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
347 /* abort_stat */
348 #define STAT_IO_NOT_VALID 0x1
349 #define STAT_IO_NO_DEVICE 0x2
350 #define STAT_IO_COMPLETE 0x3
351 #define STAT_IO_ABORTED 0x4
352 /* dw1 */
353 #define CMPLT_HDR_IPTT_OFF 0
354 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
355 #define CMPLT_HDR_DEV_ID_OFF 16
356 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
357
358 /* ITCT header */
359 /* qw0 */
360 #define ITCT_HDR_DEV_TYPE_OFF 0
361 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
362 #define ITCT_HDR_VALID_OFF 2
363 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
364 #define ITCT_HDR_MCR_OFF 5
365 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
366 #define ITCT_HDR_VLN_OFF 9
367 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
368 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
369 #define ITCT_HDR_SMP_TIMEOUT_8US 1
370 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
371 250) /* 2ms */
372 #define ITCT_HDR_AWT_CONTINUE_OFF 25
373 #define ITCT_HDR_PORT_ID_OFF 28
374 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
375 /* qw2 */
376 #define ITCT_HDR_INLT_OFF 0
377 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
378 #define ITCT_HDR_BITLT_OFF 16
379 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
380 #define ITCT_HDR_MCTLT_OFF 32
381 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
382 #define ITCT_HDR_RTOLT_OFF 48
383 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
384
385 #define HISI_SAS_FATAL_INT_NR 2
386
387 struct hisi_sas_complete_v2_hdr {
388 __le32 dw0;
389 __le32 dw1;
390 __le32 act;
391 __le32 dw3;
392 };
393
394 struct hisi_sas_err_record_v2 {
395 /* dw0 */
396 __le32 trans_tx_fail_type;
397
398 /* dw1 */
399 __le32 trans_rx_fail_type;
400
401 /* dw2 */
402 __le16 dma_tx_err_type;
403 __le16 sipc_rx_err_type;
404
405 /* dw3 */
406 __le32 dma_rx_err_type;
407 };
408
409 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
410 {
411 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
412 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
413 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
414 .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
415 .reg = HGC_DQE_ECC_ADDR,
416 },
417 {
418 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
419 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
420 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
421 .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
422 .reg = HGC_IOST_ECC_ADDR,
423 },
424 {
425 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
426 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
427 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
428 .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
429 .reg = HGC_ITCT_ECC_ADDR,
430 },
431 {
432 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
433 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
434 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
435 .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
436 .reg = HGC_LM_DFX_STATUS2,
437 },
438 {
439 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
440 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
441 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
442 .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
443 .reg = HGC_LM_DFX_STATUS2,
444 },
445 {
446 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
447 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
448 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
449 .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
450 .reg = HGC_CQE_ECC_ADDR,
451 },
452 {
453 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
454 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
455 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
456 .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
457 .reg = HGC_RXM_DFX_STATUS14,
458 },
459 {
460 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
461 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
462 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
463 .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
464 .reg = HGC_RXM_DFX_STATUS14,
465 },
466 {
467 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
468 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
469 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
470 .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
471 .reg = HGC_RXM_DFX_STATUS14,
472 },
473 {
474 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
475 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
476 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
477 .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
478 .reg = HGC_RXM_DFX_STATUS15,
479 },
480 };
481
482 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
483 {
484 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
485 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
486 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
487 .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
488 .reg = HGC_DQE_ECC_ADDR,
489 },
490 {
491 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
492 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
493 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
494 .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
495 .reg = HGC_IOST_ECC_ADDR,
496 },
497 {
498 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
499 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
500 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
501 .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
502 .reg = HGC_ITCT_ECC_ADDR,
503 },
504 {
505 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
506 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
507 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
508 .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
509 .reg = HGC_LM_DFX_STATUS2,
510 },
511 {
512 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
513 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
514 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
515 .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
516 .reg = HGC_LM_DFX_STATUS2,
517 },
518 {
519 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
520 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
521 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
522 .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
523 .reg = HGC_CQE_ECC_ADDR,
524 },
525 {
526 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
527 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
528 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
529 .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
530 .reg = HGC_RXM_DFX_STATUS14,
531 },
532 {
533 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
534 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
535 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
536 .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
537 .reg = HGC_RXM_DFX_STATUS14,
538 },
539 {
540 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
541 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
542 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
543 .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
544 .reg = HGC_RXM_DFX_STATUS14,
545 },
546 {
547 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
548 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
549 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
550 .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
551 .reg = HGC_RXM_DFX_STATUS15,
552 },
553 };
554
555 enum {
556 HISI_SAS_PHY_PHY_UPDOWN,
557 HISI_SAS_PHY_CHNL_INT,
558 HISI_SAS_PHY_INT_NR
559 };
560
561 enum {
562 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
563 TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
564 DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
565 SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
566 DMA_RX_ERR_BASE = 0x60, /* dw3 */
567
568 /* trans tx*/
569 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
570 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
571 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
572 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
573 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
574 RESERVED0, /* 0x5 */
575 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
576 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
577 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
578 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
579 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
580 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
581 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
582 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
583 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
584 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
585 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
586 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
587 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
588 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
589 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
590 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
591 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
592 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
593 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
594 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
595 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
596 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
597 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
598 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
599 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
600 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
601 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
602 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
603 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
604
605 /* trans rx */
606 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
607 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
608 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
609 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
610 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
611 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
612 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
613 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
614 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
615 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
616 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
617 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
618 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
619 RESERVED1, /* 0x2b */
620 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
621 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
622 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
623 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
624 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
625 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
626 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
627 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
628 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
629 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
630 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
631 RESERVED2, /* 0x34 */
632 RESERVED3, /* 0x35 */
633 RESERVED4, /* 0x36 */
634 RESERVED5, /* 0x37 */
635 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
636 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
637 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
638 RESERVED6, /* 0x3b */
639 RESERVED7, /* 0x3c */
640 RESERVED8, /* 0x3d */
641 RESERVED9, /* 0x3e */
642 TRANS_RX_R_ERR, /* 0x3f */
643
644 /* dma tx */
645 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
646 DMA_TX_DIF_APP_ERR, /* 0x41 */
647 DMA_TX_DIF_RPP_ERR, /* 0x42 */
648 DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
649 DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
650 DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
651 DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
652 DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
653 DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
654 DMA_TX_RAM_ECC_ERR, /* 0x49 */
655 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
656 DMA_TX_MAX_ERR_CODE,
657
658 /* sipc rx */
659 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
660 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
661 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
662 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
663 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
664 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
665 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
666 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
667 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
668 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
669 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
670 SIPC_RX_MAX_ERR_CODE,
671
672 /* dma rx */
673 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
674 DMA_RX_DIF_APP_ERR, /* 0x61 */
675 DMA_RX_DIF_RPP_ERR, /* 0x62 */
676 DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
677 DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
678 DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
679 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
680 DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
681 RESERVED10, /* 0x68 */
682 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
683 DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
684 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
685 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
686 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
687 DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
688 DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
689 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
690 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
691 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
692 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
693 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
694 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
695 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
696 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
697 DMA_RX_RAM_ECC_ERR, /* 0x78 */
698 DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
699 DMA_RX_MAX_ERR_CODE,
700 };
701
702 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
703 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
704
705 #define DIR_NO_DATA 0
706 #define DIR_TO_INI 1
707 #define DIR_TO_DEVICE 2
708 #define DIR_RESERVED 3
709
710 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
711 err_phase == 0x4 || err_phase == 0x8 ||\
712 err_phase == 0x6 || err_phase == 0xa)
713 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
714 err_phase == 0x20 || err_phase == 0x40)
715
716 static void link_timeout_disable_link(struct timer_list *t);
717
718 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
719 {
720 void __iomem *regs = hisi_hba->regs + off;
721
722 return readl(regs);
723 }
724
725 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
726 {
727 void __iomem *regs = hisi_hba->regs + off;
728
729 return readl_relaxed(regs);
730 }
731
732 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
733 {
734 void __iomem *regs = hisi_hba->regs + off;
735
736 writel(val, regs);
737 }
738
739 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
740 u32 off, u32 val)
741 {
742 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
743
744 writel(val, regs);
745 }
746
747 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
748 int phy_no, u32 off)
749 {
750 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
751
752 return readl(regs);
753 }
754
755 /* This function needs to be protected from pre-emption. */
756 static int
757 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
758 struct domain_device *device)
759 {
760 int sata_dev = dev_is_sata(device);
761 void *bitmap = hisi_hba->slot_index_tags;
762 struct hisi_sas_device *sas_dev = device->lldd_dev;
763 int sata_idx = sas_dev->sata_idx;
764 int start, end;
765
766 if (!sata_dev) {
767 /*
768 * STP link SoC bug workaround: index starts from 1.
769 * additionally, we can only allocate odd IPTT(1~4095)
770 * for SAS/SMP device.
771 */
772 start = 1;
773 end = hisi_hba->slot_index_count;
774 } else {
775 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
776 return -EINVAL;
777
778 /*
779 * For SATA device: allocate even IPTT in this interval
780 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
781 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
782 * SoC bug workaround. So we ignore the first 32 even IPTTs.
783 */
784 start = 64 * (sata_idx + 1);
785 end = 64 * (sata_idx + 2);
786 }
787
788 while (1) {
789 start = find_next_zero_bit(bitmap,
790 hisi_hba->slot_index_count, start);
791 if (start >= end)
792 return -SAS_QUEUE_FULL;
793 /*
794 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
795 */
796 if (sata_dev ^ (start & 1))
797 break;
798 start++;
799 }
800
801 set_bit(start, bitmap);
802 *slot_idx = start;
803 return 0;
804 }
805
806 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
807 {
808 unsigned int index;
809 struct device *dev = hisi_hba->dev;
810 void *bitmap = hisi_hba->sata_dev_bitmap;
811
812 index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
813 if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
814 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
815 return false;
816 }
817
818 set_bit(index, bitmap);
819 *idx = index;
820 return true;
821 }
822
823
824 static struct
825 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
826 {
827 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
828 struct hisi_sas_device *sas_dev = NULL;
829 int i, sata_dev = dev_is_sata(device);
830 int sata_idx = -1;
831 unsigned long flags;
832
833 spin_lock_irqsave(&hisi_hba->lock, flags);
834
835 if (sata_dev)
836 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
837 goto out;
838
839 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
840 /*
841 * SATA device id bit0 should be 0
842 */
843 if (sata_dev && (i & 1))
844 continue;
845 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
846 int queue = i % hisi_hba->queue_count;
847 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
848
849 hisi_hba->devices[i].device_id = i;
850 sas_dev = &hisi_hba->devices[i];
851 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
852 sas_dev->dev_type = device->dev_type;
853 sas_dev->hisi_hba = hisi_hba;
854 sas_dev->sas_device = device;
855 sas_dev->sata_idx = sata_idx;
856 sas_dev->dq = dq;
857 INIT_LIST_HEAD(&hisi_hba->devices[i].list);
858 break;
859 }
860 }
861
862 out:
863 spin_unlock_irqrestore(&hisi_hba->lock, flags);
864
865 return sas_dev;
866 }
867
868 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
869 {
870 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
871
872 cfg &= ~PHY_CFG_DC_OPT_MSK;
873 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
874 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
875 }
876
877 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
878 {
879 struct sas_identify_frame identify_frame;
880 u32 *identify_buffer;
881
882 memset(&identify_frame, 0, sizeof(identify_frame));
883 identify_frame.dev_type = SAS_END_DEVICE;
884 identify_frame.frame_type = 0;
885 identify_frame._un1 = 1;
886 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
887 identify_frame.target_bits = SAS_PROTOCOL_NONE;
888 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
889 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
890 identify_frame.phy_id = phy_no;
891 identify_buffer = (u32 *)(&identify_frame);
892
893 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
894 __swab32(identify_buffer[0]));
895 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
896 __swab32(identify_buffer[1]));
897 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
898 __swab32(identify_buffer[2]));
899 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
900 __swab32(identify_buffer[3]));
901 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
902 __swab32(identify_buffer[4]));
903 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
904 __swab32(identify_buffer[5]));
905 }
906
907 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
908 struct hisi_sas_device *sas_dev)
909 {
910 struct domain_device *device = sas_dev->sas_device;
911 struct device *dev = hisi_hba->dev;
912 u64 qw0, device_id = sas_dev->device_id;
913 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
914 struct domain_device *parent_dev = device->parent;
915 struct asd_sas_port *sas_port = device->port;
916 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
917
918 memset(itct, 0, sizeof(*itct));
919
920 /* qw0 */
921 qw0 = 0;
922 switch (sas_dev->dev_type) {
923 case SAS_END_DEVICE:
924 case SAS_EDGE_EXPANDER_DEVICE:
925 case SAS_FANOUT_EXPANDER_DEVICE:
926 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
927 break;
928 case SAS_SATA_DEV:
929 case SAS_SATA_PENDING:
930 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
931 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
932 else
933 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
934 break;
935 default:
936 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
937 sas_dev->dev_type);
938 }
939
940 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
941 (device->linkrate << ITCT_HDR_MCR_OFF) |
942 (1 << ITCT_HDR_VLN_OFF) |
943 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
944 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
945 (port->id << ITCT_HDR_PORT_ID_OFF));
946 itct->qw0 = cpu_to_le64(qw0);
947
948 /* qw1 */
949 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
950 itct->sas_addr = __swab64(itct->sas_addr);
951
952 /* qw2 */
953 if (!dev_is_sata(device))
954 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
955 (0x1ULL << ITCT_HDR_BITLT_OFF) |
956 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
957 (0x1ULL << ITCT_HDR_RTOLT_OFF));
958 }
959
960 static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
961 struct hisi_sas_device *sas_dev)
962 {
963 DECLARE_COMPLETION_ONSTACK(completion);
964 u64 dev_id = sas_dev->device_id;
965 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
966 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
967 int i;
968
969 sas_dev->completion = &completion;
970
971 /* clear the itct interrupt state */
972 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
973 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
974 ENT_INT_SRC3_ITC_INT_MSK);
975
976 for (i = 0; i < 2; i++) {
977 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
978 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
979 wait_for_completion(sas_dev->completion);
980
981 memset(itct, 0, sizeof(struct hisi_sas_itct));
982 }
983 }
984
985 static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
986 {
987 struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
988
989 /* SoC bug workaround */
990 if (dev_is_sata(sas_dev->sas_device))
991 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
992 }
993
994 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
995 {
996 int i, reset_val;
997 u32 val;
998 unsigned long end_time;
999 struct device *dev = hisi_hba->dev;
1000
1001 /* The mask needs to be set depending on the number of phys */
1002 if (hisi_hba->n_phy == 9)
1003 reset_val = 0x1fffff;
1004 else
1005 reset_val = 0x7ffff;
1006
1007 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1008
1009 /* Disable all of the PHYs */
1010 for (i = 0; i < hisi_hba->n_phy; i++) {
1011 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1012
1013 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1014 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1015 }
1016 udelay(50);
1017
1018 /* Ensure DMA tx & rx idle */
1019 for (i = 0; i < hisi_hba->n_phy; i++) {
1020 u32 dma_tx_status, dma_rx_status;
1021
1022 end_time = jiffies + msecs_to_jiffies(1000);
1023
1024 while (1) {
1025 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1026 DMA_TX_STATUS);
1027 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1028 DMA_RX_STATUS);
1029
1030 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1031 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1032 break;
1033
1034 msleep(20);
1035 if (time_after(jiffies, end_time))
1036 return -EIO;
1037 }
1038 }
1039
1040 /* Ensure axi bus idle */
1041 end_time = jiffies + msecs_to_jiffies(1000);
1042 while (1) {
1043 u32 axi_status =
1044 hisi_sas_read32(hisi_hba, AXI_CFG);
1045
1046 if (axi_status == 0)
1047 break;
1048
1049 msleep(20);
1050 if (time_after(jiffies, end_time))
1051 return -EIO;
1052 }
1053
1054 if (ACPI_HANDLE(dev)) {
1055 acpi_status s;
1056
1057 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1058 if (ACPI_FAILURE(s)) {
1059 dev_err(dev, "Reset failed\n");
1060 return -EIO;
1061 }
1062 } else if (hisi_hba->ctrl) {
1063 /* reset and disable clock*/
1064 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1065 reset_val);
1066 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1067 reset_val);
1068 msleep(1);
1069 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1070 if (reset_val != (val & reset_val)) {
1071 dev_err(dev, "SAS reset fail.\n");
1072 return -EIO;
1073 }
1074
1075 /* De-reset and enable clock*/
1076 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1077 reset_val);
1078 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1079 reset_val);
1080 msleep(1);
1081 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1082 &val);
1083 if (val & reset_val) {
1084 dev_err(dev, "SAS de-reset fail.\n");
1085 return -EIO;
1086 }
1087 } else
1088 dev_warn(dev, "no reset method\n");
1089
1090 return 0;
1091 }
1092
1093 /* This function needs to be called after resetting SAS controller. */
1094 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1095 {
1096 u32 cfg;
1097 int phy_no;
1098
1099 hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1100 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1101 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1102 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1103 continue;
1104
1105 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1106 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1107 }
1108 }
1109
1110 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1111 {
1112 int phy_no;
1113 u32 dma_tx_dfx1;
1114
1115 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1116 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1117 continue;
1118
1119 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1120 DMA_TX_DFX1);
1121 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1122 u32 cfg = hisi_sas_phy_read32(hisi_hba,
1123 phy_no, CON_CONTROL);
1124
1125 cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1126 hisi_sas_phy_write32(hisi_hba, phy_no,
1127 CON_CONTROL, cfg);
1128 clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1129 }
1130 }
1131 }
1132
1133 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1134 {
1135 struct device *dev = hisi_hba->dev;
1136 int i;
1137
1138 /* Global registers init */
1139
1140 /* Deal with am-max-transmissions quirk */
1141 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1142 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1143 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1144 0x2020);
1145 } /* Else, use defaults -> do nothing */
1146
1147 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1148 (u32)((1ULL << hisi_hba->queue_count) - 1));
1149 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1150 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1151 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1152 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1153 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1154 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1155 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1156 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1157 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1158 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1159 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1160 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1161 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1162 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1163 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1164 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1165 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1166 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1167 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1168 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1169 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1170 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1171 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1172 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1173 for (i = 0; i < hisi_hba->queue_count; i++)
1174 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1175
1176 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1177 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1178
1179 for (i = 0; i < hisi_hba->n_phy; i++) {
1180 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
1181 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
1182 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1183 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1184 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1185 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1186 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1187 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1188 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1189 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1190 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
1191 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe);
1192 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1193 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1194 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1195 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1196 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1197 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1198 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1199 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1200 if (hisi_hba->refclk_frequency_mhz == 66)
1201 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1202 /* else, do nothing -> leave it how you found it */
1203 }
1204
1205 for (i = 0; i < hisi_hba->queue_count; i++) {
1206 /* Delivery queue */
1207 hisi_sas_write32(hisi_hba,
1208 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1209 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1210
1211 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1212 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1213
1214 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1215 HISI_SAS_QUEUE_SLOTS);
1216
1217 /* Completion queue */
1218 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1219 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1220
1221 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1222 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1223
1224 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1225 HISI_SAS_QUEUE_SLOTS);
1226 }
1227
1228 /* itct */
1229 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1230 lower_32_bits(hisi_hba->itct_dma));
1231
1232 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1233 upper_32_bits(hisi_hba->itct_dma));
1234
1235 /* iost */
1236 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1237 lower_32_bits(hisi_hba->iost_dma));
1238
1239 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1240 upper_32_bits(hisi_hba->iost_dma));
1241
1242 /* breakpoint */
1243 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1244 lower_32_bits(hisi_hba->breakpoint_dma));
1245
1246 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1247 upper_32_bits(hisi_hba->breakpoint_dma));
1248
1249 /* SATA broken msg */
1250 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1251 lower_32_bits(hisi_hba->sata_breakpoint_dma));
1252
1253 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1254 upper_32_bits(hisi_hba->sata_breakpoint_dma));
1255
1256 /* SATA initial fis */
1257 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1258 lower_32_bits(hisi_hba->initial_fis_dma));
1259
1260 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1261 upper_32_bits(hisi_hba->initial_fis_dma));
1262 }
1263
1264 static void link_timeout_enable_link(struct timer_list *t)
1265 {
1266 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1267 int i, reg_val;
1268
1269 for (i = 0; i < hisi_hba->n_phy; i++) {
1270 if (hisi_hba->reject_stp_links_msk & BIT(i))
1271 continue;
1272
1273 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1274 if (!(reg_val & BIT(0))) {
1275 hisi_sas_phy_write32(hisi_hba, i,
1276 CON_CONTROL, 0x7);
1277 break;
1278 }
1279 }
1280
1281 hisi_hba->timer.function = link_timeout_disable_link;
1282 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1283 }
1284
1285 static void link_timeout_disable_link(struct timer_list *t)
1286 {
1287 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1288 int i, reg_val;
1289
1290 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1291 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1292 if (hisi_hba->reject_stp_links_msk & BIT(i))
1293 continue;
1294
1295 if (reg_val & BIT(i)) {
1296 hisi_sas_phy_write32(hisi_hba, i,
1297 CON_CONTROL, 0x6);
1298 break;
1299 }
1300 }
1301
1302 hisi_hba->timer.function = link_timeout_enable_link;
1303 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1304 }
1305
1306 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1307 {
1308 hisi_hba->timer.function = link_timeout_disable_link;
1309 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1310 add_timer(&hisi_hba->timer);
1311 }
1312
1313 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1314 {
1315 struct device *dev = hisi_hba->dev;
1316 int rc;
1317
1318 rc = reset_hw_v2_hw(hisi_hba);
1319 if (rc) {
1320 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1321 return rc;
1322 }
1323
1324 msleep(100);
1325 init_reg_v2_hw(hisi_hba);
1326
1327 return 0;
1328 }
1329
1330 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1331 {
1332 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1333
1334 cfg |= PHY_CFG_ENA_MSK;
1335 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1336 }
1337
1338 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1339 {
1340 u32 context;
1341
1342 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1343 if (context & (1 << phy_no))
1344 return true;
1345
1346 return false;
1347 }
1348
1349 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1350 {
1351 u32 dfx_val;
1352
1353 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1354
1355 if (dfx_val & BIT(16))
1356 return false;
1357
1358 return true;
1359 }
1360
1361 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1362 {
1363 int i, max_loop = 1000;
1364 struct device *dev = hisi_hba->dev;
1365 u32 status, axi_status, dfx_val, dfx_tx_val;
1366
1367 for (i = 0; i < max_loop; i++) {
1368 status = hisi_sas_read32_relaxed(hisi_hba,
1369 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1370
1371 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1372 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1373 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1374 phy_no, DMA_TX_FIFO_DFX0);
1375
1376 if ((status == 0x3) && (axi_status == 0x0) &&
1377 (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1378 return true;
1379 udelay(10);
1380 }
1381 dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1382 phy_no, status, axi_status,
1383 dfx_val, dfx_tx_val);
1384 return false;
1385 }
1386
1387 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1388 {
1389 int i, max_loop = 1000;
1390 struct device *dev = hisi_hba->dev;
1391 u32 status, tx_dfx0;
1392
1393 for (i = 0; i < max_loop; i++) {
1394 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1395 status = (status & 0x3fc0) >> 6;
1396
1397 if (status != 0x1)
1398 return true;
1399
1400 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1401 if ((tx_dfx0 & 0x1ff) == 0x2)
1402 return true;
1403 udelay(10);
1404 }
1405 dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1406 phy_no, status, tx_dfx0);
1407 return false;
1408 }
1409
1410 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1411 {
1412 if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1413 return true;
1414
1415 if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1416 return false;
1417
1418 if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1419 return false;
1420
1421 return true;
1422 }
1423
1424
1425 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1426 {
1427 u32 cfg, axi_val, dfx0_val, txid_auto;
1428 struct device *dev = hisi_hba->dev;
1429
1430 /* Close axi bus. */
1431 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1432 AM_CTRL_GLOBAL);
1433 axi_val |= 0x1;
1434 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1435 AM_CTRL_GLOBAL, axi_val);
1436
1437 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1438 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1439 goto do_disable;
1440
1441 /* Reset host controller. */
1442 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1443 return;
1444 }
1445
1446 dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1447 dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1448 if (dfx0_val != 0x4)
1449 goto do_disable;
1450
1451 if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1452 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1453 phy_no);
1454 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1455 TXID_AUTO);
1456 txid_auto |= TXID_AUTO_CTB_MSK;
1457 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1458 txid_auto);
1459 }
1460
1461 do_disable:
1462 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1463 cfg &= ~PHY_CFG_ENA_MSK;
1464 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1465
1466 /* Open axi bus. */
1467 axi_val &= ~0x1;
1468 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1469 AM_CTRL_GLOBAL, axi_val);
1470 }
1471
1472 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1473 {
1474 config_id_frame_v2_hw(hisi_hba, phy_no);
1475 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1476 enable_phy_v2_hw(hisi_hba, phy_no);
1477 }
1478
1479 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1480 {
1481 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1482 u32 txid_auto;
1483
1484 disable_phy_v2_hw(hisi_hba, phy_no);
1485 if (phy->identify.device_type == SAS_END_DEVICE) {
1486 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1487 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1488 txid_auto | TX_HARDRST_MSK);
1489 }
1490 msleep(100);
1491 start_phy_v2_hw(hisi_hba, phy_no);
1492 }
1493
1494 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1495 {
1496 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1497 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1498 struct sas_phy *sphy = sas_phy->phy;
1499 u32 err4_reg_val, err6_reg_val;
1500
1501 /* loss dword syn, phy reset problem */
1502 err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1503
1504 /* disparity err, invalid dword */
1505 err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1506
1507 sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1508 sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1509 sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1510 sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1511 }
1512
1513 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1514 {
1515 int i;
1516
1517 for (i = 0; i < hisi_hba->n_phy; i++) {
1518 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1519 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1520
1521 if (!sas_phy->phy->enabled)
1522 continue;
1523
1524 start_phy_v2_hw(hisi_hba, i);
1525 }
1526 }
1527
1528 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1529 {
1530 u32 sl_control;
1531
1532 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1533 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1534 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1535 msleep(1);
1536 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1537 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1538 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1539 }
1540
1541 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1542 {
1543 return SAS_LINK_RATE_12_0_GBPS;
1544 }
1545
1546 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1547 struct sas_phy_linkrates *r)
1548 {
1549 u32 prog_phy_link_rate =
1550 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1551 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1552 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1553 int i;
1554 enum sas_linkrate min, max;
1555 u32 rate_mask = 0;
1556
1557 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1558 max = sas_phy->phy->maximum_linkrate;
1559 min = r->minimum_linkrate;
1560 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1561 max = r->maximum_linkrate;
1562 min = sas_phy->phy->minimum_linkrate;
1563 } else
1564 return;
1565
1566 sas_phy->phy->maximum_linkrate = max;
1567 sas_phy->phy->minimum_linkrate = min;
1568
1569 min -= SAS_LINK_RATE_1_5_GBPS;
1570 max -= SAS_LINK_RATE_1_5_GBPS;
1571
1572 for (i = 0; i <= max; i++)
1573 rate_mask |= 1 << (i * 2);
1574
1575 prog_phy_link_rate &= ~0xff;
1576 prog_phy_link_rate |= rate_mask;
1577
1578 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1579 prog_phy_link_rate);
1580
1581 phy_hard_reset_v2_hw(hisi_hba, phy_no);
1582 }
1583
1584 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1585 {
1586 int i, bitmap = 0;
1587 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1588 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1589
1590 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1591 if (phy_state & 1 << i)
1592 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1593 bitmap |= 1 << i;
1594
1595 if (hisi_hba->n_phy == 9) {
1596 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1597
1598 if (phy_state & 1 << 8)
1599 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1600 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1601 bitmap |= 1 << 9;
1602 }
1603
1604 return bitmap;
1605 }
1606
1607 /*
1608 * The callpath to this function and upto writing the write
1609 * queue pointer should be safe from interruption.
1610 */
1611 static int
1612 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1613 {
1614 struct device *dev = hisi_hba->dev;
1615 int queue = dq->id;
1616 u32 r, w;
1617
1618 w = dq->wr_point;
1619 r = hisi_sas_read32_relaxed(hisi_hba,
1620 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1621 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1622 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
1623 queue, r, w);
1624 return -EAGAIN;
1625 }
1626
1627 return 0;
1628 }
1629
1630 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1631 {
1632 struct hisi_hba *hisi_hba = dq->hisi_hba;
1633 int dlvry_queue = dq->slot_prep->dlvry_queue;
1634 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
1635
1636 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1637 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1638 dq->wr_point);
1639 }
1640
1641 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1642 struct hisi_sas_slot *slot,
1643 struct hisi_sas_cmd_hdr *hdr,
1644 struct scatterlist *scatter,
1645 int n_elem)
1646 {
1647 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1648 struct device *dev = hisi_hba->dev;
1649 struct scatterlist *sg;
1650 int i;
1651
1652 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1653 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1654 n_elem);
1655 return -EINVAL;
1656 }
1657
1658 for_each_sg(scatter, sg, n_elem, i) {
1659 struct hisi_sas_sge *entry = &sge_page->sge[i];
1660
1661 entry->addr = cpu_to_le64(sg_dma_address(sg));
1662 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1663 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1664 entry->data_off = 0;
1665 }
1666
1667 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1668
1669 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1670
1671 return 0;
1672 }
1673
1674 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1675 struct hisi_sas_slot *slot)
1676 {
1677 struct sas_task *task = slot->task;
1678 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1679 struct domain_device *device = task->dev;
1680 struct device *dev = hisi_hba->dev;
1681 struct hisi_sas_port *port = slot->port;
1682 struct scatterlist *sg_req, *sg_resp;
1683 struct hisi_sas_device *sas_dev = device->lldd_dev;
1684 dma_addr_t req_dma_addr;
1685 unsigned int req_len, resp_len;
1686 int elem, rc;
1687
1688 /*
1689 * DMA-map SMP request, response buffers
1690 */
1691 /* req */
1692 sg_req = &task->smp_task.smp_req;
1693 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1694 if (!elem)
1695 return -ENOMEM;
1696 req_len = sg_dma_len(sg_req);
1697 req_dma_addr = sg_dma_address(sg_req);
1698
1699 /* resp */
1700 sg_resp = &task->smp_task.smp_resp;
1701 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1702 if (!elem) {
1703 rc = -ENOMEM;
1704 goto err_out_req;
1705 }
1706 resp_len = sg_dma_len(sg_resp);
1707 if ((req_len & 0x3) || (resp_len & 0x3)) {
1708 rc = -EINVAL;
1709 goto err_out_resp;
1710 }
1711
1712 /* create header */
1713 /* dw0 */
1714 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1715 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1716 (2 << CMD_HDR_CMD_OFF)); /* smp */
1717
1718 /* map itct entry */
1719 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1720 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1721 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1722
1723 /* dw2 */
1724 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1725 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1726 CMD_HDR_MRFL_OFF));
1727
1728 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1729
1730 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1731 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1732
1733 return 0;
1734
1735 err_out_resp:
1736 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1737 DMA_FROM_DEVICE);
1738 err_out_req:
1739 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1740 DMA_TO_DEVICE);
1741 return rc;
1742 }
1743
1744 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1745 struct hisi_sas_slot *slot, int is_tmf,
1746 struct hisi_sas_tmf_task *tmf)
1747 {
1748 struct sas_task *task = slot->task;
1749 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1750 struct domain_device *device = task->dev;
1751 struct hisi_sas_device *sas_dev = device->lldd_dev;
1752 struct hisi_sas_port *port = slot->port;
1753 struct sas_ssp_task *ssp_task = &task->ssp_task;
1754 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1755 int has_data = 0, rc, priority = is_tmf;
1756 u8 *buf_cmd;
1757 u32 dw1 = 0, dw2 = 0;
1758
1759 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1760 (2 << CMD_HDR_TLR_CTRL_OFF) |
1761 (port->id << CMD_HDR_PORT_OFF) |
1762 (priority << CMD_HDR_PRIORITY_OFF) |
1763 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1764
1765 dw1 = 1 << CMD_HDR_VDTL_OFF;
1766 if (is_tmf) {
1767 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1768 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1769 } else {
1770 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1771 switch (scsi_cmnd->sc_data_direction) {
1772 case DMA_TO_DEVICE:
1773 has_data = 1;
1774 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1775 break;
1776 case DMA_FROM_DEVICE:
1777 has_data = 1;
1778 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1779 break;
1780 default:
1781 dw1 &= ~CMD_HDR_DIR_MSK;
1782 }
1783 }
1784
1785 /* map itct entry */
1786 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1787 hdr->dw1 = cpu_to_le32(dw1);
1788
1789 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1790 + 3) / 4) << CMD_HDR_CFL_OFF) |
1791 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1792 (2 << CMD_HDR_SG_MOD_OFF);
1793 hdr->dw2 = cpu_to_le32(dw2);
1794
1795 hdr->transfer_tags = cpu_to_le32(slot->idx);
1796
1797 if (has_data) {
1798 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1799 slot->n_elem);
1800 if (rc)
1801 return rc;
1802 }
1803
1804 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1805 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1806 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1807
1808 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1809 sizeof(struct ssp_frame_hdr);
1810
1811 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1812 if (!is_tmf) {
1813 buf_cmd[9] = task->ssp_task.task_attr |
1814 (task->ssp_task.task_prio << 3);
1815 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1816 task->ssp_task.cmd->cmd_len);
1817 } else {
1818 buf_cmd[10] = tmf->tmf;
1819 switch (tmf->tmf) {
1820 case TMF_ABORT_TASK:
1821 case TMF_QUERY_TASK:
1822 buf_cmd[12] =
1823 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1824 buf_cmd[13] =
1825 tmf->tag_of_task_to_be_managed & 0xff;
1826 break;
1827 default:
1828 break;
1829 }
1830 }
1831
1832 return 0;
1833 }
1834
1835 #define TRANS_TX_ERR 0
1836 #define TRANS_RX_ERR 1
1837 #define DMA_TX_ERR 2
1838 #define SIPC_RX_ERR 3
1839 #define DMA_RX_ERR 4
1840
1841 #define DMA_TX_ERR_OFF 0
1842 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1843 #define SIPC_RX_ERR_OFF 16
1844 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1845
1846 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1847 {
1848 static const u8 trans_tx_err_code_prio[] = {
1849 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1850 TRANS_TX_ERR_PHY_NOT_ENABLE,
1851 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1852 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1853 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1854 RESERVED0,
1855 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1856 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1857 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1858 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1859 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1860 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1861 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1862 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1863 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1864 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1865 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1866 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1867 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1868 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1869 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1870 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1871 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1872 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1873 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1874 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1875 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1876 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1877 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1878 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1879 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1880 };
1881 int index, i;
1882
1883 for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1884 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1885 if (err_msk & (1 << index))
1886 return trans_tx_err_code_prio[i];
1887 }
1888 return -1;
1889 }
1890
1891 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1892 {
1893 static const u8 trans_rx_err_code_prio[] = {
1894 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1895 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1896 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1897 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1898 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1899 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1900 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1901 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1902 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1903 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1904 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1905 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1906 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1907 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1908 RESERVED1,
1909 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1910 TRANS_RX_ERR_WITH_DATA_LEN0,
1911 TRANS_RX_ERR_WITH_BAD_HASH,
1912 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1913 TRANS_RX_SSP_FRM_LEN_ERR,
1914 RESERVED2,
1915 RESERVED3,
1916 RESERVED4,
1917 RESERVED5,
1918 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1919 TRANS_RX_SMP_FRM_LEN_ERR,
1920 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1921 RESERVED6,
1922 RESERVED7,
1923 RESERVED8,
1924 RESERVED9,
1925 TRANS_RX_R_ERR,
1926 };
1927 int index, i;
1928
1929 for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1930 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1931 if (err_msk & (1 << index))
1932 return trans_rx_err_code_prio[i];
1933 }
1934 return -1;
1935 }
1936
1937 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1938 {
1939 static const u8 dma_tx_err_code_prio[] = {
1940 DMA_TX_UNEXP_XFER_ERR,
1941 DMA_TX_UNEXP_RETRANS_ERR,
1942 DMA_TX_XFER_LEN_OVERFLOW,
1943 DMA_TX_XFER_OFFSET_ERR,
1944 DMA_TX_RAM_ECC_ERR,
1945 DMA_TX_DIF_LEN_ALIGN_ERR,
1946 DMA_TX_DIF_CRC_ERR,
1947 DMA_TX_DIF_APP_ERR,
1948 DMA_TX_DIF_RPP_ERR,
1949 DMA_TX_DATA_SGL_OVERFLOW,
1950 DMA_TX_DIF_SGL_OVERFLOW,
1951 };
1952 int index, i;
1953
1954 for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1955 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1956 err_msk = err_msk & DMA_TX_ERR_MSK;
1957 if (err_msk & (1 << index))
1958 return dma_tx_err_code_prio[i];
1959 }
1960 return -1;
1961 }
1962
1963 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1964 {
1965 static const u8 sipc_rx_err_code_prio[] = {
1966 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1967 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1968 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1969 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1970 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1971 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1972 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1973 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1974 SIPC_RX_SATA_UNEXP_FIS_ERR,
1975 SIPC_RX_WRSETUP_ESTATUS_ERR,
1976 SIPC_RX_DATA_UNDERFLOW_ERR,
1977 };
1978 int index, i;
1979
1980 for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1981 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1982 err_msk = err_msk & SIPC_RX_ERR_MSK;
1983 if (err_msk & (1 << (index + 0x10)))
1984 return sipc_rx_err_code_prio[i];
1985 }
1986 return -1;
1987 }
1988
1989 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
1990 {
1991 static const u8 dma_rx_err_code_prio[] = {
1992 DMA_RX_UNKNOWN_FRM_ERR,
1993 DMA_RX_DATA_LEN_OVERFLOW,
1994 DMA_RX_DATA_LEN_UNDERFLOW,
1995 DMA_RX_DATA_OFFSET_ERR,
1996 RESERVED10,
1997 DMA_RX_SATA_FRAME_TYPE_ERR,
1998 DMA_RX_RESP_BUF_OVERFLOW,
1999 DMA_RX_UNEXP_RETRANS_RESP_ERR,
2000 DMA_RX_UNEXP_NORM_RESP_ERR,
2001 DMA_RX_UNEXP_RDFRAME_ERR,
2002 DMA_RX_PIO_DATA_LEN_ERR,
2003 DMA_RX_RDSETUP_STATUS_ERR,
2004 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2005 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2006 DMA_RX_RDSETUP_LEN_ODD_ERR,
2007 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2008 DMA_RX_RDSETUP_LEN_OVER_ERR,
2009 DMA_RX_RDSETUP_OFFSET_ERR,
2010 DMA_RX_RDSETUP_ACTIVE_ERR,
2011 DMA_RX_RDSETUP_ESTATUS_ERR,
2012 DMA_RX_RAM_ECC_ERR,
2013 DMA_RX_DIF_CRC_ERR,
2014 DMA_RX_DIF_APP_ERR,
2015 DMA_RX_DIF_RPP_ERR,
2016 DMA_RX_DATA_SGL_OVERFLOW,
2017 DMA_RX_DIF_SGL_OVERFLOW,
2018 };
2019 int index, i;
2020
2021 for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2022 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2023 if (err_msk & (1 << index))
2024 return dma_rx_err_code_prio[i];
2025 }
2026 return -1;
2027 }
2028
2029 /* by default, task resp is complete */
2030 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2031 struct sas_task *task,
2032 struct hisi_sas_slot *slot,
2033 int err_phase)
2034 {
2035 struct task_status_struct *ts = &task->task_status;
2036 struct hisi_sas_err_record_v2 *err_record =
2037 hisi_sas_status_buf_addr_mem(slot);
2038 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2039 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2040 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2041 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2042 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2043 int error = -1;
2044
2045 if (err_phase == 1) {
2046 /* error in TX phase, the priority of error is: DW2 > DW0 */
2047 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2048 if (error == -1)
2049 error = parse_trans_tx_err_code_v2_hw(
2050 trans_tx_fail_type);
2051 } else if (err_phase == 2) {
2052 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2053 error = parse_trans_rx_err_code_v2_hw(
2054 trans_rx_fail_type);
2055 if (error == -1) {
2056 error = parse_dma_rx_err_code_v2_hw(
2057 dma_rx_err_type);
2058 if (error == -1)
2059 error = parse_sipc_rx_err_code_v2_hw(
2060 sipc_rx_err_type);
2061 }
2062 }
2063
2064 switch (task->task_proto) {
2065 case SAS_PROTOCOL_SSP:
2066 {
2067 switch (error) {
2068 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2069 {
2070 ts->stat = SAS_OPEN_REJECT;
2071 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2072 break;
2073 }
2074 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2075 {
2076 ts->stat = SAS_OPEN_REJECT;
2077 ts->open_rej_reason = SAS_OREJ_EPROTO;
2078 break;
2079 }
2080 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2081 {
2082 ts->stat = SAS_OPEN_REJECT;
2083 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2084 break;
2085 }
2086 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2087 {
2088 ts->stat = SAS_OPEN_REJECT;
2089 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2090 break;
2091 }
2092 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2093 {
2094 ts->stat = SAS_OPEN_REJECT;
2095 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2096 break;
2097 }
2098 case DMA_RX_UNEXP_NORM_RESP_ERR:
2099 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2100 case DMA_RX_RESP_BUF_OVERFLOW:
2101 {
2102 ts->stat = SAS_OPEN_REJECT;
2103 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2104 break;
2105 }
2106 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2107 {
2108 /* not sure */
2109 ts->stat = SAS_DEV_NO_RESPONSE;
2110 break;
2111 }
2112 case DMA_RX_DATA_LEN_OVERFLOW:
2113 {
2114 ts->stat = SAS_DATA_OVERRUN;
2115 ts->residual = 0;
2116 break;
2117 }
2118 case DMA_RX_DATA_LEN_UNDERFLOW:
2119 {
2120 ts->residual = trans_tx_fail_type;
2121 ts->stat = SAS_DATA_UNDERRUN;
2122 break;
2123 }
2124 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2125 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2126 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2127 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2128 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2129 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2130 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2131 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2132 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2133 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2134 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2135 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2136 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2137 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2138 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2139 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2140 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2141 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2142 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2143 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2144 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2145 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2146 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2147 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2148 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2149 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2150 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2151 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2152 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2153 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2154 case TRANS_TX_ERR_FRAME_TXED:
2155 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2156 case TRANS_RX_ERR_WITH_DATA_LEN0:
2157 case TRANS_RX_ERR_WITH_BAD_HASH:
2158 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2159 case TRANS_RX_SSP_FRM_LEN_ERR:
2160 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2161 case DMA_TX_DATA_SGL_OVERFLOW:
2162 case DMA_TX_UNEXP_XFER_ERR:
2163 case DMA_TX_UNEXP_RETRANS_ERR:
2164 case DMA_TX_XFER_LEN_OVERFLOW:
2165 case DMA_TX_XFER_OFFSET_ERR:
2166 case SIPC_RX_DATA_UNDERFLOW_ERR:
2167 case DMA_RX_DATA_SGL_OVERFLOW:
2168 case DMA_RX_DATA_OFFSET_ERR:
2169 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2170 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2171 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2172 case DMA_RX_SATA_FRAME_TYPE_ERR:
2173 case DMA_RX_UNKNOWN_FRM_ERR:
2174 {
2175 /* This will request a retry */
2176 ts->stat = SAS_QUEUE_FULL;
2177 slot->abort = 1;
2178 break;
2179 }
2180 default:
2181 break;
2182 }
2183 }
2184 break;
2185 case SAS_PROTOCOL_SMP:
2186 ts->stat = SAM_STAT_CHECK_CONDITION;
2187 break;
2188
2189 case SAS_PROTOCOL_SATA:
2190 case SAS_PROTOCOL_STP:
2191 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2192 {
2193 switch (error) {
2194 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2195 {
2196 ts->stat = SAS_OPEN_REJECT;
2197 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2198 break;
2199 }
2200 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2201 {
2202 ts->resp = SAS_TASK_UNDELIVERED;
2203 ts->stat = SAS_DEV_NO_RESPONSE;
2204 break;
2205 }
2206 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2207 {
2208 ts->stat = SAS_OPEN_REJECT;
2209 ts->open_rej_reason = SAS_OREJ_EPROTO;
2210 break;
2211 }
2212 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2213 {
2214 ts->stat = SAS_OPEN_REJECT;
2215 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2216 break;
2217 }
2218 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2219 {
2220 ts->stat = SAS_OPEN_REJECT;
2221 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2222 break;
2223 }
2224 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2225 {
2226 ts->stat = SAS_OPEN_REJECT;
2227 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2228 break;
2229 }
2230 case DMA_RX_RESP_BUF_OVERFLOW:
2231 case DMA_RX_UNEXP_NORM_RESP_ERR:
2232 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2233 {
2234 ts->stat = SAS_OPEN_REJECT;
2235 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2236 break;
2237 }
2238 case DMA_RX_DATA_LEN_OVERFLOW:
2239 {
2240 ts->stat = SAS_DATA_OVERRUN;
2241 ts->residual = 0;
2242 break;
2243 }
2244 case DMA_RX_DATA_LEN_UNDERFLOW:
2245 {
2246 ts->residual = trans_tx_fail_type;
2247 ts->stat = SAS_DATA_UNDERRUN;
2248 break;
2249 }
2250 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2251 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2252 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2253 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2254 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2255 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2256 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2257 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2258 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2259 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2260 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2261 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2262 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2263 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2264 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2265 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2266 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2267 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2268 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2269 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2270 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2271 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2272 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2273 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2274 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2275 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2276 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2277 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2278 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2279 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2280 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2281 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2282 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2283 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2284 case TRANS_RX_ERR_WITH_DATA_LEN0:
2285 case TRANS_RX_ERR_WITH_BAD_HASH:
2286 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2287 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2288 case DMA_TX_DATA_SGL_OVERFLOW:
2289 case DMA_TX_UNEXP_XFER_ERR:
2290 case DMA_TX_UNEXP_RETRANS_ERR:
2291 case DMA_TX_XFER_LEN_OVERFLOW:
2292 case DMA_TX_XFER_OFFSET_ERR:
2293 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2294 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2295 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2296 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2297 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2298 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2299 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2300 case DMA_RX_DATA_SGL_OVERFLOW:
2301 case DMA_RX_DATA_OFFSET_ERR:
2302 case DMA_RX_SATA_FRAME_TYPE_ERR:
2303 case DMA_RX_UNEXP_RDFRAME_ERR:
2304 case DMA_RX_PIO_DATA_LEN_ERR:
2305 case DMA_RX_RDSETUP_STATUS_ERR:
2306 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2307 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2308 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2309 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2310 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2311 case DMA_RX_RDSETUP_OFFSET_ERR:
2312 case DMA_RX_RDSETUP_ACTIVE_ERR:
2313 case DMA_RX_RDSETUP_ESTATUS_ERR:
2314 case DMA_RX_UNKNOWN_FRM_ERR:
2315 case TRANS_RX_SSP_FRM_LEN_ERR:
2316 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2317 {
2318 slot->abort = 1;
2319 ts->stat = SAS_PHY_DOWN;
2320 break;
2321 }
2322 default:
2323 {
2324 ts->stat = SAS_PROTO_RESPONSE;
2325 break;
2326 }
2327 }
2328 hisi_sas_sata_done(task, slot);
2329 }
2330 break;
2331 default:
2332 break;
2333 }
2334 }
2335
2336 static int
2337 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2338 {
2339 struct sas_task *task = slot->task;
2340 struct hisi_sas_device *sas_dev;
2341 struct device *dev = hisi_hba->dev;
2342 struct task_status_struct *ts;
2343 struct domain_device *device;
2344 enum exec_status sts;
2345 struct hisi_sas_complete_v2_hdr *complete_queue =
2346 hisi_hba->complete_hdr[slot->cmplt_queue];
2347 struct hisi_sas_complete_v2_hdr *complete_hdr =
2348 &complete_queue[slot->cmplt_queue_slot];
2349 unsigned long flags;
2350 int aborted;
2351
2352 if (unlikely(!task || !task->lldd_task || !task->dev))
2353 return -EINVAL;
2354
2355 ts = &task->task_status;
2356 device = task->dev;
2357 sas_dev = device->lldd_dev;
2358
2359 spin_lock_irqsave(&task->task_state_lock, flags);
2360 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
2361 task->task_state_flags &=
2362 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2363 spin_unlock_irqrestore(&task->task_state_lock, flags);
2364
2365 memset(ts, 0, sizeof(*ts));
2366 ts->resp = SAS_TASK_COMPLETE;
2367
2368 if (unlikely(aborted)) {
2369 dev_dbg(dev, "slot_complete: task(%p) aborted\n", task);
2370 ts->stat = SAS_ABORTED_TASK;
2371 spin_lock_irqsave(&hisi_hba->lock, flags);
2372 hisi_sas_slot_task_free(hisi_hba, task, slot);
2373 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2374 return -1;
2375 }
2376
2377 if (unlikely(!sas_dev)) {
2378 dev_dbg(dev, "slot complete: port has no device\n");
2379 ts->stat = SAS_PHY_DOWN;
2380 goto out;
2381 }
2382
2383 /* Use SAS+TMF status codes */
2384 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2385 >> CMPLT_HDR_ABORT_STAT_OFF) {
2386 case STAT_IO_ABORTED:
2387 /* this io has been aborted by abort command */
2388 ts->stat = SAS_ABORTED_TASK;
2389 goto out;
2390 case STAT_IO_COMPLETE:
2391 /* internal abort command complete */
2392 ts->stat = TMF_RESP_FUNC_SUCC;
2393 del_timer(&slot->internal_abort_timer);
2394 goto out;
2395 case STAT_IO_NO_DEVICE:
2396 ts->stat = TMF_RESP_FUNC_COMPLETE;
2397 del_timer(&slot->internal_abort_timer);
2398 goto out;
2399 case STAT_IO_NOT_VALID:
2400 /* abort single io, controller don't find
2401 * the io need to abort
2402 */
2403 ts->stat = TMF_RESP_FUNC_FAILED;
2404 del_timer(&slot->internal_abort_timer);
2405 goto out;
2406 default:
2407 break;
2408 }
2409
2410 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2411 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2412 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2413 >> CMPLT_HDR_ERR_PHASE_OFF;
2414 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2415
2416 /* Analyse error happens on which phase TX or RX */
2417 if (ERR_ON_TX_PHASE(err_phase))
2418 slot_err_v2_hw(hisi_hba, task, slot, 1);
2419 else if (ERR_ON_RX_PHASE(err_phase))
2420 slot_err_v2_hw(hisi_hba, task, slot, 2);
2421
2422 if (ts->stat != SAS_DATA_UNDERRUN)
2423 dev_info(dev, "erroneous completion iptt=%d task=%p "
2424 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
2425 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
2426 slot->idx, task,
2427 complete_hdr->dw0, complete_hdr->dw1,
2428 complete_hdr->act, complete_hdr->dw3,
2429 error_info[0], error_info[1],
2430 error_info[2], error_info[3]);
2431
2432 if (unlikely(slot->abort))
2433 return ts->stat;
2434 goto out;
2435 }
2436
2437 switch (task->task_proto) {
2438 case SAS_PROTOCOL_SSP:
2439 {
2440 struct hisi_sas_status_buffer *status_buffer =
2441 hisi_sas_status_buf_addr_mem(slot);
2442 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2443 &status_buffer->iu[0];
2444
2445 sas_ssp_task_response(dev, task, iu);
2446 break;
2447 }
2448 case SAS_PROTOCOL_SMP:
2449 {
2450 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2451 void *to;
2452
2453 ts->stat = SAM_STAT_GOOD;
2454 to = kmap_atomic(sg_page(sg_resp));
2455
2456 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2457 DMA_FROM_DEVICE);
2458 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2459 DMA_TO_DEVICE);
2460 memcpy(to + sg_resp->offset,
2461 hisi_sas_status_buf_addr_mem(slot) +
2462 sizeof(struct hisi_sas_err_record),
2463 sg_dma_len(sg_resp));
2464 kunmap_atomic(to);
2465 break;
2466 }
2467 case SAS_PROTOCOL_SATA:
2468 case SAS_PROTOCOL_STP:
2469 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2470 {
2471 ts->stat = SAM_STAT_GOOD;
2472 hisi_sas_sata_done(task, slot);
2473 break;
2474 }
2475 default:
2476 ts->stat = SAM_STAT_CHECK_CONDITION;
2477 break;
2478 }
2479
2480 if (!slot->port->port_attached) {
2481 dev_warn(dev, "slot complete: port %d has removed\n",
2482 slot->port->sas_port.id);
2483 ts->stat = SAS_PHY_DOWN;
2484 }
2485
2486 out:
2487 spin_lock_irqsave(&task->task_state_lock, flags);
2488 task->task_state_flags |= SAS_TASK_STATE_DONE;
2489 spin_unlock_irqrestore(&task->task_state_lock, flags);
2490 spin_lock_irqsave(&hisi_hba->lock, flags);
2491 hisi_sas_slot_task_free(hisi_hba, task, slot);
2492 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2493 sts = ts->stat;
2494
2495 if (task->task_done)
2496 task->task_done(task);
2497
2498 return sts;
2499 }
2500
2501 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2502 struct hisi_sas_slot *slot)
2503 {
2504 struct sas_task *task = slot->task;
2505 struct domain_device *device = task->dev;
2506 struct domain_device *parent_dev = device->parent;
2507 struct hisi_sas_device *sas_dev = device->lldd_dev;
2508 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2509 struct asd_sas_port *sas_port = device->port;
2510 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2511 u8 *buf_cmd;
2512 int has_data = 0, rc = 0, hdr_tag = 0;
2513 u32 dw1 = 0, dw2 = 0;
2514
2515 /* create header */
2516 /* dw0 */
2517 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2518 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2519 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2520 else
2521 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2522
2523 /* dw1 */
2524 switch (task->data_dir) {
2525 case DMA_TO_DEVICE:
2526 has_data = 1;
2527 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2528 break;
2529 case DMA_FROM_DEVICE:
2530 has_data = 1;
2531 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2532 break;
2533 default:
2534 dw1 &= ~CMD_HDR_DIR_MSK;
2535 }
2536
2537 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2538 (task->ata_task.fis.control & ATA_SRST))
2539 dw1 |= 1 << CMD_HDR_RESET_OFF;
2540
2541 dw1 |= (hisi_sas_get_ata_protocol(
2542 &task->ata_task.fis, task->data_dir))
2543 << CMD_HDR_FRAME_TYPE_OFF;
2544 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2545 hdr->dw1 = cpu_to_le32(dw1);
2546
2547 /* dw2 */
2548 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2549 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2550 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2551 }
2552
2553 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2554 2 << CMD_HDR_SG_MOD_OFF;
2555 hdr->dw2 = cpu_to_le32(dw2);
2556
2557 /* dw3 */
2558 hdr->transfer_tags = cpu_to_le32(slot->idx);
2559
2560 if (has_data) {
2561 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2562 slot->n_elem);
2563 if (rc)
2564 return rc;
2565 }
2566
2567 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2568 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2569 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2570
2571 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2572
2573 if (likely(!task->ata_task.device_control_reg_update))
2574 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2575 /* fill in command FIS */
2576 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2577
2578 return 0;
2579 }
2580
2581 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2582 {
2583 struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2584 struct hisi_sas_port *port = slot->port;
2585 struct asd_sas_port *asd_sas_port;
2586 struct asd_sas_phy *sas_phy;
2587
2588 if (!port)
2589 return;
2590
2591 asd_sas_port = &port->sas_port;
2592
2593 /* Kick the hardware - send break command */
2594 list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2595 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2596 struct hisi_hba *hisi_hba = phy->hisi_hba;
2597 int phy_no = sas_phy->id;
2598 u32 link_dfx2;
2599
2600 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2601 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2602 (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2603 u32 txid_auto;
2604
2605 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2606 TXID_AUTO);
2607 txid_auto |= TXID_AUTO_CTB_MSK;
2608 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2609 txid_auto);
2610 return;
2611 }
2612 }
2613 }
2614
2615 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2616 struct hisi_sas_slot *slot,
2617 int device_id, int abort_flag, int tag_to_abort)
2618 {
2619 struct sas_task *task = slot->task;
2620 struct domain_device *dev = task->dev;
2621 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2622 struct hisi_sas_port *port = slot->port;
2623 struct timer_list *timer = &slot->internal_abort_timer;
2624
2625 /* setup the quirk timer */
2626 timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2627 /* Set the timeout to 10ms less than internal abort timeout */
2628 mod_timer(timer, jiffies + msecs_to_jiffies(100));
2629
2630 /* dw0 */
2631 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2632 (port->id << CMD_HDR_PORT_OFF) |
2633 ((dev_is_sata(dev) ? 1:0) <<
2634 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2635 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2636
2637 /* dw1 */
2638 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2639
2640 /* dw7 */
2641 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2642 hdr->transfer_tags = cpu_to_le32(slot->idx);
2643
2644 return 0;
2645 }
2646
2647 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2648 {
2649 int i, res = IRQ_HANDLED;
2650 u32 port_id, link_rate, hard_phy_linkrate;
2651 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2652 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2653 struct device *dev = hisi_hba->dev;
2654 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2655 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2656
2657 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2658
2659 if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2660 goto end;
2661
2662 if (phy_no == 8) {
2663 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2664
2665 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2666 PORT_STATE_PHY8_PORT_NUM_OFF;
2667 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2668 PORT_STATE_PHY8_CONN_RATE_OFF;
2669 } else {
2670 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2671 port_id = (port_id >> (4 * phy_no)) & 0xf;
2672 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2673 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2674 }
2675
2676 if (port_id == 0xf) {
2677 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2678 res = IRQ_NONE;
2679 goto end;
2680 }
2681
2682 for (i = 0; i < 6; i++) {
2683 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2684 RX_IDAF_DWORD0 + (i * 4));
2685 frame_rcvd[i] = __swab32(idaf);
2686 }
2687
2688 sas_phy->linkrate = link_rate;
2689 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2690 HARD_PHY_LINKRATE);
2691 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2692 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2693
2694 sas_phy->oob_mode = SAS_OOB_MODE;
2695 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2696 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2697 phy->port_id = port_id;
2698 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2699 phy->phy_type |= PORT_TYPE_SAS;
2700 phy->phy_attached = 1;
2701 phy->identify.device_type = id->dev_type;
2702 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
2703 if (phy->identify.device_type == SAS_END_DEVICE)
2704 phy->identify.target_port_protocols =
2705 SAS_PROTOCOL_SSP;
2706 else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2707 phy->identify.target_port_protocols =
2708 SAS_PROTOCOL_SMP;
2709 if (!timer_pending(&hisi_hba->timer))
2710 set_link_timer_quirk(hisi_hba);
2711 }
2712 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
2713
2714 end:
2715 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2716 CHL_INT0_SL_PHY_ENABLE_MSK);
2717 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2718
2719 return res;
2720 }
2721
2722 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2723 {
2724 u32 port_state;
2725
2726 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2727 if (port_state & 0x1ff)
2728 return true;
2729
2730 return false;
2731 }
2732
2733 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2734 {
2735 u32 phy_state, sl_ctrl, txid_auto;
2736 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2737 struct hisi_sas_port *port = phy->port;
2738 struct device *dev = hisi_hba->dev;
2739
2740 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2741
2742 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2743 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
2744 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2745
2746 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2747 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2748 sl_ctrl & ~SL_CONTROL_CTA_MSK);
2749 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2750 if (!check_any_wideports_v2_hw(hisi_hba) &&
2751 timer_pending(&hisi_hba->timer))
2752 del_timer(&hisi_hba->timer);
2753
2754 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2755 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2756 txid_auto | TXID_AUTO_CT3_MSK);
2757
2758 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2759 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2760
2761 return IRQ_HANDLED;
2762 }
2763
2764 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2765 {
2766 struct hisi_hba *hisi_hba = p;
2767 u32 irq_msk;
2768 int phy_no = 0;
2769 irqreturn_t res = IRQ_NONE;
2770
2771 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2772 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2773 while (irq_msk) {
2774 if (irq_msk & 1) {
2775 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2776 CHL_INT0);
2777
2778 switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2779 CHL_INT0_SL_PHY_ENABLE_MSK)) {
2780
2781 case CHL_INT0_SL_PHY_ENABLE_MSK:
2782 /* phy up */
2783 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2784 IRQ_HANDLED)
2785 res = IRQ_HANDLED;
2786 break;
2787
2788 case CHL_INT0_NOT_RDY_MSK:
2789 /* phy down */
2790 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2791 IRQ_HANDLED)
2792 res = IRQ_HANDLED;
2793 break;
2794
2795 case (CHL_INT0_NOT_RDY_MSK |
2796 CHL_INT0_SL_PHY_ENABLE_MSK):
2797 reg_value = hisi_sas_read32(hisi_hba,
2798 PHY_STATE);
2799 if (reg_value & BIT(phy_no)) {
2800 /* phy up */
2801 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2802 IRQ_HANDLED)
2803 res = IRQ_HANDLED;
2804 } else {
2805 /* phy down */
2806 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2807 IRQ_HANDLED)
2808 res = IRQ_HANDLED;
2809 }
2810 break;
2811
2812 default:
2813 break;
2814 }
2815
2816 }
2817 irq_msk >>= 1;
2818 phy_no++;
2819 }
2820
2821 return res;
2822 }
2823
2824 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2825 {
2826 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2827 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2828 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2829 u32 bcast_status;
2830
2831 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2832 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2833 if (bcast_status & RX_BCAST_CHG_MSK)
2834 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2835 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2836 CHL_INT0_SL_RX_BCST_ACK_MSK);
2837 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2838 }
2839
2840 static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
2841 {
2842 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
2843 .msg = "dmac_tx_ecc_bad_err",
2844 },
2845 {
2846 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
2847 .msg = "dmac_rx_ecc_bad_err",
2848 },
2849 {
2850 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
2851 .msg = "dma_tx_axi_wr_err",
2852 },
2853 {
2854 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
2855 .msg = "dma_tx_axi_rd_err",
2856 },
2857 {
2858 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
2859 .msg = "dma_rx_axi_wr_err",
2860 },
2861 {
2862 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
2863 .msg = "dma_rx_axi_rd_err",
2864 },
2865 };
2866
2867 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2868 {
2869 struct hisi_hba *hisi_hba = p;
2870 struct device *dev = hisi_hba->dev;
2871 u32 ent_msk, ent_tmp, irq_msk;
2872 int phy_no = 0;
2873
2874 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2875 ent_tmp = ent_msk;
2876 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2877 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2878
2879 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2880 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2881
2882 while (irq_msk) {
2883 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2884 CHL_INT0);
2885 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2886 CHL_INT1);
2887 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2888 CHL_INT2);
2889
2890 if ((irq_msk & (1 << phy_no)) && irq_value1) {
2891 int i;
2892
2893 for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
2894 const struct hisi_sas_hw_error *error =
2895 &port_ecc_axi_error[i];
2896
2897 if (!(irq_value1 & error->irq_msk))
2898 continue;
2899
2900 dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
2901 error->msg, phy_no, irq_value1);
2902 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2903 }
2904
2905 hisi_sas_phy_write32(hisi_hba, phy_no,
2906 CHL_INT1, irq_value1);
2907 }
2908
2909 if ((irq_msk & (1 << phy_no)) && irq_value2) {
2910 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2911
2912 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
2913 dev_warn(dev, "phy%d identify timeout\n",
2914 phy_no);
2915 hisi_sas_notify_phy_event(phy,
2916 HISI_PHYE_LINK_RESET);
2917 }
2918
2919 hisi_sas_phy_write32(hisi_hba, phy_no,
2920 CHL_INT2, irq_value2);
2921 }
2922
2923 if ((irq_msk & (1 << phy_no)) && irq_value0) {
2924 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2925 phy_bcast_v2_hw(phy_no, hisi_hba);
2926
2927 hisi_sas_phy_write32(hisi_hba, phy_no,
2928 CHL_INT0, irq_value0
2929 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2930 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2931 & (~CHL_INT0_NOT_RDY_MSK));
2932 }
2933 irq_msk &= ~(1 << phy_no);
2934 phy_no++;
2935 }
2936
2937 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2938
2939 return IRQ_HANDLED;
2940 }
2941
2942 static void
2943 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2944 {
2945 struct device *dev = hisi_hba->dev;
2946 const struct hisi_sas_hw_error *ecc_error;
2947 u32 val;
2948 int i;
2949
2950 for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2951 ecc_error = &one_bit_ecc_errors[i];
2952 if (irq_value & ecc_error->irq_msk) {
2953 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2954 val &= ecc_error->msk;
2955 val >>= ecc_error->shift;
2956 dev_warn(dev, ecc_error->msg, val);
2957 }
2958 }
2959 }
2960
2961 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2962 u32 irq_value)
2963 {
2964 struct device *dev = hisi_hba->dev;
2965 const struct hisi_sas_hw_error *ecc_error;
2966 u32 val;
2967 int i;
2968
2969 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2970 ecc_error = &multi_bit_ecc_errors[i];
2971 if (irq_value & ecc_error->irq_msk) {
2972 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2973 val &= ecc_error->msk;
2974 val >>= ecc_error->shift;
2975 dev_err(dev, ecc_error->msg, irq_value, val);
2976 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2977 }
2978 }
2979
2980 return;
2981 }
2982
2983 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
2984 {
2985 struct hisi_hba *hisi_hba = p;
2986 u32 irq_value, irq_msk;
2987
2988 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2989 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
2990
2991 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2992 if (irq_value) {
2993 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2994 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2995 }
2996
2997 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2998 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2999
3000 return IRQ_HANDLED;
3001 }
3002
3003 static const struct hisi_sas_hw_error axi_error[] = {
3004 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
3005 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
3006 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
3007 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
3008 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
3009 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
3010 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
3011 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
3012 {},
3013 };
3014
3015 static const struct hisi_sas_hw_error fifo_error[] = {
3016 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
3017 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
3018 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
3019 { .msk = BIT(11), .msg = "CMDP_FIFO" },
3020 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
3021 {},
3022 };
3023
3024 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
3025 {
3026 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
3027 .msg = "write pointer and depth",
3028 },
3029 {
3030 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
3031 .msg = "iptt no match slot",
3032 },
3033 {
3034 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
3035 .msg = "read pointer and depth",
3036 },
3037 {
3038 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
3039 .reg = HGC_AXI_FIFO_ERR_INFO,
3040 .sub = axi_error,
3041 },
3042 {
3043 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
3044 .reg = HGC_AXI_FIFO_ERR_INFO,
3045 .sub = fifo_error,
3046 },
3047 {
3048 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
3049 .msg = "LM add/fetch list",
3050 },
3051 {
3052 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
3053 .msg = "SAS_HGC_ABT fetch LM list",
3054 },
3055 };
3056
3057 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
3058 {
3059 struct hisi_hba *hisi_hba = p;
3060 u32 irq_value, irq_msk, err_value;
3061 struct device *dev = hisi_hba->dev;
3062 const struct hisi_sas_hw_error *axi_error;
3063 int i;
3064
3065 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3066 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3067
3068 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3069
3070 for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3071 axi_error = &fatal_axi_errors[i];
3072 if (!(irq_value & axi_error->irq_msk))
3073 continue;
3074
3075 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3076 1 << axi_error->shift);
3077 if (axi_error->sub) {
3078 const struct hisi_sas_hw_error *sub = axi_error->sub;
3079
3080 err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3081 for (; sub->msk || sub->msg; sub++) {
3082 if (!(err_value & sub->msk))
3083 continue;
3084 dev_err(dev, "%s (0x%x) found!\n",
3085 sub->msg, irq_value);
3086 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3087 }
3088 } else {
3089 dev_err(dev, "%s (0x%x) found!\n",
3090 axi_error->msg, irq_value);
3091 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3092 }
3093 }
3094
3095 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3096 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3097 u32 dev_id = reg_val & ITCT_DEV_MSK;
3098 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3099
3100 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3101 dev_dbg(dev, "clear ITCT ok\n");
3102 complete(sas_dev->completion);
3103 }
3104
3105 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3106 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3107
3108 return IRQ_HANDLED;
3109 }
3110
3111 static void cq_tasklet_v2_hw(unsigned long val)
3112 {
3113 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3114 struct hisi_hba *hisi_hba = cq->hisi_hba;
3115 struct hisi_sas_slot *slot;
3116 struct hisi_sas_itct *itct;
3117 struct hisi_sas_complete_v2_hdr *complete_queue;
3118 u32 rd_point = cq->rd_point, wr_point, dev_id;
3119 int queue = cq->id;
3120 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
3121
3122 if (unlikely(hisi_hba->reject_stp_links_msk))
3123 phys_try_accept_stp_links_v2_hw(hisi_hba);
3124
3125 complete_queue = hisi_hba->complete_hdr[queue];
3126
3127 spin_lock(&dq->lock);
3128 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3129 (0x14 * queue));
3130
3131 while (rd_point != wr_point) {
3132 struct hisi_sas_complete_v2_hdr *complete_hdr;
3133 int iptt;
3134
3135 complete_hdr = &complete_queue[rd_point];
3136
3137 /* Check for NCQ completion */
3138 if (complete_hdr->act) {
3139 u32 act_tmp = complete_hdr->act;
3140 int ncq_tag_count = ffs(act_tmp);
3141
3142 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3143 CMPLT_HDR_DEV_ID_OFF;
3144 itct = &hisi_hba->itct[dev_id];
3145
3146 /* The NCQ tags are held in the itct header */
3147 while (ncq_tag_count) {
3148 __le64 *ncq_tag = &itct->qw4_15[0];
3149
3150 ncq_tag_count -= 1;
3151 iptt = (ncq_tag[ncq_tag_count / 5]
3152 >> (ncq_tag_count % 5) * 12) & 0xfff;
3153
3154 slot = &hisi_hba->slot_info[iptt];
3155 slot->cmplt_queue_slot = rd_point;
3156 slot->cmplt_queue = queue;
3157 slot_complete_v2_hw(hisi_hba, slot);
3158
3159 act_tmp &= ~(1 << ncq_tag_count);
3160 ncq_tag_count = ffs(act_tmp);
3161 }
3162 } else {
3163 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3164 slot = &hisi_hba->slot_info[iptt];
3165 slot->cmplt_queue_slot = rd_point;
3166 slot->cmplt_queue = queue;
3167 slot_complete_v2_hw(hisi_hba, slot);
3168 }
3169
3170 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3171 rd_point = 0;
3172 }
3173
3174 /* update rd_point */
3175 cq->rd_point = rd_point;
3176 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3177 spin_unlock(&dq->lock);
3178 }
3179
3180 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3181 {
3182 struct hisi_sas_cq *cq = p;
3183 struct hisi_hba *hisi_hba = cq->hisi_hba;
3184 int queue = cq->id;
3185
3186 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3187
3188 tasklet_schedule(&cq->tasklet);
3189
3190 return IRQ_HANDLED;
3191 }
3192
3193 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3194 {
3195 struct hisi_sas_phy *phy = p;
3196 struct hisi_hba *hisi_hba = phy->hisi_hba;
3197 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3198 struct device *dev = hisi_hba->dev;
3199 struct hisi_sas_initial_fis *initial_fis;
3200 struct dev_to_host_fis *fis;
3201 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3202 irqreturn_t res = IRQ_HANDLED;
3203 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3204 int phy_no, offset;
3205
3206 phy_no = sas_phy->id;
3207 initial_fis = &hisi_hba->initial_fis[phy_no];
3208 fis = &initial_fis->fis;
3209
3210 offset = 4 * (phy_no / 4);
3211 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3212 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3213 ent_msk | 1 << ((phy_no % 4) * 8));
3214
3215 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3216 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3217 (phy_no % 4)));
3218 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3219 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3220 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3221 res = IRQ_NONE;
3222 goto end;
3223 }
3224
3225 /* check ERR bit of Status Register */
3226 if (fis->status & ATA_ERR) {
3227 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3228 fis->status);
3229 disable_phy_v2_hw(hisi_hba, phy_no);
3230 enable_phy_v2_hw(hisi_hba, phy_no);
3231 res = IRQ_NONE;
3232 goto end;
3233 }
3234
3235 if (unlikely(phy_no == 8)) {
3236 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3237
3238 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3239 PORT_STATE_PHY8_PORT_NUM_OFF;
3240 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3241 PORT_STATE_PHY8_CONN_RATE_OFF;
3242 } else {
3243 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3244 port_id = (port_id >> (4 * phy_no)) & 0xf;
3245 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3246 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3247 }
3248
3249 if (port_id == 0xf) {
3250 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3251 res = IRQ_NONE;
3252 goto end;
3253 }
3254
3255 sas_phy->linkrate = link_rate;
3256 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3257 HARD_PHY_LINKRATE);
3258 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3259 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3260
3261 sas_phy->oob_mode = SATA_OOB_MODE;
3262 /* Make up some unique SAS address */
3263 attached_sas_addr[0] = 0x50;
3264 attached_sas_addr[7] = phy_no;
3265 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3266 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3267 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3268 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3269 phy->port_id = port_id;
3270 phy->phy_type |= PORT_TYPE_SATA;
3271 phy->phy_attached = 1;
3272 phy->identify.device_type = SAS_SATA_DEV;
3273 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3274 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3275 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
3276
3277 end:
3278 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3279 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3280
3281 return res;
3282 }
3283
3284 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3285 int_phy_updown_v2_hw,
3286 int_chnl_int_v2_hw,
3287 };
3288
3289 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3290 fatal_ecc_int_v2_hw,
3291 fatal_axi_int_v2_hw
3292 };
3293
3294 /**
3295 * There is a limitation in the hip06 chipset that we need
3296 * to map in all mbigen interrupts, even if they are not used.
3297 */
3298 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3299 {
3300 struct platform_device *pdev = hisi_hba->platform_dev;
3301 struct device *dev = &pdev->dev;
3302 int irq, rc, irq_map[128];
3303 int i, phy_no, fatal_no, queue_no, k;
3304
3305 for (i = 0; i < 128; i++)
3306 irq_map[i] = platform_get_irq(pdev, i);
3307
3308 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3309 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3310 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3311 DRV_NAME " phy", hisi_hba);
3312 if (rc) {
3313 dev_err(dev, "irq init: could not request "
3314 "phy interrupt %d, rc=%d\n",
3315 irq, rc);
3316 rc = -ENOENT;
3317 goto free_phy_int_irqs;
3318 }
3319 }
3320
3321 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3322 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3323
3324 irq = irq_map[phy_no + 72];
3325 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3326 DRV_NAME " sata", phy);
3327 if (rc) {
3328 dev_err(dev, "irq init: could not request "
3329 "sata interrupt %d, rc=%d\n",
3330 irq, rc);
3331 rc = -ENOENT;
3332 goto free_sata_int_irqs;
3333 }
3334 }
3335
3336 for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3337 irq = irq_map[fatal_no + 81];
3338 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3339 DRV_NAME " fatal", hisi_hba);
3340 if (rc) {
3341 dev_err(dev,
3342 "irq init: could not request fatal interrupt %d, rc=%d\n",
3343 irq, rc);
3344 rc = -ENOENT;
3345 goto free_fatal_int_irqs;
3346 }
3347 }
3348
3349 for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3350 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3351 struct tasklet_struct *t = &cq->tasklet;
3352
3353 irq = irq_map[queue_no + 96];
3354 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3355 DRV_NAME " cq", cq);
3356 if (rc) {
3357 dev_err(dev,
3358 "irq init: could not request cq interrupt %d, rc=%d\n",
3359 irq, rc);
3360 rc = -ENOENT;
3361 goto free_cq_int_irqs;
3362 }
3363 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3364 }
3365
3366 return 0;
3367
3368 free_cq_int_irqs:
3369 for (k = 0; k < queue_no; k++) {
3370 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3371
3372 free_irq(irq_map[k + 96], cq);
3373 tasklet_kill(&cq->tasklet);
3374 }
3375 free_fatal_int_irqs:
3376 for (k = 0; k < fatal_no; k++)
3377 free_irq(irq_map[k + 81], hisi_hba);
3378 free_sata_int_irqs:
3379 for (k = 0; k < phy_no; k++) {
3380 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3381
3382 free_irq(irq_map[k + 72], phy);
3383 }
3384 free_phy_int_irqs:
3385 for (k = 0; k < i; k++)
3386 free_irq(irq_map[k + 1], hisi_hba);
3387 return rc;
3388 }
3389
3390 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3391 {
3392 int rc;
3393
3394 memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3395
3396 rc = hw_init_v2_hw(hisi_hba);
3397 if (rc)
3398 return rc;
3399
3400 rc = interrupt_init_v2_hw(hisi_hba);
3401 if (rc)
3402 return rc;
3403
3404 return 0;
3405 }
3406
3407 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3408 {
3409 struct platform_device *pdev = hisi_hba->platform_dev;
3410 int i;
3411
3412 for (i = 0; i < hisi_hba->queue_count; i++)
3413 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3414
3415 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3416 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3417 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3418 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3419
3420 for (i = 0; i < hisi_hba->n_phy; i++) {
3421 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3422 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3423 }
3424
3425 for (i = 0; i < 128; i++)
3426 synchronize_irq(platform_get_irq(pdev, i));
3427 }
3428
3429
3430 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3431 {
3432 return hisi_sas_read32(hisi_hba, PHY_STATE);
3433 }
3434
3435 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3436 {
3437 struct device *dev = hisi_hba->dev;
3438 int rc, cnt;
3439
3440 interrupt_disable_v2_hw(hisi_hba);
3441 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3442 hisi_sas_kill_tasklets(hisi_hba);
3443
3444 hisi_sas_stop_phys(hisi_hba);
3445
3446 mdelay(10);
3447
3448 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3449
3450 /* wait until bus idle */
3451 cnt = 0;
3452 while (1) {
3453 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3454 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3455
3456 if (status == 0x3)
3457 break;
3458
3459 udelay(10);
3460 if (cnt++ > 10) {
3461 dev_err(dev, "wait axi bus state to idle timeout!\n");
3462 return -1;
3463 }
3464 }
3465
3466 hisi_sas_init_mem(hisi_hba);
3467
3468 rc = hw_init_v2_hw(hisi_hba);
3469 if (rc)
3470 return rc;
3471
3472 phys_reject_stp_links_v2_hw(hisi_hba);
3473
3474 return 0;
3475 }
3476
3477 static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3478 u8 reg_index, u8 reg_count, u8 *write_data)
3479 {
3480 struct device *dev = hisi_hba->dev;
3481 int phy_no, count;
3482
3483 if (!hisi_hba->sgpio_regs)
3484 return -EOPNOTSUPP;
3485
3486 switch (reg_type) {
3487 case SAS_GPIO_REG_TX:
3488 count = reg_count * 4;
3489 count = min(count, hisi_hba->n_phy);
3490
3491 for (phy_no = 0; phy_no < count; phy_no++) {
3492 /*
3493 * GPIO_TX[n] register has the highest numbered drive
3494 * of the four in the first byte and the lowest
3495 * numbered drive in the fourth byte.
3496 * See SFF-8485 Rev. 0.7 Table 24.
3497 */
3498 void __iomem *reg_addr = hisi_hba->sgpio_regs +
3499 reg_index * 4 + phy_no;
3500 int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3501
3502 writeb(write_data[data_idx], reg_addr);
3503 }
3504
3505 break;
3506 default:
3507 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3508 reg_type);
3509 return -EINVAL;
3510 }
3511
3512 return 0;
3513 }
3514
3515 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3516 .hw_init = hisi_sas_v2_init,
3517 .setup_itct = setup_itct_v2_hw,
3518 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3519 .alloc_dev = alloc_dev_quirk_v2_hw,
3520 .sl_notify = sl_notify_v2_hw,
3521 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3522 .clear_itct = clear_itct_v2_hw,
3523 .free_device = free_device_v2_hw,
3524 .prep_smp = prep_smp_v2_hw,
3525 .prep_ssp = prep_ssp_v2_hw,
3526 .prep_stp = prep_ata_v2_hw,
3527 .prep_abort = prep_abort_v2_hw,
3528 .get_free_slot = get_free_slot_v2_hw,
3529 .start_delivery = start_delivery_v2_hw,
3530 .slot_complete = slot_complete_v2_hw,
3531 .phys_init = phys_init_v2_hw,
3532 .phy_start = start_phy_v2_hw,
3533 .phy_disable = disable_phy_v2_hw,
3534 .phy_hard_reset = phy_hard_reset_v2_hw,
3535 .get_events = phy_get_events_v2_hw,
3536 .phy_set_linkrate = phy_set_linkrate_v2_hw,
3537 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3538 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3539 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3540 .soft_reset = soft_reset_v2_hw,
3541 .get_phys_state = get_phys_state_v2_hw,
3542 .write_gpio = write_gpio_v2_hw,
3543 };
3544
3545 static int hisi_sas_v2_probe(struct platform_device *pdev)
3546 {
3547 /*
3548 * Check if we should defer the probe before we probe the
3549 * upper layer, as it's hard to defer later on.
3550 */
3551 int ret = platform_get_irq(pdev, 0);
3552
3553 if (ret < 0) {
3554 if (ret != -EPROBE_DEFER)
3555 dev_err(&pdev->dev, "cannot obtain irq\n");
3556 return ret;
3557 }
3558
3559 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3560 }
3561
3562 static int hisi_sas_v2_remove(struct platform_device *pdev)
3563 {
3564 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3565 struct hisi_hba *hisi_hba = sha->lldd_ha;
3566
3567 if (timer_pending(&hisi_hba->timer))
3568 del_timer(&hisi_hba->timer);
3569
3570 hisi_sas_kill_tasklets(hisi_hba);
3571
3572 return hisi_sas_remove(pdev);
3573 }
3574
3575 static const struct of_device_id sas_v2_of_match[] = {
3576 { .compatible = "hisilicon,hip06-sas-v2",},
3577 { .compatible = "hisilicon,hip07-sas-v2",},
3578 {},
3579 };
3580 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3581
3582 static const struct acpi_device_id sas_v2_acpi_match[] = {
3583 { "HISI0162", 0 },
3584 { }
3585 };
3586
3587 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3588
3589 static struct platform_driver hisi_sas_v2_driver = {
3590 .probe = hisi_sas_v2_probe,
3591 .remove = hisi_sas_v2_remove,
3592 .driver = {
3593 .name = DRV_NAME,
3594 .of_match_table = sas_v2_of_match,
3595 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3596 },
3597 };
3598
3599 module_platform_driver(hisi_sas_v2_driver);
3600
3601 MODULE_LICENSE("GPL");
3602 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3603 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3604 MODULE_ALIAS("platform:" DRV_NAME);
Linux with added FPC-III support