2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27 * All rights reserved.
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 #include <linux/circ_buf.h>
56 #include <linux/device.h>
61 #include "probe_roms.h"
62 #include "remote_device.h"
64 #include "scu_completion_codes.h"
65 #include "scu_event_codes.h"
66 #include "registers.h"
67 #include "scu_remote_node_context.h"
68 #include "scu_task_context.h"
70 #define SCU_CONTEXT_RAM_INIT_STALL_TIME 200
72 #define smu_max_ports(dcc_value) \
74 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
75 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
78 #define smu_max_task_contexts(dcc_value) \
80 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
81 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
84 #define smu_max_rncs(dcc_value) \
86 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
87 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
90 #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100
95 * The number of milliseconds to wait while a given phy is consuming power
96 * before allowing another set of phys to consume power. Ultimately, this will
97 * be specified by OEM parameter.
99 #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
102 * NORMALIZE_PUT_POINTER() -
104 * This macro will normalize the completion queue put pointer so its value can
105 * be used as an array inde
107 #define NORMALIZE_PUT_POINTER(x) \
108 ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
112 * NORMALIZE_EVENT_POINTER() -
114 * This macro will normalize the completion queue event entry so its value can
115 * be used as an index.
117 #define NORMALIZE_EVENT_POINTER(x) \
119 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
120 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
124 * NORMALIZE_GET_POINTER() -
126 * This macro will normalize the completion queue get pointer so its value can
127 * be used as an index into an array
129 #define NORMALIZE_GET_POINTER(x) \
130 ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
133 * NORMALIZE_GET_POINTER_CYCLE_BIT() -
135 * This macro will normalize the completion queue cycle pointer so it matches
136 * the completion queue cycle bit
138 #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
139 ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
142 * COMPLETION_QUEUE_CYCLE_BIT() -
144 * This macro will return the cycle bit of the completion queue entry
146 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
148 /* Init the state machine and call the state entry function (if any) */
149 void sci_init_sm(struct sci_base_state_machine
*sm
,
150 const struct sci_base_state
*state_table
, u32 initial_state
)
152 sci_state_transition_t handler
;
154 sm
->initial_state_id
= initial_state
;
155 sm
->previous_state_id
= initial_state
;
156 sm
->current_state_id
= initial_state
;
157 sm
->state_table
= state_table
;
159 handler
= sm
->state_table
[initial_state
].enter_state
;
164 /* Call the state exit fn, update the current state, call the state entry fn */
165 void sci_change_state(struct sci_base_state_machine
*sm
, u32 next_state
)
167 sci_state_transition_t handler
;
169 handler
= sm
->state_table
[sm
->current_state_id
].exit_state
;
173 sm
->previous_state_id
= sm
->current_state_id
;
174 sm
->current_state_id
= next_state
;
176 handler
= sm
->state_table
[sm
->current_state_id
].enter_state
;
181 static bool sci_controller_completion_queue_has_entries(struct isci_host
*ihost
)
183 u32 get_value
= ihost
->completion_queue_get
;
184 u32 get_index
= get_value
& SMU_COMPLETION_QUEUE_GET_POINTER_MASK
;
186 if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value
) ==
187 COMPLETION_QUEUE_CYCLE_BIT(ihost
->completion_queue
[get_index
]))
193 static bool sci_controller_isr(struct isci_host
*ihost
)
195 if (sci_controller_completion_queue_has_entries(ihost
))
198 /* we have a spurious interrupt it could be that we have already
199 * emptied the completion queue from a previous interrupt
202 writel(SMU_ISR_COMPLETION
, &ihost
->smu_registers
->interrupt_status
);
204 /* There is a race in the hardware that could cause us not to be
205 * notified of an interrupt completion if we do not take this
206 * step. We will mask then unmask the interrupts so if there is
207 * another interrupt pending the clearing of the interrupt
208 * source we get the next interrupt message.
210 spin_lock(&ihost
->scic_lock
);
211 if (test_bit(IHOST_IRQ_ENABLED
, &ihost
->flags
)) {
212 writel(0xFF000000, &ihost
->smu_registers
->interrupt_mask
);
213 writel(0, &ihost
->smu_registers
->interrupt_mask
);
215 spin_unlock(&ihost
->scic_lock
);
220 irqreturn_t
isci_msix_isr(int vec
, void *data
)
222 struct isci_host
*ihost
= data
;
224 if (sci_controller_isr(ihost
))
225 tasklet_schedule(&ihost
->completion_tasklet
);
230 static bool sci_controller_error_isr(struct isci_host
*ihost
)
232 u32 interrupt_status
;
235 readl(&ihost
->smu_registers
->interrupt_status
);
236 interrupt_status
&= (SMU_ISR_QUEUE_ERROR
| SMU_ISR_QUEUE_SUSPEND
);
238 if (interrupt_status
!= 0) {
240 * There is an error interrupt pending so let it through and handle
246 * There is a race in the hardware that could cause us not to be notified
247 * of an interrupt completion if we do not take this step. We will mask
248 * then unmask the error interrupts so if there was another interrupt
249 * pending we will be notified.
250 * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
251 writel(0xff, &ihost
->smu_registers
->interrupt_mask
);
252 writel(0, &ihost
->smu_registers
->interrupt_mask
);
257 static void sci_controller_task_completion(struct isci_host
*ihost
, u32 ent
)
259 u32 index
= SCU_GET_COMPLETION_INDEX(ent
);
260 struct isci_request
*ireq
= ihost
->reqs
[index
];
262 /* Make sure that we really want to process this IO request */
263 if (test_bit(IREQ_ACTIVE
, &ireq
->flags
) &&
264 ireq
->io_tag
!= SCI_CONTROLLER_INVALID_IO_TAG
&&
265 ISCI_TAG_SEQ(ireq
->io_tag
) == ihost
->io_request_sequence
[index
])
266 /* Yep this is a valid io request pass it along to the
269 sci_io_request_tc_completion(ireq
, ent
);
272 static void sci_controller_sdma_completion(struct isci_host
*ihost
, u32 ent
)
275 struct isci_request
*ireq
;
276 struct isci_remote_device
*idev
;
278 index
= SCU_GET_COMPLETION_INDEX(ent
);
280 switch (scu_get_command_request_type(ent
)) {
281 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC
:
282 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC
:
283 ireq
= ihost
->reqs
[index
];
284 dev_warn(&ihost
->pdev
->dev
, "%s: %x for io request %p\n",
285 __func__
, ent
, ireq
);
286 /* @todo For a post TC operation we need to fail the IO
290 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC
:
291 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC
:
292 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC
:
293 idev
= ihost
->device_table
[index
];
294 dev_warn(&ihost
->pdev
->dev
, "%s: %x for device %p\n",
295 __func__
, ent
, idev
);
296 /* @todo For a port RNC operation we need to fail the
301 dev_warn(&ihost
->pdev
->dev
, "%s: unknown completion type %x\n",
307 static void sci_controller_unsolicited_frame(struct isci_host
*ihost
, u32 ent
)
312 struct scu_unsolicited_frame_header
*frame_header
;
313 struct isci_phy
*iphy
;
314 struct isci_remote_device
*idev
;
316 enum sci_status result
= SCI_FAILURE
;
318 frame_index
= SCU_GET_FRAME_INDEX(ent
);
320 frame_header
= ihost
->uf_control
.buffers
.array
[frame_index
].header
;
321 ihost
->uf_control
.buffers
.array
[frame_index
].state
= UNSOLICITED_FRAME_IN_USE
;
323 if (SCU_GET_FRAME_ERROR(ent
)) {
325 * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
326 * / this cause a problem? We expect the phy initialization will
327 * / fail if there is an error in the frame. */
328 sci_controller_release_frame(ihost
, frame_index
);
332 if (frame_header
->is_address_frame
) {
333 index
= SCU_GET_PROTOCOL_ENGINE_INDEX(ent
);
334 iphy
= &ihost
->phys
[index
];
335 result
= sci_phy_frame_handler(iphy
, frame_index
);
338 index
= SCU_GET_COMPLETION_INDEX(ent
);
340 if (index
== SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX
) {
342 * This is a signature fis or a frame from a direct attached SATA
343 * device that has not yet been created. In either case forwared
344 * the frame to the PE and let it take care of the frame data. */
345 index
= SCU_GET_PROTOCOL_ENGINE_INDEX(ent
);
346 iphy
= &ihost
->phys
[index
];
347 result
= sci_phy_frame_handler(iphy
, frame_index
);
349 if (index
< ihost
->remote_node_entries
)
350 idev
= ihost
->device_table
[index
];
355 result
= sci_remote_device_frame_handler(idev
, frame_index
);
357 sci_controller_release_frame(ihost
, frame_index
);
361 if (result
!= SCI_SUCCESS
) {
363 * / @todo Is there any reason to report some additional error message
364 * / when we get this failure notifiction? */
368 static void sci_controller_event_completion(struct isci_host
*ihost
, u32 ent
)
370 struct isci_remote_device
*idev
;
371 struct isci_request
*ireq
;
372 struct isci_phy
*iphy
;
375 index
= SCU_GET_COMPLETION_INDEX(ent
);
377 switch (scu_get_event_type(ent
)) {
378 case SCU_EVENT_TYPE_SMU_COMMAND_ERROR
:
379 /* / @todo The driver did something wrong and we need to fix the condtion. */
380 dev_err(&ihost
->pdev
->dev
,
381 "%s: SCIC Controller 0x%p received SMU command error "
388 case SCU_EVENT_TYPE_SMU_PCQ_ERROR
:
389 case SCU_EVENT_TYPE_SMU_ERROR
:
390 case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR
:
392 * / @todo This is a hardware failure and its likely that we want to
393 * / reset the controller. */
394 dev_err(&ihost
->pdev
->dev
,
395 "%s: SCIC Controller 0x%p received fatal controller "
402 case SCU_EVENT_TYPE_TRANSPORT_ERROR
:
403 ireq
= ihost
->reqs
[index
];
404 sci_io_request_event_handler(ireq
, ent
);
407 case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT
:
408 switch (scu_get_event_specifier(ent
)) {
409 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE
:
410 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT
:
411 ireq
= ihost
->reqs
[index
];
413 sci_io_request_event_handler(ireq
, ent
);
415 dev_warn(&ihost
->pdev
->dev
,
416 "%s: SCIC Controller 0x%p received "
417 "event 0x%x for io request object "
418 "that doesnt exist.\n",
425 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT
:
426 idev
= ihost
->device_table
[index
];
428 sci_remote_device_event_handler(idev
, ent
);
430 dev_warn(&ihost
->pdev
->dev
,
431 "%s: SCIC Controller 0x%p received "
432 "event 0x%x for remote device object "
433 "that doesnt exist.\n",
442 case SCU_EVENT_TYPE_BROADCAST_CHANGE
:
444 * direct the broadcast change event to the phy first and then let
445 * the phy redirect the broadcast change to the port object */
446 case SCU_EVENT_TYPE_ERR_CNT_EVENT
:
448 * direct error counter event to the phy object since that is where
449 * we get the event notification. This is a type 4 event. */
450 case SCU_EVENT_TYPE_OSSP_EVENT
:
451 index
= SCU_GET_PROTOCOL_ENGINE_INDEX(ent
);
452 iphy
= &ihost
->phys
[index
];
453 sci_phy_event_handler(iphy
, ent
);
456 case SCU_EVENT_TYPE_RNC_SUSPEND_TX
:
457 case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX
:
458 case SCU_EVENT_TYPE_RNC_OPS_MISC
:
459 if (index
< ihost
->remote_node_entries
) {
460 idev
= ihost
->device_table
[index
];
463 sci_remote_device_event_handler(idev
, ent
);
465 dev_err(&ihost
->pdev
->dev
,
466 "%s: SCIC Controller 0x%p received event 0x%x "
467 "for remote device object 0x%0x that doesnt "
477 dev_warn(&ihost
->pdev
->dev
,
478 "%s: SCIC Controller received unknown event code %x\n",
485 static void sci_controller_process_completions(struct isci_host
*ihost
)
487 u32 completion_count
= 0;
494 dev_dbg(&ihost
->pdev
->dev
,
495 "%s: completion queue beginning get:0x%08x\n",
497 ihost
->completion_queue_get
);
499 /* Get the component parts of the completion queue */
500 get_index
= NORMALIZE_GET_POINTER(ihost
->completion_queue_get
);
501 get_cycle
= SMU_CQGR_CYCLE_BIT
& ihost
->completion_queue_get
;
503 event_get
= NORMALIZE_EVENT_POINTER(ihost
->completion_queue_get
);
504 event_cycle
= SMU_CQGR_EVENT_CYCLE_BIT
& ihost
->completion_queue_get
;
507 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle
)
508 == COMPLETION_QUEUE_CYCLE_BIT(ihost
->completion_queue
[get_index
])
512 ent
= ihost
->completion_queue
[get_index
];
514 /* increment the get pointer and check for rollover to toggle the cycle bit */
515 get_cycle
^= ((get_index
+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES
) <<
516 (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT
- SCU_MAX_COMPLETION_QUEUE_SHIFT
);
517 get_index
= (get_index
+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES
-1);
519 dev_dbg(&ihost
->pdev
->dev
,
520 "%s: completion queue entry:0x%08x\n",
524 switch (SCU_GET_COMPLETION_TYPE(ent
)) {
525 case SCU_COMPLETION_TYPE_TASK
:
526 sci_controller_task_completion(ihost
, ent
);
529 case SCU_COMPLETION_TYPE_SDMA
:
530 sci_controller_sdma_completion(ihost
, ent
);
533 case SCU_COMPLETION_TYPE_UFI
:
534 sci_controller_unsolicited_frame(ihost
, ent
);
537 case SCU_COMPLETION_TYPE_EVENT
:
538 sci_controller_event_completion(ihost
, ent
);
541 case SCU_COMPLETION_TYPE_NOTIFY
: {
542 event_cycle
^= ((event_get
+1) & SCU_MAX_EVENTS
) <<
543 (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT
- SCU_MAX_EVENTS_SHIFT
);
544 event_get
= (event_get
+1) & (SCU_MAX_EVENTS
-1);
546 sci_controller_event_completion(ihost
, ent
);
550 dev_warn(&ihost
->pdev
->dev
,
551 "%s: SCIC Controller received unknown "
552 "completion type %x\n",
559 /* Update the get register if we completed one or more entries */
560 if (completion_count
> 0) {
561 ihost
->completion_queue_get
=
562 SMU_CQGR_GEN_BIT(ENABLE
) |
563 SMU_CQGR_GEN_BIT(EVENT_ENABLE
) |
565 SMU_CQGR_GEN_VAL(EVENT_POINTER
, event_get
) |
567 SMU_CQGR_GEN_VAL(POINTER
, get_index
);
569 writel(ihost
->completion_queue_get
,
570 &ihost
->smu_registers
->completion_queue_get
);
574 dev_dbg(&ihost
->pdev
->dev
,
575 "%s: completion queue ending get:0x%08x\n",
577 ihost
->completion_queue_get
);
581 static void sci_controller_error_handler(struct isci_host
*ihost
)
583 u32 interrupt_status
;
586 readl(&ihost
->smu_registers
->interrupt_status
);
588 if ((interrupt_status
& SMU_ISR_QUEUE_SUSPEND
) &&
589 sci_controller_completion_queue_has_entries(ihost
)) {
591 sci_controller_process_completions(ihost
);
592 writel(SMU_ISR_QUEUE_SUSPEND
, &ihost
->smu_registers
->interrupt_status
);
594 dev_err(&ihost
->pdev
->dev
, "%s: status: %#x\n", __func__
,
597 sci_change_state(&ihost
->sm
, SCIC_FAILED
);
602 /* If we dont process any completions I am not sure that we want to do this.
603 * We are in the middle of a hardware fault and should probably be reset.
605 writel(0, &ihost
->smu_registers
->interrupt_mask
);
608 irqreturn_t
isci_intx_isr(int vec
, void *data
)
610 irqreturn_t ret
= IRQ_NONE
;
611 struct isci_host
*ihost
= data
;
613 if (sci_controller_isr(ihost
)) {
614 writel(SMU_ISR_COMPLETION
, &ihost
->smu_registers
->interrupt_status
);
615 tasklet_schedule(&ihost
->completion_tasklet
);
617 } else if (sci_controller_error_isr(ihost
)) {
618 spin_lock(&ihost
->scic_lock
);
619 sci_controller_error_handler(ihost
);
620 spin_unlock(&ihost
->scic_lock
);
627 irqreturn_t
isci_error_isr(int vec
, void *data
)
629 struct isci_host
*ihost
= data
;
631 if (sci_controller_error_isr(ihost
))
632 sci_controller_error_handler(ihost
);
638 * isci_host_start_complete() - This function is called by the core library,
639 * through the ISCI Module, to indicate controller start status.
640 * @isci_host: This parameter specifies the ISCI host object
641 * @completion_status: This parameter specifies the completion status from the
645 static void isci_host_start_complete(struct isci_host
*ihost
, enum sci_status completion_status
)
647 if (completion_status
!= SCI_SUCCESS
)
648 dev_info(&ihost
->pdev
->dev
,
649 "controller start timed out, continuing...\n");
650 clear_bit(IHOST_START_PENDING
, &ihost
->flags
);
651 wake_up(&ihost
->eventq
);
654 int isci_host_scan_finished(struct Scsi_Host
*shost
, unsigned long time
)
656 struct sas_ha_struct
*ha
= SHOST_TO_SAS_HA(shost
);
657 struct isci_host
*ihost
= ha
->lldd_ha
;
659 if (test_bit(IHOST_START_PENDING
, &ihost
->flags
))
668 * sci_controller_get_suggested_start_timeout() - This method returns the
669 * suggested sci_controller_start() timeout amount. The user is free to
670 * use any timeout value, but this method provides the suggested minimum
671 * start timeout value. The returned value is based upon empirical
672 * information determined as a result of interoperability testing.
673 * @controller: the handle to the controller object for which to return the
674 * suggested start timeout.
676 * This method returns the number of milliseconds for the suggested start
679 static u32
sci_controller_get_suggested_start_timeout(struct isci_host
*ihost
)
681 /* Validate the user supplied parameters. */
686 * The suggested minimum timeout value for a controller start operation:
688 * Signature FIS Timeout
689 * + Phy Start Timeout
690 * + Number of Phy Spin Up Intervals
691 * ---------------------------------
692 * Number of milliseconds for the controller start operation.
694 * NOTE: The number of phy spin up intervals will be equivalent
695 * to the number of phys divided by the number phys allowed
696 * per interval - 1 (once OEM parameters are supported).
697 * Currently we assume only 1 phy per interval. */
699 return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
700 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
701 + ((SCI_MAX_PHYS
- 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL
);
704 static void sci_controller_enable_interrupts(struct isci_host
*ihost
)
706 set_bit(IHOST_IRQ_ENABLED
, &ihost
->flags
);
707 writel(0, &ihost
->smu_registers
->interrupt_mask
);
710 void sci_controller_disable_interrupts(struct isci_host
*ihost
)
712 clear_bit(IHOST_IRQ_ENABLED
, &ihost
->flags
);
713 writel(0xffffffff, &ihost
->smu_registers
->interrupt_mask
);
714 readl(&ihost
->smu_registers
->interrupt_mask
); /* flush */
717 static void sci_controller_enable_port_task_scheduler(struct isci_host
*ihost
)
719 u32 port_task_scheduler_value
;
721 port_task_scheduler_value
=
722 readl(&ihost
->scu_registers
->peg0
.ptsg
.control
);
723 port_task_scheduler_value
|=
724 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE
) |
725 SCU_PTSGCR_GEN_BIT(PTSG_ENABLE
));
726 writel(port_task_scheduler_value
,
727 &ihost
->scu_registers
->peg0
.ptsg
.control
);
730 static void sci_controller_assign_task_entries(struct isci_host
*ihost
)
735 * Assign all the TCs to function 0
736 * TODO: Do we actually need to read this register to write it back?
740 readl(&ihost
->smu_registers
->task_context_assignment
[0]);
742 task_assignment
|= (SMU_TCA_GEN_VAL(STARTING
, 0)) |
743 (SMU_TCA_GEN_VAL(ENDING
, ihost
->task_context_entries
- 1)) |
744 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE
));
746 writel(task_assignment
,
747 &ihost
->smu_registers
->task_context_assignment
[0]);
751 static void sci_controller_initialize_completion_queue(struct isci_host
*ihost
)
754 u32 completion_queue_control_value
;
755 u32 completion_queue_get_value
;
756 u32 completion_queue_put_value
;
758 ihost
->completion_queue_get
= 0;
760 completion_queue_control_value
=
761 (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES
- 1) |
762 SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS
- 1));
764 writel(completion_queue_control_value
,
765 &ihost
->smu_registers
->completion_queue_control
);
768 /* Set the completion queue get pointer and enable the queue */
769 completion_queue_get_value
= (
770 (SMU_CQGR_GEN_VAL(POINTER
, 0))
771 | (SMU_CQGR_GEN_VAL(EVENT_POINTER
, 0))
772 | (SMU_CQGR_GEN_BIT(ENABLE
))
773 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE
))
776 writel(completion_queue_get_value
,
777 &ihost
->smu_registers
->completion_queue_get
);
779 /* Set the completion queue put pointer */
780 completion_queue_put_value
= (
781 (SMU_CQPR_GEN_VAL(POINTER
, 0))
782 | (SMU_CQPR_GEN_VAL(EVENT_POINTER
, 0))
785 writel(completion_queue_put_value
,
786 &ihost
->smu_registers
->completion_queue_put
);
788 /* Initialize the cycle bit of the completion queue entries */
789 for (index
= 0; index
< SCU_MAX_COMPLETION_QUEUE_ENTRIES
; index
++) {
791 * If get.cycle_bit != completion_queue.cycle_bit
792 * its not a valid completion queue entry
793 * so at system start all entries are invalid */
794 ihost
->completion_queue
[index
] = 0x80000000;
798 static void sci_controller_initialize_unsolicited_frame_queue(struct isci_host
*ihost
)
800 u32 frame_queue_control_value
;
801 u32 frame_queue_get_value
;
802 u32 frame_queue_put_value
;
804 /* Write the queue size */
805 frame_queue_control_value
=
806 SCU_UFQC_GEN_VAL(QUEUE_SIZE
, SCU_MAX_UNSOLICITED_FRAMES
);
808 writel(frame_queue_control_value
,
809 &ihost
->scu_registers
->sdma
.unsolicited_frame_queue_control
);
811 /* Setup the get pointer for the unsolicited frame queue */
812 frame_queue_get_value
= (
813 SCU_UFQGP_GEN_VAL(POINTER
, 0)
814 | SCU_UFQGP_GEN_BIT(ENABLE_BIT
)
817 writel(frame_queue_get_value
,
818 &ihost
->scu_registers
->sdma
.unsolicited_frame_get_pointer
);
819 /* Setup the put pointer for the unsolicited frame queue */
820 frame_queue_put_value
= SCU_UFQPP_GEN_VAL(POINTER
, 0);
821 writel(frame_queue_put_value
,
822 &ihost
->scu_registers
->sdma
.unsolicited_frame_put_pointer
);
825 void sci_controller_transition_to_ready(struct isci_host
*ihost
, enum sci_status status
)
827 if (ihost
->sm
.current_state_id
== SCIC_STARTING
) {
829 * We move into the ready state, because some of the phys/ports
830 * may be up and operational.
832 sci_change_state(&ihost
->sm
, SCIC_READY
);
834 isci_host_start_complete(ihost
, status
);
838 static bool is_phy_starting(struct isci_phy
*iphy
)
840 enum sci_phy_states state
;
842 state
= iphy
->sm
.current_state_id
;
844 case SCI_PHY_STARTING
:
845 case SCI_PHY_SUB_INITIAL
:
846 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN
:
847 case SCI_PHY_SUB_AWAIT_IAF_UF
:
848 case SCI_PHY_SUB_AWAIT_SAS_POWER
:
849 case SCI_PHY_SUB_AWAIT_SATA_POWER
:
850 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN
:
851 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN
:
852 case SCI_PHY_SUB_AWAIT_OSSP_EN
:
853 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF
:
854 case SCI_PHY_SUB_FINAL
:
861 bool is_controller_start_complete(struct isci_host
*ihost
)
865 for (i
= 0; i
< SCI_MAX_PHYS
; i
++) {
866 struct isci_phy
*iphy
= &ihost
->phys
[i
];
867 u32 state
= iphy
->sm
.current_state_id
;
869 /* in apc mode we need to check every phy, in
870 * mpc mode we only need to check phys that have
871 * been configured into a port
873 if (is_port_config_apc(ihost
))
875 else if (!phy_get_non_dummy_port(iphy
))
878 /* The controller start operation is complete iff:
879 * - all links have been given an opportunity to start
880 * - have no indication of a connected device
881 * - have an indication of a connected device and it has
882 * finished the link training process.
884 if ((iphy
->is_in_link_training
== false && state
== SCI_PHY_INITIAL
) ||
885 (iphy
->is_in_link_training
== false && state
== SCI_PHY_STOPPED
) ||
886 (iphy
->is_in_link_training
== true && is_phy_starting(iphy
)) ||
887 (ihost
->port_agent
.phy_ready_mask
!= ihost
->port_agent
.phy_configured_mask
))
895 * sci_controller_start_next_phy - start phy
898 * If all the phys have been started, then attempt to transition the
899 * controller to the READY state and inform the user
900 * (sci_cb_controller_start_complete()).
902 static enum sci_status
sci_controller_start_next_phy(struct isci_host
*ihost
)
904 struct sci_oem_params
*oem
= &ihost
->oem_parameters
;
905 struct isci_phy
*iphy
;
906 enum sci_status status
;
908 status
= SCI_SUCCESS
;
910 if (ihost
->phy_startup_timer_pending
)
913 if (ihost
->next_phy_to_start
>= SCI_MAX_PHYS
) {
914 if (is_controller_start_complete(ihost
)) {
915 sci_controller_transition_to_ready(ihost
, SCI_SUCCESS
);
916 sci_del_timer(&ihost
->phy_timer
);
917 ihost
->phy_startup_timer_pending
= false;
920 iphy
= &ihost
->phys
[ihost
->next_phy_to_start
];
922 if (oem
->controller
.mode_type
== SCIC_PORT_MANUAL_CONFIGURATION_MODE
) {
923 if (phy_get_non_dummy_port(iphy
) == NULL
) {
924 ihost
->next_phy_to_start
++;
926 /* Caution recursion ahead be forwarned
928 * The PHY was never added to a PORT in MPC mode
929 * so start the next phy in sequence This phy
930 * will never go link up and will not draw power
931 * the OEM parameters either configured the phy
932 * incorrectly for the PORT or it was never
935 return sci_controller_start_next_phy(ihost
);
939 status
= sci_phy_start(iphy
);
941 if (status
== SCI_SUCCESS
) {
942 sci_mod_timer(&ihost
->phy_timer
,
943 SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
);
944 ihost
->phy_startup_timer_pending
= true;
946 dev_warn(&ihost
->pdev
->dev
,
947 "%s: Controller stop operation failed "
948 "to stop phy %d because of status "
951 ihost
->phys
[ihost
->next_phy_to_start
].phy_index
,
955 ihost
->next_phy_to_start
++;
961 static void phy_startup_timeout(struct timer_list
*t
)
963 struct sci_timer
*tmr
= from_timer(tmr
, t
, timer
);
964 struct isci_host
*ihost
= container_of(tmr
, typeof(*ihost
), phy_timer
);
966 enum sci_status status
;
968 spin_lock_irqsave(&ihost
->scic_lock
, flags
);
973 ihost
->phy_startup_timer_pending
= false;
976 status
= sci_controller_start_next_phy(ihost
);
977 } while (status
!= SCI_SUCCESS
);
980 spin_unlock_irqrestore(&ihost
->scic_lock
, flags
);
983 static u16
isci_tci_active(struct isci_host
*ihost
)
985 return CIRC_CNT(ihost
->tci_head
, ihost
->tci_tail
, SCI_MAX_IO_REQUESTS
);
988 static enum sci_status
sci_controller_start(struct isci_host
*ihost
,
991 enum sci_status result
;
994 if (ihost
->sm
.current_state_id
!= SCIC_INITIALIZED
) {
995 dev_warn(&ihost
->pdev
->dev
, "%s invalid state: %d\n",
996 __func__
, ihost
->sm
.current_state_id
);
997 return SCI_FAILURE_INVALID_STATE
;
1000 /* Build the TCi free pool */
1001 BUILD_BUG_ON(SCI_MAX_IO_REQUESTS
> 1 << sizeof(ihost
->tci_pool
[0]) * 8);
1002 ihost
->tci_head
= 0;
1003 ihost
->tci_tail
= 0;
1004 for (index
= 0; index
< ihost
->task_context_entries
; index
++)
1005 isci_tci_free(ihost
, index
);
1007 /* Build the RNi free pool */
1008 sci_remote_node_table_initialize(&ihost
->available_remote_nodes
,
1009 ihost
->remote_node_entries
);
1012 * Before anything else lets make sure we will not be
1013 * interrupted by the hardware.
1015 sci_controller_disable_interrupts(ihost
);
1017 /* Enable the port task scheduler */
1018 sci_controller_enable_port_task_scheduler(ihost
);
1020 /* Assign all the task entries to ihost physical function */
1021 sci_controller_assign_task_entries(ihost
);
1023 /* Now initialize the completion queue */
1024 sci_controller_initialize_completion_queue(ihost
);
1026 /* Initialize the unsolicited frame queue for use */
1027 sci_controller_initialize_unsolicited_frame_queue(ihost
);
1029 /* Start all of the ports on this controller */
1030 for (index
= 0; index
< ihost
->logical_port_entries
; index
++) {
1031 struct isci_port
*iport
= &ihost
->ports
[index
];
1033 result
= sci_port_start(iport
);
1038 sci_controller_start_next_phy(ihost
);
1040 sci_mod_timer(&ihost
->timer
, timeout
);
1042 sci_change_state(&ihost
->sm
, SCIC_STARTING
);
1047 void isci_host_start(struct Scsi_Host
*shost
)
1049 struct isci_host
*ihost
= SHOST_TO_SAS_HA(shost
)->lldd_ha
;
1050 unsigned long tmo
= sci_controller_get_suggested_start_timeout(ihost
);
1052 set_bit(IHOST_START_PENDING
, &ihost
->flags
);
1054 spin_lock_irq(&ihost
->scic_lock
);
1055 sci_controller_start(ihost
, tmo
);
1056 sci_controller_enable_interrupts(ihost
);
1057 spin_unlock_irq(&ihost
->scic_lock
);
1060 static void isci_host_stop_complete(struct isci_host
*ihost
)
1062 sci_controller_disable_interrupts(ihost
);
1063 clear_bit(IHOST_STOP_PENDING
, &ihost
->flags
);
1064 wake_up(&ihost
->eventq
);
1067 static void sci_controller_completion_handler(struct isci_host
*ihost
)
1069 /* Empty out the completion queue */
1070 if (sci_controller_completion_queue_has_entries(ihost
))
1071 sci_controller_process_completions(ihost
);
1073 /* Clear the interrupt and enable all interrupts again */
1074 writel(SMU_ISR_COMPLETION
, &ihost
->smu_registers
->interrupt_status
);
1075 /* Could we write the value of SMU_ISR_COMPLETION? */
1076 writel(0xFF000000, &ihost
->smu_registers
->interrupt_mask
);
1077 writel(0, &ihost
->smu_registers
->interrupt_mask
);
1080 void ireq_done(struct isci_host
*ihost
, struct isci_request
*ireq
, struct sas_task
*task
)
1082 if (!test_bit(IREQ_ABORT_PATH_ACTIVE
, &ireq
->flags
) &&
1083 !(task
->task_state_flags
& SAS_TASK_STATE_ABORTED
)) {
1084 if (test_bit(IREQ_COMPLETE_IN_TARGET
, &ireq
->flags
)) {
1085 /* Normal notification (task_done) */
1086 dev_dbg(&ihost
->pdev
->dev
,
1087 "%s: Normal - ireq/task = %p/%p\n",
1088 __func__
, ireq
, task
);
1089 task
->lldd_task
= NULL
;
1090 task
->task_done(task
);
1092 dev_dbg(&ihost
->pdev
->dev
,
1093 "%s: Error - ireq/task = %p/%p\n",
1094 __func__
, ireq
, task
);
1095 if (sas_protocol_ata(task
->task_proto
))
1096 task
->lldd_task
= NULL
;
1097 sas_task_abort(task
);
1100 task
->lldd_task
= NULL
;
1102 if (test_and_clear_bit(IREQ_ABORT_PATH_ACTIVE
, &ireq
->flags
))
1103 wake_up_all(&ihost
->eventq
);
1105 if (!test_bit(IREQ_NO_AUTO_FREE_TAG
, &ireq
->flags
))
1106 isci_free_tag(ihost
, ireq
->io_tag
);
1109 * isci_host_completion_routine() - This function is the delayed service
1110 * routine that calls the sci core library's completion handler. It's
1111 * scheduled as a tasklet from the interrupt service routine when interrupts
1112 * in use, or set as the timeout function in polled mode.
1113 * @data: This parameter specifies the ISCI host object
1116 void isci_host_completion_routine(unsigned long data
)
1118 struct isci_host
*ihost
= (struct isci_host
*)data
;
1121 spin_lock_irq(&ihost
->scic_lock
);
1122 sci_controller_completion_handler(ihost
);
1123 spin_unlock_irq(&ihost
->scic_lock
);
1126 * we subtract SCI_MAX_PORTS to account for the number of dummy TCs
1127 * issued for hardware issue workaround
1129 active
= isci_tci_active(ihost
) - SCI_MAX_PORTS
;
1132 * the coalesence timeout doubles at each encoding step, so
1133 * update it based on the ilog2 value of the outstanding requests
1135 writel(SMU_ICC_GEN_VAL(NUMBER
, active
) |
1136 SMU_ICC_GEN_VAL(TIMER
, ISCI_COALESCE_BASE
+ ilog2(active
)),
1137 &ihost
->smu_registers
->interrupt_coalesce_control
);
1141 * sci_controller_stop() - This method will stop an individual controller
1142 * object.This method will invoke the associated user callback upon
1143 * completion. The completion callback is called when the following
1144 * conditions are met: -# the method return status is SCI_SUCCESS. -# the
1145 * controller has been quiesced. This method will ensure that all IO
1146 * requests are quiesced, phys are stopped, and all additional operation by
1147 * the hardware is halted.
1148 * @controller: the handle to the controller object to stop.
1149 * @timeout: This parameter specifies the number of milliseconds in which the
1150 * stop operation should complete.
1152 * The controller must be in the STARTED or STOPPED state. Indicate if the
1153 * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
1154 * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
1155 * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
1156 * controller is not either in the STARTED or STOPPED states.
1158 static enum sci_status
sci_controller_stop(struct isci_host
*ihost
, u32 timeout
)
1160 if (ihost
->sm
.current_state_id
!= SCIC_READY
) {
1161 dev_warn(&ihost
->pdev
->dev
, "%s invalid state: %d\n",
1162 __func__
, ihost
->sm
.current_state_id
);
1163 return SCI_FAILURE_INVALID_STATE
;
1166 sci_mod_timer(&ihost
->timer
, timeout
);
1167 sci_change_state(&ihost
->sm
, SCIC_STOPPING
);
1172 * sci_controller_reset() - This method will reset the supplied core
1173 * controller regardless of the state of said controller. This operation is
1174 * considered destructive. In other words, all current operations are wiped
1175 * out. No IO completions for outstanding devices occur. Outstanding IO
1176 * requests are not aborted or completed at the actual remote device.
1177 * @controller: the handle to the controller object to reset.
1179 * Indicate if the controller reset method succeeded or failed in some way.
1180 * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
1181 * the controller reset operation is unable to complete.
1183 static enum sci_status
sci_controller_reset(struct isci_host
*ihost
)
1185 switch (ihost
->sm
.current_state_id
) {
1191 * The reset operation is not a graceful cleanup, just
1192 * perform the state transition.
1194 sci_change_state(&ihost
->sm
, SCIC_RESETTING
);
1197 dev_warn(&ihost
->pdev
->dev
, "%s invalid state: %d\n",
1198 __func__
, ihost
->sm
.current_state_id
);
1199 return SCI_FAILURE_INVALID_STATE
;
1203 static enum sci_status
sci_controller_stop_phys(struct isci_host
*ihost
)
1206 enum sci_status status
;
1207 enum sci_status phy_status
;
1209 status
= SCI_SUCCESS
;
1211 for (index
= 0; index
< SCI_MAX_PHYS
; index
++) {
1212 phy_status
= sci_phy_stop(&ihost
->phys
[index
]);
1214 if (phy_status
!= SCI_SUCCESS
&&
1215 phy_status
!= SCI_FAILURE_INVALID_STATE
) {
1216 status
= SCI_FAILURE
;
1218 dev_warn(&ihost
->pdev
->dev
,
1219 "%s: Controller stop operation failed to stop "
1220 "phy %d because of status %d.\n",
1222 ihost
->phys
[index
].phy_index
, phy_status
);
1231 * isci_host_deinit - shutdown frame reception and dma
1232 * @ihost: host to take down
1234 * This is called in either the driver shutdown or the suspend path. In
1235 * the shutdown case libsas went through port teardown and normal device
1236 * removal (i.e. physical links stayed up to service scsi_device removal
1237 * commands). In the suspend case we disable the hardware without
1238 * notifying libsas of the link down events since we want libsas to
1239 * remember the domain across the suspend/resume cycle
1241 void isci_host_deinit(struct isci_host
*ihost
)
1245 /* disable output data selects */
1246 for (i
= 0; i
< isci_gpio_count(ihost
); i
++)
1247 writel(SGPIO_HW_CONTROL
, &ihost
->scu_registers
->peg0
.sgpio
.output_data_select
[i
]);
1249 set_bit(IHOST_STOP_PENDING
, &ihost
->flags
);
1251 spin_lock_irq(&ihost
->scic_lock
);
1252 sci_controller_stop(ihost
, SCIC_CONTROLLER_STOP_TIMEOUT
);
1253 spin_unlock_irq(&ihost
->scic_lock
);
1255 wait_for_stop(ihost
);
1257 /* phy stop is after controller stop to allow port and device to
1258 * go idle before shutting down the phys, but the expectation is
1259 * that i/o has been shut off well before we reach this
1262 sci_controller_stop_phys(ihost
);
1264 /* disable sgpio: where the above wait should give time for the
1265 * enclosure to sample the gpios going inactive
1267 writel(0, &ihost
->scu_registers
->peg0
.sgpio
.interface_control
);
1269 spin_lock_irq(&ihost
->scic_lock
);
1270 sci_controller_reset(ihost
);
1271 spin_unlock_irq(&ihost
->scic_lock
);
1273 /* Cancel any/all outstanding port timers */
1274 for (i
= 0; i
< ihost
->logical_port_entries
; i
++) {
1275 struct isci_port
*iport
= &ihost
->ports
[i
];
1276 del_timer_sync(&iport
->timer
.timer
);
1279 /* Cancel any/all outstanding phy timers */
1280 for (i
= 0; i
< SCI_MAX_PHYS
; i
++) {
1281 struct isci_phy
*iphy
= &ihost
->phys
[i
];
1282 del_timer_sync(&iphy
->sata_timer
.timer
);
1285 del_timer_sync(&ihost
->port_agent
.timer
.timer
);
1287 del_timer_sync(&ihost
->power_control
.timer
.timer
);
1289 del_timer_sync(&ihost
->timer
.timer
);
1291 del_timer_sync(&ihost
->phy_timer
.timer
);
1294 static void __iomem
*scu_base(struct isci_host
*isci_host
)
1296 struct pci_dev
*pdev
= isci_host
->pdev
;
1297 int id
= isci_host
->id
;
1299 return pcim_iomap_table(pdev
)[SCI_SCU_BAR
* 2] + SCI_SCU_BAR_SIZE
* id
;
1302 static void __iomem
*smu_base(struct isci_host
*isci_host
)
1304 struct pci_dev
*pdev
= isci_host
->pdev
;
1305 int id
= isci_host
->id
;
1307 return pcim_iomap_table(pdev
)[SCI_SMU_BAR
* 2] + SCI_SMU_BAR_SIZE
* id
;
1310 static void sci_controller_initial_state_enter(struct sci_base_state_machine
*sm
)
1312 struct isci_host
*ihost
= container_of(sm
, typeof(*ihost
), sm
);
1314 sci_change_state(&ihost
->sm
, SCIC_RESET
);
1317 static inline void sci_controller_starting_state_exit(struct sci_base_state_machine
*sm
)
1319 struct isci_host
*ihost
= container_of(sm
, typeof(*ihost
), sm
);
1321 sci_del_timer(&ihost
->timer
);
1324 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
1325 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
1326 #define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000
1327 #define INTERRUPT_COALESCE_NUMBER_MAX 256
1328 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7
1329 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28
1332 * sci_controller_set_interrupt_coalescence() - This method allows the user to
1333 * configure the interrupt coalescence.
1334 * @controller: This parameter represents the handle to the controller object
1335 * for which its interrupt coalesce register is overridden.
1336 * @coalesce_number: Used to control the number of entries in the Completion
1337 * Queue before an interrupt is generated. If the number of entries exceed
1338 * this number, an interrupt will be generated. The valid range of the input
1339 * is [0, 256]. A setting of 0 results in coalescing being disabled.
1340 * @coalesce_timeout: Timeout value in microseconds. The valid range of the
1341 * input is [0, 2700000] . A setting of 0 is allowed and results in no
1342 * interrupt coalescing timeout.
1344 * Indicate if the user successfully set the interrupt coalesce parameters.
1345 * SCI_SUCCESS The user successfully updated the interrutp coalescence.
1346 * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
1348 static enum sci_status
1349 sci_controller_set_interrupt_coalescence(struct isci_host
*ihost
,
1350 u32 coalesce_number
,
1351 u32 coalesce_timeout
)
1353 u8 timeout_encode
= 0;
1357 /* Check if the input parameters fall in the range. */
1358 if (coalesce_number
> INTERRUPT_COALESCE_NUMBER_MAX
)
1359 return SCI_FAILURE_INVALID_PARAMETER_VALUE
;
1362 * Defined encoding for interrupt coalescing timeout:
1363 * Value Min Max Units
1364 * ----- --- --- -----
1394 * Others Undefined */
1397 * Use the table above to decide the encode of interrupt coalescing timeout
1398 * value for register writing. */
1399 if (coalesce_timeout
== 0)
1402 /* make the timeout value in unit of (10 ns). */
1403 coalesce_timeout
= coalesce_timeout
* 100;
1404 min
= INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS
/ 10;
1405 max
= INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS
/ 10;
1407 /* get the encode of timeout for register writing. */
1408 for (timeout_encode
= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN
;
1409 timeout_encode
<= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX
;
1411 if (min
<= coalesce_timeout
&& max
> coalesce_timeout
)
1413 else if (coalesce_timeout
>= max
&& coalesce_timeout
< min
* 2
1414 && coalesce_timeout
<= INTERRUPT_COALESCE_TIMEOUT_MAX_US
* 100) {
1415 if ((coalesce_timeout
- max
) < (2 * min
- coalesce_timeout
))
1427 if (timeout_encode
== INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX
+ 1)
1428 /* the value is out of range. */
1429 return SCI_FAILURE_INVALID_PARAMETER_VALUE
;
1432 writel(SMU_ICC_GEN_VAL(NUMBER
, coalesce_number
) |
1433 SMU_ICC_GEN_VAL(TIMER
, timeout_encode
),
1434 &ihost
->smu_registers
->interrupt_coalesce_control
);
1437 ihost
->interrupt_coalesce_number
= (u16
)coalesce_number
;
1438 ihost
->interrupt_coalesce_timeout
= coalesce_timeout
/ 100;
1444 static void sci_controller_ready_state_enter(struct sci_base_state_machine
*sm
)
1446 struct isci_host
*ihost
= container_of(sm
, typeof(*ihost
), sm
);
1449 /* enable clock gating for power control of the scu unit */
1450 val
= readl(&ihost
->smu_registers
->clock_gating_control
);
1451 val
&= ~(SMU_CGUCR_GEN_BIT(REGCLK_ENABLE
) |
1452 SMU_CGUCR_GEN_BIT(TXCLK_ENABLE
) |
1453 SMU_CGUCR_GEN_BIT(XCLK_ENABLE
));
1454 val
|= SMU_CGUCR_GEN_BIT(IDLE_ENABLE
);
1455 writel(val
, &ihost
->smu_registers
->clock_gating_control
);
1457 /* set the default interrupt coalescence number and timeout value. */
1458 sci_controller_set_interrupt_coalescence(ihost
, 0, 0);
1461 static void sci_controller_ready_state_exit(struct sci_base_state_machine
*sm
)
1463 struct isci_host
*ihost
= container_of(sm
, typeof(*ihost
), sm
);
1465 /* disable interrupt coalescence. */
1466 sci_controller_set_interrupt_coalescence(ihost
, 0, 0);
1469 static enum sci_status
sci_controller_stop_ports(struct isci_host
*ihost
)
1472 enum sci_status port_status
;
1473 enum sci_status status
= SCI_SUCCESS
;
1475 for (index
= 0; index
< ihost
->logical_port_entries
; index
++) {
1476 struct isci_port
*iport
= &ihost
->ports
[index
];
1478 port_status
= sci_port_stop(iport
);
1480 if ((port_status
!= SCI_SUCCESS
) &&
1481 (port_status
!= SCI_FAILURE_INVALID_STATE
)) {
1482 status
= SCI_FAILURE
;
1484 dev_warn(&ihost
->pdev
->dev
,
1485 "%s: Controller stop operation failed to "
1486 "stop port %d because of status %d.\n",
1488 iport
->logical_port_index
,
1496 static enum sci_status
sci_controller_stop_devices(struct isci_host
*ihost
)
1499 enum sci_status status
;
1500 enum sci_status device_status
;
1502 status
= SCI_SUCCESS
;
1504 for (index
= 0; index
< ihost
->remote_node_entries
; index
++) {
1505 if (ihost
->device_table
[index
] != NULL
) {
1506 /* / @todo What timeout value do we want to provide to this request? */
1507 device_status
= sci_remote_device_stop(ihost
->device_table
[index
], 0);
1509 if ((device_status
!= SCI_SUCCESS
) &&
1510 (device_status
!= SCI_FAILURE_INVALID_STATE
)) {
1511 dev_warn(&ihost
->pdev
->dev
,
1512 "%s: Controller stop operation failed "
1513 "to stop device 0x%p because of "
1516 ihost
->device_table
[index
], device_status
);
1524 static void sci_controller_stopping_state_enter(struct sci_base_state_machine
*sm
)
1526 struct isci_host
*ihost
= container_of(sm
, typeof(*ihost
), sm
);
1528 sci_controller_stop_devices(ihost
);
1529 sci_controller_stop_ports(ihost
);
1531 if (!sci_controller_has_remote_devices_stopping(ihost
))
1532 isci_host_stop_complete(ihost
);
1535 static void sci_controller_stopping_state_exit(struct sci_base_state_machine
*sm
)
1537 struct isci_host
*ihost
= container_of(sm
, typeof(*ihost
), sm
);
1539 sci_del_timer(&ihost
->timer
);
1542 static void sci_controller_reset_hardware(struct isci_host
*ihost
)
1544 /* Disable interrupts so we dont take any spurious interrupts */
1545 sci_controller_disable_interrupts(ihost
);
1548 writel(0xFFFFFFFF, &ihost
->smu_registers
->soft_reset_control
);
1550 /* Delay for 1ms to before clearing the CQP and UFQPR. */
1553 /* The write to the CQGR clears the CQP */
1554 writel(0x00000000, &ihost
->smu_registers
->completion_queue_get
);
1556 /* The write to the UFQGP clears the UFQPR */
1557 writel(0, &ihost
->scu_registers
->sdma
.unsolicited_frame_get_pointer
);
1559 /* clear all interrupts */
1560 writel(~SMU_INTERRUPT_STATUS_RESERVED_MASK
, &ihost
->smu_registers
->interrupt_status
);
1563 static void sci_controller_resetting_state_enter(struct sci_base_state_machine
*sm
)
1565 struct isci_host
*ihost
= container_of(sm
, typeof(*ihost
), sm
);
1567 sci_controller_reset_hardware(ihost
);
1568 sci_change_state(&ihost
->sm
, SCIC_RESET
);
1571 static const struct sci_base_state sci_controller_state_table
[] = {
1573 .enter_state
= sci_controller_initial_state_enter
,
1576 [SCIC_INITIALIZING
] = {},
1577 [SCIC_INITIALIZED
] = {},
1579 .exit_state
= sci_controller_starting_state_exit
,
1582 .enter_state
= sci_controller_ready_state_enter
,
1583 .exit_state
= sci_controller_ready_state_exit
,
1585 [SCIC_RESETTING
] = {
1586 .enter_state
= sci_controller_resetting_state_enter
,
1589 .enter_state
= sci_controller_stopping_state_enter
,
1590 .exit_state
= sci_controller_stopping_state_exit
,
1595 static void controller_timeout(struct timer_list
*t
)
1597 struct sci_timer
*tmr
= from_timer(tmr
, t
, timer
);
1598 struct isci_host
*ihost
= container_of(tmr
, typeof(*ihost
), timer
);
1599 struct sci_base_state_machine
*sm
= &ihost
->sm
;
1600 unsigned long flags
;
1602 spin_lock_irqsave(&ihost
->scic_lock
, flags
);
1607 if (sm
->current_state_id
== SCIC_STARTING
)
1608 sci_controller_transition_to_ready(ihost
, SCI_FAILURE_TIMEOUT
);
1609 else if (sm
->current_state_id
== SCIC_STOPPING
) {
1610 sci_change_state(sm
, SCIC_FAILED
);
1611 isci_host_stop_complete(ihost
);
1612 } else /* / @todo Now what do we want to do in this case? */
1613 dev_err(&ihost
->pdev
->dev
,
1614 "%s: Controller timer fired when controller was not "
1615 "in a state being timed.\n",
1619 spin_unlock_irqrestore(&ihost
->scic_lock
, flags
);
1622 static enum sci_status
sci_controller_construct(struct isci_host
*ihost
,
1623 void __iomem
*scu_base
,
1624 void __iomem
*smu_base
)
1628 sci_init_sm(&ihost
->sm
, sci_controller_state_table
, SCIC_INITIAL
);
1630 ihost
->scu_registers
= scu_base
;
1631 ihost
->smu_registers
= smu_base
;
1633 sci_port_configuration_agent_construct(&ihost
->port_agent
);
1635 /* Construct the ports for this controller */
1636 for (i
= 0; i
< SCI_MAX_PORTS
; i
++)
1637 sci_port_construct(&ihost
->ports
[i
], i
, ihost
);
1638 sci_port_construct(&ihost
->ports
[i
], SCIC_SDS_DUMMY_PORT
, ihost
);
1640 /* Construct the phys for this controller */
1641 for (i
= 0; i
< SCI_MAX_PHYS
; i
++) {
1642 /* Add all the PHYs to the dummy port */
1643 sci_phy_construct(&ihost
->phys
[i
],
1644 &ihost
->ports
[SCI_MAX_PORTS
], i
);
1647 ihost
->invalid_phy_mask
= 0;
1649 sci_init_timer(&ihost
->timer
, controller_timeout
);
1651 return sci_controller_reset(ihost
);
1654 int sci_oem_parameters_validate(struct sci_oem_params
*oem
, u8 version
)
1658 for (i
= 0; i
< SCI_MAX_PORTS
; i
++)
1659 if (oem
->ports
[i
].phy_mask
> SCIC_SDS_PARM_PHY_MASK_MAX
)
1662 for (i
= 0; i
< SCI_MAX_PHYS
; i
++)
1663 if (oem
->phys
[i
].sas_address
.high
== 0 &&
1664 oem
->phys
[i
].sas_address
.low
== 0)
1667 if (oem
->controller
.mode_type
== SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE
) {
1668 for (i
= 0; i
< SCI_MAX_PHYS
; i
++)
1669 if (oem
->ports
[i
].phy_mask
!= 0)
1671 } else if (oem
->controller
.mode_type
== SCIC_PORT_MANUAL_CONFIGURATION_MODE
) {
1674 for (i
= 0; i
< SCI_MAX_PHYS
; i
++)
1675 phy_mask
|= oem
->ports
[i
].phy_mask
;
1682 if (oem
->controller
.max_concurr_spin_up
> MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT
||
1683 oem
->controller
.max_concurr_spin_up
< 1)
1686 if (oem
->controller
.do_enable_ssc
) {
1687 if (version
< ISCI_ROM_VER_1_1
&& oem
->controller
.do_enable_ssc
!= 1)
1690 if (version
>= ISCI_ROM_VER_1_1
) {
1691 u8 test
= oem
->controller
.ssc_sata_tx_spread_level
;
1704 test
= oem
->controller
.ssc_sas_tx_spread_level
;
1705 if (oem
->controller
.ssc_sas_tx_type
== 0) {
1714 } else if (oem
->controller
.ssc_sas_tx_type
== 1) {
1730 static u8
max_spin_up(struct isci_host
*ihost
)
1732 if (ihost
->user_parameters
.max_concurr_spinup
)
1733 return min_t(u8
, ihost
->user_parameters
.max_concurr_spinup
,
1734 MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT
);
1736 return min_t(u8
, ihost
->oem_parameters
.controller
.max_concurr_spin_up
,
1737 MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT
);
1740 static void power_control_timeout(struct timer_list
*t
)
1742 struct sci_timer
*tmr
= from_timer(tmr
, t
, timer
);
1743 struct isci_host
*ihost
= container_of(tmr
, typeof(*ihost
), power_control
.timer
);
1744 struct isci_phy
*iphy
;
1745 unsigned long flags
;
1748 spin_lock_irqsave(&ihost
->scic_lock
, flags
);
1753 ihost
->power_control
.phys_granted_power
= 0;
1755 if (ihost
->power_control
.phys_waiting
== 0) {
1756 ihost
->power_control
.timer_started
= false;
1760 for (i
= 0; i
< SCI_MAX_PHYS
; i
++) {
1762 if (ihost
->power_control
.phys_waiting
== 0)
1765 iphy
= ihost
->power_control
.requesters
[i
];
1769 if (ihost
->power_control
.phys_granted_power
>= max_spin_up(ihost
))
1772 ihost
->power_control
.requesters
[i
] = NULL
;
1773 ihost
->power_control
.phys_waiting
--;
1774 ihost
->power_control
.phys_granted_power
++;
1775 sci_phy_consume_power_handler(iphy
);
1777 if (iphy
->protocol
== SAS_PROTOCOL_SSP
) {
1780 for (j
= 0; j
< SCI_MAX_PHYS
; j
++) {
1781 struct isci_phy
*requester
= ihost
->power_control
.requesters
[j
];
1784 * Search the power_control queue to see if there are other phys
1785 * attached to the same remote device. If found, take all of
1786 * them out of await_sas_power state.
1788 if (requester
!= NULL
&& requester
!= iphy
) {
1789 u8 other
= memcmp(requester
->frame_rcvd
.iaf
.sas_addr
,
1790 iphy
->frame_rcvd
.iaf
.sas_addr
,
1791 sizeof(requester
->frame_rcvd
.iaf
.sas_addr
));
1794 ihost
->power_control
.requesters
[j
] = NULL
;
1795 ihost
->power_control
.phys_waiting
--;
1796 sci_phy_consume_power_handler(requester
);
1804 * It doesn't matter if the power list is empty, we need to start the
1805 * timer in case another phy becomes ready.
1807 sci_mod_timer(tmr
, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL
);
1808 ihost
->power_control
.timer_started
= true;
1811 spin_unlock_irqrestore(&ihost
->scic_lock
, flags
);
1814 void sci_controller_power_control_queue_insert(struct isci_host
*ihost
,
1815 struct isci_phy
*iphy
)
1817 BUG_ON(iphy
== NULL
);
1819 if (ihost
->power_control
.phys_granted_power
< max_spin_up(ihost
)) {
1820 ihost
->power_control
.phys_granted_power
++;
1821 sci_phy_consume_power_handler(iphy
);
1824 * stop and start the power_control timer. When the timer fires, the
1825 * no_of_phys_granted_power will be set to 0
1827 if (ihost
->power_control
.timer_started
)
1828 sci_del_timer(&ihost
->power_control
.timer
);
1830 sci_mod_timer(&ihost
->power_control
.timer
,
1831 SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL
);
1832 ihost
->power_control
.timer_started
= true;
1836 * There are phys, attached to the same sas address as this phy, are
1837 * already in READY state, this phy don't need wait.
1840 struct isci_phy
*current_phy
;
1842 for (i
= 0; i
< SCI_MAX_PHYS
; i
++) {
1844 current_phy
= &ihost
->phys
[i
];
1846 other
= memcmp(current_phy
->frame_rcvd
.iaf
.sas_addr
,
1847 iphy
->frame_rcvd
.iaf
.sas_addr
,
1848 sizeof(current_phy
->frame_rcvd
.iaf
.sas_addr
));
1850 if (current_phy
->sm
.current_state_id
== SCI_PHY_READY
&&
1851 current_phy
->protocol
== SAS_PROTOCOL_SSP
&&
1853 sci_phy_consume_power_handler(iphy
);
1858 if (i
== SCI_MAX_PHYS
) {
1859 /* Add the phy in the waiting list */
1860 ihost
->power_control
.requesters
[iphy
->phy_index
] = iphy
;
1861 ihost
->power_control
.phys_waiting
++;
1866 void sci_controller_power_control_queue_remove(struct isci_host
*ihost
,
1867 struct isci_phy
*iphy
)
1869 BUG_ON(iphy
== NULL
);
1871 if (ihost
->power_control
.requesters
[iphy
->phy_index
])
1872 ihost
->power_control
.phys_waiting
--;
1874 ihost
->power_control
.requesters
[iphy
->phy_index
] = NULL
;
1877 static int is_long_cable(int phy
, unsigned char selection_byte
)
1879 return !!(selection_byte
& (1 << phy
));
1882 static int is_medium_cable(int phy
, unsigned char selection_byte
)
1884 return !!(selection_byte
& (1 << (phy
+ 4)));
1887 static enum cable_selections
decode_selection_byte(
1889 unsigned char selection_byte
)
1891 return ((selection_byte
& (1 << phy
)) ? 1 : 0)
1892 + (selection_byte
& (1 << (phy
+ 4)) ? 2 : 0);
1895 static unsigned char *to_cable_select(struct isci_host
*ihost
)
1897 if (is_cable_select_overridden())
1898 return ((unsigned char *)&cable_selection_override
)
1901 return &ihost
->oem_parameters
.controller
.cable_selection_mask
;
1904 enum cable_selections
decode_cable_selection(struct isci_host
*ihost
, int phy
)
1906 return decode_selection_byte(phy
, *to_cable_select(ihost
));
1909 char *lookup_cable_names(enum cable_selections selection
)
1911 static char *cable_names
[] = {
1912 [short_cable
] = "short",
1913 [long_cable
] = "long",
1914 [medium_cable
] = "medium",
1915 [undefined_cable
] = "<undefined, assumed long>" /* bit 0==1 */
1917 return (selection
<= undefined_cable
) ? cable_names
[selection
]
1918 : cable_names
[undefined_cable
];
1921 #define AFE_REGISTER_WRITE_DELAY 10
1923 static void sci_controller_afe_initialization(struct isci_host
*ihost
)
1925 struct scu_afe_registers __iomem
*afe
= &ihost
->scu_registers
->afe
;
1926 const struct sci_oem_params
*oem
= &ihost
->oem_parameters
;
1927 struct pci_dev
*pdev
= ihost
->pdev
;
1930 unsigned char cable_selection_mask
= *to_cable_select(ihost
);
1932 /* Clear DFX Status registers */
1933 writel(0x0081000f, &afe
->afe_dfx_master_control0
);
1934 udelay(AFE_REGISTER_WRITE_DELAY
);
1936 if (is_b0(pdev
) || is_c0(pdev
) || is_c1(pdev
)) {
1937 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
1938 * Timer, PM Stagger Timer
1940 writel(0x0007FFFF, &afe
->afe_pmsn_master_control2
);
1941 udelay(AFE_REGISTER_WRITE_DELAY
);
1944 /* Configure bias currents to normal */
1946 writel(0x00005A00, &afe
->afe_bias_control
);
1947 else if (is_b0(pdev
) || is_c0(pdev
))
1948 writel(0x00005F00, &afe
->afe_bias_control
);
1949 else if (is_c1(pdev
))
1950 writel(0x00005500, &afe
->afe_bias_control
);
1952 udelay(AFE_REGISTER_WRITE_DELAY
);
1956 writel(0x80040908, &afe
->afe_pll_control0
);
1957 else if (is_b0(pdev
) || is_c0(pdev
))
1958 writel(0x80040A08, &afe
->afe_pll_control0
);
1959 else if (is_c1(pdev
)) {
1960 writel(0x80000B08, &afe
->afe_pll_control0
);
1961 udelay(AFE_REGISTER_WRITE_DELAY
);
1962 writel(0x00000B08, &afe
->afe_pll_control0
);
1963 udelay(AFE_REGISTER_WRITE_DELAY
);
1964 writel(0x80000B08, &afe
->afe_pll_control0
);
1967 udelay(AFE_REGISTER_WRITE_DELAY
);
1969 /* Wait for the PLL to lock */
1971 afe_status
= readl(&afe
->afe_common_block_status
);
1972 udelay(AFE_REGISTER_WRITE_DELAY
);
1973 } while ((afe_status
& 0x00001000) == 0);
1976 /* Shorten SAS SNW lock time (RxLock timer value from 76
1979 writel(0x7bcc96ad, &afe
->afe_pmsn_master_control0
);
1980 udelay(AFE_REGISTER_WRITE_DELAY
);
1983 for (phy_id
= 0; phy_id
< SCI_MAX_PHYS
; phy_id
++) {
1984 struct scu_afe_transceiver __iomem
*xcvr
= &afe
->scu_afe_xcvr
[phy_id
];
1985 const struct sci_phy_oem_params
*oem_phy
= &oem
->phys
[phy_id
];
1986 int cable_length_long
=
1987 is_long_cable(phy_id
, cable_selection_mask
);
1988 int cable_length_medium
=
1989 is_medium_cable(phy_id
, cable_selection_mask
);
1992 /* All defaults, except the Receive Word
1993 * Alignament/Comma Detect Enable....(0xe800)
1995 writel(0x00004512, &xcvr
->afe_xcvr_control0
);
1996 udelay(AFE_REGISTER_WRITE_DELAY
);
1998 writel(0x0050100F, &xcvr
->afe_xcvr_control1
);
1999 udelay(AFE_REGISTER_WRITE_DELAY
);
2000 } else if (is_b0(pdev
)) {
2001 /* Configure transmitter SSC parameters */
2002 writel(0x00030000, &xcvr
->afe_tx_ssc_control
);
2003 udelay(AFE_REGISTER_WRITE_DELAY
);
2004 } else if (is_c0(pdev
)) {
2005 /* Configure transmitter SSC parameters */
2006 writel(0x00010202, &xcvr
->afe_tx_ssc_control
);
2007 udelay(AFE_REGISTER_WRITE_DELAY
);
2009 /* All defaults, except the Receive Word
2010 * Alignament/Comma Detect Enable....(0xe800)
2012 writel(0x00014500, &xcvr
->afe_xcvr_control0
);
2013 udelay(AFE_REGISTER_WRITE_DELAY
);
2014 } else if (is_c1(pdev
)) {
2015 /* Configure transmitter SSC parameters */
2016 writel(0x00010202, &xcvr
->afe_tx_ssc_control
);
2017 udelay(AFE_REGISTER_WRITE_DELAY
);
2019 /* All defaults, except the Receive Word
2020 * Alignament/Comma Detect Enable....(0xe800)
2022 writel(0x0001C500, &xcvr
->afe_xcvr_control0
);
2023 udelay(AFE_REGISTER_WRITE_DELAY
);
2026 /* Power up TX and RX out from power down (PWRDNTX and
2027 * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c)
2030 writel(0x000003F0, &xcvr
->afe_channel_control
);
2031 else if (is_b0(pdev
)) {
2032 writel(0x000003D7, &xcvr
->afe_channel_control
);
2033 udelay(AFE_REGISTER_WRITE_DELAY
);
2035 writel(0x000003D4, &xcvr
->afe_channel_control
);
2036 } else if (is_c0(pdev
)) {
2037 writel(0x000001E7, &xcvr
->afe_channel_control
);
2038 udelay(AFE_REGISTER_WRITE_DELAY
);
2040 writel(0x000001E4, &xcvr
->afe_channel_control
);
2041 } else if (is_c1(pdev
)) {
2042 writel(cable_length_long
? 0x000002F7 : 0x000001F7,
2043 &xcvr
->afe_channel_control
);
2044 udelay(AFE_REGISTER_WRITE_DELAY
);
2046 writel(cable_length_long
? 0x000002F4 : 0x000001F4,
2047 &xcvr
->afe_channel_control
);
2049 udelay(AFE_REGISTER_WRITE_DELAY
);
2052 /* Enable TX equalization (0xe824) */
2053 writel(0x00040000, &xcvr
->afe_tx_control
);
2054 udelay(AFE_REGISTER_WRITE_DELAY
);
2057 if (is_a2(pdev
) || is_b0(pdev
))
2058 /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0,
2059 * TPD=0x0(TX Power On), RDD=0x0(RX Detect
2060 * Enabled) ....(0xe800)
2062 writel(0x00004100, &xcvr
->afe_xcvr_control0
);
2063 else if (is_c0(pdev
))
2064 writel(0x00014100, &xcvr
->afe_xcvr_control0
);
2065 else if (is_c1(pdev
))
2066 writel(0x0001C100, &xcvr
->afe_xcvr_control0
);
2067 udelay(AFE_REGISTER_WRITE_DELAY
);
2069 /* Leave DFE/FFE on */
2071 writel(0x3F11103F, &xcvr
->afe_rx_ssc_control0
);
2072 else if (is_b0(pdev
)) {
2073 writel(0x3F11103F, &xcvr
->afe_rx_ssc_control0
);
2074 udelay(AFE_REGISTER_WRITE_DELAY
);
2075 /* Enable TX equalization (0xe824) */
2076 writel(0x00040000, &xcvr
->afe_tx_control
);
2077 } else if (is_c0(pdev
)) {
2078 writel(0x01400C0F, &xcvr
->afe_rx_ssc_control1
);
2079 udelay(AFE_REGISTER_WRITE_DELAY
);
2081 writel(0x3F6F103F, &xcvr
->afe_rx_ssc_control0
);
2082 udelay(AFE_REGISTER_WRITE_DELAY
);
2084 /* Enable TX equalization (0xe824) */
2085 writel(0x00040000, &xcvr
->afe_tx_control
);
2086 } else if (is_c1(pdev
)) {
2087 writel(cable_length_long
? 0x01500C0C :
2088 cable_length_medium
? 0x01400C0D : 0x02400C0D,
2089 &xcvr
->afe_xcvr_control1
);
2090 udelay(AFE_REGISTER_WRITE_DELAY
);
2092 writel(0x000003E0, &xcvr
->afe_dfx_rx_control1
);
2093 udelay(AFE_REGISTER_WRITE_DELAY
);
2095 writel(cable_length_long
? 0x33091C1F :
2096 cable_length_medium
? 0x3315181F : 0x2B17161F,
2097 &xcvr
->afe_rx_ssc_control0
);
2098 udelay(AFE_REGISTER_WRITE_DELAY
);
2100 /* Enable TX equalization (0xe824) */
2101 writel(0x00040000, &xcvr
->afe_tx_control
);
2104 udelay(AFE_REGISTER_WRITE_DELAY
);
2106 writel(oem_phy
->afe_tx_amp_control0
, &xcvr
->afe_tx_amp_control0
);
2107 udelay(AFE_REGISTER_WRITE_DELAY
);
2109 writel(oem_phy
->afe_tx_amp_control1
, &xcvr
->afe_tx_amp_control1
);
2110 udelay(AFE_REGISTER_WRITE_DELAY
);
2112 writel(oem_phy
->afe_tx_amp_control2
, &xcvr
->afe_tx_amp_control2
);
2113 udelay(AFE_REGISTER_WRITE_DELAY
);
2115 writel(oem_phy
->afe_tx_amp_control3
, &xcvr
->afe_tx_amp_control3
);
2116 udelay(AFE_REGISTER_WRITE_DELAY
);
2119 /* Transfer control to the PEs */
2120 writel(0x00010f00, &afe
->afe_dfx_master_control0
);
2121 udelay(AFE_REGISTER_WRITE_DELAY
);
2124 static void sci_controller_initialize_power_control(struct isci_host
*ihost
)
2126 sci_init_timer(&ihost
->power_control
.timer
, power_control_timeout
);
2128 memset(ihost
->power_control
.requesters
, 0,
2129 sizeof(ihost
->power_control
.requesters
));
2131 ihost
->power_control
.phys_waiting
= 0;
2132 ihost
->power_control
.phys_granted_power
= 0;
2135 static enum sci_status
sci_controller_initialize(struct isci_host
*ihost
)
2137 struct sci_base_state_machine
*sm
= &ihost
->sm
;
2138 enum sci_status result
= SCI_FAILURE
;
2139 unsigned long i
, state
, val
;
2141 if (ihost
->sm
.current_state_id
!= SCIC_RESET
) {
2142 dev_warn(&ihost
->pdev
->dev
, "%s invalid state: %d\n",
2143 __func__
, ihost
->sm
.current_state_id
);
2144 return SCI_FAILURE_INVALID_STATE
;
2147 sci_change_state(sm
, SCIC_INITIALIZING
);
2149 sci_init_timer(&ihost
->phy_timer
, phy_startup_timeout
);
2151 ihost
->next_phy_to_start
= 0;
2152 ihost
->phy_startup_timer_pending
= false;
2154 sci_controller_initialize_power_control(ihost
);
2157 * There is nothing to do here for B0 since we do not have to
2158 * program the AFE registers.
2159 * / @todo The AFE settings are supposed to be correct for the B0 but
2160 * / presently they seem to be wrong. */
2161 sci_controller_afe_initialization(ihost
);
2164 /* Take the hardware out of reset */
2165 writel(0, &ihost
->smu_registers
->soft_reset_control
);
2168 * / @todo Provide meaningfull error code for hardware failure
2169 * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
2170 for (i
= 100; i
>= 1; i
--) {
2173 /* Loop until the hardware reports success */
2174 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME
);
2175 status
= readl(&ihost
->smu_registers
->control_status
);
2177 if ((status
& SCU_RAM_INIT_COMPLETED
) == SCU_RAM_INIT_COMPLETED
)
2184 * Determine what are the actaul device capacities that the
2185 * hardware will support */
2186 val
= readl(&ihost
->smu_registers
->device_context_capacity
);
2188 /* Record the smaller of the two capacity values */
2189 ihost
->logical_port_entries
= min(smu_max_ports(val
), SCI_MAX_PORTS
);
2190 ihost
->task_context_entries
= min(smu_max_task_contexts(val
), SCI_MAX_IO_REQUESTS
);
2191 ihost
->remote_node_entries
= min(smu_max_rncs(val
), SCI_MAX_REMOTE_DEVICES
);
2194 * Make all PEs that are unassigned match up with the
2197 for (i
= 0; i
< ihost
->logical_port_entries
; i
++) {
2198 struct scu_port_task_scheduler_group_registers __iomem
2199 *ptsg
= &ihost
->scu_registers
->peg0
.ptsg
;
2201 writel(i
, &ptsg
->protocol_engine
[i
]);
2204 /* Initialize hardware PCI Relaxed ordering in DMA engines */
2205 val
= readl(&ihost
->scu_registers
->sdma
.pdma_configuration
);
2206 val
|= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE
);
2207 writel(val
, &ihost
->scu_registers
->sdma
.pdma_configuration
);
2209 val
= readl(&ihost
->scu_registers
->sdma
.cdma_configuration
);
2210 val
|= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE
);
2211 writel(val
, &ihost
->scu_registers
->sdma
.cdma_configuration
);
2214 * Initialize the PHYs before the PORTs because the PHY registers
2215 * are accessed during the port initialization.
2217 for (i
= 0; i
< SCI_MAX_PHYS
; i
++) {
2218 result
= sci_phy_initialize(&ihost
->phys
[i
],
2219 &ihost
->scu_registers
->peg0
.pe
[i
].tl
,
2220 &ihost
->scu_registers
->peg0
.pe
[i
].ll
);
2221 if (result
!= SCI_SUCCESS
)
2225 for (i
= 0; i
< ihost
->logical_port_entries
; i
++) {
2226 struct isci_port
*iport
= &ihost
->ports
[i
];
2228 iport
->port_task_scheduler_registers
= &ihost
->scu_registers
->peg0
.ptsg
.port
[i
];
2229 iport
->port_pe_configuration_register
= &ihost
->scu_registers
->peg0
.ptsg
.protocol_engine
[0];
2230 iport
->viit_registers
= &ihost
->scu_registers
->peg0
.viit
[i
];
2233 result
= sci_port_configuration_agent_initialize(ihost
, &ihost
->port_agent
);
2236 /* Advance the controller state machine */
2237 if (result
== SCI_SUCCESS
)
2238 state
= SCIC_INITIALIZED
;
2240 state
= SCIC_FAILED
;
2241 sci_change_state(sm
, state
);
2246 static int sci_controller_dma_alloc(struct isci_host
*ihost
)
2248 struct device
*dev
= &ihost
->pdev
->dev
;
2252 /* detect re-initialization */
2253 if (ihost
->completion_queue
)
2256 size
= SCU_MAX_COMPLETION_QUEUE_ENTRIES
* sizeof(u32
);
2257 ihost
->completion_queue
= dmam_alloc_coherent(dev
, size
, &ihost
->cq_dma
,
2259 if (!ihost
->completion_queue
)
2262 size
= ihost
->remote_node_entries
* sizeof(union scu_remote_node_context
);
2263 ihost
->remote_node_context_table
= dmam_alloc_coherent(dev
, size
, &ihost
->rnc_dma
,
2266 if (!ihost
->remote_node_context_table
)
2269 size
= ihost
->task_context_entries
* sizeof(struct scu_task_context
),
2270 ihost
->task_context_table
= dmam_alloc_coherent(dev
, size
, &ihost
->tc_dma
,
2272 if (!ihost
->task_context_table
)
2275 size
= SCI_UFI_TOTAL_SIZE
;
2276 ihost
->ufi_buf
= dmam_alloc_coherent(dev
, size
, &ihost
->ufi_dma
, GFP_KERNEL
);
2277 if (!ihost
->ufi_buf
)
2280 for (i
= 0; i
< SCI_MAX_IO_REQUESTS
; i
++) {
2281 struct isci_request
*ireq
;
2284 ireq
= dmam_alloc_coherent(dev
, sizeof(*ireq
), &dma
, GFP_KERNEL
);
2288 ireq
->tc
= &ihost
->task_context_table
[i
];
2289 ireq
->owning_controller
= ihost
;
2290 ireq
->request_daddr
= dma
;
2291 ireq
->isci_host
= ihost
;
2292 ihost
->reqs
[i
] = ireq
;
2298 static int sci_controller_mem_init(struct isci_host
*ihost
)
2300 int err
= sci_controller_dma_alloc(ihost
);
2305 writel(lower_32_bits(ihost
->cq_dma
), &ihost
->smu_registers
->completion_queue_lower
);
2306 writel(upper_32_bits(ihost
->cq_dma
), &ihost
->smu_registers
->completion_queue_upper
);
2308 writel(lower_32_bits(ihost
->rnc_dma
), &ihost
->smu_registers
->remote_node_context_lower
);
2309 writel(upper_32_bits(ihost
->rnc_dma
), &ihost
->smu_registers
->remote_node_context_upper
);
2311 writel(lower_32_bits(ihost
->tc_dma
), &ihost
->smu_registers
->host_task_table_lower
);
2312 writel(upper_32_bits(ihost
->tc_dma
), &ihost
->smu_registers
->host_task_table_upper
);
2314 sci_unsolicited_frame_control_construct(ihost
);
2317 * Inform the silicon as to the location of the UF headers and
2320 writel(lower_32_bits(ihost
->uf_control
.headers
.physical_address
),
2321 &ihost
->scu_registers
->sdma
.uf_header_base_address_lower
);
2322 writel(upper_32_bits(ihost
->uf_control
.headers
.physical_address
),
2323 &ihost
->scu_registers
->sdma
.uf_header_base_address_upper
);
2325 writel(lower_32_bits(ihost
->uf_control
.address_table
.physical_address
),
2326 &ihost
->scu_registers
->sdma
.uf_address_table_lower
);
2327 writel(upper_32_bits(ihost
->uf_control
.address_table
.physical_address
),
2328 &ihost
->scu_registers
->sdma
.uf_address_table_upper
);
2334 * isci_host_init - (re-)initialize hardware and internal (private) state
2335 * @ihost: host to init
2337 * Any public facing objects (like asd_sas_port, and asd_sas_phys), or
2338 * one-time initialization objects like locks and waitqueues, are
2339 * not touched (they are initialized in isci_host_alloc)
2341 int isci_host_init(struct isci_host
*ihost
)
2344 enum sci_status status
;
2346 spin_lock_irq(&ihost
->scic_lock
);
2347 status
= sci_controller_construct(ihost
, scu_base(ihost
), smu_base(ihost
));
2348 spin_unlock_irq(&ihost
->scic_lock
);
2349 if (status
!= SCI_SUCCESS
) {
2350 dev_err(&ihost
->pdev
->dev
,
2351 "%s: sci_controller_construct failed - status = %x\n",
2357 spin_lock_irq(&ihost
->scic_lock
);
2358 status
= sci_controller_initialize(ihost
);
2359 spin_unlock_irq(&ihost
->scic_lock
);
2360 if (status
!= SCI_SUCCESS
) {
2361 dev_warn(&ihost
->pdev
->dev
,
2362 "%s: sci_controller_initialize failed -"
2368 err
= sci_controller_mem_init(ihost
);
2373 writel(1, &ihost
->scu_registers
->peg0
.sgpio
.interface_control
);
2374 for (i
= 0; i
< isci_gpio_count(ihost
); i
++)
2375 writel(SGPIO_HW_CONTROL
, &ihost
->scu_registers
->peg0
.sgpio
.output_data_select
[i
]);
2376 writel(0, &ihost
->scu_registers
->peg0
.sgpio
.vendor_specific_code
);
2381 void sci_controller_link_up(struct isci_host
*ihost
, struct isci_port
*iport
,
2382 struct isci_phy
*iphy
)
2384 switch (ihost
->sm
.current_state_id
) {
2386 sci_del_timer(&ihost
->phy_timer
);
2387 ihost
->phy_startup_timer_pending
= false;
2388 ihost
->port_agent
.link_up_handler(ihost
, &ihost
->port_agent
,
2390 sci_controller_start_next_phy(ihost
);
2393 ihost
->port_agent
.link_up_handler(ihost
, &ihost
->port_agent
,
2397 dev_dbg(&ihost
->pdev
->dev
,
2398 "%s: SCIC Controller linkup event from phy %d in "
2399 "unexpected state %d\n", __func__
, iphy
->phy_index
,
2400 ihost
->sm
.current_state_id
);
2404 void sci_controller_link_down(struct isci_host
*ihost
, struct isci_port
*iport
,
2405 struct isci_phy
*iphy
)
2407 switch (ihost
->sm
.current_state_id
) {
2410 ihost
->port_agent
.link_down_handler(ihost
, &ihost
->port_agent
,
2414 dev_dbg(&ihost
->pdev
->dev
,
2415 "%s: SCIC Controller linkdown event from phy %d in "
2416 "unexpected state %d\n",
2419 ihost
->sm
.current_state_id
);
2423 bool sci_controller_has_remote_devices_stopping(struct isci_host
*ihost
)
2427 for (index
= 0; index
< ihost
->remote_node_entries
; index
++) {
2428 if ((ihost
->device_table
[index
] != NULL
) &&
2429 (ihost
->device_table
[index
]->sm
.current_state_id
== SCI_DEV_STOPPING
))
2436 void sci_controller_remote_device_stopped(struct isci_host
*ihost
,
2437 struct isci_remote_device
*idev
)
2439 if (ihost
->sm
.current_state_id
!= SCIC_STOPPING
) {
2440 dev_dbg(&ihost
->pdev
->dev
,
2441 "SCIC Controller 0x%p remote device stopped event "
2442 "from device 0x%p in unexpected state %d\n",
2444 ihost
->sm
.current_state_id
);
2448 if (!sci_controller_has_remote_devices_stopping(ihost
))
2449 isci_host_stop_complete(ihost
);
2452 void sci_controller_post_request(struct isci_host
*ihost
, u32 request
)
2454 dev_dbg(&ihost
->pdev
->dev
, "%s[%d]: %#x\n",
2455 __func__
, ihost
->id
, request
);
2457 writel(request
, &ihost
->smu_registers
->post_context_port
);
2460 struct isci_request
*sci_request_by_tag(struct isci_host
*ihost
, u16 io_tag
)
2465 task_index
= ISCI_TAG_TCI(io_tag
);
2467 if (task_index
< ihost
->task_context_entries
) {
2468 struct isci_request
*ireq
= ihost
->reqs
[task_index
];
2470 if (test_bit(IREQ_ACTIVE
, &ireq
->flags
)) {
2471 task_sequence
= ISCI_TAG_SEQ(io_tag
);
2473 if (task_sequence
== ihost
->io_request_sequence
[task_index
])
2482 * This method allocates remote node index and the reserves the remote node
2483 * context space for use. This method can fail if there are no more remote
2484 * node index available.
2485 * @scic: This is the controller object which contains the set of
2486 * free remote node ids
2487 * @sci_dev: This is the device object which is requesting the a remote node
2489 * @node_id: This is the remote node id that is assinged to the device if one
2492 * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
2493 * node index available.
2495 enum sci_status
sci_controller_allocate_remote_node_context(struct isci_host
*ihost
,
2496 struct isci_remote_device
*idev
,
2500 u32 remote_node_count
= sci_remote_device_node_count(idev
);
2502 node_index
= sci_remote_node_table_allocate_remote_node(
2503 &ihost
->available_remote_nodes
, remote_node_count
2506 if (node_index
!= SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX
) {
2507 ihost
->device_table
[node_index
] = idev
;
2509 *node_id
= node_index
;
2514 return SCI_FAILURE_INSUFFICIENT_RESOURCES
;
2517 void sci_controller_free_remote_node_context(struct isci_host
*ihost
,
2518 struct isci_remote_device
*idev
,
2521 u32 remote_node_count
= sci_remote_device_node_count(idev
);
2523 if (ihost
->device_table
[node_id
] == idev
) {
2524 ihost
->device_table
[node_id
] = NULL
;
2526 sci_remote_node_table_release_remote_node_index(
2527 &ihost
->available_remote_nodes
, remote_node_count
, node_id
2532 void sci_controller_copy_sata_response(void *response_buffer
,
2536 /* XXX type safety? */
2537 memcpy(response_buffer
, frame_header
, sizeof(u32
));
2539 memcpy(response_buffer
+ sizeof(u32
),
2541 sizeof(struct dev_to_host_fis
) - sizeof(u32
));
2544 void sci_controller_release_frame(struct isci_host
*ihost
, u32 frame_index
)
2546 if (sci_unsolicited_frame_control_release_frame(&ihost
->uf_control
, frame_index
))
2547 writel(ihost
->uf_control
.get
,
2548 &ihost
->scu_registers
->sdma
.unsolicited_frame_get_pointer
);
2551 void isci_tci_free(struct isci_host
*ihost
, u16 tci
)
2553 u16 tail
= ihost
->tci_tail
& (SCI_MAX_IO_REQUESTS
-1);
2555 ihost
->tci_pool
[tail
] = tci
;
2556 ihost
->tci_tail
= tail
+ 1;
2559 static u16
isci_tci_alloc(struct isci_host
*ihost
)
2561 u16 head
= ihost
->tci_head
& (SCI_MAX_IO_REQUESTS
-1);
2562 u16 tci
= ihost
->tci_pool
[head
];
2564 ihost
->tci_head
= head
+ 1;
2568 static u16
isci_tci_space(struct isci_host
*ihost
)
2570 return CIRC_SPACE(ihost
->tci_head
, ihost
->tci_tail
, SCI_MAX_IO_REQUESTS
);
2573 u16
isci_alloc_tag(struct isci_host
*ihost
)
2575 if (isci_tci_space(ihost
)) {
2576 u16 tci
= isci_tci_alloc(ihost
);
2577 u8 seq
= ihost
->io_request_sequence
[tci
];
2579 return ISCI_TAG(seq
, tci
);
2582 return SCI_CONTROLLER_INVALID_IO_TAG
;
2585 enum sci_status
isci_free_tag(struct isci_host
*ihost
, u16 io_tag
)
2587 u16 tci
= ISCI_TAG_TCI(io_tag
);
2588 u16 seq
= ISCI_TAG_SEQ(io_tag
);
2590 /* prevent tail from passing head */
2591 if (isci_tci_active(ihost
) == 0)
2592 return SCI_FAILURE_INVALID_IO_TAG
;
2594 if (seq
== ihost
->io_request_sequence
[tci
]) {
2595 ihost
->io_request_sequence
[tci
] = (seq
+1) & (SCI_MAX_SEQ
-1);
2597 isci_tci_free(ihost
, tci
);
2601 return SCI_FAILURE_INVALID_IO_TAG
;
2604 enum sci_status
sci_controller_start_io(struct isci_host
*ihost
,
2605 struct isci_remote_device
*idev
,
2606 struct isci_request
*ireq
)
2608 enum sci_status status
;
2610 if (ihost
->sm
.current_state_id
!= SCIC_READY
) {
2611 dev_warn(&ihost
->pdev
->dev
, "%s invalid state: %d\n",
2612 __func__
, ihost
->sm
.current_state_id
);
2613 return SCI_FAILURE_INVALID_STATE
;
2616 status
= sci_remote_device_start_io(ihost
, idev
, ireq
);
2617 if (status
!= SCI_SUCCESS
)
2620 set_bit(IREQ_ACTIVE
, &ireq
->flags
);
2621 sci_controller_post_request(ihost
, ireq
->post_context
);
2625 enum sci_status
sci_controller_terminate_request(struct isci_host
*ihost
,
2626 struct isci_remote_device
*idev
,
2627 struct isci_request
*ireq
)
2629 /* terminate an ongoing (i.e. started) core IO request. This does not
2630 * abort the IO request at the target, but rather removes the IO
2631 * request from the host controller.
2633 enum sci_status status
;
2635 if (ihost
->sm
.current_state_id
!= SCIC_READY
) {
2636 dev_warn(&ihost
->pdev
->dev
, "%s invalid state: %d\n",
2637 __func__
, ihost
->sm
.current_state_id
);
2638 return SCI_FAILURE_INVALID_STATE
;
2640 status
= sci_io_request_terminate(ireq
);
2642 dev_dbg(&ihost
->pdev
->dev
, "%s: status=%d; ireq=%p; flags=%lx\n",
2643 __func__
, status
, ireq
, ireq
->flags
);
2645 if ((status
== SCI_SUCCESS
) &&
2646 !test_bit(IREQ_PENDING_ABORT
, &ireq
->flags
) &&
2647 !test_and_set_bit(IREQ_TC_ABORT_POSTED
, &ireq
->flags
)) {
2648 /* Utilize the original post context command and or in the
2649 * POST_TC_ABORT request sub-type.
2651 sci_controller_post_request(
2652 ihost
, ireq
->post_context
|
2653 SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT
);
2659 * sci_controller_complete_io() - This method will perform core specific
2660 * completion operations for an IO request. After this method is invoked,
2661 * the user should consider the IO request as invalid until it is properly
2662 * reused (i.e. re-constructed).
2663 * @ihost: The handle to the controller object for which to complete the
2665 * @idev: The handle to the remote device object for which to complete
2667 * @ireq: the handle to the io request object to complete.
2669 enum sci_status
sci_controller_complete_io(struct isci_host
*ihost
,
2670 struct isci_remote_device
*idev
,
2671 struct isci_request
*ireq
)
2673 enum sci_status status
;
2676 switch (ihost
->sm
.current_state_id
) {
2678 /* XXX: Implement this function */
2681 status
= sci_remote_device_complete_io(ihost
, idev
, ireq
);
2682 if (status
!= SCI_SUCCESS
)
2685 index
= ISCI_TAG_TCI(ireq
->io_tag
);
2686 clear_bit(IREQ_ACTIVE
, &ireq
->flags
);
2689 dev_warn(&ihost
->pdev
->dev
, "%s invalid state: %d\n",
2690 __func__
, ihost
->sm
.current_state_id
);
2691 return SCI_FAILURE_INVALID_STATE
;
2696 enum sci_status
sci_controller_continue_io(struct isci_request
*ireq
)
2698 struct isci_host
*ihost
= ireq
->owning_controller
;
2700 if (ihost
->sm
.current_state_id
!= SCIC_READY
) {
2701 dev_warn(&ihost
->pdev
->dev
, "%s invalid state: %d\n",
2702 __func__
, ihost
->sm
.current_state_id
);
2703 return SCI_FAILURE_INVALID_STATE
;
2706 set_bit(IREQ_ACTIVE
, &ireq
->flags
);
2707 sci_controller_post_request(ihost
, ireq
->post_context
);
2712 * sci_controller_start_task() - This method is called by the SCIC user to
2713 * send/start a framework task management request.
2714 * @controller: the handle to the controller object for which to start the task
2715 * management request.
2716 * @remote_device: the handle to the remote device object for which to start
2717 * the task management request.
2718 * @task_request: the handle to the task request object to start.
2720 enum sci_task_status
sci_controller_start_task(struct isci_host
*ihost
,
2721 struct isci_remote_device
*idev
,
2722 struct isci_request
*ireq
)
2724 enum sci_status status
;
2726 if (ihost
->sm
.current_state_id
!= SCIC_READY
) {
2727 dev_warn(&ihost
->pdev
->dev
,
2728 "%s: SCIC Controller starting task from invalid "
2731 return SCI_TASK_FAILURE_INVALID_STATE
;
2734 status
= sci_remote_device_start_task(ihost
, idev
, ireq
);
2736 case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS
:
2737 set_bit(IREQ_ACTIVE
, &ireq
->flags
);
2740 * We will let framework know this task request started successfully,
2741 * although core is still woring on starting the request (to post tc when
2746 set_bit(IREQ_ACTIVE
, &ireq
->flags
);
2747 sci_controller_post_request(ihost
, ireq
->post_context
);
2756 static int sci_write_gpio_tx_gp(struct isci_host
*ihost
, u8 reg_index
, u8 reg_count
, u8
*write_data
)
2760 /* no support for TX_GP_CFG */
2764 for (d
= 0; d
< isci_gpio_count(ihost
); d
++) {
2765 u32 val
= 0x444; /* all ODx.n clear */
2768 for (i
= 0; i
< 3; i
++) {
2769 int bit
= (i
<< 2) + 2;
2771 bit
= try_test_sas_gpio_gp_bit(to_sas_gpio_od(d
, i
),
2772 write_data
, reg_index
,
2777 /* if od is set, clear the 'invert' bit */
2778 val
&= ~(bit
<< ((i
<< 2) + 2));
2783 writel(val
, &ihost
->scu_registers
->peg0
.sgpio
.output_data_select
[d
]);
2786 /* unless reg_index is > 1, we should always be able to write at
2787 * least one register
2792 int isci_gpio_write(struct sas_ha_struct
*sas_ha
, u8 reg_type
, u8 reg_index
,
2793 u8 reg_count
, u8
*write_data
)
2795 struct isci_host
*ihost
= sas_ha
->lldd_ha
;
2799 case SAS_GPIO_REG_TX_GP
:
2800 written
= sci_write_gpio_tx_gp(ihost
, reg_index
, reg_count
, write_data
);