1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2017 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Limited and/or its subsidiaries. *
6 * Copyright (C) 2009-2016 Emulex. All rights reserved. *
7 * EMULEX and SLI are trademarks of Emulex. *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
23 /* Macros to deal with bit fields. Each bit field must have 3 #defines
24 * associated with it (_SHIFT, _MASK, and _WORD).
25 * EG. For a bit field that is in the 7th bit of the "field4" field of a
26 * structure and is 2 bits in size the following #defines must exist:
32 * #define example_bit_field_SHIFT 7
33 * #define example_bit_field_MASK 0x03
34 * #define example_bit_field_WORD field4
37 * Then the macros below may be used to get or set the value of that field.
38 * EG. To get the value of the bit field from the above example:
40 * value = bf_get(example_bit_field, &t1);
41 * And then to set that bit field:
42 * bf_set(example_bit_field, &t1, 2);
43 * Or clear that bit field:
44 * bf_set(example_bit_field, &t1, 0);
46 #define bf_get_be32(name, ptr) \
47 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
48 #define bf_get_le32(name, ptr) \
49 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
50 #define bf_get(name, ptr) \
51 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
52 #define bf_set_le32(name, ptr, value) \
53 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
54 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
55 ~(name##_MASK << name##_SHIFT)))))
56 #define bf_set(name, ptr, value) \
57 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
58 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
65 struct lpfc_sli_intf
{
67 #define lpfc_sli_intf_valid_SHIFT 29
68 #define lpfc_sli_intf_valid_MASK 0x00000007
69 #define lpfc_sli_intf_valid_WORD word0
70 #define LPFC_SLI_INTF_VALID 6
71 #define lpfc_sli_intf_sli_hint2_SHIFT 24
72 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
73 #define lpfc_sli_intf_sli_hint2_WORD word0
74 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
75 #define lpfc_sli_intf_sli_hint1_SHIFT 16
76 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
77 #define lpfc_sli_intf_sli_hint1_WORD word0
78 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
79 #define LPFC_SLI_INTF_SLI_HINT1_1 1
80 #define LPFC_SLI_INTF_SLI_HINT1_2 2
81 #define lpfc_sli_intf_if_type_SHIFT 12
82 #define lpfc_sli_intf_if_type_MASK 0x0000000F
83 #define lpfc_sli_intf_if_type_WORD word0
84 #define LPFC_SLI_INTF_IF_TYPE_0 0
85 #define LPFC_SLI_INTF_IF_TYPE_1 1
86 #define LPFC_SLI_INTF_IF_TYPE_2 2
87 #define lpfc_sli_intf_sli_family_SHIFT 8
88 #define lpfc_sli_intf_sli_family_MASK 0x0000000F
89 #define lpfc_sli_intf_sli_family_WORD word0
90 #define LPFC_SLI_INTF_FAMILY_BE2 0x0
91 #define LPFC_SLI_INTF_FAMILY_BE3 0x1
92 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
93 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
94 #define lpfc_sli_intf_slirev_SHIFT 4
95 #define lpfc_sli_intf_slirev_MASK 0x0000000F
96 #define lpfc_sli_intf_slirev_WORD word0
97 #define LPFC_SLI_INTF_REV_SLI3 3
98 #define LPFC_SLI_INTF_REV_SLI4 4
99 #define lpfc_sli_intf_func_type_SHIFT 0
100 #define lpfc_sli_intf_func_type_MASK 0x00000001
101 #define lpfc_sli_intf_func_type_WORD word0
102 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0
103 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1
106 #define LPFC_SLI4_MBX_EMBED true
107 #define LPFC_SLI4_MBX_NEMBED false
109 #define LPFC_SLI4_MB_WORD_COUNT 64
110 #define LPFC_MAX_MQ_PAGE 8
111 #define LPFC_MAX_WQ_PAGE_V0 4
112 #define LPFC_MAX_WQ_PAGE 8
113 #define LPFC_MAX_RQ_PAGE 8
114 #define LPFC_MAX_CQ_PAGE 4
115 #define LPFC_MAX_EQ_PAGE 8
117 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */
118 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */
119 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
121 /* Define SLI4 Alignment requirements. */
122 #define LPFC_ALIGN_16_BYTE 16
123 #define LPFC_ALIGN_64_BYTE 64
125 /* Define SLI4 specific definitions. */
126 #define LPFC_MQ_CQE_BYTE_OFFSET 256
127 #define LPFC_MBX_CMD_HDR_LENGTH 16
128 #define LPFC_MBX_ERROR_RANGE 0x4000
129 #define LPFC_BMBX_BIT1_ADDR_HI 0x2
130 #define LPFC_BMBX_BIT1_ADDR_LO 0
131 #define LPFC_RPI_HDR_COUNT 64
132 #define LPFC_HDR_TEMPLATE_SIZE 4096
133 #define LPFC_RPI_ALLOC_ERROR 0xFFFF
134 #define LPFC_FCF_RECORD_WD_CNT 132
135 #define LPFC_ENTIRE_FCF_DATABASE 0
136 #define LPFC_DFLT_FCF_INDEX 0
138 /* Virtual function numbers */
172 /* PCI function numbers */
173 #define LPFC_PCI_FUNC0 0
174 #define LPFC_PCI_FUNC1 1
175 #define LPFC_PCI_FUNC2 2
176 #define LPFC_PCI_FUNC3 3
177 #define LPFC_PCI_FUNC4 4
179 /* SLI4 interface type-2 PDEV_CTL register */
180 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414
181 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001
182 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002
183 #define LPFC_CTL_PDEV_CTL_DD 0x00000004
184 #define LPFC_CTL_PDEV_CTL_LC 0x00000008
185 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00
186 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10
187 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20
189 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
191 /* Active interrupt test count */
192 #define LPFC_ACT_INTR_CNT 4
194 /* Algrithmns for scheduling FCP commands to WQs */
195 #define LPFC_FCP_SCHED_ROUND_ROBIN 0
196 #define LPFC_FCP_SCHED_BY_CPU 1
198 /* Delay Multiplier constant */
199 #define LPFC_DMULT_CONST 651042
200 #define LPFC_DMULT_MAX 1023
202 /* Configuration of Interrupts / sec for entire HBA port */
203 #define LPFC_MIN_IMAX 5000
204 #define LPFC_MAX_IMAX 5000000
205 #define LPFC_DEF_IMAX 150000
207 #define LPFC_MIN_CPU_MAP 0
208 #define LPFC_MAX_CPU_MAP 2
209 #define LPFC_HBA_CPU_MAP 1
210 #define LPFC_DRIVER_CPU_MAP 2 /* Default */
212 /* PORT_CAPABILITIES constants. */
213 #define LPFC_MAX_SUPPORTED_PAGES 8
219 #ifdef __BIG_ENDIAN_BITFIELD
220 uint32_t bdeFlags
:8; /* BDE Flags 0 IS A SUPPORTED
222 uint32_t bdeSize
:24; /* Size of buffer (in bytes) */
223 #else /* __LITTLE_ENDIAN_BITFIELD */
224 uint32_t bdeSize
:24; /* Size of buffer (in bytes) */
225 uint32_t bdeFlags
:8; /* BDE Flags 0 IS A SUPPORTED
228 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
229 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
230 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
231 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
232 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
233 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
234 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
241 /* Maximun size of immediate data that can fit into a 128 byte WQE */
242 #define LPFC_MAX_BDE_IMM_SIZE 64
244 struct lpfc_sli4_flags
{
246 #define lpfc_idx_rsrc_rdy_SHIFT 0
247 #define lpfc_idx_rsrc_rdy_MASK 0x00000001
248 #define lpfc_idx_rsrc_rdy_WORD word0
249 #define LPFC_IDX_RSRC_RDY 1
250 #define lpfc_rpi_rsrc_rdy_SHIFT 1
251 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001
252 #define lpfc_rpi_rsrc_rdy_WORD word0
253 #define LPFC_RPI_RSRC_RDY 1
254 #define lpfc_vpi_rsrc_rdy_SHIFT 2
255 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001
256 #define lpfc_vpi_rsrc_rdy_WORD word0
257 #define LPFC_VPI_RSRC_RDY 1
258 #define lpfc_vfi_rsrc_rdy_SHIFT 3
259 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001
260 #define lpfc_vfi_rsrc_rdy_WORD word0
261 #define LPFC_VFI_RSRC_RDY 1
264 struct sli4_bls_rsp
{
265 uint32_t word0_rsvd
; /* Word0 must be reserved */
267 #define lpfc_abts_orig_SHIFT 0
268 #define lpfc_abts_orig_MASK 0x00000001
269 #define lpfc_abts_orig_WORD word1
270 #define LPFC_ABTS_UNSOL_RSP 1
271 #define LPFC_ABTS_UNSOL_INT 0
273 #define lpfc_abts_rxid_SHIFT 0
274 #define lpfc_abts_rxid_MASK 0x0000FFFF
275 #define lpfc_abts_rxid_WORD word2
276 #define lpfc_abts_oxid_SHIFT 16
277 #define lpfc_abts_oxid_MASK 0x0000FFFF
278 #define lpfc_abts_oxid_WORD word2
280 #define lpfc_vndr_code_SHIFT 0
281 #define lpfc_vndr_code_MASK 0x000000FF
282 #define lpfc_vndr_code_WORD word3
283 #define lpfc_rsn_expln_SHIFT 8
284 #define lpfc_rsn_expln_MASK 0x000000FF
285 #define lpfc_rsn_expln_WORD word3
286 #define lpfc_rsn_code_SHIFT 16
287 #define lpfc_rsn_code_MASK 0x000000FF
288 #define lpfc_rsn_code_WORD word3
291 uint32_t word5_rsvd
; /* Word5 must be reserved */
294 /* event queue entry structure */
297 #define lpfc_eqe_resource_id_SHIFT 16
298 #define lpfc_eqe_resource_id_MASK 0x0000FFFF
299 #define lpfc_eqe_resource_id_WORD word0
300 #define lpfc_eqe_minor_code_SHIFT 4
301 #define lpfc_eqe_minor_code_MASK 0x00000FFF
302 #define lpfc_eqe_minor_code_WORD word0
303 #define lpfc_eqe_major_code_SHIFT 1
304 #define lpfc_eqe_major_code_MASK 0x00000007
305 #define lpfc_eqe_major_code_WORD word0
306 #define lpfc_eqe_valid_SHIFT 0
307 #define lpfc_eqe_valid_MASK 0x00000001
308 #define lpfc_eqe_valid_WORD word0
311 /* completion queue entry structure (common fields for all cqe types) */
317 #define lpfc_cqe_valid_SHIFT 31
318 #define lpfc_cqe_valid_MASK 0x00000001
319 #define lpfc_cqe_valid_WORD word3
320 #define lpfc_cqe_code_SHIFT 16
321 #define lpfc_cqe_code_MASK 0x000000FF
322 #define lpfc_cqe_code_WORD word3
325 /* Completion Queue Entry Status Codes */
326 #define CQE_STATUS_SUCCESS 0x0
327 #define CQE_STATUS_FCP_RSP_FAILURE 0x1
328 #define CQE_STATUS_REMOTE_STOP 0x2
329 #define CQE_STATUS_LOCAL_REJECT 0x3
330 #define CQE_STATUS_NPORT_RJT 0x4
331 #define CQE_STATUS_FABRIC_RJT 0x5
332 #define CQE_STATUS_NPORT_BSY 0x6
333 #define CQE_STATUS_FABRIC_BSY 0x7
334 #define CQE_STATUS_INTERMED_RSP 0x8
335 #define CQE_STATUS_LS_RJT 0x9
336 #define CQE_STATUS_CMD_REJECT 0xb
337 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc
338 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf
339 #define CQE_STATUS_DI_ERROR 0x16
341 /* Used when mapping CQE status to IOCB */
342 #define LPFC_IOCB_STATUS_MASK 0xf
344 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
345 #define CQE_HW_STATUS_NO_ERR 0x0
346 #define CQE_HW_STATUS_UNDERRUN 0x1
347 #define CQE_HW_STATUS_OVERRUN 0x2
349 /* Completion Queue Entry Codes */
350 #define CQE_CODE_COMPL_WQE 0x1
351 #define CQE_CODE_RELEASE_WQE 0x2
352 #define CQE_CODE_RECEIVE 0x4
353 #define CQE_CODE_XRI_ABORTED 0x5
354 #define CQE_CODE_RECEIVE_V1 0x9
355 #define CQE_CODE_NVME_ERSP 0xd
358 * Define mask value for xri_aborted and wcqe completed CQE extended status.
359 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
361 #define WCQE_PARAM_MASK 0x1FF
363 /* completion queue entry for wqe completions */
364 struct lpfc_wcqe_complete
{
366 #define lpfc_wcqe_c_request_tag_SHIFT 16
367 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
368 #define lpfc_wcqe_c_request_tag_WORD word0
369 #define lpfc_wcqe_c_status_SHIFT 8
370 #define lpfc_wcqe_c_status_MASK 0x000000FF
371 #define lpfc_wcqe_c_status_WORD word0
372 #define lpfc_wcqe_c_hw_status_SHIFT 0
373 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF
374 #define lpfc_wcqe_c_hw_status_WORD word0
375 #define lpfc_wcqe_c_ersp0_SHIFT 0
376 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF
377 #define lpfc_wcqe_c_ersp0_WORD word0
378 uint32_t total_data_placed
;
380 #define lpfc_wcqe_c_bg_edir_SHIFT 5
381 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001
382 #define lpfc_wcqe_c_bg_edir_WORD parameter
383 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3
384 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001
385 #define lpfc_wcqe_c_bg_tdpv_WORD parameter
386 #define lpfc_wcqe_c_bg_re_SHIFT 2
387 #define lpfc_wcqe_c_bg_re_MASK 0x00000001
388 #define lpfc_wcqe_c_bg_re_WORD parameter
389 #define lpfc_wcqe_c_bg_ae_SHIFT 1
390 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001
391 #define lpfc_wcqe_c_bg_ae_WORD parameter
392 #define lpfc_wcqe_c_bg_ge_SHIFT 0
393 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001
394 #define lpfc_wcqe_c_bg_ge_WORD parameter
396 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT
397 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK
398 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD
399 #define lpfc_wcqe_c_xb_SHIFT 28
400 #define lpfc_wcqe_c_xb_MASK 0x00000001
401 #define lpfc_wcqe_c_xb_WORD word3
402 #define lpfc_wcqe_c_pv_SHIFT 27
403 #define lpfc_wcqe_c_pv_MASK 0x00000001
404 #define lpfc_wcqe_c_pv_WORD word3
405 #define lpfc_wcqe_c_priority_SHIFT 24
406 #define lpfc_wcqe_c_priority_MASK 0x00000007
407 #define lpfc_wcqe_c_priority_WORD word3
408 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT
409 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK
410 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD
411 #define lpfc_wcqe_c_sqhead_SHIFT 0
412 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF
413 #define lpfc_wcqe_c_sqhead_WORD word3
416 /* completion queue entry for wqe release */
417 struct lpfc_wcqe_release
{
421 #define lpfc_wcqe_r_wq_id_SHIFT 16
422 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
423 #define lpfc_wcqe_r_wq_id_WORD word2
424 #define lpfc_wcqe_r_wqe_index_SHIFT 0
425 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
426 #define lpfc_wcqe_r_wqe_index_WORD word2
428 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT
429 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK
430 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD
431 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT
432 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK
433 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD
436 struct sli4_wcqe_xri_aborted
{
438 #define lpfc_wcqe_xa_status_SHIFT 8
439 #define lpfc_wcqe_xa_status_MASK 0x000000FF
440 #define lpfc_wcqe_xa_status_WORD word0
443 #define lpfc_wcqe_xa_remote_xid_SHIFT 16
444 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
445 #define lpfc_wcqe_xa_remote_xid_WORD word2
446 #define lpfc_wcqe_xa_xri_SHIFT 0
447 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
448 #define lpfc_wcqe_xa_xri_WORD word2
450 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT
451 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK
452 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD
453 #define lpfc_wcqe_xa_ia_SHIFT 30
454 #define lpfc_wcqe_xa_ia_MASK 0x00000001
455 #define lpfc_wcqe_xa_ia_WORD word3
456 #define CQE_XRI_ABORTED_IA_REMOTE 0
457 #define CQE_XRI_ABORTED_IA_LOCAL 1
458 #define lpfc_wcqe_xa_br_SHIFT 29
459 #define lpfc_wcqe_xa_br_MASK 0x00000001
460 #define lpfc_wcqe_xa_br_WORD word3
461 #define CQE_XRI_ABORTED_BR_BA_ACC 0
462 #define CQE_XRI_ABORTED_BR_BA_RJT 1
463 #define lpfc_wcqe_xa_eo_SHIFT 28
464 #define lpfc_wcqe_xa_eo_MASK 0x00000001
465 #define lpfc_wcqe_xa_eo_WORD word3
466 #define CQE_XRI_ABORTED_EO_REMOTE 0
467 #define CQE_XRI_ABORTED_EO_LOCAL 1
468 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT
469 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK
470 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD
473 /* completion queue entry structure for rqe completion */
476 #define lpfc_rcqe_bindex_SHIFT 16
477 #define lpfc_rcqe_bindex_MASK 0x0000FFF
478 #define lpfc_rcqe_bindex_WORD word0
479 #define lpfc_rcqe_status_SHIFT 8
480 #define lpfc_rcqe_status_MASK 0x000000FF
481 #define lpfc_rcqe_status_WORD word0
482 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
483 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
484 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
485 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
487 #define lpfc_rcqe_fcf_id_v1_SHIFT 0
488 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F
489 #define lpfc_rcqe_fcf_id_v1_WORD word1
491 #define lpfc_rcqe_length_SHIFT 16
492 #define lpfc_rcqe_length_MASK 0x0000FFFF
493 #define lpfc_rcqe_length_WORD word2
494 #define lpfc_rcqe_rq_id_SHIFT 6
495 #define lpfc_rcqe_rq_id_MASK 0x000003FF
496 #define lpfc_rcqe_rq_id_WORD word2
497 #define lpfc_rcqe_fcf_id_SHIFT 0
498 #define lpfc_rcqe_fcf_id_MASK 0x0000003F
499 #define lpfc_rcqe_fcf_id_WORD word2
500 #define lpfc_rcqe_rq_id_v1_SHIFT 0
501 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF
502 #define lpfc_rcqe_rq_id_v1_WORD word2
504 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT
505 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK
506 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD
507 #define lpfc_rcqe_port_SHIFT 30
508 #define lpfc_rcqe_port_MASK 0x00000001
509 #define lpfc_rcqe_port_WORD word3
510 #define lpfc_rcqe_hdr_length_SHIFT 24
511 #define lpfc_rcqe_hdr_length_MASK 0x0000001F
512 #define lpfc_rcqe_hdr_length_WORD word3
513 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT
514 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK
515 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD
516 #define lpfc_rcqe_eof_SHIFT 8
517 #define lpfc_rcqe_eof_MASK 0x000000FF
518 #define lpfc_rcqe_eof_WORD word3
519 #define FCOE_EOFn 0x41
520 #define FCOE_EOFt 0x42
521 #define FCOE_EOFni 0x49
522 #define FCOE_EOFa 0x50
523 #define lpfc_rcqe_sof_SHIFT 0
524 #define lpfc_rcqe_sof_MASK 0x000000FF
525 #define lpfc_rcqe_sof_WORD word3
526 #define FCOE_SOFi2 0x2d
527 #define FCOE_SOFi3 0x2e
528 #define FCOE_SOFn2 0x35
529 #define FCOE_SOFn3 0x36
537 /* buffer descriptors */
542 #define lpfc_bde4_last_SHIFT 31
543 #define lpfc_bde4_last_MASK 0x00000001
544 #define lpfc_bde4_last_WORD word2
545 #define lpfc_bde4_sge_offset_SHIFT 0
546 #define lpfc_bde4_sge_offset_MASK 0x000003FF
547 #define lpfc_bde4_sge_offset_WORD word2
549 #define lpfc_bde4_length_SHIFT 0
550 #define lpfc_bde4_length_MASK 0x000000FF
551 #define lpfc_bde4_length_WORD word3
554 struct lpfc_register
{
558 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000
559 #define LPFC_PORT_SEM_MASK 0xF000
560 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
561 #define LPFC_UERR_STATUS_HI 0x00A4
562 #define LPFC_UERR_STATUS_LO 0x00A0
563 #define LPFC_UE_MASK_HI 0x00AC
564 #define LPFC_UE_MASK_LO 0x00A8
566 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
567 #define LPFC_SLI_INTF 0x0058
569 #define LPFC_CTL_PORT_SEM_OFFSET 0x400
570 #define lpfc_port_smphr_perr_SHIFT 31
571 #define lpfc_port_smphr_perr_MASK 0x1
572 #define lpfc_port_smphr_perr_WORD word0
573 #define lpfc_port_smphr_sfi_SHIFT 30
574 #define lpfc_port_smphr_sfi_MASK 0x1
575 #define lpfc_port_smphr_sfi_WORD word0
576 #define lpfc_port_smphr_nip_SHIFT 29
577 #define lpfc_port_smphr_nip_MASK 0x1
578 #define lpfc_port_smphr_nip_WORD word0
579 #define lpfc_port_smphr_ipc_SHIFT 28
580 #define lpfc_port_smphr_ipc_MASK 0x1
581 #define lpfc_port_smphr_ipc_WORD word0
582 #define lpfc_port_smphr_scr1_SHIFT 27
583 #define lpfc_port_smphr_scr1_MASK 0x1
584 #define lpfc_port_smphr_scr1_WORD word0
585 #define lpfc_port_smphr_scr2_SHIFT 26
586 #define lpfc_port_smphr_scr2_MASK 0x1
587 #define lpfc_port_smphr_scr2_WORD word0
588 #define lpfc_port_smphr_host_scratch_SHIFT 16
589 #define lpfc_port_smphr_host_scratch_MASK 0xFF
590 #define lpfc_port_smphr_host_scratch_WORD word0
591 #define lpfc_port_smphr_port_status_SHIFT 0
592 #define lpfc_port_smphr_port_status_MASK 0xFFFF
593 #define lpfc_port_smphr_port_status_WORD word0
595 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
596 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
597 #define LPFC_POST_STAGE_HOST_RDY 0x0002
598 #define LPFC_POST_STAGE_BE_RESET 0x0003
599 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
600 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
601 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
602 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
603 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
604 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
605 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400
606 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
607 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
608 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
609 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
610 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
611 #define LPFC_POST_STAGE_ARMFW_START 0x0800
612 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
613 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
614 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
615 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
616 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
617 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
618 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
619 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
620 #define LPFC_POST_STAGE_PARSE_XML 0x0B04
621 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
622 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
623 #define LPFC_POST_STAGE_RC_DONE 0x0B07
624 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
625 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
626 #define LPFC_POST_STAGE_PORT_READY 0xC000
627 #define LPFC_POST_STAGE_PORT_UE 0xF000
629 #define LPFC_CTL_PORT_STA_OFFSET 0x404
630 #define lpfc_sliport_status_err_SHIFT 31
631 #define lpfc_sliport_status_err_MASK 0x1
632 #define lpfc_sliport_status_err_WORD word0
633 #define lpfc_sliport_status_end_SHIFT 30
634 #define lpfc_sliport_status_end_MASK 0x1
635 #define lpfc_sliport_status_end_WORD word0
636 #define lpfc_sliport_status_oti_SHIFT 29
637 #define lpfc_sliport_status_oti_MASK 0x1
638 #define lpfc_sliport_status_oti_WORD word0
639 #define lpfc_sliport_status_rn_SHIFT 24
640 #define lpfc_sliport_status_rn_MASK 0x1
641 #define lpfc_sliport_status_rn_WORD word0
642 #define lpfc_sliport_status_rdy_SHIFT 23
643 #define lpfc_sliport_status_rdy_MASK 0x1
644 #define lpfc_sliport_status_rdy_WORD word0
645 #define MAX_IF_TYPE_2_RESETS 6
647 #define LPFC_CTL_PORT_CTL_OFFSET 0x408
648 #define lpfc_sliport_ctrl_end_SHIFT 30
649 #define lpfc_sliport_ctrl_end_MASK 0x1
650 #define lpfc_sliport_ctrl_end_WORD word0
651 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
652 #define LPFC_SLIPORT_BIG_ENDIAN 1
653 #define lpfc_sliport_ctrl_ip_SHIFT 27
654 #define lpfc_sliport_ctrl_ip_MASK 0x1
655 #define lpfc_sliport_ctrl_ip_WORD word0
656 #define LPFC_SLIPORT_INIT_PORT 1
658 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C
659 #define LPFC_CTL_PORT_ER2_OFFSET 0x410
661 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418
662 #define lpfc_sliport_eqdelay_delay_SHIFT 16
663 #define lpfc_sliport_eqdelay_delay_MASK 0xffff
664 #define lpfc_sliport_eqdelay_delay_WORD word0
665 #define lpfc_sliport_eqdelay_id_SHIFT 0
666 #define lpfc_sliport_eqdelay_id_MASK 0xfff
667 #define lpfc_sliport_eqdelay_id_WORD word0
668 #define LPFC_SEC_TO_USEC 1000000
670 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
673 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC
675 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF
676 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
678 #define LPFC_HST_ISR0 0x0C18
679 #define LPFC_HST_ISR1 0x0C1C
680 #define LPFC_HST_ISR2 0x0C20
681 #define LPFC_HST_ISR3 0x0C24
682 #define LPFC_HST_ISR4 0x0C28
684 #define LPFC_HST_IMR0 0x0C48
685 #define LPFC_HST_IMR1 0x0C4C
686 #define LPFC_HST_IMR2 0x0C50
687 #define LPFC_HST_IMR3 0x0C54
688 #define LPFC_HST_IMR4 0x0C58
690 #define LPFC_HST_ISCR0 0x0C78
691 #define LPFC_HST_ISCR1 0x0C7C
692 #define LPFC_HST_ISCR2 0x0C80
693 #define LPFC_HST_ISCR3 0x0C84
694 #define LPFC_HST_ISCR4 0x0C88
696 #define LPFC_SLI4_INTR0 BIT0
697 #define LPFC_SLI4_INTR1 BIT1
698 #define LPFC_SLI4_INTR2 BIT2
699 #define LPFC_SLI4_INTR3 BIT3
700 #define LPFC_SLI4_INTR4 BIT4
701 #define LPFC_SLI4_INTR5 BIT5
702 #define LPFC_SLI4_INTR6 BIT6
703 #define LPFC_SLI4_INTR7 BIT7
704 #define LPFC_SLI4_INTR8 BIT8
705 #define LPFC_SLI4_INTR9 BIT9
706 #define LPFC_SLI4_INTR10 BIT10
707 #define LPFC_SLI4_INTR11 BIT11
708 #define LPFC_SLI4_INTR12 BIT12
709 #define LPFC_SLI4_INTR13 BIT13
710 #define LPFC_SLI4_INTR14 BIT14
711 #define LPFC_SLI4_INTR15 BIT15
712 #define LPFC_SLI4_INTR16 BIT16
713 #define LPFC_SLI4_INTR17 BIT17
714 #define LPFC_SLI4_INTR18 BIT18
715 #define LPFC_SLI4_INTR19 BIT19
716 #define LPFC_SLI4_INTR20 BIT20
717 #define LPFC_SLI4_INTR21 BIT21
718 #define LPFC_SLI4_INTR22 BIT22
719 #define LPFC_SLI4_INTR23 BIT23
720 #define LPFC_SLI4_INTR24 BIT24
721 #define LPFC_SLI4_INTR25 BIT25
722 #define LPFC_SLI4_INTR26 BIT26
723 #define LPFC_SLI4_INTR27 BIT27
724 #define LPFC_SLI4_INTR28 BIT28
725 #define LPFC_SLI4_INTR29 BIT29
726 #define LPFC_SLI4_INTR30 BIT30
727 #define LPFC_SLI4_INTR31 BIT31
730 * The Doorbell registers defined here exist in different BAR
731 * register sets depending on the UCNA Port's reported if_type
732 * value. For UCNA ports running SLI4 and if_type 0, they reside in
733 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in
734 * BAR0. The offsets are the same so the driver must account for
735 * any base address difference.
737 #define LPFC_ULP0_RQ_DOORBELL 0x00A0
738 #define LPFC_ULP1_RQ_DOORBELL 0x00C0
739 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24
740 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF
741 #define lpfc_rq_db_list_fm_num_posted_WORD word0
742 #define lpfc_rq_db_list_fm_index_SHIFT 16
743 #define lpfc_rq_db_list_fm_index_MASK 0x00FF
744 #define lpfc_rq_db_list_fm_index_WORD word0
745 #define lpfc_rq_db_list_fm_id_SHIFT 0
746 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF
747 #define lpfc_rq_db_list_fm_id_WORD word0
748 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16
749 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF
750 #define lpfc_rq_db_ring_fm_num_posted_WORD word0
751 #define lpfc_rq_db_ring_fm_id_SHIFT 0
752 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF
753 #define lpfc_rq_db_ring_fm_id_WORD word0
755 #define LPFC_ULP0_WQ_DOORBELL 0x0040
756 #define LPFC_ULP1_WQ_DOORBELL 0x0060
757 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24
758 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF
759 #define lpfc_wq_db_list_fm_num_posted_WORD word0
760 #define lpfc_wq_db_list_fm_index_SHIFT 16
761 #define lpfc_wq_db_list_fm_index_MASK 0x00FF
762 #define lpfc_wq_db_list_fm_index_WORD word0
763 #define lpfc_wq_db_list_fm_id_SHIFT 0
764 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF
765 #define lpfc_wq_db_list_fm_id_WORD word0
766 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16
767 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF
768 #define lpfc_wq_db_ring_fm_num_posted_WORD word0
769 #define lpfc_wq_db_ring_fm_id_SHIFT 0
770 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF
771 #define lpfc_wq_db_ring_fm_id_WORD word0
773 #define LPFC_EQCQ_DOORBELL 0x0120
774 #define lpfc_eqcq_doorbell_se_SHIFT 31
775 #define lpfc_eqcq_doorbell_se_MASK 0x0001
776 #define lpfc_eqcq_doorbell_se_WORD word0
777 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
778 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1
779 #define lpfc_eqcq_doorbell_arm_SHIFT 29
780 #define lpfc_eqcq_doorbell_arm_MASK 0x0001
781 #define lpfc_eqcq_doorbell_arm_WORD word0
782 #define lpfc_eqcq_doorbell_num_released_SHIFT 16
783 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
784 #define lpfc_eqcq_doorbell_num_released_WORD word0
785 #define lpfc_eqcq_doorbell_qt_SHIFT 10
786 #define lpfc_eqcq_doorbell_qt_MASK 0x0001
787 #define lpfc_eqcq_doorbell_qt_WORD word0
788 #define LPFC_QUEUE_TYPE_COMPLETION 0
789 #define LPFC_QUEUE_TYPE_EVENT 1
790 #define lpfc_eqcq_doorbell_eqci_SHIFT 9
791 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001
792 #define lpfc_eqcq_doorbell_eqci_WORD word0
793 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0
794 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF
795 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0
796 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11
797 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F
798 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0
799 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0
800 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF
801 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0
802 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11
803 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F
804 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0
805 #define LPFC_CQID_HI_FIELD_SHIFT 10
806 #define LPFC_EQID_HI_FIELD_SHIFT 9
808 #define LPFC_BMBX 0x0160
809 #define lpfc_bmbx_addr_SHIFT 2
810 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF
811 #define lpfc_bmbx_addr_WORD word0
812 #define lpfc_bmbx_hi_SHIFT 1
813 #define lpfc_bmbx_hi_MASK 0x0001
814 #define lpfc_bmbx_hi_WORD word0
815 #define lpfc_bmbx_rdy_SHIFT 0
816 #define lpfc_bmbx_rdy_MASK 0x0001
817 #define lpfc_bmbx_rdy_WORD word0
819 #define LPFC_MQ_DOORBELL 0x0140
820 #define lpfc_mq_doorbell_num_posted_SHIFT 16
821 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
822 #define lpfc_mq_doorbell_num_posted_WORD word0
823 #define lpfc_mq_doorbell_id_SHIFT 0
824 #define lpfc_mq_doorbell_id_MASK 0xFFFF
825 #define lpfc_mq_doorbell_id_WORD word0
827 struct lpfc_sli4_cfg_mhdr
{
829 #define lpfc_mbox_hdr_emb_SHIFT 0
830 #define lpfc_mbox_hdr_emb_MASK 0x00000001
831 #define lpfc_mbox_hdr_emb_WORD word1
832 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3
833 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
834 #define lpfc_mbox_hdr_sge_cnt_WORD word1
835 uint32_t payload_length
;
841 union lpfc_sli4_cfg_shdr
{
844 #define lpfc_mbox_hdr_opcode_SHIFT 0
845 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
846 #define lpfc_mbox_hdr_opcode_WORD word6
847 #define lpfc_mbox_hdr_subsystem_SHIFT 8
848 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
849 #define lpfc_mbox_hdr_subsystem_WORD word6
850 #define lpfc_mbox_hdr_port_number_SHIFT 16
851 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF
852 #define lpfc_mbox_hdr_port_number_WORD word6
853 #define lpfc_mbox_hdr_domain_SHIFT 24
854 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
855 #define lpfc_mbox_hdr_domain_WORD word6
857 uint32_t request_length
;
859 #define lpfc_mbox_hdr_version_SHIFT 0
860 #define lpfc_mbox_hdr_version_MASK 0x000000FF
861 #define lpfc_mbox_hdr_version_WORD word9
862 #define lpfc_mbox_hdr_pf_num_SHIFT 16
863 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF
864 #define lpfc_mbox_hdr_pf_num_WORD word9
865 #define lpfc_mbox_hdr_vh_num_SHIFT 24
866 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF
867 #define lpfc_mbox_hdr_vh_num_WORD word9
868 #define LPFC_Q_CREATE_VERSION_2 2
869 #define LPFC_Q_CREATE_VERSION_1 1
870 #define LPFC_Q_CREATE_VERSION_0 0
871 #define LPFC_OPCODE_VERSION_0 0
872 #define LPFC_OPCODE_VERSION_1 1
876 #define lpfc_mbox_hdr_opcode_SHIFT 0
877 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
878 #define lpfc_mbox_hdr_opcode_WORD word6
879 #define lpfc_mbox_hdr_subsystem_SHIFT 8
880 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
881 #define lpfc_mbox_hdr_subsystem_WORD word6
882 #define lpfc_mbox_hdr_domain_SHIFT 24
883 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
884 #define lpfc_mbox_hdr_domain_WORD word6
886 #define lpfc_mbox_hdr_status_SHIFT 0
887 #define lpfc_mbox_hdr_status_MASK 0x000000FF
888 #define lpfc_mbox_hdr_status_WORD word7
889 #define lpfc_mbox_hdr_add_status_SHIFT 8
890 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF
891 #define lpfc_mbox_hdr_add_status_WORD word7
892 uint32_t response_length
;
893 uint32_t actual_response_length
;
897 /* Mailbox Header structures.
898 * struct mbox_header is defined for first generation SLI4_CFG mailbox
899 * calls deployed for BE-based ports.
901 * struct sli4_mbox_header is defined for second generation SLI4
902 * ports that don't deploy the SLI4_CFG mechanism.
905 struct lpfc_sli4_cfg_mhdr cfg_mhdr
;
906 union lpfc_sli4_cfg_shdr cfg_shdr
;
909 #define LPFC_EXTENT_LOCAL 0
910 #define LPFC_TIMEOUT_DEFAULT 0
911 #define LPFC_EXTENT_VERSION_DEFAULT 0
913 /* Subsystem Definitions */
914 #define LPFC_MBOX_SUBSYSTEM_NA 0x0
915 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
916 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
918 /* Device Specific Definitions */
920 /* The HOST ENDIAN defines are in Big Endian format. */
921 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
922 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
925 #define LPFC_MBOX_OPCODE_NA 0x00
926 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
927 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
928 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
929 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
930 #define LPFC_MBOX_OPCODE_NOP 0x21
931 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29
932 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
933 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
934 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
935 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
936 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
937 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E
938 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43
939 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45
940 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46
941 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D
942 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A
943 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B
944 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D
945 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73
946 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74
947 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A
948 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B
949 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C
950 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D
951 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0
952 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1
953 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4
954 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5
955 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6
956 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8
957 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9
958 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB
959 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC
960 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD
961 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE
962 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5
963 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF
966 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
967 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
968 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
969 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
970 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
971 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
972 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
973 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
974 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
975 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
976 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10
977 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D
978 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21
979 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22
980 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23
982 /* Mailbox command structures */
985 #define lpfc_eq_context_size_SHIFT 31
986 #define lpfc_eq_context_size_MASK 0x00000001
987 #define lpfc_eq_context_size_WORD word0
988 #define LPFC_EQE_SIZE_4 0x0
989 #define LPFC_EQE_SIZE_16 0x1
990 #define lpfc_eq_context_valid_SHIFT 29
991 #define lpfc_eq_context_valid_MASK 0x00000001
992 #define lpfc_eq_context_valid_WORD word0
994 #define lpfc_eq_context_count_SHIFT 26
995 #define lpfc_eq_context_count_MASK 0x00000003
996 #define lpfc_eq_context_count_WORD word1
997 #define LPFC_EQ_CNT_256 0x0
998 #define LPFC_EQ_CNT_512 0x1
999 #define LPFC_EQ_CNT_1024 0x2
1000 #define LPFC_EQ_CNT_2048 0x3
1001 #define LPFC_EQ_CNT_4096 0x4
1003 #define lpfc_eq_context_delay_multi_SHIFT 13
1004 #define lpfc_eq_context_delay_multi_MASK 0x000003FF
1005 #define lpfc_eq_context_delay_multi_WORD word2
1009 struct eq_delay_info
{
1012 uint32_t delay_multi
;
1014 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8
1016 struct sgl_page_pairs
{
1017 uint32_t sgl_pg0_addr_lo
;
1018 uint32_t sgl_pg0_addr_hi
;
1019 uint32_t sgl_pg1_addr_lo
;
1020 uint32_t sgl_pg1_addr_hi
;
1023 struct lpfc_mbx_post_sgl_pages
{
1024 struct mbox_header header
;
1026 #define lpfc_post_sgl_pages_xri_SHIFT 0
1027 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
1028 #define lpfc_post_sgl_pages_xri_WORD word0
1029 #define lpfc_post_sgl_pages_xricnt_SHIFT 16
1030 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1031 #define lpfc_post_sgl_pages_xricnt_WORD word0
1032 struct sgl_page_pairs sgl_pg_pairs
[1];
1035 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
1036 struct lpfc_mbx_post_uembed_sgl_page1
{
1037 union lpfc_sli4_cfg_shdr cfg_shdr
;
1039 struct sgl_page_pairs sgl_pg_pairs
;
1042 struct lpfc_mbx_sge
{
1048 struct lpfc_mbx_nembed_cmd
{
1049 struct lpfc_sli4_cfg_mhdr cfg_mhdr
;
1050 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19
1051 struct lpfc_mbx_sge sge
[LPFC_SLI4_MBX_SGE_MAX_PAGES
];
1054 struct lpfc_mbx_nembed_sge_virt
{
1055 void *addr
[LPFC_SLI4_MBX_SGE_MAX_PAGES
];
1058 struct lpfc_mbx_eq_create
{
1059 struct mbox_header header
;
1063 #define lpfc_mbx_eq_create_num_pages_SHIFT 0
1064 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
1065 #define lpfc_mbx_eq_create_num_pages_WORD word0
1066 struct eq_context context
;
1067 struct dma_address page
[LPFC_MAX_EQ_PAGE
];
1071 #define lpfc_mbx_eq_create_q_id_SHIFT 0
1072 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
1073 #define lpfc_mbx_eq_create_q_id_WORD word0
1078 struct lpfc_mbx_modify_eq_delay
{
1079 struct mbox_header header
;
1083 struct eq_delay_info eq
[LPFC_MAX_EQ_DELAY_EQID_CNT
];
1091 struct lpfc_mbx_eq_destroy
{
1092 struct mbox_header header
;
1096 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0
1097 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
1098 #define lpfc_mbx_eq_destroy_q_id_WORD word0
1106 struct lpfc_mbx_nop
{
1107 struct mbox_header header
;
1108 uint32_t context
[2];
1113 #define lpfc_cq_context_event_SHIFT 31
1114 #define lpfc_cq_context_event_MASK 0x00000001
1115 #define lpfc_cq_context_event_WORD word0
1116 #define lpfc_cq_context_valid_SHIFT 29
1117 #define lpfc_cq_context_valid_MASK 0x00000001
1118 #define lpfc_cq_context_valid_WORD word0
1119 #define lpfc_cq_context_count_SHIFT 27
1120 #define lpfc_cq_context_count_MASK 0x00000003
1121 #define lpfc_cq_context_count_WORD word0
1122 #define LPFC_CQ_CNT_256 0x0
1123 #define LPFC_CQ_CNT_512 0x1
1124 #define LPFC_CQ_CNT_1024 0x2
1125 #define LPFC_CQ_CNT_WORD7 0x3
1127 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */
1128 #define lpfc_cq_eq_id_MASK 0x000000FF
1129 #define lpfc_cq_eq_id_WORD word1
1130 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */
1131 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF
1132 #define lpfc_cq_eq_id_2_WORD word1
1133 uint32_t lpfc_cq_context_count
; /* Version 2 Only */
1137 struct lpfc_mbx_cq_create
{
1138 struct mbox_header header
;
1142 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */
1143 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF
1144 #define lpfc_mbx_cq_create_page_size_WORD word0
1145 #define lpfc_mbx_cq_create_num_pages_SHIFT 0
1146 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
1147 #define lpfc_mbx_cq_create_num_pages_WORD word0
1148 struct cq_context context
;
1149 struct dma_address page
[LPFC_MAX_CQ_PAGE
];
1153 #define lpfc_mbx_cq_create_q_id_SHIFT 0
1154 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
1155 #define lpfc_mbx_cq_create_q_id_WORD word0
1160 struct lpfc_mbx_cq_create_set
{
1161 union lpfc_sli4_cfg_shdr cfg_shdr
;
1165 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */
1166 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF
1167 #define lpfc_mbx_cq_create_set_page_size_WORD word0
1168 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0
1169 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF
1170 #define lpfc_mbx_cq_create_set_num_pages_WORD word0
1172 #define lpfc_mbx_cq_create_set_evt_SHIFT 31
1173 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001
1174 #define lpfc_mbx_cq_create_set_evt_WORD word1
1175 #define lpfc_mbx_cq_create_set_valid_SHIFT 29
1176 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001
1177 #define lpfc_mbx_cq_create_set_valid_WORD word1
1178 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27
1179 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003
1180 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1
1181 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25
1182 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003
1183 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1
1184 #define lpfc_mbx_cq_create_set_auto_SHIFT 15
1185 #define lpfc_mbx_cq_create_set_auto_MASK 0x0000001
1186 #define lpfc_mbx_cq_create_set_auto_WORD word1
1187 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14
1188 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001
1189 #define lpfc_mbx_cq_create_set_nodelay_WORD word1
1190 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12
1191 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003
1192 #define lpfc_mbx_cq_create_set_clswm_WORD word1
1194 #define lpfc_mbx_cq_create_set_arm_SHIFT 31
1195 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001
1196 #define lpfc_mbx_cq_create_set_arm_WORD word2
1197 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16
1198 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF
1199 #define lpfc_mbx_cq_create_set_cq_cnt_WORD word2
1200 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0
1201 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF
1202 #define lpfc_mbx_cq_create_set_num_cq_WORD word2
1204 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16
1205 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF
1206 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3
1207 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0
1208 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF
1209 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3
1211 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16
1212 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF
1213 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4
1214 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0
1215 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF
1216 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4
1218 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16
1219 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF
1220 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5
1221 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0
1222 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF
1223 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5
1225 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16
1226 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF
1227 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6
1228 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0
1229 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF
1230 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6
1232 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16
1233 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF
1234 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7
1235 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0
1236 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF
1237 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7
1239 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16
1240 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF
1241 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8
1242 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0
1243 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF
1244 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8
1246 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16
1247 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF
1248 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9
1249 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0
1250 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF
1251 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9
1253 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16
1254 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF
1255 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10
1256 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0
1257 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF
1258 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10
1259 struct dma_address page
[1];
1263 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16
1264 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF
1265 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0
1266 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0
1267 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF
1268 #define lpfc_mbx_cq_create_set_base_id_WORD word0
1273 struct lpfc_mbx_cq_destroy
{
1274 struct mbox_header header
;
1278 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0
1279 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
1280 #define lpfc_mbx_cq_destroy_q_id_WORD word0
1295 struct lpfc_mbx_wq_create
{
1296 struct mbox_header header
;
1298 struct { /* Version 0 Request */
1300 #define lpfc_mbx_wq_create_num_pages_SHIFT 0
1301 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF
1302 #define lpfc_mbx_wq_create_num_pages_WORD word0
1303 #define lpfc_mbx_wq_create_dua_SHIFT 8
1304 #define lpfc_mbx_wq_create_dua_MASK 0x00000001
1305 #define lpfc_mbx_wq_create_dua_WORD word0
1306 #define lpfc_mbx_wq_create_cq_id_SHIFT 16
1307 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
1308 #define lpfc_mbx_wq_create_cq_id_WORD word0
1309 struct dma_address page
[LPFC_MAX_WQ_PAGE_V0
];
1311 #define lpfc_mbx_wq_create_bua_SHIFT 0
1312 #define lpfc_mbx_wq_create_bua_MASK 0x00000001
1313 #define lpfc_mbx_wq_create_bua_WORD word9
1314 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8
1315 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF
1316 #define lpfc_mbx_wq_create_ulp_num_WORD word9
1318 struct { /* Version 1 Request */
1319 uint32_t word0
; /* Word 0 is the same as in v0 */
1321 #define lpfc_mbx_wq_create_page_size_SHIFT 0
1322 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF
1323 #define lpfc_mbx_wq_create_page_size_WORD word1
1324 #define LPFC_WQ_PAGE_SIZE_4096 0x1
1325 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8
1326 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F
1327 #define lpfc_mbx_wq_create_wqe_size_WORD word1
1328 #define LPFC_WQ_WQE_SIZE_64 0x5
1329 #define LPFC_WQ_WQE_SIZE_128 0x6
1330 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16
1331 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF
1332 #define lpfc_mbx_wq_create_wqe_count_WORD word1
1334 struct dma_address page
[LPFC_MAX_WQ_PAGE
-1];
1338 #define lpfc_mbx_wq_create_q_id_SHIFT 0
1339 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
1340 #define lpfc_mbx_wq_create_q_id_WORD word0
1341 uint32_t doorbell_offset
;
1343 #define lpfc_mbx_wq_create_bar_set_SHIFT 0
1344 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF
1345 #define lpfc_mbx_wq_create_bar_set_WORD word2
1346 #define WQ_PCI_BAR_0_AND_1 0x00
1347 #define WQ_PCI_BAR_2_AND_3 0x01
1348 #define WQ_PCI_BAR_4_AND_5 0x02
1349 #define lpfc_mbx_wq_create_db_format_SHIFT 16
1350 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF
1351 #define lpfc_mbx_wq_create_db_format_WORD word2
1356 struct lpfc_mbx_wq_destroy
{
1357 struct mbox_header header
;
1361 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0
1362 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
1363 #define lpfc_mbx_wq_destroy_q_id_WORD word0
1371 #define LPFC_HDR_BUF_SIZE 128
1372 #define LPFC_DATA_BUF_SIZE 2048
1373 #define LPFC_NVMET_DATA_BUF_SIZE 128
1376 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */
1377 #define lpfc_rq_context_rqe_count_MASK 0x0000000F
1378 #define lpfc_rq_context_rqe_count_WORD word0
1379 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */
1380 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */
1381 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */
1382 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */
1383 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */
1384 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF
1385 #define lpfc_rq_context_rqe_count_1_WORD word0
1386 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */
1387 #define lpfc_rq_context_rqe_size_MASK 0x0000000F
1388 #define lpfc_rq_context_rqe_size_WORD word0
1389 #define LPFC_RQE_SIZE_8 2
1390 #define LPFC_RQE_SIZE_16 3
1391 #define LPFC_RQE_SIZE_32 4
1392 #define LPFC_RQE_SIZE_64 5
1393 #define LPFC_RQE_SIZE_128 6
1394 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */
1395 #define lpfc_rq_context_page_size_MASK 0x000000FF
1396 #define lpfc_rq_context_page_size_WORD word0
1397 #define LPFC_RQ_PAGE_SIZE_4096 0x1
1399 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */
1400 #define lpfc_rq_context_data_size_MASK 0x0000FFFF
1401 #define lpfc_rq_context_data_size_WORD word1
1402 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */
1403 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF
1404 #define lpfc_rq_context_hdr_size_WORD word1
1406 #define lpfc_rq_context_cq_id_SHIFT 16
1407 #define lpfc_rq_context_cq_id_MASK 0x000003FF
1408 #define lpfc_rq_context_cq_id_WORD word2
1409 #define lpfc_rq_context_buf_size_SHIFT 0
1410 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1411 #define lpfc_rq_context_buf_size_WORD word2
1412 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */
1413 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF
1414 #define lpfc_rq_context_base_cq_WORD word2
1415 uint32_t buffer_size
; /* Version 1 Only */
1418 struct lpfc_mbx_rq_create
{
1419 struct mbox_header header
;
1423 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1424 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1425 #define lpfc_mbx_rq_create_num_pages_WORD word0
1426 #define lpfc_mbx_rq_create_dua_SHIFT 16
1427 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1428 #define lpfc_mbx_rq_create_dua_WORD word0
1429 #define lpfc_mbx_rq_create_bqu_SHIFT 17
1430 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1431 #define lpfc_mbx_rq_create_bqu_WORD word0
1432 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24
1433 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1434 #define lpfc_mbx_rq_create_ulp_num_WORD word0
1435 struct rq_context context
;
1436 struct dma_address page
[LPFC_MAX_RQ_PAGE
];
1440 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16
1441 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1442 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0
1443 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1444 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1445 #define lpfc_mbx_rq_create_q_id_WORD word0
1446 uint32_t doorbell_offset
;
1448 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1449 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1450 #define lpfc_mbx_rq_create_bar_set_WORD word2
1451 #define lpfc_mbx_rq_create_db_format_SHIFT 16
1452 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1453 #define lpfc_mbx_rq_create_db_format_WORD word2
1458 struct lpfc_mbx_rq_create_v2
{
1459 union lpfc_sli4_cfg_shdr cfg_shdr
;
1463 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1464 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1465 #define lpfc_mbx_rq_create_num_pages_WORD word0
1466 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16
1467 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF
1468 #define lpfc_mbx_rq_create_rq_cnt_WORD word0
1469 #define lpfc_mbx_rq_create_dua_SHIFT 16
1470 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1471 #define lpfc_mbx_rq_create_dua_WORD word0
1472 #define lpfc_mbx_rq_create_bqu_SHIFT 17
1473 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1474 #define lpfc_mbx_rq_create_bqu_WORD word0
1475 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24
1476 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1477 #define lpfc_mbx_rq_create_ulp_num_WORD word0
1478 #define lpfc_mbx_rq_create_dim_SHIFT 29
1479 #define lpfc_mbx_rq_create_dim_MASK 0x00000001
1480 #define lpfc_mbx_rq_create_dim_WORD word0
1481 #define lpfc_mbx_rq_create_dfd_SHIFT 30
1482 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001
1483 #define lpfc_mbx_rq_create_dfd_WORD word0
1484 #define lpfc_mbx_rq_create_dnb_SHIFT 31
1485 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001
1486 #define lpfc_mbx_rq_create_dnb_WORD word0
1487 struct rq_context context
;
1488 struct dma_address page
[1];
1492 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16
1493 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1494 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0
1495 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1496 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1497 #define lpfc_mbx_rq_create_q_id_WORD word0
1498 uint32_t doorbell_offset
;
1500 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1501 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1502 #define lpfc_mbx_rq_create_bar_set_WORD word2
1503 #define lpfc_mbx_rq_create_db_format_SHIFT 16
1504 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1505 #define lpfc_mbx_rq_create_db_format_WORD word2
1510 struct lpfc_mbx_rq_destroy
{
1511 struct mbox_header header
;
1515 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1516 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1517 #define lpfc_mbx_rq_destroy_q_id_WORD word0
1527 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */
1528 #define lpfc_mq_context_cq_id_MASK 0x000003FF
1529 #define lpfc_mq_context_cq_id_WORD word0
1530 #define lpfc_mq_context_ring_size_SHIFT 16
1531 #define lpfc_mq_context_ring_size_MASK 0x0000000F
1532 #define lpfc_mq_context_ring_size_WORD word0
1533 #define LPFC_MQ_RING_SIZE_16 0x5
1534 #define LPFC_MQ_RING_SIZE_32 0x6
1535 #define LPFC_MQ_RING_SIZE_64 0x7
1536 #define LPFC_MQ_RING_SIZE_128 0x8
1538 #define lpfc_mq_context_valid_SHIFT 31
1539 #define lpfc_mq_context_valid_MASK 0x00000001
1540 #define lpfc_mq_context_valid_WORD word1
1545 struct lpfc_mbx_mq_create
{
1546 struct mbox_header header
;
1550 #define lpfc_mbx_mq_create_num_pages_SHIFT 0
1551 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1552 #define lpfc_mbx_mq_create_num_pages_WORD word0
1553 struct mq_context context
;
1554 struct dma_address page
[LPFC_MAX_MQ_PAGE
];
1558 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1559 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1560 #define lpfc_mbx_mq_create_q_id_WORD word0
1565 struct lpfc_mbx_mq_create_ext
{
1566 struct mbox_header header
;
1570 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0
1571 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF
1572 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0
1573 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */
1574 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF
1575 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0
1576 uint32_t async_evt_bmap
;
1577 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK
1578 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1579 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap
1580 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0
1581 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1
1582 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2
1583 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3
1584 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4
1585 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE
1586 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1587 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap
1588 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5
1589 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1590 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap
1591 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC
1592 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1593 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap
1594 #define LPFC_EVT_CODE_FC_NO_LINK 0x0
1595 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1
1596 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2
1597 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4
1598 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8
1599 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA
1600 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10
1601 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI
1602 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1603 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap
1604 struct mq_context context
;
1605 struct dma_address page
[LPFC_MAX_MQ_PAGE
];
1609 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1610 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1611 #define lpfc_mbx_mq_create_q_id_WORD word0
1614 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2
1615 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4
1616 #define LPFC_ASYNC_EVENT_GROUP5 0x20
1619 struct lpfc_mbx_mq_destroy
{
1620 struct mbox_header header
;
1624 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1625 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1626 #define lpfc_mbx_mq_destroy_q_id_WORD word0
1634 /* Start Gen 2 SLI4 Mailbox definitions: */
1636 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1637 #define LPFC_RSC_TYPE_FCOE_VFI 0x20
1638 #define LPFC_RSC_TYPE_FCOE_VPI 0x21
1639 #define LPFC_RSC_TYPE_FCOE_RPI 0x22
1640 #define LPFC_RSC_TYPE_FCOE_XRI 0x23
1642 struct lpfc_mbx_get_rsrc_extent_info
{
1643 struct mbox_header header
;
1647 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0
1648 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF
1649 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4
1653 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0
1654 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF
1655 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4
1656 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16
1657 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF
1658 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4
1663 struct lpfc_mbx_query_fw_config
{
1664 struct mbox_header header
;
1666 uint32_t config_number
;
1667 #define LPFC_FC_FCOE 0x00000007
1668 uint32_t asic_revision
;
1669 uint32_t physical_port
;
1670 uint32_t function_mode
;
1671 #define LPFC_FCOE_INI_MODE 0x00000040
1672 #define LPFC_FCOE_TGT_MODE 0x00000080
1673 #define LPFC_DUA_MODE 0x00000800
1675 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1676 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080
1677 uint32_t ulp0_nap_words
[12];
1679 uint32_t ulp1_nap_words
[12];
1680 uint32_t function_capabilities
;
1685 uint32_t ulp0_nap2_words
[2];
1686 uint32_t ulp1_nap2_words
[2];
1690 struct lpfc_mbx_set_beacon_config
{
1691 struct mbox_header header
;
1693 #define lpfc_mbx_set_beacon_port_num_SHIFT 0
1694 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F
1695 #define lpfc_mbx_set_beacon_port_num_WORD word4
1696 #define lpfc_mbx_set_beacon_port_type_SHIFT 6
1697 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003
1698 #define lpfc_mbx_set_beacon_port_type_WORD word4
1699 #define lpfc_mbx_set_beacon_state_SHIFT 8
1700 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF
1701 #define lpfc_mbx_set_beacon_state_WORD word4
1702 #define lpfc_mbx_set_beacon_duration_SHIFT 16
1703 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF
1704 #define lpfc_mbx_set_beacon_duration_WORD word4
1705 #define lpfc_mbx_set_beacon_status_duration_SHIFT 24
1706 #define lpfc_mbx_set_beacon_status_duration_MASK 0x000000FF
1707 #define lpfc_mbx_set_beacon_status_duration_WORD word4
1710 struct lpfc_id_range
{
1712 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
1713 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF
1714 #define lpfc_mbx_rsrc_id_word4_0_WORD word5
1715 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16
1716 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF
1717 #define lpfc_mbx_rsrc_id_word4_1_WORD word5
1720 struct lpfc_mbx_set_link_diag_state
{
1721 struct mbox_header header
;
1725 #define lpfc_mbx_set_diag_state_diag_SHIFT 0
1726 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001
1727 #define lpfc_mbx_set_diag_state_diag_WORD word0
1728 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2
1729 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001
1730 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0
1731 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0
1732 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1
1733 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16
1734 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F
1735 #define lpfc_mbx_set_diag_state_link_num_WORD word0
1736 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1737 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003
1738 #define lpfc_mbx_set_diag_state_link_type_WORD word0
1746 struct lpfc_mbx_set_link_diag_loopback
{
1747 struct mbox_header header
;
1751 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0
1752 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003
1753 #define lpfc_mbx_set_diag_lpbk_type_WORD word0
1754 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0
1755 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1
1756 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2
1757 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16
1758 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F
1759 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0
1760 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22
1761 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003
1762 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0
1770 struct lpfc_mbx_run_link_diag_test
{
1771 struct mbox_header header
;
1775 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16
1776 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F
1777 #define lpfc_mbx_run_diag_test_link_num_WORD word0
1778 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22
1779 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003
1780 #define lpfc_mbx_run_diag_test_link_type_WORD word0
1782 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0
1783 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF
1784 #define lpfc_mbx_run_diag_test_test_id_WORD word1
1785 #define lpfc_mbx_run_diag_test_loops_SHIFT 16
1786 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF
1787 #define lpfc_mbx_run_diag_test_loops_WORD word1
1789 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0
1790 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF
1791 #define lpfc_mbx_run_diag_test_test_ver_WORD word2
1792 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16
1793 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF
1794 #define lpfc_mbx_run_diag_test_err_act_WORD word2
1803 * struct lpfc_mbx_alloc_rsrc_extents:
1804 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
1805 * 6 words of header + 4 words of shared subcommand header +
1806 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
1808 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
1809 * for extents payload.
1811 * 212/2 (bytes per extent) = 106 extents.
1812 * 106/2 (extents per word) = 53 words.
1813 * lpfc_id_range id is statically size to 53.
1815 * This mailbox definition is used for ALLOC or GET_ALLOCATED
1816 * extent ranges. For ALLOC, the type and cnt are required.
1817 * For GET_ALLOCATED, only the type is required.
1819 struct lpfc_mbx_alloc_rsrc_extents
{
1820 struct mbox_header header
;
1824 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0
1825 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF
1826 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4
1827 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16
1828 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF
1829 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4
1833 #define lpfc_mbx_rsrc_cnt_SHIFT 0
1834 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF
1835 #define lpfc_mbx_rsrc_cnt_WORD word4
1836 struct lpfc_id_range id
[53];
1842 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
1843 * structure shares the same SHIFT/MASK/WORD defines provided in the
1844 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
1845 * the structures defined above. This non-embedded structure provides for the
1846 * maximum number of extents supported by the port.
1848 struct lpfc_mbx_nembed_rsrc_extent
{
1849 union lpfc_sli4_cfg_shdr cfg_shdr
;
1851 struct lpfc_id_range id
;
1854 struct lpfc_mbx_dealloc_rsrc_extents
{
1855 struct mbox_header header
;
1858 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0
1859 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF
1860 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4
1865 /* Start SLI4 FCoE specific mbox structures. */
1867 struct lpfc_mbx_post_hdr_tmpl
{
1868 struct mbox_header header
;
1870 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
1871 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
1872 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10
1873 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16
1874 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
1875 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10
1876 uint32_t rpi_paddr_lo
;
1877 uint32_t rpi_paddr_hi
;
1880 struct sli4_sge
{ /* SLI-4 */
1885 #define lpfc_sli4_sge_offset_SHIFT 0
1886 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF
1887 #define lpfc_sli4_sge_offset_WORD word2
1888 #define lpfc_sli4_sge_type_SHIFT 27
1889 #define lpfc_sli4_sge_type_MASK 0x0000000F
1890 #define lpfc_sli4_sge_type_WORD word2
1891 #define LPFC_SGE_TYPE_DATA 0x0
1892 #define LPFC_SGE_TYPE_DIF 0x4
1893 #define LPFC_SGE_TYPE_LSP 0x5
1894 #define LPFC_SGE_TYPE_PEDIF 0x6
1895 #define LPFC_SGE_TYPE_PESEED 0x7
1896 #define LPFC_SGE_TYPE_DISEED 0x8
1897 #define LPFC_SGE_TYPE_ENC 0x9
1898 #define LPFC_SGE_TYPE_ATM 0xA
1899 #define LPFC_SGE_TYPE_SKIP 0xC
1900 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */
1901 #define lpfc_sli4_sge_last_MASK 0x00000001
1902 #define lpfc_sli4_sge_last_WORD word2
1906 struct sli4_sge_diseed
{ /* SLI-4 */
1908 uint32_t ref_tag_tran
;
1911 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
1912 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF
1913 #define lpfc_sli4_sge_dif_apptran_WORD word2
1914 #define lpfc_sli4_sge_dif_af_SHIFT 24
1915 #define lpfc_sli4_sge_dif_af_MASK 0x00000001
1916 #define lpfc_sli4_sge_dif_af_WORD word2
1917 #define lpfc_sli4_sge_dif_na_SHIFT 25
1918 #define lpfc_sli4_sge_dif_na_MASK 0x00000001
1919 #define lpfc_sli4_sge_dif_na_WORD word2
1920 #define lpfc_sli4_sge_dif_hi_SHIFT 26
1921 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001
1922 #define lpfc_sli4_sge_dif_hi_WORD word2
1923 #define lpfc_sli4_sge_dif_type_SHIFT 27
1924 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F
1925 #define lpfc_sli4_sge_dif_type_WORD word2
1926 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */
1927 #define lpfc_sli4_sge_dif_last_MASK 0x00000001
1928 #define lpfc_sli4_sge_dif_last_WORD word2
1930 #define lpfc_sli4_sge_dif_apptag_SHIFT 0
1931 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF
1932 #define lpfc_sli4_sge_dif_apptag_WORD word3
1933 #define lpfc_sli4_sge_dif_bs_SHIFT 16
1934 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007
1935 #define lpfc_sli4_sge_dif_bs_WORD word3
1936 #define lpfc_sli4_sge_dif_ai_SHIFT 19
1937 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001
1938 #define lpfc_sli4_sge_dif_ai_WORD word3
1939 #define lpfc_sli4_sge_dif_me_SHIFT 20
1940 #define lpfc_sli4_sge_dif_me_MASK 0x00000001
1941 #define lpfc_sli4_sge_dif_me_WORD word3
1942 #define lpfc_sli4_sge_dif_re_SHIFT 21
1943 #define lpfc_sli4_sge_dif_re_MASK 0x00000001
1944 #define lpfc_sli4_sge_dif_re_WORD word3
1945 #define lpfc_sli4_sge_dif_ce_SHIFT 22
1946 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001
1947 #define lpfc_sli4_sge_dif_ce_WORD word3
1948 #define lpfc_sli4_sge_dif_nr_SHIFT 23
1949 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001
1950 #define lpfc_sli4_sge_dif_nr_WORD word3
1951 #define lpfc_sli4_sge_dif_oprx_SHIFT 24
1952 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F
1953 #define lpfc_sli4_sge_dif_oprx_WORD word3
1954 #define lpfc_sli4_sge_dif_optx_SHIFT 28
1955 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F
1956 #define lpfc_sli4_sge_dif_optx_WORD word3
1957 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
1961 uint32_t max_rcv_size
;
1962 uint32_t fka_adv_period
;
1963 uint32_t fip_priority
;
1965 #define lpfc_fcf_record_mac_0_SHIFT 0
1966 #define lpfc_fcf_record_mac_0_MASK 0x000000FF
1967 #define lpfc_fcf_record_mac_0_WORD word3
1968 #define lpfc_fcf_record_mac_1_SHIFT 8
1969 #define lpfc_fcf_record_mac_1_MASK 0x000000FF
1970 #define lpfc_fcf_record_mac_1_WORD word3
1971 #define lpfc_fcf_record_mac_2_SHIFT 16
1972 #define lpfc_fcf_record_mac_2_MASK 0x000000FF
1973 #define lpfc_fcf_record_mac_2_WORD word3
1974 #define lpfc_fcf_record_mac_3_SHIFT 24
1975 #define lpfc_fcf_record_mac_3_MASK 0x000000FF
1976 #define lpfc_fcf_record_mac_3_WORD word3
1978 #define lpfc_fcf_record_mac_4_SHIFT 0
1979 #define lpfc_fcf_record_mac_4_MASK 0x000000FF
1980 #define lpfc_fcf_record_mac_4_WORD word4
1981 #define lpfc_fcf_record_mac_5_SHIFT 8
1982 #define lpfc_fcf_record_mac_5_MASK 0x000000FF
1983 #define lpfc_fcf_record_mac_5_WORD word4
1984 #define lpfc_fcf_record_fcf_avail_SHIFT 16
1985 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
1986 #define lpfc_fcf_record_fcf_avail_WORD word4
1987 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24
1988 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
1989 #define lpfc_fcf_record_mac_addr_prov_WORD word4
1990 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */
1991 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */
1993 #define lpfc_fcf_record_fab_name_0_SHIFT 0
1994 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
1995 #define lpfc_fcf_record_fab_name_0_WORD word5
1996 #define lpfc_fcf_record_fab_name_1_SHIFT 8
1997 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
1998 #define lpfc_fcf_record_fab_name_1_WORD word5
1999 #define lpfc_fcf_record_fab_name_2_SHIFT 16
2000 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
2001 #define lpfc_fcf_record_fab_name_2_WORD word5
2002 #define lpfc_fcf_record_fab_name_3_SHIFT 24
2003 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
2004 #define lpfc_fcf_record_fab_name_3_WORD word5
2006 #define lpfc_fcf_record_fab_name_4_SHIFT 0
2007 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
2008 #define lpfc_fcf_record_fab_name_4_WORD word6
2009 #define lpfc_fcf_record_fab_name_5_SHIFT 8
2010 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
2011 #define lpfc_fcf_record_fab_name_5_WORD word6
2012 #define lpfc_fcf_record_fab_name_6_SHIFT 16
2013 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
2014 #define lpfc_fcf_record_fab_name_6_WORD word6
2015 #define lpfc_fcf_record_fab_name_7_SHIFT 24
2016 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
2017 #define lpfc_fcf_record_fab_name_7_WORD word6
2019 #define lpfc_fcf_record_fc_map_0_SHIFT 0
2020 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
2021 #define lpfc_fcf_record_fc_map_0_WORD word7
2022 #define lpfc_fcf_record_fc_map_1_SHIFT 8
2023 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
2024 #define lpfc_fcf_record_fc_map_1_WORD word7
2025 #define lpfc_fcf_record_fc_map_2_SHIFT 16
2026 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
2027 #define lpfc_fcf_record_fc_map_2_WORD word7
2028 #define lpfc_fcf_record_fcf_valid_SHIFT 24
2029 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001
2030 #define lpfc_fcf_record_fcf_valid_WORD word7
2031 #define lpfc_fcf_record_fcf_fc_SHIFT 25
2032 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001
2033 #define lpfc_fcf_record_fcf_fc_WORD word7
2034 #define lpfc_fcf_record_fcf_sol_SHIFT 31
2035 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001
2036 #define lpfc_fcf_record_fcf_sol_WORD word7
2038 #define lpfc_fcf_record_fcf_index_SHIFT 0
2039 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
2040 #define lpfc_fcf_record_fcf_index_WORD word8
2041 #define lpfc_fcf_record_fcf_state_SHIFT 16
2042 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
2043 #define lpfc_fcf_record_fcf_state_WORD word8
2044 uint8_t vlan_bitmap
[512];
2046 #define lpfc_fcf_record_switch_name_0_SHIFT 0
2047 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
2048 #define lpfc_fcf_record_switch_name_0_WORD word137
2049 #define lpfc_fcf_record_switch_name_1_SHIFT 8
2050 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
2051 #define lpfc_fcf_record_switch_name_1_WORD word137
2052 #define lpfc_fcf_record_switch_name_2_SHIFT 16
2053 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
2054 #define lpfc_fcf_record_switch_name_2_WORD word137
2055 #define lpfc_fcf_record_switch_name_3_SHIFT 24
2056 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
2057 #define lpfc_fcf_record_switch_name_3_WORD word137
2059 #define lpfc_fcf_record_switch_name_4_SHIFT 0
2060 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
2061 #define lpfc_fcf_record_switch_name_4_WORD word138
2062 #define lpfc_fcf_record_switch_name_5_SHIFT 8
2063 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
2064 #define lpfc_fcf_record_switch_name_5_WORD word138
2065 #define lpfc_fcf_record_switch_name_6_SHIFT 16
2066 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
2067 #define lpfc_fcf_record_switch_name_6_WORD word138
2068 #define lpfc_fcf_record_switch_name_7_SHIFT 24
2069 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
2070 #define lpfc_fcf_record_switch_name_7_WORD word138
2073 struct lpfc_mbx_read_fcf_tbl
{
2074 union lpfc_sli4_cfg_shdr cfg_shdr
;
2078 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
2079 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
2080 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10
2087 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
2088 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
2089 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11
2092 struct lpfc_mbx_add_fcf_tbl_entry
{
2093 union lpfc_sli4_cfg_shdr cfg_shdr
;
2095 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
2096 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
2097 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10
2098 struct lpfc_mbx_sge fcf_sge
;
2101 struct lpfc_mbx_del_fcf_tbl_entry
{
2102 struct mbox_header header
;
2104 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
2105 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
2106 #define lpfc_mbx_del_fcf_tbl_count_WORD word10
2107 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16
2108 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
2109 #define lpfc_mbx_del_fcf_tbl_index_WORD word10
2112 struct lpfc_mbx_redisc_fcf_tbl
{
2113 struct mbox_header header
;
2115 #define lpfc_mbx_redisc_fcf_count_SHIFT 0
2116 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF
2117 #define lpfc_mbx_redisc_fcf_count_WORD word10
2120 #define lpfc_mbx_redisc_fcf_index_SHIFT 0
2121 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF
2122 #define lpfc_mbx_redisc_fcf_index_WORD word12
2125 /* Status field for embedded SLI_CONFIG mailbox command */
2126 #define STATUS_SUCCESS 0x0
2127 #define STATUS_FAILED 0x1
2128 #define STATUS_ILLEGAL_REQUEST 0x2
2129 #define STATUS_ILLEGAL_FIELD 0x3
2130 #define STATUS_INSUFFICIENT_BUFFER 0x4
2131 #define STATUS_UNAUTHORIZED_REQUEST 0x5
2132 #define STATUS_FLASHROM_SAVE_FAILED 0x17
2133 #define STATUS_FLASHROM_RESTORE_FAILED 0x18
2134 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
2135 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
2136 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
2137 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
2138 #define STATUS_ASSERT_FAILED 0x1e
2139 #define STATUS_INVALID_SESSION 0x1f
2140 #define STATUS_INVALID_CONNECTION 0x20
2141 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
2142 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
2143 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
2144 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
2145 #define STATUS_FLASHROM_READ_FAILED 0x27
2146 #define STATUS_POLL_IOCTL_TIMEOUT 0x28
2147 #define STATUS_ERROR_ACITMAIN 0x2a
2148 #define STATUS_REBOOT_REQUIRED 0x2c
2149 #define STATUS_FCF_IN_USE 0x3a
2150 #define STATUS_FCF_TABLE_EMPTY 0x43
2153 * Additional status field for embedded SLI_CONFIG mailbox
2156 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67
2158 struct lpfc_mbx_sli4_config
{
2159 struct mbox_header header
;
2162 struct lpfc_mbx_init_vfi
{
2164 #define lpfc_init_vfi_vr_SHIFT 31
2165 #define lpfc_init_vfi_vr_MASK 0x00000001
2166 #define lpfc_init_vfi_vr_WORD word1
2167 #define lpfc_init_vfi_vt_SHIFT 30
2168 #define lpfc_init_vfi_vt_MASK 0x00000001
2169 #define lpfc_init_vfi_vt_WORD word1
2170 #define lpfc_init_vfi_vf_SHIFT 29
2171 #define lpfc_init_vfi_vf_MASK 0x00000001
2172 #define lpfc_init_vfi_vf_WORD word1
2173 #define lpfc_init_vfi_vp_SHIFT 28
2174 #define lpfc_init_vfi_vp_MASK 0x00000001
2175 #define lpfc_init_vfi_vp_WORD word1
2176 #define lpfc_init_vfi_vfi_SHIFT 0
2177 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF
2178 #define lpfc_init_vfi_vfi_WORD word1
2180 #define lpfc_init_vfi_vpi_SHIFT 16
2181 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF
2182 #define lpfc_init_vfi_vpi_WORD word2
2183 #define lpfc_init_vfi_fcfi_SHIFT 0
2184 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
2185 #define lpfc_init_vfi_fcfi_WORD word2
2187 #define lpfc_init_vfi_pri_SHIFT 13
2188 #define lpfc_init_vfi_pri_MASK 0x00000007
2189 #define lpfc_init_vfi_pri_WORD word3
2190 #define lpfc_init_vfi_vf_id_SHIFT 1
2191 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF
2192 #define lpfc_init_vfi_vf_id_WORD word3
2194 #define lpfc_init_vfi_hop_count_SHIFT 24
2195 #define lpfc_init_vfi_hop_count_MASK 0x000000FF
2196 #define lpfc_init_vfi_hop_count_WORD word4
2198 #define MBX_VFI_IN_USE 0x9F02
2201 struct lpfc_mbx_reg_vfi
{
2203 #define lpfc_reg_vfi_upd_SHIFT 29
2204 #define lpfc_reg_vfi_upd_MASK 0x00000001
2205 #define lpfc_reg_vfi_upd_WORD word1
2206 #define lpfc_reg_vfi_vp_SHIFT 28
2207 #define lpfc_reg_vfi_vp_MASK 0x00000001
2208 #define lpfc_reg_vfi_vp_WORD word1
2209 #define lpfc_reg_vfi_vfi_SHIFT 0
2210 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
2211 #define lpfc_reg_vfi_vfi_WORD word1
2213 #define lpfc_reg_vfi_vpi_SHIFT 16
2214 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
2215 #define lpfc_reg_vfi_vpi_WORD word2
2216 #define lpfc_reg_vfi_fcfi_SHIFT 0
2217 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
2218 #define lpfc_reg_vfi_fcfi_WORD word2
2220 struct ulp_bde64 bde
;
2224 #define lpfc_reg_vfi_nport_id_SHIFT 0
2225 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
2226 #define lpfc_reg_vfi_nport_id_WORD word10
2227 #define lpfc_reg_vfi_bbcr_SHIFT 27
2228 #define lpfc_reg_vfi_bbcr_MASK 0x00000001
2229 #define lpfc_reg_vfi_bbcr_WORD word10
2230 #define lpfc_reg_vfi_bbscn_SHIFT 28
2231 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F
2232 #define lpfc_reg_vfi_bbscn_WORD word10
2235 struct lpfc_mbx_init_vpi
{
2237 #define lpfc_init_vpi_vfi_SHIFT 16
2238 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF
2239 #define lpfc_init_vpi_vfi_WORD word1
2240 #define lpfc_init_vpi_vpi_SHIFT 0
2241 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF
2242 #define lpfc_init_vpi_vpi_WORD word1
2245 struct lpfc_mbx_read_vpi
{
2246 uint32_t word1_rsvd
;
2248 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0
2249 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
2250 #define lpfc_mbx_read_vpi_vnportid_WORD word2
2251 uint32_t word3_rsvd
;
2253 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
2254 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
2255 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4
2256 #define lpfc_mbx_read_vpi_pb_SHIFT 15
2257 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001
2258 #define lpfc_mbx_read_vpi_pb_WORD word4
2259 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16
2260 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
2261 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4
2262 #define lpfc_mbx_read_vpi_ns_SHIFT 30
2263 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001
2264 #define lpfc_mbx_read_vpi_ns_WORD word4
2265 #define lpfc_mbx_read_vpi_hl_SHIFT 31
2266 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001
2267 #define lpfc_mbx_read_vpi_hl_WORD word4
2268 uint32_t word5_rsvd
;
2270 #define lpfc_mbx_read_vpi_vpi_SHIFT 0
2271 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
2272 #define lpfc_mbx_read_vpi_vpi_WORD word6
2274 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0
2275 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
2276 #define lpfc_mbx_read_vpi_mac_0_WORD word7
2277 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8
2278 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
2279 #define lpfc_mbx_read_vpi_mac_1_WORD word7
2280 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16
2281 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
2282 #define lpfc_mbx_read_vpi_mac_2_WORD word7
2283 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24
2284 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
2285 #define lpfc_mbx_read_vpi_mac_3_WORD word7
2287 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0
2288 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
2289 #define lpfc_mbx_read_vpi_mac_4_WORD word8
2290 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8
2291 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
2292 #define lpfc_mbx_read_vpi_mac_5_WORD word8
2293 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16
2294 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
2295 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8
2296 #define lpfc_mbx_read_vpi_vv_SHIFT 28
2297 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001
2298 #define lpfc_mbx_read_vpi_vv_WORD word8
2301 struct lpfc_mbx_unreg_vfi
{
2302 uint32_t word1_rsvd
;
2304 #define lpfc_unreg_vfi_vfi_SHIFT 0
2305 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
2306 #define lpfc_unreg_vfi_vfi_WORD word2
2309 struct lpfc_mbx_resume_rpi
{
2311 #define lpfc_resume_rpi_index_SHIFT 0
2312 #define lpfc_resume_rpi_index_MASK 0x0000FFFF
2313 #define lpfc_resume_rpi_index_WORD word1
2314 #define lpfc_resume_rpi_ii_SHIFT 30
2315 #define lpfc_resume_rpi_ii_MASK 0x00000003
2316 #define lpfc_resume_rpi_ii_WORD word1
2317 #define RESUME_INDEX_RPI 0
2318 #define RESUME_INDEX_VPI 1
2319 #define RESUME_INDEX_VFI 2
2320 #define RESUME_INDEX_FCFI 3
2324 #define REG_FCF_INVALID_QID 0xFFFF
2325 struct lpfc_mbx_reg_fcfi
{
2327 #define lpfc_reg_fcfi_info_index_SHIFT 0
2328 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
2329 #define lpfc_reg_fcfi_info_index_WORD word1
2330 #define lpfc_reg_fcfi_fcfi_SHIFT 16
2331 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
2332 #define lpfc_reg_fcfi_fcfi_WORD word1
2334 #define lpfc_reg_fcfi_rq_id1_SHIFT 0
2335 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
2336 #define lpfc_reg_fcfi_rq_id1_WORD word2
2337 #define lpfc_reg_fcfi_rq_id0_SHIFT 16
2338 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
2339 #define lpfc_reg_fcfi_rq_id0_WORD word2
2341 #define lpfc_reg_fcfi_rq_id3_SHIFT 0
2342 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
2343 #define lpfc_reg_fcfi_rq_id3_WORD word3
2344 #define lpfc_reg_fcfi_rq_id2_SHIFT 16
2345 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
2346 #define lpfc_reg_fcfi_rq_id2_WORD word3
2348 #define lpfc_reg_fcfi_type_match0_SHIFT 24
2349 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
2350 #define lpfc_reg_fcfi_type_match0_WORD word4
2351 #define lpfc_reg_fcfi_type_mask0_SHIFT 16
2352 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
2353 #define lpfc_reg_fcfi_type_mask0_WORD word4
2354 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
2355 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
2356 #define lpfc_reg_fcfi_rctl_match0_WORD word4
2357 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
2358 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
2359 #define lpfc_reg_fcfi_rctl_mask0_WORD word4
2361 #define lpfc_reg_fcfi_type_match1_SHIFT 24
2362 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
2363 #define lpfc_reg_fcfi_type_match1_WORD word5
2364 #define lpfc_reg_fcfi_type_mask1_SHIFT 16
2365 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
2366 #define lpfc_reg_fcfi_type_mask1_WORD word5
2367 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
2368 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
2369 #define lpfc_reg_fcfi_rctl_match1_WORD word5
2370 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
2371 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
2372 #define lpfc_reg_fcfi_rctl_mask1_WORD word5
2374 #define lpfc_reg_fcfi_type_match2_SHIFT 24
2375 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
2376 #define lpfc_reg_fcfi_type_match2_WORD word6
2377 #define lpfc_reg_fcfi_type_mask2_SHIFT 16
2378 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
2379 #define lpfc_reg_fcfi_type_mask2_WORD word6
2380 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
2381 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
2382 #define lpfc_reg_fcfi_rctl_match2_WORD word6
2383 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
2384 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
2385 #define lpfc_reg_fcfi_rctl_mask2_WORD word6
2387 #define lpfc_reg_fcfi_type_match3_SHIFT 24
2388 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
2389 #define lpfc_reg_fcfi_type_match3_WORD word7
2390 #define lpfc_reg_fcfi_type_mask3_SHIFT 16
2391 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
2392 #define lpfc_reg_fcfi_type_mask3_WORD word7
2393 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
2394 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
2395 #define lpfc_reg_fcfi_rctl_match3_WORD word7
2396 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
2397 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
2398 #define lpfc_reg_fcfi_rctl_mask3_WORD word7
2400 #define lpfc_reg_fcfi_mam_SHIFT 13
2401 #define lpfc_reg_fcfi_mam_MASK 0x00000003
2402 #define lpfc_reg_fcfi_mam_WORD word8
2403 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
2404 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */
2405 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */
2406 #define lpfc_reg_fcfi_vv_SHIFT 12
2407 #define lpfc_reg_fcfi_vv_MASK 0x00000001
2408 #define lpfc_reg_fcfi_vv_WORD word8
2409 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0
2410 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
2411 #define lpfc_reg_fcfi_vlan_tag_WORD word8
2414 struct lpfc_mbx_reg_fcfi_mrq
{
2416 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0
2417 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF
2418 #define lpfc_reg_fcfi_mrq_info_index_WORD word1
2419 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16
2420 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF
2421 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1
2423 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0
2424 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF
2425 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2
2426 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16
2427 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF
2428 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2
2430 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0
2431 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF
2432 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3
2433 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16
2434 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF
2435 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3
2437 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24
2438 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF
2439 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4
2440 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16
2441 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF
2442 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4
2443 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8
2444 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF
2445 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4
2446 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0
2447 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF
2448 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4
2450 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24
2451 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF
2452 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5
2453 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16
2454 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF
2455 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5
2456 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8
2457 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF
2458 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5
2459 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0
2460 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF
2461 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5
2463 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24
2464 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF
2465 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6
2466 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16
2467 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF
2468 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6
2469 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8
2470 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF
2471 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6
2472 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0
2473 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF
2474 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6
2476 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24
2477 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF
2478 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7
2479 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16
2480 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF
2481 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7
2482 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8
2483 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF
2484 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7
2485 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0
2486 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF
2487 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7
2489 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31
2490 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001
2491 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8
2492 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30
2493 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001
2494 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8
2495 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29
2496 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001
2497 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8
2498 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28
2499 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001
2500 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8
2501 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27
2502 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001
2503 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8
2504 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26
2505 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001
2506 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8
2507 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25
2508 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001
2509 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8
2510 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24
2511 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001
2512 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8
2513 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23
2514 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001
2515 #define lpfc_reg_fcfi_mrq_pt7_WORD word8
2516 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22
2517 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001
2518 #define lpfc_reg_fcfi_mrq_pt6_WORD word8
2519 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21
2520 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001
2521 #define lpfc_reg_fcfi_mrq_pt5_WORD word8
2522 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20
2523 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001
2524 #define lpfc_reg_fcfi_mrq_pt4_WORD word8
2525 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19
2526 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001
2527 #define lpfc_reg_fcfi_mrq_pt3_WORD word8
2528 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18
2529 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001
2530 #define lpfc_reg_fcfi_mrq_pt2_WORD word8
2531 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17
2532 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001
2533 #define lpfc_reg_fcfi_mrq_pt1_WORD word8
2534 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16
2535 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001
2536 #define lpfc_reg_fcfi_mrq_pt0_WORD word8
2537 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15
2538 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001
2539 #define lpfc_reg_fcfi_mrq_xmv_WORD word8
2540 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13
2541 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001
2542 #define lpfc_reg_fcfi_mrq_mode_WORD word8
2543 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12
2544 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001
2545 #define lpfc_reg_fcfi_mrq_vv_WORD word8
2546 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0
2547 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF
2548 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8
2550 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12
2551 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F
2552 #define lpfc_reg_fcfi_mrq_policy_WORD word9
2553 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8
2554 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F
2555 #define lpfc_reg_fcfi_mrq_filter_WORD word9
2556 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0
2557 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF
2558 #define lpfc_reg_fcfi_mrq_npairs_WORD word9
2568 struct lpfc_mbx_unreg_fcfi
{
2571 #define lpfc_unreg_fcfi_SHIFT 0
2572 #define lpfc_unreg_fcfi_MASK 0x0000FFFF
2573 #define lpfc_unreg_fcfi_WORD word2
2576 struct lpfc_mbx_read_rev
{
2578 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16
2579 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
2580 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1
2581 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20
2582 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
2583 #define lpfc_mbx_rd_rev_fcoe_WORD word1
2584 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21
2585 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
2586 #define lpfc_mbx_rd_rev_cee_ver_WORD word1
2587 #define LPFC_PREDCBX_CEE_MODE 0
2588 #define LPFC_DCBX_CEE_MODE 1
2589 #define lpfc_mbx_rd_rev_vpd_SHIFT 29
2590 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
2591 #define lpfc_mbx_rd_rev_vpd_WORD word1
2592 uint32_t first_hw_rev
;
2593 uint32_t second_hw_rev
;
2594 uint32_t word4_rsvd
;
2595 uint32_t third_hw_rev
;
2597 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
2598 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
2599 #define lpfc_mbx_rd_rev_fcph_low_WORD word6
2600 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8
2601 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
2602 #define lpfc_mbx_rd_rev_fcph_high_WORD word6
2603 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16
2604 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
2605 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6
2606 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24
2607 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
2608 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6
2609 uint32_t word7_rsvd
;
2611 uint8_t fw_name
[16];
2612 uint32_t ulp_fw_id_rev
;
2613 uint8_t ulp_fw_name
[16];
2614 uint32_t word18_47_rsvd
[30];
2616 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0
2617 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
2618 #define lpfc_mbx_rd_rev_avail_len_WORD word48
2619 uint32_t vpd_paddr_low
;
2620 uint32_t vpd_paddr_high
;
2621 uint32_t avail_vpd_len
;
2622 uint32_t rsvd_52_63
[12];
2625 struct lpfc_mbx_read_config
{
2627 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31
2628 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001
2629 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1
2631 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0
2632 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F
2633 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2
2634 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6
2635 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003
2636 #define lpfc_mbx_rd_conf_lnk_type_WORD word2
2637 #define LPFC_LNK_TYPE_GE 0
2638 #define LPFC_LNK_TYPE_FC 1
2639 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8
2640 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001
2641 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2
2642 #define lpfc_mbx_rd_conf_topology_SHIFT 24
2643 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
2644 #define lpfc_mbx_rd_conf_topology_WORD word2
2647 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
2648 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
2649 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4
2652 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
2653 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
2654 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6
2655 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16
2656 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF
2657 #define lpfc_mbx_rd_conf_link_speed_WORD word6
2660 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0
2661 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F
2662 #define lpfc_mbx_rd_conf_bbscn_min_WORD word8
2663 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4
2664 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F
2665 #define lpfc_mbx_rd_conf_bbscn_max_WORD word8
2666 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8
2667 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F
2668 #define lpfc_mbx_rd_conf_bbscn_def_WORD word8
2670 #define lpfc_mbx_rd_conf_lmt_SHIFT 0
2671 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
2672 #define lpfc_mbx_rd_conf_lmt_WORD word9
2676 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0
2677 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
2678 #define lpfc_mbx_rd_conf_xri_base_WORD word12
2679 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16
2680 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
2681 #define lpfc_mbx_rd_conf_xri_count_WORD word12
2683 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
2684 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
2685 #define lpfc_mbx_rd_conf_rpi_base_WORD word13
2686 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16
2687 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
2688 #define lpfc_mbx_rd_conf_rpi_count_WORD word13
2690 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
2691 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
2692 #define lpfc_mbx_rd_conf_vpi_base_WORD word14
2693 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16
2694 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
2695 #define lpfc_mbx_rd_conf_vpi_count_WORD word14
2697 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
2698 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
2699 #define lpfc_mbx_rd_conf_vfi_base_WORD word15
2700 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16
2701 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
2702 #define lpfc_mbx_rd_conf_vfi_count_WORD word15
2704 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16
2705 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
2706 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16
2708 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0
2709 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
2710 #define lpfc_mbx_rd_conf_rq_count_WORD word17
2711 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16
2712 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
2713 #define lpfc_mbx_rd_conf_eq_count_WORD word17
2715 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0
2716 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
2717 #define lpfc_mbx_rd_conf_wq_count_WORD word18
2718 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16
2719 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
2720 #define lpfc_mbx_rd_conf_cq_count_WORD word18
2723 struct lpfc_mbx_request_features
{
2725 #define lpfc_mbx_rq_ftr_qry_SHIFT 0
2726 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
2727 #define lpfc_mbx_rq_ftr_qry_WORD word1
2729 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
2730 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
2731 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2
2732 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1
2733 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
2734 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2
2735 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2
2736 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
2737 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2
2738 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3
2739 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
2740 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2
2741 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4
2742 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
2743 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2
2744 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5
2745 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
2746 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2
2747 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6
2748 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
2749 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2
2750 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7
2751 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
2752 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2
2753 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9
2754 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001
2755 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2
2756 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11
2757 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001
2758 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2
2759 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16
2760 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001
2761 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2
2763 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
2764 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
2765 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3
2766 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1
2767 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
2768 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3
2769 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2
2770 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
2771 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3
2772 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3
2773 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
2774 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3
2775 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4
2776 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
2777 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3
2778 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5
2779 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
2780 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3
2781 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6
2782 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
2783 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3
2784 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7
2785 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
2786 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3
2787 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11
2788 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001
2789 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3
2790 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16
2791 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001
2792 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3
2795 struct lpfc_mbx_supp_pages
{
2798 #define qs_MASK 0x00000001
2799 #define qs_WORD word1
2801 #define wr_MASK 0x00000001
2802 #define wr_WORD word1
2804 #define pf_MASK 0x000000ff
2805 #define pf_WORD word1
2806 #define cpn_SHIFT 16
2807 #define cpn_MASK 0x000000ff
2808 #define cpn_WORD word1
2810 #define list_offset_SHIFT 0
2811 #define list_offset_MASK 0x000000ff
2812 #define list_offset_WORD word2
2813 #define next_offset_SHIFT 8
2814 #define next_offset_MASK 0x000000ff
2815 #define next_offset_WORD word2
2816 #define elem_cnt_SHIFT 16
2817 #define elem_cnt_MASK 0x000000ff
2818 #define elem_cnt_WORD word2
2820 #define pn_0_SHIFT 24
2821 #define pn_0_MASK 0x000000ff
2822 #define pn_0_WORD word3
2823 #define pn_1_SHIFT 16
2824 #define pn_1_MASK 0x000000ff
2825 #define pn_1_WORD word3
2826 #define pn_2_SHIFT 8
2827 #define pn_2_MASK 0x000000ff
2828 #define pn_2_WORD word3
2829 #define pn_3_SHIFT 0
2830 #define pn_3_MASK 0x000000ff
2831 #define pn_3_WORD word3
2833 #define pn_4_SHIFT 24
2834 #define pn_4_MASK 0x000000ff
2835 #define pn_4_WORD word4
2836 #define pn_5_SHIFT 16
2837 #define pn_5_MASK 0x000000ff
2838 #define pn_5_WORD word4
2839 #define pn_6_SHIFT 8
2840 #define pn_6_MASK 0x000000ff
2841 #define pn_6_WORD word4
2842 #define pn_7_SHIFT 0
2843 #define pn_7_MASK 0x000000ff
2844 #define pn_7_WORD word4
2846 #define LPFC_SUPP_PAGES 0
2847 #define LPFC_BLOCK_GUARD_PROFILES 1
2848 #define LPFC_SLI4_PARAMETERS 2
2851 struct lpfc_mbx_memory_dump_type3
{
2853 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0
2854 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f
2855 #define lpfc_mbx_memory_dump_type3_type_WORD word1
2856 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24
2857 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff
2858 #define lpfc_mbx_memory_dump_type3_link_WORD word1
2860 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0
2861 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff
2862 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2
2863 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16
2864 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff
2865 #define lpfc_mbx_memory_dump_type3_offset_WORD word2
2867 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0
2868 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff
2869 #define lpfc_mbx_memory_dump_type3_length_WORD word3
2872 uint32_t return_len
;
2875 #define DMP_PAGE_A0 0xa0
2876 #define DMP_PAGE_A2 0xa2
2877 #define DMP_SFF_PAGE_A0_SIZE 256
2878 #define DMP_SFF_PAGE_A2_SIZE 256
2880 #define SFP_WAVELENGTH_LC1310 1310
2881 #define SFP_WAVELENGTH_LL1550 1550
2885 * * SFF-8472 TABLE 3.4
2887 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */
2888 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */
2889 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */
2890 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */
2891 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */
2892 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */
2893 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */
2894 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */
2895 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */
2896 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */
2897 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */
2898 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
2899 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
2900 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */
2901 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
2902 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */
2904 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */
2906 #define SSF_IDENTIFIER 0
2907 #define SSF_EXT_IDENTIFIER 1
2908 #define SSF_CONNECTOR 2
2909 #define SSF_TRANSCEIVER_CODE_B0 3
2910 #define SSF_TRANSCEIVER_CODE_B1 4
2911 #define SSF_TRANSCEIVER_CODE_B2 5
2912 #define SSF_TRANSCEIVER_CODE_B3 6
2913 #define SSF_TRANSCEIVER_CODE_B4 7
2914 #define SSF_TRANSCEIVER_CODE_B5 8
2915 #define SSF_TRANSCEIVER_CODE_B6 9
2916 #define SSF_TRANSCEIVER_CODE_B7 10
2917 #define SSF_ENCODING 11
2918 #define SSF_BR_NOMINAL 12
2919 #define SSF_RATE_IDENTIFIER 13
2920 #define SSF_LENGTH_9UM_KM 14
2921 #define SSF_LENGTH_9UM 15
2922 #define SSF_LENGTH_50UM_OM2 16
2923 #define SSF_LENGTH_62UM_OM1 17
2924 #define SFF_LENGTH_COPPER 18
2925 #define SSF_LENGTH_50UM_OM3 19
2926 #define SSF_VENDOR_NAME 20
2927 #define SSF_VENDOR_OUI 36
2928 #define SSF_VENDOR_PN 40
2929 #define SSF_VENDOR_REV 56
2930 #define SSF_WAVELENGTH_B1 60
2931 #define SSF_WAVELENGTH_B0 61
2932 #define SSF_CC_BASE 63
2933 #define SSF_OPTIONS_B1 64
2934 #define SSF_OPTIONS_B0 65
2935 #define SSF_BR_MAX 66
2936 #define SSF_BR_MIN 67
2937 #define SSF_VENDOR_SN 68
2938 #define SSF_DATE_CODE 84
2939 #define SSF_MONITORING_TYPEDIAGNOSTIC 92
2940 #define SSF_ENHANCED_OPTIONS 93
2941 #define SFF_8472_COMPLIANCE 94
2942 #define SSF_CC_EXT 95
2943 #define SSF_A0_VENDOR_SPECIFIC 96
2945 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */
2947 #define SSF_TEMP_HIGH_ALARM 0
2948 #define SSF_TEMP_LOW_ALARM 2
2949 #define SSF_TEMP_HIGH_WARNING 4
2950 #define SSF_TEMP_LOW_WARNING 6
2951 #define SSF_VOLTAGE_HIGH_ALARM 8
2952 #define SSF_VOLTAGE_LOW_ALARM 10
2953 #define SSF_VOLTAGE_HIGH_WARNING 12
2954 #define SSF_VOLTAGE_LOW_WARNING 14
2955 #define SSF_BIAS_HIGH_ALARM 16
2956 #define SSF_BIAS_LOW_ALARM 18
2957 #define SSF_BIAS_HIGH_WARNING 20
2958 #define SSF_BIAS_LOW_WARNING 22
2959 #define SSF_TXPOWER_HIGH_ALARM 24
2960 #define SSF_TXPOWER_LOW_ALARM 26
2961 #define SSF_TXPOWER_HIGH_WARNING 28
2962 #define SSF_TXPOWER_LOW_WARNING 30
2963 #define SSF_RXPOWER_HIGH_ALARM 32
2964 #define SSF_RXPOWER_LOW_ALARM 34
2965 #define SSF_RXPOWER_HIGH_WARNING 36
2966 #define SSF_RXPOWER_LOW_WARNING 38
2967 #define SSF_EXT_CAL_CONSTANTS 56
2968 #define SSF_CC_DMI 95
2969 #define SFF_TEMPERATURE_B1 96
2970 #define SFF_TEMPERATURE_B0 97
2971 #define SFF_VCC_B1 98
2972 #define SFF_VCC_B0 99
2973 #define SFF_TX_BIAS_CURRENT_B1 100
2974 #define SFF_TX_BIAS_CURRENT_B0 101
2975 #define SFF_TXPOWER_B1 102
2976 #define SFF_TXPOWER_B0 103
2977 #define SFF_RXPOWER_B1 104
2978 #define SFF_RXPOWER_B0 105
2979 #define SSF_STATUS_CONTROL 110
2980 #define SSF_ALARM_FLAGS 112
2981 #define SSF_WARNING_FLAGS 116
2982 #define SSF_EXT_TATUS_CONTROL_B1 118
2983 #define SSF_EXT_TATUS_CONTROL_B0 119
2984 #define SSF_A2_VENDOR_SPECIFIC 120
2985 #define SSF_USER_EEPROM 128
2986 #define SSF_VENDOR_CONTROL 148
2990 * Tranceiver codes Fibre Channel SFF-8472
2994 struct sff_trasnceiver_codes_byte0
{
2995 uint8_t inifiband
:4;
2996 uint8_t teng_ethernet
:4;
2999 struct sff_trasnceiver_codes_byte1
{
3004 struct sff_trasnceiver_codes_byte2
{
3008 struct sff_trasnceiver_codes_byte3
{
3012 struct sff_trasnceiver_codes_byte4
{
3014 uint8_t fc_lw_laser
:1;
3015 uint8_t fc_sw_laser
:1;
3016 uint8_t fc_md_distance
:1;
3017 uint8_t fc_lg_distance
:1;
3018 uint8_t fc_int_distance
:1;
3019 uint8_t fc_short_distance
:1;
3020 uint8_t fc_vld_distance
:1;
3023 struct sff_trasnceiver_codes_byte5
{
3024 uint8_t reserved1
:1;
3025 uint8_t reserved2
:1;
3026 uint8_t fc_sfp_active
:1; /* Active cable */
3027 uint8_t fc_sfp_passive
:1; /* Passive cable */
3028 uint8_t fc_lw_laser
:1; /* Longwave laser */
3029 uint8_t fc_sw_laser_sl
:1;
3030 uint8_t fc_sw_laser_sn
:1;
3031 uint8_t fc_el_hi
:1; /* Electrical enclosure high bit */
3034 struct sff_trasnceiver_codes_byte6
{
3035 uint8_t fc_tm_sm
:1; /* Single Mode */
3037 uint8_t fc_tm_m6
:1; /* Multimode, 62.5um (M6) */
3038 uint8_t fc_tm_tv
:1; /* Video Coax (TV) */
3039 uint8_t fc_tm_mi
:1; /* Miniature Coax (MI) */
3040 uint8_t fc_tm_tp
:1; /* Twisted Pair (TP) */
3041 uint8_t fc_tm_tw
:1; /* Twin Axial Pair */
3044 struct sff_trasnceiver_codes_byte7
{
3045 uint8_t fc_sp_100MB
:1; /* 100 MB/sec */
3047 uint8_t fc_sp_200mb
:1; /* 200 MB/sec */
3048 uint8_t fc_sp_3200MB
:1; /* 3200 MB/sec */
3049 uint8_t fc_sp_400MB
:1; /* 400 MB/sec */
3050 uint8_t fc_sp_1600MB
:1; /* 1600 MB/sec */
3051 uint8_t fc_sp_800MB
:1; /* 800 MB/sec */
3052 uint8_t fc_sp_1200MB
:1; /* 1200 MB/sec */
3055 /* User writable non-volatile memory, SFF-8472 Table 3.20 */
3056 struct user_eeprom
{
3057 uint8_t vendor_name
[16];
3058 uint8_t vendor_oui
[3];
3059 uint8_t vendor_pn
[816];
3060 uint8_t vendor_rev
[4];
3061 uint8_t vendor_sn
[16];
3062 uint8_t datecode
[6];
3063 uint8_t lot_code
[2];
3064 uint8_t reserved191
[57];
3067 struct lpfc_mbx_pc_sli4_params
{
3070 #define qs_MASK 0x00000001
3071 #define qs_WORD word1
3073 #define wr_MASK 0x00000001
3074 #define wr_WORD word1
3076 #define pf_MASK 0x000000ff
3077 #define pf_WORD word1
3078 #define cpn_SHIFT 16
3079 #define cpn_MASK 0x000000ff
3080 #define cpn_WORD word1
3082 #define if_type_SHIFT 0
3083 #define if_type_MASK 0x00000007
3084 #define if_type_WORD word2
3085 #define sli_rev_SHIFT 4
3086 #define sli_rev_MASK 0x0000000f
3087 #define sli_rev_WORD word2
3088 #define sli_family_SHIFT 8
3089 #define sli_family_MASK 0x000000ff
3090 #define sli_family_WORD word2
3091 #define featurelevel_1_SHIFT 16
3092 #define featurelevel_1_MASK 0x000000ff
3093 #define featurelevel_1_WORD word2
3094 #define featurelevel_2_SHIFT 24
3095 #define featurelevel_2_MASK 0x0000001f
3096 #define featurelevel_2_WORD word2
3098 #define fcoe_SHIFT 0
3099 #define fcoe_MASK 0x00000001
3100 #define fcoe_WORD word3
3102 #define fc_MASK 0x00000001
3103 #define fc_WORD word3
3105 #define nic_MASK 0x00000001
3106 #define nic_WORD word3
3107 #define iscsi_SHIFT 3
3108 #define iscsi_MASK 0x00000001
3109 #define iscsi_WORD word3
3110 #define rdma_SHIFT 4
3111 #define rdma_MASK 0x00000001
3112 #define rdma_WORD word3
3113 uint32_t sge_supp_len
;
3114 #define SLI4_PAGE_SIZE 4096
3116 #define if_page_sz_SHIFT 0
3117 #define if_page_sz_MASK 0x0000ffff
3118 #define if_page_sz_WORD word5
3119 #define loopbk_scope_SHIFT 24
3120 #define loopbk_scope_MASK 0x0000000f
3121 #define loopbk_scope_WORD word5
3122 #define rq_db_window_SHIFT 28
3123 #define rq_db_window_MASK 0x0000000f
3124 #define rq_db_window_WORD word5
3126 #define eq_pages_SHIFT 0
3127 #define eq_pages_MASK 0x0000000f
3128 #define eq_pages_WORD word6
3129 #define eqe_size_SHIFT 8
3130 #define eqe_size_MASK 0x000000ff
3131 #define eqe_size_WORD word6
3133 #define cq_pages_SHIFT 0
3134 #define cq_pages_MASK 0x0000000f
3135 #define cq_pages_WORD word7
3136 #define cqe_size_SHIFT 8
3137 #define cqe_size_MASK 0x000000ff
3138 #define cqe_size_WORD word7
3140 #define mq_pages_SHIFT 0
3141 #define mq_pages_MASK 0x0000000f
3142 #define mq_pages_WORD word8
3143 #define mqe_size_SHIFT 8
3144 #define mqe_size_MASK 0x000000ff
3145 #define mqe_size_WORD word8
3146 #define mq_elem_cnt_SHIFT 16
3147 #define mq_elem_cnt_MASK 0x000000ff
3148 #define mq_elem_cnt_WORD word8
3150 #define wq_pages_SHIFT 0
3151 #define wq_pages_MASK 0x0000ffff
3152 #define wq_pages_WORD word9
3153 #define wqe_size_SHIFT 8
3154 #define wqe_size_MASK 0x000000ff
3155 #define wqe_size_WORD word9
3157 #define rq_pages_SHIFT 0
3158 #define rq_pages_MASK 0x0000ffff
3159 #define rq_pages_WORD word10
3160 #define rqe_size_SHIFT 8
3161 #define rqe_size_MASK 0x000000ff
3162 #define rqe_size_WORD word10
3164 #define hdr_pages_SHIFT 0
3165 #define hdr_pages_MASK 0x0000000f
3166 #define hdr_pages_WORD word11
3167 #define hdr_size_SHIFT 8
3168 #define hdr_size_MASK 0x0000000f
3169 #define hdr_size_WORD word11
3170 #define hdr_pp_align_SHIFT 16
3171 #define hdr_pp_align_MASK 0x0000ffff
3172 #define hdr_pp_align_WORD word11
3174 #define sgl_pages_SHIFT 0
3175 #define sgl_pages_MASK 0x0000000f
3176 #define sgl_pages_WORD word12
3177 #define sgl_pp_align_SHIFT 16
3178 #define sgl_pp_align_MASK 0x0000ffff
3179 #define sgl_pp_align_WORD word12
3180 uint32_t rsvd_13_63
[51];
3182 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
3183 &(~((SLI4_PAGE_SIZE)-1)))
3185 struct lpfc_sli4_parameters
{
3187 #define cfg_prot_type_SHIFT 0
3188 #define cfg_prot_type_MASK 0x000000FF
3189 #define cfg_prot_type_WORD word0
3191 #define cfg_ft_SHIFT 0
3192 #define cfg_ft_MASK 0x00000001
3193 #define cfg_ft_WORD word1
3194 #define cfg_sli_rev_SHIFT 4
3195 #define cfg_sli_rev_MASK 0x0000000f
3196 #define cfg_sli_rev_WORD word1
3197 #define cfg_sli_family_SHIFT 8
3198 #define cfg_sli_family_MASK 0x0000000f
3199 #define cfg_sli_family_WORD word1
3200 #define cfg_if_type_SHIFT 12
3201 #define cfg_if_type_MASK 0x0000000f
3202 #define cfg_if_type_WORD word1
3203 #define cfg_sli_hint_1_SHIFT 16
3204 #define cfg_sli_hint_1_MASK 0x000000ff
3205 #define cfg_sli_hint_1_WORD word1
3206 #define cfg_sli_hint_2_SHIFT 24
3207 #define cfg_sli_hint_2_MASK 0x0000001f
3208 #define cfg_sli_hint_2_WORD word1
3212 #define cfg_cqv_SHIFT 14
3213 #define cfg_cqv_MASK 0x00000003
3214 #define cfg_cqv_WORD word4
3217 #define cfg_mqv_SHIFT 14
3218 #define cfg_mqv_MASK 0x00000003
3219 #define cfg_mqv_WORD word6
3222 #define cfg_wqpcnt_SHIFT 0
3223 #define cfg_wqpcnt_MASK 0x0000000f
3224 #define cfg_wqpcnt_WORD word8
3225 #define cfg_wqsize_SHIFT 8
3226 #define cfg_wqsize_MASK 0x0000000f
3227 #define cfg_wqsize_WORD word8
3228 #define cfg_wqv_SHIFT 14
3229 #define cfg_wqv_MASK 0x00000003
3230 #define cfg_wqv_WORD word8
3231 #define cfg_wqpsize_SHIFT 16
3232 #define cfg_wqpsize_MASK 0x000000ff
3233 #define cfg_wqpsize_WORD word8
3236 #define cfg_rqv_SHIFT 14
3237 #define cfg_rqv_MASK 0x00000003
3238 #define cfg_rqv_WORD word10
3240 #define cfg_rq_db_window_SHIFT 28
3241 #define cfg_rq_db_window_MASK 0x0000000f
3242 #define cfg_rq_db_window_WORD word11
3244 #define cfg_fcoe_SHIFT 0
3245 #define cfg_fcoe_MASK 0x00000001
3246 #define cfg_fcoe_WORD word12
3247 #define cfg_ext_SHIFT 1
3248 #define cfg_ext_MASK 0x00000001
3249 #define cfg_ext_WORD word12
3250 #define cfg_hdrr_SHIFT 2
3251 #define cfg_hdrr_MASK 0x00000001
3252 #define cfg_hdrr_WORD word12
3253 #define cfg_phwq_SHIFT 15
3254 #define cfg_phwq_MASK 0x00000001
3255 #define cfg_phwq_WORD word12
3256 #define cfg_oas_SHIFT 25
3257 #define cfg_oas_MASK 0x00000001
3258 #define cfg_oas_WORD word12
3259 #define cfg_loopbk_scope_SHIFT 28
3260 #define cfg_loopbk_scope_MASK 0x0000000f
3261 #define cfg_loopbk_scope_WORD word12
3262 uint32_t sge_supp_len
;
3264 #define cfg_sgl_page_cnt_SHIFT 0
3265 #define cfg_sgl_page_cnt_MASK 0x0000000f
3266 #define cfg_sgl_page_cnt_WORD word14
3267 #define cfg_sgl_page_size_SHIFT 8
3268 #define cfg_sgl_page_size_MASK 0x000000ff
3269 #define cfg_sgl_page_size_WORD word14
3270 #define cfg_sgl_pp_align_SHIFT 16
3271 #define cfg_sgl_pp_align_MASK 0x000000ff
3272 #define cfg_sgl_pp_align_WORD word14
3278 #define cfg_ext_embed_cb_SHIFT 0
3279 #define cfg_ext_embed_cb_MASK 0x00000001
3280 #define cfg_ext_embed_cb_WORD word19
3281 #define cfg_mds_diags_SHIFT 1
3282 #define cfg_mds_diags_MASK 0x00000001
3283 #define cfg_mds_diags_WORD word19
3284 #define cfg_nvme_SHIFT 3
3285 #define cfg_nvme_MASK 0x00000001
3286 #define cfg_nvme_WORD word19
3287 #define cfg_xib_SHIFT 4
3288 #define cfg_xib_MASK 0x00000001
3289 #define cfg_xib_WORD word19
3290 #define cfg_eqdr_SHIFT 8
3291 #define cfg_eqdr_MASK 0x00000001
3292 #define cfg_eqdr_WORD word19
3293 #define LPFC_NODELAY_MAX_IO 32
3296 #define LPFC_SET_UE_RECOVERY 0x10
3297 #define LPFC_SET_MDS_DIAGS 0x11
3298 struct lpfc_mbx_set_feature
{
3299 struct mbox_header header
;
3303 #define lpfc_mbx_set_feature_UER_SHIFT 0
3304 #define lpfc_mbx_set_feature_UER_MASK 0x00000001
3305 #define lpfc_mbx_set_feature_UER_WORD word6
3306 #define lpfc_mbx_set_feature_mds_SHIFT 0
3307 #define lpfc_mbx_set_feature_mds_MASK 0x00000001
3308 #define lpfc_mbx_set_feature_mds_WORD word6
3309 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1
3310 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001
3311 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6
3313 #define lpfc_mbx_set_feature_UERP_SHIFT 0
3314 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff
3315 #define lpfc_mbx_set_feature_UERP_WORD word7
3316 #define lpfc_mbx_set_feature_UESR_SHIFT 16
3317 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff
3318 #define lpfc_mbx_set_feature_UESR_WORD word7
3322 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2
3323 struct lpfc_mbx_set_host_data
{
3324 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48
3325 struct mbox_header header
;
3328 uint8_t data
[LPFC_HOST_OS_DRIVER_VERSION_SIZE
];
3332 struct lpfc_mbx_get_sli4_parameters
{
3333 struct mbox_header header
;
3334 struct lpfc_sli4_parameters sli4_parameters
;
3337 struct lpfc_rscr_desc_generic
{
3338 #define LPFC_RSRC_DESC_WSIZE 22
3339 uint32_t desc
[LPFC_RSRC_DESC_WSIZE
];
3342 struct lpfc_rsrc_desc_pcie
{
3344 #define lpfc_rsrc_desc_pcie_type_SHIFT 0
3345 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff
3346 #define lpfc_rsrc_desc_pcie_type_WORD word0
3347 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40
3348 #define lpfc_rsrc_desc_pcie_length_SHIFT 8
3349 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff
3350 #define lpfc_rsrc_desc_pcie_length_WORD word0
3352 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0
3353 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff
3354 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1
3357 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0
3358 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff
3359 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3
3360 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8
3361 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff
3362 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3
3363 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16
3364 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff
3365 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3
3367 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0
3368 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff
3369 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4
3372 struct lpfc_rsrc_desc_fcfcoe
{
3374 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0
3375 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff
3376 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0
3377 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43
3378 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8
3379 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff
3380 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0
3381 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0
3382 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72
3383 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88
3385 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0
3386 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff
3387 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1
3388 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16
3389 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff
3390 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1
3392 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0
3393 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff
3394 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2
3395 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16
3396 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff
3397 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2
3399 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0
3400 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff
3401 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3
3402 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16
3403 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff
3404 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3
3406 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0
3407 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff
3408 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4
3409 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16
3410 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff
3411 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4
3413 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0
3414 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff
3415 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5
3416 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16
3417 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff
3418 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5
3427 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0
3428 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f
3429 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13
3430 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6
3431 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003
3432 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13
3433 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8
3434 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001
3435 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13
3436 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9
3437 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001
3438 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13
3439 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16
3440 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff
3441 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13
3442 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */
3447 uint32_t reserved
[4];
3450 struct lpfc_func_cfg
{
3451 #define LPFC_RSRC_DESC_MAX_NUM 2
3452 uint32_t rsrc_desc_count
;
3453 struct lpfc_rscr_desc_generic desc
[LPFC_RSRC_DESC_MAX_NUM
];
3456 struct lpfc_mbx_get_func_cfg
{
3457 struct mbox_header header
;
3458 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3459 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3460 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3461 struct lpfc_func_cfg func_cfg
;
3464 struct lpfc_prof_cfg
{
3465 #define LPFC_RSRC_DESC_MAX_NUM 2
3466 uint32_t rsrc_desc_count
;
3467 struct lpfc_rscr_desc_generic desc
[LPFC_RSRC_DESC_MAX_NUM
];
3470 struct lpfc_mbx_get_prof_cfg
{
3471 struct mbox_header header
;
3472 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3473 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3474 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3478 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0
3479 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff
3480 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10
3481 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8
3482 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003
3483 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10
3486 struct lpfc_prof_cfg prof_cfg
;
3491 struct lpfc_controller_attribute
{
3492 uint32_t version_string
[8];
3493 uint32_t manufacturer_name
[8];
3494 uint32_t supported_modes
;
3496 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0
3497 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff
3498 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17
3499 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8
3500 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff
3501 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17
3502 uint32_t mbx_da_struct_ver
;
3503 uint32_t ep_fw_da_struct_ver
;
3504 uint32_t ncsi_ver_str
[3];
3505 uint32_t dflt_ext_timeout
;
3506 uint32_t model_number
[8];
3507 uint32_t description
[16];
3508 uint32_t serial_number
[8];
3509 uint32_t ip_ver_str
[8];
3510 uint32_t fw_ver_str
[8];
3511 uint32_t bios_ver_str
[8];
3512 uint32_t redboot_ver_str
[8];
3513 uint32_t driver_ver_str
[8];
3514 uint32_t flash_fw_ver_str
[8];
3515 uint32_t functionality
;
3517 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0
3518 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff
3519 #define lpfc_cntl_attr_max_cbd_len_WORD word105
3520 #define lpfc_cntl_attr_asic_rev_SHIFT 16
3521 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff
3522 #define lpfc_cntl_attr_asic_rev_WORD word105
3523 #define lpfc_cntl_attr_gen_guid0_SHIFT 24
3524 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff
3525 #define lpfc_cntl_attr_gen_guid0_WORD word105
3526 uint32_t gen_guid1_12
[3];
3528 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0
3529 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff
3530 #define lpfc_cntl_attr_gen_guid13_14_WORD word109
3531 #define lpfc_cntl_attr_gen_guid15_SHIFT 16
3532 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff
3533 #define lpfc_cntl_attr_gen_guid15_WORD word109
3534 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24
3535 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff
3536 #define lpfc_cntl_attr_hba_port_cnt_WORD word109
3538 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0
3539 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff
3540 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110
3541 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24
3542 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff
3543 #define lpfc_cntl_attr_multi_func_dev_WORD word110
3545 #define lpfc_cntl_attr_cache_valid_SHIFT 0
3546 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff
3547 #define lpfc_cntl_attr_cache_valid_WORD word111
3548 #define lpfc_cntl_attr_hba_status_SHIFT 8
3549 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff
3550 #define lpfc_cntl_attr_hba_status_WORD word111
3551 #define lpfc_cntl_attr_max_domain_SHIFT 16
3552 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff
3553 #define lpfc_cntl_attr_max_domain_WORD word111
3554 #define lpfc_cntl_attr_lnk_numb_SHIFT 24
3555 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f
3556 #define lpfc_cntl_attr_lnk_numb_WORD word111
3557 #define lpfc_cntl_attr_lnk_type_SHIFT 30
3558 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003
3559 #define lpfc_cntl_attr_lnk_type_WORD word111
3560 uint32_t fw_post_status
;
3561 uint32_t hba_mtu
[8];
3563 uint32_t reserved1
[3];
3565 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0
3566 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff
3567 #define lpfc_cntl_attr_pci_vendor_id_WORD word125
3568 #define lpfc_cntl_attr_pci_device_id_SHIFT 16
3569 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff
3570 #define lpfc_cntl_attr_pci_device_id_WORD word125
3572 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0
3573 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff
3574 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126
3575 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16
3576 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff
3577 #define lpfc_cntl_attr_pci_subsys_id_WORD word126
3579 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0
3580 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff
3581 #define lpfc_cntl_attr_pci_bus_num_WORD word127
3582 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8
3583 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff
3584 #define lpfc_cntl_attr_pci_dev_num_WORD word127
3585 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16
3586 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff
3587 #define lpfc_cntl_attr_pci_fnc_num_WORD word127
3588 #define lpfc_cntl_attr_inf_type_SHIFT 24
3589 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff
3590 #define lpfc_cntl_attr_inf_type_WORD word127
3591 uint32_t unique_id
[2];
3593 #define lpfc_cntl_attr_num_netfil_SHIFT 0
3594 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff
3595 #define lpfc_cntl_attr_num_netfil_WORD word130
3596 uint32_t reserved2
[4];
3599 struct lpfc_mbx_get_cntl_attributes
{
3600 union lpfc_sli4_cfg_shdr cfg_shdr
;
3601 struct lpfc_controller_attribute cntl_attr
;
3604 struct lpfc_mbx_get_port_name
{
3605 struct mbox_header header
;
3609 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0
3610 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003
3611 #define lpfc_mbx_get_port_name_lnk_type_WORD word4
3615 #define lpfc_mbx_get_port_name_name0_SHIFT 0
3616 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF
3617 #define lpfc_mbx_get_port_name_name0_WORD word4
3618 #define lpfc_mbx_get_port_name_name1_SHIFT 8
3619 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF
3620 #define lpfc_mbx_get_port_name_name1_WORD word4
3621 #define lpfc_mbx_get_port_name_name2_SHIFT 16
3622 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF
3623 #define lpfc_mbx_get_port_name_name2_WORD word4
3624 #define lpfc_mbx_get_port_name_name3_SHIFT 24
3625 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF
3626 #define lpfc_mbx_get_port_name_name3_WORD word4
3627 #define LPFC_LINK_NUMBER_0 0
3628 #define LPFC_LINK_NUMBER_1 1
3629 #define LPFC_LINK_NUMBER_2 2
3630 #define LPFC_LINK_NUMBER_3 3
3635 /* Mailbox Completion Queue Error Messages */
3636 #define MB_CQE_STATUS_SUCCESS 0x0
3637 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
3638 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2
3639 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
3640 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
3641 #define MB_CQE_STATUS_DMA_FAILED 0x5
3643 #define LPFC_MBX_WR_CONFIG_MAX_BDE 1
3644 struct lpfc_mbx_wr_object
{
3645 struct mbox_header header
;
3649 #define lpfc_wr_object_eof_SHIFT 31
3650 #define lpfc_wr_object_eof_MASK 0x00000001
3651 #define lpfc_wr_object_eof_WORD word4
3652 #define lpfc_wr_object_write_length_SHIFT 0
3653 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF
3654 #define lpfc_wr_object_write_length_WORD word4
3655 uint32_t write_offset
;
3656 uint32_t object_name
[26];
3658 struct ulp_bde64 bde
[LPFC_MBX_WR_CONFIG_MAX_BDE
];
3661 uint32_t actual_write_length
;
3666 /* mailbox queue entry structure */
3669 #define lpfc_mqe_status_SHIFT 16
3670 #define lpfc_mqe_status_MASK 0x0000FFFF
3671 #define lpfc_mqe_status_WORD word0
3672 #define lpfc_mqe_command_SHIFT 8
3673 #define lpfc_mqe_command_MASK 0x000000FF
3674 #define lpfc_mqe_command_WORD word0
3676 uint32_t mb_words
[LPFC_SLI4_MB_WORD_COUNT
- 1];
3677 /* sli4 mailbox commands */
3678 struct lpfc_mbx_sli4_config sli4_config
;
3679 struct lpfc_mbx_init_vfi init_vfi
;
3680 struct lpfc_mbx_reg_vfi reg_vfi
;
3681 struct lpfc_mbx_reg_vfi unreg_vfi
;
3682 struct lpfc_mbx_init_vpi init_vpi
;
3683 struct lpfc_mbx_resume_rpi resume_rpi
;
3684 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl
;
3685 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry
;
3686 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry
;
3687 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl
;
3688 struct lpfc_mbx_reg_fcfi reg_fcfi
;
3689 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq
;
3690 struct lpfc_mbx_unreg_fcfi unreg_fcfi
;
3691 struct lpfc_mbx_mq_create mq_create
;
3692 struct lpfc_mbx_mq_create_ext mq_create_ext
;
3693 struct lpfc_mbx_eq_create eq_create
;
3694 struct lpfc_mbx_modify_eq_delay eq_delay
;
3695 struct lpfc_mbx_cq_create cq_create
;
3696 struct lpfc_mbx_cq_create_set cq_create_set
;
3697 struct lpfc_mbx_wq_create wq_create
;
3698 struct lpfc_mbx_rq_create rq_create
;
3699 struct lpfc_mbx_rq_create_v2 rq_create_v2
;
3700 struct lpfc_mbx_mq_destroy mq_destroy
;
3701 struct lpfc_mbx_eq_destroy eq_destroy
;
3702 struct lpfc_mbx_cq_destroy cq_destroy
;
3703 struct lpfc_mbx_wq_destroy wq_destroy
;
3704 struct lpfc_mbx_rq_destroy rq_destroy
;
3705 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info
;
3706 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents
;
3707 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents
;
3708 struct lpfc_mbx_post_sgl_pages post_sgl_pages
;
3709 struct lpfc_mbx_nembed_cmd nembed_cmd
;
3710 struct lpfc_mbx_read_rev read_rev
;
3711 struct lpfc_mbx_read_vpi read_vpi
;
3712 struct lpfc_mbx_read_config rd_config
;
3713 struct lpfc_mbx_request_features req_ftrs
;
3714 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl
;
3715 struct lpfc_mbx_query_fw_config query_fw_cfg
;
3716 struct lpfc_mbx_set_beacon_config beacon_config
;
3717 struct lpfc_mbx_supp_pages supp_pages
;
3718 struct lpfc_mbx_pc_sli4_params sli4_params
;
3719 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters
;
3720 struct lpfc_mbx_set_link_diag_state link_diag_state
;
3721 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback
;
3722 struct lpfc_mbx_run_link_diag_test link_diag_test
;
3723 struct lpfc_mbx_get_func_cfg get_func_cfg
;
3724 struct lpfc_mbx_get_prof_cfg get_prof_cfg
;
3725 struct lpfc_mbx_wr_object wr_object
;
3726 struct lpfc_mbx_get_port_name get_port_name
;
3727 struct lpfc_mbx_set_feature set_feature
;
3728 struct lpfc_mbx_memory_dump_type3 mem_dump_type3
;
3729 struct lpfc_mbx_set_host_data set_host_data
;
3730 struct lpfc_mbx_nop nop
;
3736 #define lpfc_mcqe_status_SHIFT 0
3737 #define lpfc_mcqe_status_MASK 0x0000FFFF
3738 #define lpfc_mcqe_status_WORD word0
3739 #define lpfc_mcqe_ext_status_SHIFT 16
3740 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF
3741 #define lpfc_mcqe_ext_status_WORD word0
3745 #define lpfc_trailer_valid_SHIFT 31
3746 #define lpfc_trailer_valid_MASK 0x00000001
3747 #define lpfc_trailer_valid_WORD trailer
3748 #define lpfc_trailer_async_SHIFT 30
3749 #define lpfc_trailer_async_MASK 0x00000001
3750 #define lpfc_trailer_async_WORD trailer
3751 #define lpfc_trailer_hpi_SHIFT 29
3752 #define lpfc_trailer_hpi_MASK 0x00000001
3753 #define lpfc_trailer_hpi_WORD trailer
3754 #define lpfc_trailer_completed_SHIFT 28
3755 #define lpfc_trailer_completed_MASK 0x00000001
3756 #define lpfc_trailer_completed_WORD trailer
3757 #define lpfc_trailer_consumed_SHIFT 27
3758 #define lpfc_trailer_consumed_MASK 0x00000001
3759 #define lpfc_trailer_consumed_WORD trailer
3760 #define lpfc_trailer_type_SHIFT 16
3761 #define lpfc_trailer_type_MASK 0x000000FF
3762 #define lpfc_trailer_type_WORD trailer
3763 #define lpfc_trailer_code_SHIFT 8
3764 #define lpfc_trailer_code_MASK 0x000000FF
3765 #define lpfc_trailer_code_WORD trailer
3766 #define LPFC_TRAILER_CODE_LINK 0x1
3767 #define LPFC_TRAILER_CODE_FCOE 0x2
3768 #define LPFC_TRAILER_CODE_DCBX 0x3
3769 #define LPFC_TRAILER_CODE_GRP5 0x5
3770 #define LPFC_TRAILER_CODE_FC 0x10
3771 #define LPFC_TRAILER_CODE_SLI 0x11
3774 struct lpfc_acqe_link
{
3776 #define lpfc_acqe_link_speed_SHIFT 24
3777 #define lpfc_acqe_link_speed_MASK 0x000000FF
3778 #define lpfc_acqe_link_speed_WORD word0
3779 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
3780 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
3781 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
3782 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
3783 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
3784 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5
3785 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6
3786 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7
3787 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8
3788 #define lpfc_acqe_link_duplex_SHIFT 16
3789 #define lpfc_acqe_link_duplex_MASK 0x000000FF
3790 #define lpfc_acqe_link_duplex_WORD word0
3791 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
3792 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
3793 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
3794 #define lpfc_acqe_link_status_SHIFT 8
3795 #define lpfc_acqe_link_status_MASK 0x000000FF
3796 #define lpfc_acqe_link_status_WORD word0
3797 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
3798 #define LPFC_ASYNC_LINK_STATUS_UP 0x1
3799 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
3800 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
3801 #define lpfc_acqe_link_type_SHIFT 6
3802 #define lpfc_acqe_link_type_MASK 0x00000003
3803 #define lpfc_acqe_link_type_WORD word0
3804 #define lpfc_acqe_link_number_SHIFT 0
3805 #define lpfc_acqe_link_number_MASK 0x0000003F
3806 #define lpfc_acqe_link_number_WORD word0
3808 #define lpfc_acqe_link_fault_SHIFT 0
3809 #define lpfc_acqe_link_fault_MASK 0x000000FF
3810 #define lpfc_acqe_link_fault_WORD word1
3811 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0
3812 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
3813 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
3814 #define lpfc_acqe_logical_link_speed_SHIFT 16
3815 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
3816 #define lpfc_acqe_logical_link_speed_WORD word1
3819 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
3820 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
3823 struct lpfc_acqe_fip
{
3826 #define lpfc_acqe_fip_fcf_count_SHIFT 0
3827 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
3828 #define lpfc_acqe_fip_fcf_count_WORD word1
3829 #define lpfc_acqe_fip_event_type_SHIFT 16
3830 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
3831 #define lpfc_acqe_fip_event_type_WORD word1
3834 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
3835 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
3836 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
3837 #define LPFC_FIP_EVENT_TYPE_CVL 0x4
3838 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
3841 struct lpfc_acqe_dcbx
{
3848 struct lpfc_acqe_grp5
{
3850 #define lpfc_acqe_grp5_type_SHIFT 6
3851 #define lpfc_acqe_grp5_type_MASK 0x00000003
3852 #define lpfc_acqe_grp5_type_WORD word0
3853 #define lpfc_acqe_grp5_number_SHIFT 0
3854 #define lpfc_acqe_grp5_number_MASK 0x0000003F
3855 #define lpfc_acqe_grp5_number_WORD word0
3857 #define lpfc_acqe_grp5_llink_spd_SHIFT 16
3858 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
3859 #define lpfc_acqe_grp5_llink_spd_WORD word1
3864 struct lpfc_acqe_fc_la
{
3866 #define lpfc_acqe_fc_la_speed_SHIFT 24
3867 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF
3868 #define lpfc_acqe_fc_la_speed_WORD word0
3869 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0
3870 #define LPFC_FC_LA_SPEED_1G 0x1
3871 #define LPFC_FC_LA_SPEED_2G 0x2
3872 #define LPFC_FC_LA_SPEED_4G 0x4
3873 #define LPFC_FC_LA_SPEED_8G 0x8
3874 #define LPFC_FC_LA_SPEED_10G 0xA
3875 #define LPFC_FC_LA_SPEED_16G 0x10
3876 #define LPFC_FC_LA_SPEED_32G 0x20
3877 #define lpfc_acqe_fc_la_topology_SHIFT 16
3878 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF
3879 #define lpfc_acqe_fc_la_topology_WORD word0
3880 #define LPFC_FC_LA_TOP_UNKOWN 0x0
3881 #define LPFC_FC_LA_TOP_P2P 0x1
3882 #define LPFC_FC_LA_TOP_FCAL 0x2
3883 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
3884 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
3885 #define lpfc_acqe_fc_la_att_type_SHIFT 8
3886 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
3887 #define lpfc_acqe_fc_la_att_type_WORD word0
3888 #define LPFC_FC_LA_TYPE_LINK_UP 0x1
3889 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
3890 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
3891 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4
3892 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5
3893 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6
3894 #define lpfc_acqe_fc_la_port_type_SHIFT 6
3895 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003
3896 #define lpfc_acqe_fc_la_port_type_WORD word0
3897 #define LPFC_LINK_TYPE_ETHERNET 0x0
3898 #define LPFC_LINK_TYPE_FC 0x1
3899 #define lpfc_acqe_fc_la_port_number_SHIFT 0
3900 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
3901 #define lpfc_acqe_fc_la_port_number_WORD word0
3903 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16
3904 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
3905 #define lpfc_acqe_fc_la_llink_spd_WORD word1
3906 #define lpfc_acqe_fc_la_fault_SHIFT 0
3907 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF
3908 #define lpfc_acqe_fc_la_fault_WORD word1
3909 #define LPFC_FC_LA_FAULT_NONE 0x0
3910 #define LPFC_FC_LA_FAULT_LOCAL 0x1
3911 #define LPFC_FC_LA_FAULT_REMOTE 0x2
3914 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
3915 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
3918 struct lpfc_acqe_misconfigured_event
{
3921 #define lpfc_sli_misconfigured_port0_state_SHIFT 0
3922 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF
3923 #define lpfc_sli_misconfigured_port0_state_WORD word0
3924 #define lpfc_sli_misconfigured_port1_state_SHIFT 8
3925 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF
3926 #define lpfc_sli_misconfigured_port1_state_WORD word0
3927 #define lpfc_sli_misconfigured_port2_state_SHIFT 16
3928 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF
3929 #define lpfc_sli_misconfigured_port2_state_WORD word0
3930 #define lpfc_sli_misconfigured_port3_state_SHIFT 24
3931 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF
3932 #define lpfc_sli_misconfigured_port3_state_WORD word0
3934 #define lpfc_sli_misconfigured_port0_op_SHIFT 0
3935 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001
3936 #define lpfc_sli_misconfigured_port0_op_WORD word1
3937 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1
3938 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003
3939 #define lpfc_sli_misconfigured_port0_severity_WORD word1
3940 #define lpfc_sli_misconfigured_port1_op_SHIFT 8
3941 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001
3942 #define lpfc_sli_misconfigured_port1_op_WORD word1
3943 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9
3944 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003
3945 #define lpfc_sli_misconfigured_port1_severity_WORD word1
3946 #define lpfc_sli_misconfigured_port2_op_SHIFT 16
3947 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001
3948 #define lpfc_sli_misconfigured_port2_op_WORD word1
3949 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17
3950 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003
3951 #define lpfc_sli_misconfigured_port2_severity_WORD word1
3952 #define lpfc_sli_misconfigured_port3_op_SHIFT 24
3953 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001
3954 #define lpfc_sli_misconfigured_port3_op_WORD word1
3955 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25
3956 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003
3957 #define lpfc_sli_misconfigured_port3_severity_WORD word1
3959 #define LPFC_SLI_EVENT_STATUS_VALID 0x00
3960 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01
3961 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02
3962 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03
3963 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04
3964 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05
3967 struct lpfc_acqe_sli
{
3968 uint32_t event_data1
;
3969 uint32_t event_data2
;
3972 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
3973 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
3974 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
3975 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
3976 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
3977 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9
3978 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA
3982 * Define the bootstrap mailbox (bmbx) region used to communicate
3983 * mailbox command between the host and port. The mailbox consists
3984 * of a payload area of 256 bytes and a completion queue of length
3987 struct lpfc_bmbx_create
{
3988 struct lpfc_mqe mqe
;
3989 struct lpfc_mcqe mcqe
;
3992 #define SGL_ALIGN_SZ 64
3993 #define SGL_PAGE_SIZE 4096
3994 /* align SGL addr on a size boundary - adjust address up */
3995 #define NO_XRI 0xffff
3999 #define wqe_xri_tag_SHIFT 0
4000 #define wqe_xri_tag_MASK 0x0000FFFF
4001 #define wqe_xri_tag_WORD word6
4002 #define wqe_ctxt_tag_SHIFT 16
4003 #define wqe_ctxt_tag_MASK 0x0000FFFF
4004 #define wqe_ctxt_tag_WORD word6
4006 #define wqe_dif_SHIFT 0
4007 #define wqe_dif_MASK 0x00000003
4008 #define wqe_dif_WORD word7
4009 #define LPFC_WQE_DIF_PASSTHRU 1
4010 #define LPFC_WQE_DIF_STRIP 2
4011 #define LPFC_WQE_DIF_INSERT 3
4012 #define wqe_ct_SHIFT 2
4013 #define wqe_ct_MASK 0x00000003
4014 #define wqe_ct_WORD word7
4015 #define wqe_status_SHIFT 4
4016 #define wqe_status_MASK 0x0000000f
4017 #define wqe_status_WORD word7
4018 #define wqe_cmnd_SHIFT 8
4019 #define wqe_cmnd_MASK 0x000000ff
4020 #define wqe_cmnd_WORD word7
4021 #define wqe_class_SHIFT 16
4022 #define wqe_class_MASK 0x00000007
4023 #define wqe_class_WORD word7
4024 #define wqe_ar_SHIFT 19
4025 #define wqe_ar_MASK 0x00000001
4026 #define wqe_ar_WORD word7
4027 #define wqe_ag_SHIFT wqe_ar_SHIFT
4028 #define wqe_ag_MASK wqe_ar_MASK
4029 #define wqe_ag_WORD wqe_ar_WORD
4030 #define wqe_pu_SHIFT 20
4031 #define wqe_pu_MASK 0x00000003
4032 #define wqe_pu_WORD word7
4033 #define wqe_erp_SHIFT 22
4034 #define wqe_erp_MASK 0x00000001
4035 #define wqe_erp_WORD word7
4036 #define wqe_conf_SHIFT wqe_erp_SHIFT
4037 #define wqe_conf_MASK wqe_erp_MASK
4038 #define wqe_conf_WORD wqe_erp_WORD
4039 #define wqe_lnk_SHIFT 23
4040 #define wqe_lnk_MASK 0x00000001
4041 #define wqe_lnk_WORD word7
4042 #define wqe_tmo_SHIFT 24
4043 #define wqe_tmo_MASK 0x000000ff
4044 #define wqe_tmo_WORD word7
4045 uint32_t abort_tag
; /* word 8 in WQE */
4047 #define wqe_reqtag_SHIFT 0
4048 #define wqe_reqtag_MASK 0x0000FFFF
4049 #define wqe_reqtag_WORD word9
4050 #define wqe_temp_rpi_SHIFT 16
4051 #define wqe_temp_rpi_MASK 0x0000FFFF
4052 #define wqe_temp_rpi_WORD word9
4053 #define wqe_rcvoxid_SHIFT 16
4054 #define wqe_rcvoxid_MASK 0x0000FFFF
4055 #define wqe_rcvoxid_WORD word9
4057 #define wqe_ebde_cnt_SHIFT 0
4058 #define wqe_ebde_cnt_MASK 0x0000000f
4059 #define wqe_ebde_cnt_WORD word10
4060 #define wqe_nvme_SHIFT 4
4061 #define wqe_nvme_MASK 0x00000001
4062 #define wqe_nvme_WORD word10
4063 #define wqe_oas_SHIFT 6
4064 #define wqe_oas_MASK 0x00000001
4065 #define wqe_oas_WORD word10
4066 #define wqe_lenloc_SHIFT 7
4067 #define wqe_lenloc_MASK 0x00000003
4068 #define wqe_lenloc_WORD word10
4069 #define LPFC_WQE_LENLOC_NONE 0
4070 #define LPFC_WQE_LENLOC_WORD3 1
4071 #define LPFC_WQE_LENLOC_WORD12 2
4072 #define LPFC_WQE_LENLOC_WORD4 3
4073 #define wqe_qosd_SHIFT 9
4074 #define wqe_qosd_MASK 0x00000001
4075 #define wqe_qosd_WORD word10
4076 #define wqe_xbl_SHIFT 11
4077 #define wqe_xbl_MASK 0x00000001
4078 #define wqe_xbl_WORD word10
4079 #define wqe_iod_SHIFT 13
4080 #define wqe_iod_MASK 0x00000001
4081 #define wqe_iod_WORD word10
4082 #define LPFC_WQE_IOD_WRITE 0
4083 #define LPFC_WQE_IOD_READ 1
4084 #define wqe_dbde_SHIFT 14
4085 #define wqe_dbde_MASK 0x00000001
4086 #define wqe_dbde_WORD word10
4087 #define wqe_wqes_SHIFT 15
4088 #define wqe_wqes_MASK 0x00000001
4089 #define wqe_wqes_WORD word10
4090 /* Note that this field overlaps above fields */
4091 #define wqe_wqid_SHIFT 1
4092 #define wqe_wqid_MASK 0x00007fff
4093 #define wqe_wqid_WORD word10
4094 #define wqe_pri_SHIFT 16
4095 #define wqe_pri_MASK 0x00000007
4096 #define wqe_pri_WORD word10
4097 #define wqe_pv_SHIFT 19
4098 #define wqe_pv_MASK 0x00000001
4099 #define wqe_pv_WORD word10
4100 #define wqe_xc_SHIFT 21
4101 #define wqe_xc_MASK 0x00000001
4102 #define wqe_xc_WORD word10
4103 #define wqe_sr_SHIFT 22
4104 #define wqe_sr_MASK 0x00000001
4105 #define wqe_sr_WORD word10
4106 #define wqe_ccpe_SHIFT 23
4107 #define wqe_ccpe_MASK 0x00000001
4108 #define wqe_ccpe_WORD word10
4109 #define wqe_ccp_SHIFT 24
4110 #define wqe_ccp_MASK 0x000000ff
4111 #define wqe_ccp_WORD word10
4113 #define wqe_cmd_type_SHIFT 0
4114 #define wqe_cmd_type_MASK 0x0000000f
4115 #define wqe_cmd_type_WORD word11
4116 #define wqe_els_id_SHIFT 4
4117 #define wqe_els_id_MASK 0x00000003
4118 #define wqe_els_id_WORD word11
4119 #define LPFC_ELS_ID_FLOGI 3
4120 #define LPFC_ELS_ID_FDISC 2
4121 #define LPFC_ELS_ID_LOGO 1
4122 #define LPFC_ELS_ID_DEFAULT 0
4123 #define wqe_irsp_SHIFT 4
4124 #define wqe_irsp_MASK 0x00000001
4125 #define wqe_irsp_WORD word11
4126 #define wqe_sup_SHIFT 6
4127 #define wqe_sup_MASK 0x00000001
4128 #define wqe_sup_WORD word11
4129 #define wqe_wqec_SHIFT 7
4130 #define wqe_wqec_MASK 0x00000001
4131 #define wqe_wqec_WORD word11
4132 #define wqe_irsplen_SHIFT 8
4133 #define wqe_irsplen_MASK 0x0000000f
4134 #define wqe_irsplen_WORD word11
4135 #define wqe_cqid_SHIFT 16
4136 #define wqe_cqid_MASK 0x0000ffff
4137 #define wqe_cqid_WORD word11
4138 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff
4143 #define wqe_els_did_SHIFT 0
4144 #define wqe_els_did_MASK 0x00FFFFFF
4145 #define wqe_els_did_WORD word5
4146 #define wqe_xmit_bls_pt_SHIFT 28
4147 #define wqe_xmit_bls_pt_MASK 0x00000003
4148 #define wqe_xmit_bls_pt_WORD word5
4149 #define wqe_xmit_bls_ar_SHIFT 30
4150 #define wqe_xmit_bls_ar_MASK 0x00000001
4151 #define wqe_xmit_bls_ar_WORD word5
4152 #define wqe_xmit_bls_xo_SHIFT 31
4153 #define wqe_xmit_bls_xo_MASK 0x00000001
4154 #define wqe_xmit_bls_xo_WORD word5
4157 struct lpfc_wqe_generic
{
4158 struct ulp_bde64 bde
;
4162 struct wqe_common wqe_com
;
4163 uint32_t payload
[4];
4166 struct els_request64_wqe
{
4167 struct ulp_bde64 bde
;
4168 uint32_t payload_len
;
4170 #define els_req64_sid_SHIFT 0
4171 #define els_req64_sid_MASK 0x00FFFFFF
4172 #define els_req64_sid_WORD word4
4173 #define els_req64_sp_SHIFT 24
4174 #define els_req64_sp_MASK 0x00000001
4175 #define els_req64_sp_WORD word4
4176 #define els_req64_vf_SHIFT 25
4177 #define els_req64_vf_MASK 0x00000001
4178 #define els_req64_vf_WORD word4
4179 struct wqe_did wqe_dest
;
4180 struct wqe_common wqe_com
; /* words 6-11 */
4182 #define els_req64_vfid_SHIFT 1
4183 #define els_req64_vfid_MASK 0x00000FFF
4184 #define els_req64_vfid_WORD word12
4185 #define els_req64_pri_SHIFT 13
4186 #define els_req64_pri_MASK 0x00000007
4187 #define els_req64_pri_WORD word12
4189 #define els_req64_hopcnt_SHIFT 24
4190 #define els_req64_hopcnt_MASK 0x000000ff
4191 #define els_req64_hopcnt_WORD word13
4193 uint32_t max_response_payload_len
;
4196 struct xmit_els_rsp64_wqe
{
4197 struct ulp_bde64 bde
;
4198 uint32_t response_payload_len
;
4200 #define els_rsp64_sid_SHIFT 0
4201 #define els_rsp64_sid_MASK 0x00FFFFFF
4202 #define els_rsp64_sid_WORD word4
4203 #define els_rsp64_sp_SHIFT 24
4204 #define els_rsp64_sp_MASK 0x00000001
4205 #define els_rsp64_sp_WORD word4
4206 struct wqe_did wqe_dest
;
4207 struct wqe_common wqe_com
; /* words 6-11 */
4209 #define wqe_rsp_temp_rpi_SHIFT 0
4210 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF
4211 #define wqe_rsp_temp_rpi_WORD word12
4212 uint32_t rsvd_13_15
[3];
4215 struct xmit_bls_rsp64_wqe
{
4217 /* Payload0 for BA_ACC */
4218 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16
4219 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
4220 #define xmit_bls_rsp64_acc_seq_id_WORD payload0
4221 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24
4222 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
4223 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0
4224 /* Payload0 for BA_RJT */
4225 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0
4226 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
4227 #define xmit_bls_rsp64_rjt_vspec_WORD payload0
4228 #define xmit_bls_rsp64_rjt_expc_SHIFT 8
4229 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
4230 #define xmit_bls_rsp64_rjt_expc_WORD payload0
4231 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16
4232 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
4233 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0
4235 #define xmit_bls_rsp64_rxid_SHIFT 0
4236 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff
4237 #define xmit_bls_rsp64_rxid_WORD word1
4238 #define xmit_bls_rsp64_oxid_SHIFT 16
4239 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff
4240 #define xmit_bls_rsp64_oxid_WORD word1
4242 #define xmit_bls_rsp64_seqcnthi_SHIFT 0
4243 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
4244 #define xmit_bls_rsp64_seqcnthi_WORD word2
4245 #define xmit_bls_rsp64_seqcntlo_SHIFT 16
4246 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
4247 #define xmit_bls_rsp64_seqcntlo_WORD word2
4250 struct wqe_did wqe_dest
;
4251 struct wqe_common wqe_com
; /* words 6-11 */
4253 #define xmit_bls_rsp64_temprpi_SHIFT 0
4254 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff
4255 #define xmit_bls_rsp64_temprpi_WORD word12
4256 uint32_t rsvd_13_15
[3];
4259 struct wqe_rctl_dfctl
{
4261 #define wqe_si_SHIFT 2
4262 #define wqe_si_MASK 0x000000001
4263 #define wqe_si_WORD word5
4264 #define wqe_la_SHIFT 3
4265 #define wqe_la_MASK 0x000000001
4266 #define wqe_la_WORD word5
4267 #define wqe_xo_SHIFT 6
4268 #define wqe_xo_MASK 0x000000001
4269 #define wqe_xo_WORD word5
4270 #define wqe_ls_SHIFT 7
4271 #define wqe_ls_MASK 0x000000001
4272 #define wqe_ls_WORD word5
4273 #define wqe_dfctl_SHIFT 8
4274 #define wqe_dfctl_MASK 0x0000000ff
4275 #define wqe_dfctl_WORD word5
4276 #define wqe_type_SHIFT 16
4277 #define wqe_type_MASK 0x0000000ff
4278 #define wqe_type_WORD word5
4279 #define wqe_rctl_SHIFT 24
4280 #define wqe_rctl_MASK 0x0000000ff
4281 #define wqe_rctl_WORD word5
4284 struct xmit_seq64_wqe
{
4285 struct ulp_bde64 bde
;
4287 uint32_t relative_offset
;
4288 struct wqe_rctl_dfctl wge_ctl
;
4289 struct wqe_common wqe_com
; /* words 6-11 */
4291 uint32_t rsvd_12_15
[3];
4293 struct xmit_bcast64_wqe
{
4294 struct ulp_bde64 bde
;
4295 uint32_t seq_payload_len
;
4297 struct wqe_rctl_dfctl wge_ctl
; /* word 5 */
4298 struct wqe_common wqe_com
; /* words 6-11 */
4299 uint32_t rsvd_12_15
[4];
4302 struct gen_req64_wqe
{
4303 struct ulp_bde64 bde
;
4304 uint32_t request_payload_len
;
4305 uint32_t relative_offset
;
4306 struct wqe_rctl_dfctl wge_ctl
; /* word 5 */
4307 struct wqe_common wqe_com
; /* words 6-11 */
4308 uint32_t rsvd_12_14
[3];
4309 uint32_t max_response_payload_len
;
4312 /* Define NVME PRLI request to fabric. NVME is a
4313 * fabric-only protocol.
4314 * Updated to red-lined v1.08 on Sept 16, 2016
4316 struct lpfc_nvme_prli
{
4318 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */
4319 #define prli_acc_rsp_code_SHIFT 8
4320 #define prli_acc_rsp_code_MASK 0x0000000f
4321 #define prli_acc_rsp_code_WORD word1
4322 #define prli_estabImagePair_SHIFT 13
4323 #define prli_estabImagePair_MASK 0x00000001
4324 #define prli_estabImagePair_WORD word1
4325 #define prli_type_code_ext_SHIFT 16
4326 #define prli_type_code_ext_MASK 0x000000ff
4327 #define prli_type_code_ext_WORD word1
4328 #define prli_type_code_SHIFT 24
4329 #define prli_type_code_MASK 0x000000ff
4330 #define prli_type_code_WORD word1
4331 uint32_t word_rsvd2
;
4332 uint32_t word_rsvd3
;
4334 #define prli_fba_SHIFT 0
4335 #define prli_fba_MASK 0x00000001
4336 #define prli_fba_WORD word4
4337 #define prli_disc_SHIFT 3
4338 #define prli_disc_MASK 0x00000001
4339 #define prli_disc_WORD word4
4340 #define prli_tgt_SHIFT 4
4341 #define prli_tgt_MASK 0x00000001
4342 #define prli_tgt_WORD word4
4343 #define prli_init_SHIFT 5
4344 #define prli_init_MASK 0x00000001
4345 #define prli_init_WORD word4
4346 #define prli_recov_SHIFT 8
4347 #define prli_recov_MASK 0x00000001
4348 #define prli_recov_WORD word4
4350 #define prli_fb_sz_SHIFT 0
4351 #define prli_fb_sz_MASK 0x0000ffff
4352 #define prli_fb_sz_WORD word5
4353 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */
4356 struct create_xri_wqe
{
4357 uint32_t rsrvd
[5]; /* words 0-4 */
4358 struct wqe_did wqe_dest
; /* word 5 */
4359 struct wqe_common wqe_com
; /* words 6-11 */
4360 uint32_t rsvd_12_15
[4]; /* word 12-15 */
4363 #define T_REQUEST_TAG 3
4366 struct abort_cmd_wqe
{
4369 #define abort_cmd_ia_SHIFT 0
4370 #define abort_cmd_ia_MASK 0x000000001
4371 #define abort_cmd_ia_WORD word3
4372 #define abort_cmd_criteria_SHIFT 8
4373 #define abort_cmd_criteria_MASK 0x0000000ff
4374 #define abort_cmd_criteria_WORD word3
4377 struct wqe_common wqe_com
; /* words 6-11 */
4378 uint32_t rsvd_12_15
[4]; /* word 12-15 */
4381 struct fcp_iwrite64_wqe
{
4382 struct ulp_bde64 bde
;
4384 #define cmd_buff_len_SHIFT 16
4385 #define cmd_buff_len_MASK 0x00000ffff
4386 #define cmd_buff_len_WORD word3
4387 #define payload_offset_len_SHIFT 0
4388 #define payload_offset_len_MASK 0x0000ffff
4389 #define payload_offset_len_WORD word3
4390 uint32_t total_xfer_len
;
4391 uint32_t initial_xfer_len
;
4392 struct wqe_common wqe_com
; /* words 6-11 */
4394 struct ulp_bde64 ph_bde
; /* words 13-15 */
4397 struct fcp_iread64_wqe
{
4398 struct ulp_bde64 bde
;
4400 #define cmd_buff_len_SHIFT 16
4401 #define cmd_buff_len_MASK 0x00000ffff
4402 #define cmd_buff_len_WORD word3
4403 #define payload_offset_len_SHIFT 0
4404 #define payload_offset_len_MASK 0x0000ffff
4405 #define payload_offset_len_WORD word3
4406 uint32_t total_xfer_len
; /* word 4 */
4407 uint32_t rsrvd5
; /* word 5 */
4408 struct wqe_common wqe_com
; /* words 6-11 */
4410 struct ulp_bde64 ph_bde
; /* words 13-15 */
4413 struct fcp_icmnd64_wqe
{
4414 struct ulp_bde64 bde
; /* words 0-2 */
4416 #define cmd_buff_len_SHIFT 16
4417 #define cmd_buff_len_MASK 0x00000ffff
4418 #define cmd_buff_len_WORD word3
4419 #define payload_offset_len_SHIFT 0
4420 #define payload_offset_len_MASK 0x0000ffff
4421 #define payload_offset_len_WORD word3
4422 uint32_t rsrvd4
; /* word 4 */
4423 uint32_t rsrvd5
; /* word 5 */
4424 struct wqe_common wqe_com
; /* words 6-11 */
4425 uint32_t rsvd_12_15
[4]; /* word 12-15 */
4428 struct fcp_trsp64_wqe
{
4429 struct ulp_bde64 bde
;
4430 uint32_t response_len
;
4431 uint32_t rsvd_4_5
[2];
4432 struct wqe_common wqe_com
; /* words 6-11 */
4433 uint32_t rsvd_12_15
[4]; /* word 12-15 */
4436 struct fcp_tsend64_wqe
{
4437 struct ulp_bde64 bde
;
4438 uint32_t payload_offset_len
;
4439 uint32_t relative_offset
;
4441 struct wqe_common wqe_com
; /* words 6-11 */
4442 uint32_t fcp_data_len
; /* word 12 */
4443 uint32_t rsvd_13_15
[3]; /* word 13-15 */
4446 struct fcp_treceive64_wqe
{
4447 struct ulp_bde64 bde
;
4448 uint32_t payload_offset_len
;
4449 uint32_t relative_offset
;
4451 struct wqe_common wqe_com
; /* words 6-11 */
4452 uint32_t fcp_data_len
; /* word 12 */
4453 uint32_t rsvd_13_15
[3]; /* word 13-15 */
4455 #define TXRDY_PAYLOAD_LEN 12
4457 #define CMD_SEND_FRAME 0xE1
4459 struct send_frame_wqe
{
4460 struct ulp_bde64 bde
; /* words 0-2 */
4461 uint32_t frame_len
; /* word 3 */
4462 uint32_t fc_hdr_wd0
; /* word 4 */
4463 uint32_t fc_hdr_wd1
; /* word 5 */
4464 struct wqe_common wqe_com
; /* words 6-11 */
4465 uint32_t fc_hdr_wd2
; /* word 12 */
4466 uint32_t fc_hdr_wd3
; /* word 13 */
4467 uint32_t fc_hdr_wd4
; /* word 14 */
4468 uint32_t fc_hdr_wd5
; /* word 15 */
4473 struct lpfc_wqe_generic generic
;
4474 struct fcp_icmnd64_wqe fcp_icmd
;
4475 struct fcp_iread64_wqe fcp_iread
;
4476 struct fcp_iwrite64_wqe fcp_iwrite
;
4477 struct abort_cmd_wqe abort_cmd
;
4478 struct create_xri_wqe create_xri
;
4479 struct xmit_bcast64_wqe xmit_bcast64
;
4480 struct xmit_seq64_wqe xmit_sequence
;
4481 struct xmit_bls_rsp64_wqe xmit_bls_rsp
;
4482 struct xmit_els_rsp64_wqe xmit_els_rsp
;
4483 struct els_request64_wqe els_req
;
4484 struct gen_req64_wqe gen_req
;
4485 struct fcp_trsp64_wqe fcp_trsp
;
4486 struct fcp_tsend64_wqe fcp_tsend
;
4487 struct fcp_treceive64_wqe fcp_treceive
;
4488 struct send_frame_wqe send_frame
;
4493 struct lpfc_wqe_generic generic
;
4494 struct fcp_icmnd64_wqe fcp_icmd
;
4495 struct fcp_iread64_wqe fcp_iread
;
4496 struct fcp_iwrite64_wqe fcp_iwrite
;
4497 struct fcp_trsp64_wqe fcp_trsp
;
4498 struct fcp_tsend64_wqe fcp_tsend
;
4499 struct fcp_treceive64_wqe fcp_treceive
;
4500 struct xmit_seq64_wqe xmit_sequence
;
4501 struct gen_req64_wqe gen_req
;
4504 #define LPFC_GROUP_OJECT_MAGIC_G5 0xfeaa0001
4505 #define LPFC_GROUP_OJECT_MAGIC_G6 0xfeaa0003
4506 #define LPFC_FILE_TYPE_GROUP 0xf7
4507 #define LPFC_FILE_ID_GROUP 0xa2
4508 struct lpfc_grp_hdr
{
4510 uint32_t magic_number
;
4512 #define lpfc_grp_hdr_file_type_SHIFT 24
4513 #define lpfc_grp_hdr_file_type_MASK 0x000000FF
4514 #define lpfc_grp_hdr_file_type_WORD word2
4515 #define lpfc_grp_hdr_id_SHIFT 16
4516 #define lpfc_grp_hdr_id_MASK 0x000000FF
4517 #define lpfc_grp_hdr_id_WORD word2
4518 uint8_t rev_name
[128];
4520 uint8_t revision
[32];
4523 /* Defines for WQE command type */
4524 #define FCP_COMMAND 0x0
4525 #define NVME_READ_CMD 0x0
4526 #define FCP_COMMAND_DATA_OUT 0x1
4527 #define NVME_WRITE_CMD 0x1
4528 #define FCP_COMMAND_TRECEIVE 0x2
4529 #define FCP_COMMAND_TRSP 0x3
4530 #define FCP_COMMAND_TSEND 0x7
4531 #define OTHER_COMMAND 0x8
4532 #define ELS_COMMAND_NON_FIP 0xC
4533 #define ELS_COMMAND_FIP 0xD
4535 #define LPFC_NVME_EMBED_CMD 0x0
4536 #define LPFC_NVME_EMBED_WRITE 0x1
4537 #define LPFC_NVME_EMBED_READ 0x2
4540 #define CMD_ABORT_XRI_WQE 0x0F
4541 #define CMD_XMIT_SEQUENCE64_WQE 0x82
4542 #define CMD_XMIT_BCAST64_WQE 0x84
4543 #define CMD_ELS_REQUEST64_WQE 0x8A
4544 #define CMD_XMIT_ELS_RSP64_WQE 0x95
4545 #define CMD_XMIT_BLS_RSP64_WQE 0x97
4546 #define CMD_FCP_IWRITE64_WQE 0x98
4547 #define CMD_FCP_IREAD64_WQE 0x9A
4548 #define CMD_FCP_ICMND64_WQE 0x9C
4549 #define CMD_FCP_TSEND64_WQE 0x9F
4550 #define CMD_FCP_TRECEIVE64_WQE 0xA1
4551 #define CMD_FCP_TRSP64_WQE 0xA3
4552 #define CMD_GEN_REQUEST64_WQE 0xC2
4554 #define CMD_WQE_MASK 0xff
4557 #define LPFC_FW_DUMP 1
4558 #define LPFC_FW_RESET 2
4559 #define LPFC_DV_RESET 3