drivers/scsi/mvsas/mv_sas.h

   1 /*
   2  * Marvell 88SE64xx/88SE94xx main function head file
   3  *
   4  * Copyright 2007 Red Hat, Inc.
   5  * Copyright 2008 Marvell. <kewei@marvell.com>
   6  * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
   7  *
   8  * This file is licensed under GPLv2.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; version 2 of the
  13  * License.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  23  * USA
  24 */
  25
  26 #ifndef _MV_SAS_H_
  27 #define _MV_SAS_H_
  28
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/delay.h>
  33 #include <linux/types.h>
  34 #include <linux/ctype.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/pci.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/irq.h>
  40 #include <linux/slab.h>
  41 #include <linux/vmalloc.h>
  42 #include <asm/unaligned.h>
  43 #include <scsi/libsas.h>
  44 #include <scsi/scsi.h>
  45 #include <scsi/scsi_tcq.h>
  46 #include <scsi/sas_ata.h>
  47 #include "mv_defs.h"
  48
  49 #define DRV_NAME                "mvsas"
  50 #define DRV_VERSION             "0.8.16"
  51 #define MVS_ID_NOT_MAPPED       0x7f
  52 #define WIDE_PORT_MAX_PHY               4
  53 #define mv_printk(fmt, arg ...) \
  54         printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
  55 #ifdef MV_DEBUG
  56 #define mv_dprintk(format, arg...)      \
  57         printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
  58 #else
  59 #define mv_dprintk(format, arg...)
  60 #endif
  61 #define MV_MAX_U32                      0xffffffff
  62
  63 extern int interrupt_coalescing;
  64 extern struct mvs_tgt_initiator mvs_tgt;
  65 extern struct mvs_info *tgt_mvi;
  66 extern const struct mvs_dispatch mvs_64xx_dispatch;
  67 extern const struct mvs_dispatch mvs_94xx_dispatch;
  68
  69 #define DEV_IS_EXPANDER(type)   \
  70         ((type == SAS_EDGE_EXPANDER_DEVICE) || (type == SAS_FANOUT_EXPANDER_DEVICE))
  71
  72 #define bit(n) ((u64)1 << n)
  73
  74 #define for_each_phy(__lseq_mask, __mc, __lseq)                 \
  75         for ((__mc) = (__lseq_mask), (__lseq) = 0;              \
  76                                         (__mc) != 0 ;           \
  77                                         (++__lseq), (__mc) >>= 1)
  78
  79 #define MVS_PHY_ID (1U << sas_phy->id)
  80 #define MV_INIT_DELAYED_WORK(w, f, d)   INIT_DELAYED_WORK(w, f)
  81 #define UNASSOC_D2H_FIS(id)             \
  82         ((void *) mvi->rx_fis + 0x100 * id)
  83 #define SATA_RECEIVED_FIS_LIST(reg_set) \
  84         ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
  85 #define SATA_RECEIVED_SDB_FIS(reg_set)  \
  86         (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
  87 #define SATA_RECEIVED_D2H_FIS(reg_set)  \
  88         (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
  89 #define SATA_RECEIVED_PIO_FIS(reg_set)  \
  90         (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
  91 #define SATA_RECEIVED_DMA_FIS(reg_set)  \
  92         (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
  93
  94 enum dev_status {
  95         MVS_DEV_NORMAL = 0x0,
  96         MVS_DEV_EH      = 0x1,
  97 };
  98
  99 enum dev_reset {
 100         MVS_SOFT_RESET  = 0,
 101         MVS_HARD_RESET  = 1,
 102         MVS_PHY_TUNE    = 2,
 103 };
 104
 105 struct mvs_info;
 106 struct mvs_prv_info;
 107
 108 struct mvs_dispatch {
 109         char *name;
 110         int (*chip_init)(struct mvs_info *mvi);
 111         int (*spi_init)(struct mvs_info *mvi);
 112         int (*chip_ioremap)(struct mvs_info *mvi);
 113         void (*chip_iounmap)(struct mvs_info *mvi);
 114         irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat);
 115         u32 (*isr_status)(struct mvs_info *mvi, int irq);
 116         void (*interrupt_enable)(struct mvs_info *mvi);
 117         void (*interrupt_disable)(struct mvs_info *mvi);
 118
 119         u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port);
 120         void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val);
 121
 122         u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port);
 123         void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val);
 124         void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr);
 125
 126         u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port);
 127         void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val);
 128         void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr);
 129
 130         u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port);
 131         void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val);
 132
 133         u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port);
 134         void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val);
 135
 136         void (*command_active)(struct mvs_info *mvi, u32 slot_idx);
 137         void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all);
 138         void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type,
 139                                 u32 tfs);
 140         void (*start_delivery)(struct mvs_info *mvi, u32 tx);
 141         u32 (*rx_update)(struct mvs_info *mvi);
 142         void (*int_full)(struct mvs_info *mvi);
 143         u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs);
 144         void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs);
 145         u32 (*prd_size)(void);
 146         u32 (*prd_count)(void);
 147         void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
 148         void (*detect_porttype)(struct mvs_info *mvi, int i);
 149         int (*oob_done)(struct mvs_info *mvi, int i);
 150         void (*fix_phy_info)(struct mvs_info *mvi, int i,
 151                                 struct sas_identify_frame *id);
 152         void (*phy_work_around)(struct mvs_info *mvi, int i);
 153         void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id,
 154                                 struct sas_phy_linkrates *rates);
 155         u32 (*phy_max_link_rate)(void);
 156         void (*phy_disable)(struct mvs_info *mvi, u32 phy_id);
 157         void (*phy_enable)(struct mvs_info *mvi, u32 phy_id);
 158         void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard);
 159         void (*stp_reset)(struct mvs_info *mvi, u32 phy_id);
 160         void (*clear_active_cmds)(struct mvs_info *mvi);
 161         u32 (*spi_read_data)(struct mvs_info *mvi);
 162         void (*spi_write_data)(struct mvs_info *mvi, u32 data);
 163         int (*spi_buildcmd)(struct mvs_info *mvi,
 164                                                 u32      *dwCmd,
 165                                                 u8       cmd,
 166                                                 u8       read,
 167                                                 u8       length,
 168                                                 u32      addr
 169                                                 );
 170         int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd);
 171         int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout);
 172         void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask,
 173                                 int buf_len, int from, void *prd);
 174         void (*tune_interrupt)(struct mvs_info *mvi, u32 time);
 175         void (*non_spec_ncq_error)(struct mvs_info *mvi);
 176         int (*gpio_write)(struct mvs_prv_info *mvs_prv, u8 reg_type,
 177                         u8 reg_index, u8 reg_count, u8 *write_data);
 178
 179 };
 180
 181 struct mvs_chip_info {
 182         u32             n_host;
 183         u32             n_phy;
 184         u32             fis_offs;
 185         u32             fis_count;
 186         u32             srs_sz;
 187         u32             sg_width;
 188         u32             slot_width;
 189         const struct mvs_dispatch *dispatch;
 190 };
 191 #define MVS_MAX_SG              (1U << mvi->chip->sg_width)
 192 #define MVS_CHIP_SLOT_SZ        (1U << mvi->chip->slot_width)
 193 #define MVS_RX_FISL_SZ          \
 194         (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
 195 #define MVS_CHIP_DISP           (mvi->chip->dispatch)
 196
 197 struct mvs_err_info {
 198         __le32                  flags;
 199         __le32                  flags2;
 200 };
 201
 202 struct mvs_cmd_hdr {
 203         __le32                  flags;  /* PRD tbl len; SAS, SATA ctl */
 204         __le32                  lens;   /* cmd, max resp frame len */
 205         __le32                  tags;   /* targ port xfer tag; tag */
 206         __le32                  data_len;       /* data xfer len */
 207         __le64                  cmd_tbl;        /* command table address */
 208         __le64                  open_frame;     /* open addr frame address */
 209         __le64                  status_buf;     /* status buffer address */
 210         __le64                  prd_tbl;                /* PRD tbl address */
 211         __le32                  reserved[4];
 212 };
 213
 214 struct mvs_port {
 215         struct asd_sas_port     sas_port;
 216         u8                      port_attached;
 217         u8                      wide_port_phymap;
 218         struct list_head        list;
 219 };
 220
 221 struct mvs_phy {
 222         struct mvs_info                 *mvi;
 223         struct mvs_port         *port;
 224         struct asd_sas_phy      sas_phy;
 225         struct sas_identify     identify;
 226         struct scsi_device      *sdev;
 227         struct timer_list timer;
 228         u64             dev_sas_addr;
 229         u64             att_dev_sas_addr;
 230         u32             att_dev_info;
 231         u32             dev_info;
 232         u32             phy_type;
 233         u32             phy_status;
 234         u32             irq_status;
 235         u32             frame_rcvd_size;
 236         u8              frame_rcvd[32];
 237         u8              phy_attached;
 238         u8              phy_mode;
 239         u8              reserved[2];
 240         u32             phy_event;
 241         enum sas_linkrate       minimum_linkrate;
 242         enum sas_linkrate       maximum_linkrate;
 243 };
 244
 245 struct mvs_device {
 246         struct list_head                dev_entry;
 247         enum sas_device_type dev_type;
 248         struct mvs_info *mvi_info;
 249         struct domain_device *sas_device;
 250         u32 attached_phy;
 251         u32 device_id;
 252         u32 running_req;
 253         u8 taskfileset;
 254         u8 dev_status;
 255         u16 reserved;
 256 };
 257
 258 /* Generate  PHY tunning parameters */
 259 struct phy_tuning {
 260         /* 1 bit,  transmitter emphasis enable  */
 261         u8      trans_emp_en:1;
 262         /* 4 bits, transmitter emphasis amplitude */
 263         u8      trans_emp_amp:4;
 264         /* 3 bits, reserved space */
 265         u8      Reserved_2bit_1:3;
 266         /* 5 bits, transmitter amplitude */
 267         u8      trans_amp:5;
 268         /* 2 bits, transmitter amplitude adjust */
 269         u8      trans_amp_adj:2;
 270         /* 1 bit, reserved space */
 271         u8      resv_2bit_2:1;
 272         /* 2 bytes, reserved space */
 273         u8      reserved[2];
 274 };
 275
 276 struct ffe_control {
 277         /* 4 bits,  FFE Capacitor Select  (value range 0~F)  */
 278         u8 ffe_cap_sel:4;
 279         /* 3 bits,  FFE Resistor Select (value range 0~7) */
 280         u8 ffe_rss_sel:3;
 281         /* 1 bit reserve*/
 282         u8 reserved:1;
 283 };
 284
 285 /*
 286  * HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes.
 287  * The data area is valid only Signature="MRVL".
 288  * If any member fills with 0xFF, the member is invalid.
 289  */
 290 struct hba_info_page {
 291         /* Dword 0 */
 292         /* 4 bytes, structure signature,should be "MRVL" at first initial */
 293         u8 signature[4];
 294
 295         /* Dword 1-13 */
 296         u32 reserved1[13];
 297
 298         /* Dword 14-29 */
 299         /* 64 bytes, SAS address for each port */
 300         u64 sas_addr[8];
 301
 302         /* Dword 30-31 */
 303         /* 8 bytes for vanir 8 port PHY FFE seeting
 304          * BIT 0~3 : FFE Capacitor select(value range 0~F)
 305          * BIT 4~6 : FFE Resistor select(value range 0~7)
 306          * BIT 7: reserve.
 307          */
 308
 309         struct ffe_control  ffe_ctl[8];
 310         /* Dword 32 -43 */
 311         u32 reserved2[12];
 312
 313         /* Dword 44-45 */
 314         /* 8 bytes,  0:  1.5G, 1: 3.0G, should be 0x01 at first initial */
 315         u8 phy_rate[8];
 316
 317         /* Dword 46-53 */
 318         /* 32 bytes, PHY tuning parameters for each PHY*/
 319         struct phy_tuning   phy_tuning[8];
 320
 321         /* Dword 54-63 */
 322         u32 reserved3[10];
 323 };      /* total 256 bytes */
 324
 325 struct mvs_slot_info {
 326         struct list_head entry;
 327         union {
 328                 struct sas_task *task;
 329                 void *tdata;
 330         };
 331         u32 n_elem;
 332         u32 tx;
 333         u32 slot_tag;
 334
 335         /* DMA buffer for storing cmd tbl, open addr frame, status buffer,
 336          * and PRD table
 337          */
 338         void *buf;
 339         dma_addr_t buf_dma;
 340         void *response;
 341         struct mvs_port *port;
 342         struct mvs_device       *device;
 343         void *open_frame;
 344 };
 345
 346 struct mvs_info {
 347         unsigned long flags;
 348
 349         /* host-wide lock */
 350         spinlock_t lock;
 351
 352         /* our device */
 353         struct pci_dev *pdev;
 354         struct device *dev;
 355
 356         /* enhanced mode registers */
 357         void __iomem *regs;
 358
 359         /* peripheral or soc registers */
 360         void __iomem *regs_ex;
 361         u8 sas_addr[SAS_ADDR_SIZE];
 362
 363         /* SCSI/SAS glue */
 364         struct sas_ha_struct *sas;
 365         struct Scsi_Host *shost;
 366
 367         /* TX (delivery) DMA ring */
 368         __le32 *tx;
 369         dma_addr_t tx_dma;
 370
 371         /* cached next-producer idx */
 372         u32 tx_prod;
 373
 374         /* RX (completion) DMA ring */
 375         __le32  *rx;
 376         dma_addr_t rx_dma;
 377
 378         /* RX consumer idx */
 379         u32 rx_cons;
 380
 381         /* RX'd FIS area */
 382         __le32 *rx_fis;
 383         dma_addr_t rx_fis_dma;
 384
 385         /* DMA command header slots */
 386         struct mvs_cmd_hdr *slot;
 387         dma_addr_t slot_dma;
 388
 389         u32 chip_id;
 390         const struct mvs_chip_info *chip;
 391
 392         int tags_num;
 393         unsigned long *tags;
 394         /* further per-slot information */
 395         struct mvs_phy phy[MVS_MAX_PHYS];
 396         struct mvs_port port[MVS_MAX_PHYS];
 397         u32 id;
 398         u64 sata_reg_set;
 399         struct list_head *hba_list;
 400         struct list_head soc_entry;
 401         struct list_head wq_list;
 402         unsigned long instance;
 403         u16 flashid;
 404         u32 flashsize;
 405         u32 flashsectSize;
 406
 407         void *addon;
 408         struct hba_info_page hba_info_param;
 409         struct mvs_device       devices[MVS_MAX_DEVICES];
 410         void *bulk_buffer;
 411         dma_addr_t bulk_buffer_dma;
 412         void *bulk_buffer1;
 413         dma_addr_t bulk_buffer_dma1;
 414 #define TRASH_BUCKET_SIZE       0x20000
 415         void *dma_pool;
 416         struct mvs_slot_info slot_info[0];
 417 };
 418
 419 struct mvs_prv_info{
 420         u8 n_host;
 421         u8 n_phy;
 422         u8 scan_finished;
 423         u8 reserve;
 424         struct mvs_info *mvi[2];
 425         struct tasklet_struct mv_tasklet;
 426 };
 427
 428 struct mvs_wq {
 429         struct delayed_work work_q;
 430         struct mvs_info *mvi;
 431         void *data;
 432         int handler;
 433         struct list_head entry;
 434 };
 435
 436 struct mvs_task_exec_info {
 437         struct sas_task *task;
 438         struct mvs_cmd_hdr *hdr;
 439         struct mvs_port *port;
 440         u32 tag;
 441         int n_elem;
 442 };
 443
 444 /******************** function prototype *********************/
 445 void mvs_get_sas_addr(void *buf, u32 buflen);
 446 void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
 447 void mvs_tag_free(struct mvs_info *mvi, u32 tag);
 448 void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
 449 int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out);
 450 void mvs_tag_init(struct mvs_info *mvi);
 451 void mvs_iounmap(void __iomem *regs);
 452 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
 453 void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
 454 int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
 455                         void *funcdata);
 456 void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
 457                       u32 off_hi, u64 sas_addr);
 458 void mvs_scan_start(struct Scsi_Host *shost);
 459 int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
 460 int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags);
 461 int mvs_abort_task(struct sas_task *task);
 462 int mvs_abort_task_set(struct domain_device *dev, u8 *lun);
 463 int mvs_clear_aca(struct domain_device *dev, u8 *lun);
 464 int mvs_clear_task_set(struct domain_device *dev, u8 * lun);
 465 void mvs_port_formed(struct asd_sas_phy *sas_phy);
 466 void mvs_port_deformed(struct asd_sas_phy *sas_phy);
 467 int mvs_dev_found(struct domain_device *dev);
 468 void mvs_dev_gone(struct domain_device *dev);
 469 int mvs_lu_reset(struct domain_device *dev, u8 *lun);
 470 int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
 471 int mvs_I_T_nexus_reset(struct domain_device *dev);
 472 int mvs_query_task(struct sas_task *task);
 473 void mvs_release_task(struct mvs_info *mvi,
 474                         struct domain_device *dev);
 475 void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
 476                         struct domain_device *dev);
 477 void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
 478 void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
 479 int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
 480 struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set);
 481 int mvs_gpio_write(struct sas_ha_struct *, u8 reg_type, u8 reg_index,
 482                         u8 reg_count, u8 *write_data);
 483 #endif
 484