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[linux/fpc-iii.git] / drivers / scsi / pm8001 / pm80xx_hwi.h
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1 /*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
41 #ifndef _PMC8001_REG_H_
42 #define _PMC8001_REG_H_
44 #include <linux/types.h>
45 #include <scsi/libsas.h>
47 /* for Request Opcode of IOMB */
48 #define OPC_INB_ECHO 1 /* 0x000 */
49 #define OPC_INB_PHYSTART 4 /* 0x004 */
50 #define OPC_INB_PHYSTOP 5 /* 0x005 */
51 #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
52 #define OPC_INB_SSPINITMSTART 7 /* 0x007 */
53 /* 0x8 RESV IN SPCv */
54 #define OPC_INB_RSVD 8 /* 0x008 */
55 #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
56 #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
57 #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
58 /* 0xC, 0xD, 0xE removed in SPCv */
59 #define OPC_INB_SSP_ABORT 15 /* 0x00F */
60 #define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */
61 #define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */
62 #define OPC_INB_SMP_REQUEST 18 /* 0x012 */
63 /* 0x13 SMP_RESPONSE is removed in SPCv */
64 #define OPC_INB_SMP_ABORT 20 /* 0x014 */
65 /* 0x16 RESV IN SPCv */
66 #define OPC_INB_RSVD1 22 /* 0x016 */
67 #define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */
68 #define OPC_INB_SATA_ABORT 24 /* 0x018 */
69 #define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */
70 /* 0x1A RESV IN SPCv */
71 #define OPC_INB_RSVD2 26 /* 0x01A */
72 #define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */
73 #define OPC_INB_GPIO 34 /* 0x022 */
74 #define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */
75 #define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */
76 /* 0x25 RESV IN SPCv */
77 #define OPC_INB_RSVD3 37 /* 0x025 */
78 #define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */
79 #define OPC_INB_PORT_CONTROL 39 /* 0x027 */
80 #define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */
81 #define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */
82 #define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */
83 #define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */
84 #define OPC_INB_SET_DEV_INFO 44 /* 0x02C */
85 /* 0x2D RESV IN SPCv */
86 #define OPC_INB_RSVD4 45 /* 0x02D */
87 #define OPC_INB_SGPIO_REGISTER 46 /* 0x02E */
88 #define OPC_INB_PCIE_DIAG_EXEC 47 /* 0x02F */
89 #define OPC_INB_SET_CONTROLLER_CONFIG 48 /* 0x030 */
90 #define OPC_INB_GET_CONTROLLER_CONFIG 49 /* 0x031 */
91 #define OPC_INB_REG_DEV 50 /* 0x032 */
92 #define OPC_INB_SAS_HW_EVENT_ACK 51 /* 0x033 */
93 #define OPC_INB_GET_DEVICE_INFO 52 /* 0x034 */
94 #define OPC_INB_GET_PHY_PROFILE 53 /* 0x035 */
95 #define OPC_INB_FLASH_OP_EXT 54 /* 0x036 */
96 #define OPC_INB_SET_PHY_PROFILE 55 /* 0x037 */
97 #define OPC_INB_KEK_MANAGEMENT 256 /* 0x100 */
98 #define OPC_INB_DEK_MANAGEMENT 257 /* 0x101 */
99 #define OPC_INB_SSP_INI_DIF_ENC_IO 258 /* 0x102 */
100 #define OPC_INB_SATA_DIF_ENC_IO 259 /* 0x103 */
102 /* for Response Opcode of IOMB */
103 #define OPC_OUB_ECHO 1 /* 0x001 */
104 #define OPC_OUB_RSVD 4 /* 0x004 */
105 #define OPC_OUB_SSP_COMP 5 /* 0x005 */
106 #define OPC_OUB_SMP_COMP 6 /* 0x006 */
107 #define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */
108 #define OPC_OUB_RSVD1 10 /* 0x00A */
109 #define OPC_OUB_DEREG_DEV 11 /* 0x00B */
110 #define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */
111 #define OPC_OUB_SATA_COMP 13 /* 0x00D */
112 #define OPC_OUB_SATA_EVENT 14 /* 0x00E */
113 #define OPC_OUB_SSP_EVENT 15 /* 0x00F */
114 #define OPC_OUB_RSVD2 16 /* 0x010 */
115 /* 0x11 - SMP_RECEIVED Notification removed in SPCv*/
116 #define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */
117 #define OPC_OUB_RSVD3 19 /* 0x013 */
118 #define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */
119 #define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */
120 #define OPC_OUB_GPIO_EVENT 23 /* 0x017 */
121 #define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */
122 #define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */
123 #define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */
124 #define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */
125 #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
126 #define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */
127 #define OPC_OUB_RSVD4 31 /* 0x01F */
128 #define OPC_OUB_PORT_CONTROL 32 /* 0x020 */
129 #define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */
130 #define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */
131 #define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */
132 #define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */
133 #define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */
134 #define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */
135 #define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */
136 #define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */
137 #define OPC_OUB_RSVD5 41 /* 0x029 */
138 #define OPC_OUB_HW_EVENT 1792 /* 0x700 */
139 #define OPC_OUB_DEV_HANDLE_ARRIV 1824 /* 0x720 */
140 #define OPC_OUB_THERM_HW_EVENT 1840 /* 0x730 */
141 #define OPC_OUB_SGPIO_RESP 2094 /* 0x82E */
142 #define OPC_OUB_PCIE_DIAG_EXECUTE 2095 /* 0x82F */
143 #define OPC_OUB_DEV_REGIST 2098 /* 0x832 */
144 #define OPC_OUB_SAS_HW_EVENT_ACK 2099 /* 0x833 */
145 #define OPC_OUB_GET_DEVICE_INFO 2100 /* 0x834 */
146 /* spcv specific commands */
147 #define OPC_OUB_PHY_START_RESP 2052 /* 0x804 */
148 #define OPC_OUB_PHY_STOP_RESP 2053 /* 0x805 */
149 #define OPC_OUB_SET_CONTROLLER_CONFIG 2096 /* 0x830 */
150 #define OPC_OUB_GET_CONTROLLER_CONFIG 2097 /* 0x831 */
151 #define OPC_OUB_GET_PHY_PROFILE 2101 /* 0x835 */
152 #define OPC_OUB_FLASH_OP_EXT 2102 /* 0x836 */
153 #define OPC_OUB_SET_PHY_PROFILE 2103 /* 0x837 */
154 #define OPC_OUB_KEK_MANAGEMENT_RESP 2304 /* 0x900 */
155 #define OPC_OUB_DEK_MANAGEMENT_RESP 2305 /* 0x901 */
156 #define OPC_OUB_SSP_COALESCED_COMP_RESP 2306 /* 0x902 */
158 /* for phy start*/
159 #define SSC_DISABLE_15 (0x01 << 16)
160 #define SSC_DISABLE_30 (0x02 << 16)
161 #define SSC_DISABLE_60 (0x04 << 16)
162 #define SAS_ASE (0x01 << 15)
163 #define SPINHOLD_DISABLE (0x00 << 14)
164 #define SPINHOLD_ENABLE (0x01 << 14)
165 #define LINKMODE_SAS (0x01 << 12)
166 #define LINKMODE_DSATA (0x02 << 12)
167 #define LINKMODE_AUTO (0x03 << 12)
168 #define LINKRATE_15 (0x01 << 8)
169 #define LINKRATE_30 (0x02 << 8)
170 #define LINKRATE_60 (0x04 << 8)
171 #define LINKRATE_120 (0x08 << 8)
173 /* phy_profile */
174 #define SAS_PHY_ANALOG_SETTINGS_PAGE 0x04
175 #define PHY_DWORD_LENGTH 0xC
177 /* Thermal related */
178 #define THERMAL_ENABLE 0x1
179 #define THERMAL_LOG_ENABLE 0x1
180 #define THERMAL_PAGE_CODE_7H 0x6
181 #define THERMAL_PAGE_CODE_8H 0x7
182 #define LTEMPHIL 70
183 #define RTEMPHIL 100
185 /* Encryption info */
186 #define SCRATCH_PAD3_ENC_DISABLED 0x00000000
187 #define SCRATCH_PAD3_ENC_DIS_ERR 0x00000001
188 #define SCRATCH_PAD3_ENC_ENA_ERR 0x00000002
189 #define SCRATCH_PAD3_ENC_READY 0x00000003
190 #define SCRATCH_PAD3_ENC_MASK SCRATCH_PAD3_ENC_READY
192 #define SCRATCH_PAD3_XTS_ENABLED (1 << 14)
193 #define SCRATCH_PAD3_SMA_ENABLED (1 << 4)
194 #define SCRATCH_PAD3_SMB_ENABLED (1 << 5)
195 #define SCRATCH_PAD3_SMF_ENABLED 0
196 #define SCRATCH_PAD3_SM_MASK 0x000000F0
197 #define SCRATCH_PAD3_ERR_CODE 0x00FF0000
199 #define SEC_MODE_SMF 0x0
200 #define SEC_MODE_SMA 0x100
201 #define SEC_MODE_SMB 0x200
202 #define CIPHER_MODE_ECB 0x00000001
203 #define CIPHER_MODE_XTS 0x00000002
204 #define KEK_MGMT_SUBOP_KEYCARDUPDATE 0x4
206 /* SAS protocol timer configuration page */
207 #define SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04
208 #define STP_MCT_TMO 32
209 #define SSP_MCT_TMO 32
210 #define SAS_MAX_OPEN_TIME 5
211 #define SMP_MAX_CONN_TIMER 0xFF
212 #define STP_FRM_TIMER 0
213 #define STP_IDLE_TIME 5 /* 5 us; controller default */
214 #define SAS_MFD 0
215 #define SAS_OPNRJT_RTRY_INTVL 2
216 #define SAS_DOPNRJT_RTRY_TMO 128
217 #define SAS_COPNRJT_RTRY_TMO 128
219 /* for phy state */
220 #define PHY_STATE_LINK_UP_SPCV 0x2
222 Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second.
223 Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128
224 is DOPNRJT_RTRY_TMO
226 #define SAS_DOPNRJT_RTRY_THR 23438
227 #define SAS_COPNRJT_RTRY_THR 23438
228 #define SAS_MAX_AIP 0x200000
229 #define IT_NEXUS_TIMEOUT 0x7D0
230 #define PORT_RECOVERY_TIMEOUT ((IT_NEXUS_TIMEOUT/100) + 30)
232 #ifdef __LITTLE_ENDIAN_BITFIELD
233 struct sas_identify_frame_local {
234 /* Byte 0 */
235 u8 frame_type:4;
236 u8 dev_type:3;
237 u8 _un0:1;
239 /* Byte 1 */
240 u8 _un1;
242 /* Byte 2 */
243 union {
244 struct {
245 u8 _un20:1;
246 u8 smp_iport:1;
247 u8 stp_iport:1;
248 u8 ssp_iport:1;
249 u8 _un247:4;
251 u8 initiator_bits;
254 /* Byte 3 */
255 union {
256 struct {
257 u8 _un30:1;
258 u8 smp_tport:1;
259 u8 stp_tport:1;
260 u8 ssp_tport:1;
261 u8 _un347:4;
263 u8 target_bits;
266 /* Byte 4 - 11 */
267 u8 _un4_11[8];
269 /* Byte 12 - 19 */
270 u8 sas_addr[SAS_ADDR_SIZE];
272 /* Byte 20 */
273 u8 phy_id;
275 u8 _un21_27[7];
277 } __packed;
279 #elif defined(__BIG_ENDIAN_BITFIELD)
280 struct sas_identify_frame_local {
281 /* Byte 0 */
282 u8 _un0:1;
283 u8 dev_type:3;
284 u8 frame_type:4;
286 /* Byte 1 */
287 u8 _un1;
289 /* Byte 2 */
290 union {
291 struct {
292 u8 _un247:4;
293 u8 ssp_iport:1;
294 u8 stp_iport:1;
295 u8 smp_iport:1;
296 u8 _un20:1;
298 u8 initiator_bits;
301 /* Byte 3 */
302 union {
303 struct {
304 u8 _un347:4;
305 u8 ssp_tport:1;
306 u8 stp_tport:1;
307 u8 smp_tport:1;
308 u8 _un30:1;
310 u8 target_bits;
313 /* Byte 4 - 11 */
314 u8 _un4_11[8];
316 /* Byte 12 - 19 */
317 u8 sas_addr[SAS_ADDR_SIZE];
319 /* Byte 20 */
320 u8 phy_id;
322 u8 _un21_27[7];
323 } __packed;
324 #else
325 #error "Bitfield order not defined!"
326 #endif
328 struct mpi_msg_hdr {
329 __le32 header; /* Bits [11:0] - Message operation code */
330 /* Bits [15:12] - Message Category */
331 /* Bits [21:16] - Outboundqueue ID for the
332 operation completion message */
333 /* Bits [23:22] - Reserved */
334 /* Bits [28:24] - Buffer Count, indicates how
335 many buffer are allocated for the massage */
336 /* Bits [30:29] - Reserved */
337 /* Bits [31] - Message Valid bit */
338 } __attribute__((packed, aligned(4)));
341 * brief the data structure of PHY Start Command
342 * use to describe enable the phy (128 bytes)
344 struct phy_start_req {
345 __le32 tag;
346 __le32 ase_sh_lm_slr_phyid;
347 struct sas_identify_frame_local sas_identify; /* 28 Bytes */
348 __le32 spasti;
349 u32 reserved[21];
350 } __attribute__((packed, aligned(4)));
353 * brief the data structure of PHY Start Command
354 * use to disable the phy (128 bytes)
356 struct phy_stop_req {
357 __le32 tag;
358 __le32 phy_id;
359 u32 reserved[29];
360 } __attribute__((packed, aligned(4)));
362 /* set device bits fis - device to host */
363 struct set_dev_bits_fis {
364 u8 fis_type; /* 0xA1*/
365 u8 n_i_pmport;
366 /* b7 : n Bit. Notification bit. If set device needs attention. */
367 /* b6 : i Bit. Interrupt Bit */
368 /* b5-b4: reserved2 */
369 /* b3-b0: PM Port */
370 u8 status;
371 u8 error;
372 u32 _r_a;
373 } __attribute__ ((packed));
374 /* PIO setup FIS - device to host */
375 struct pio_setup_fis {
376 u8 fis_type; /* 0x5f */
377 u8 i_d_pmPort;
378 /* b7 : reserved */
379 /* b6 : i bit. Interrupt bit */
380 /* b5 : d bit. data transfer direction. set to 1 for device to host
381 xfer */
382 /* b4 : reserved */
383 /* b3-b0: PM Port */
384 u8 status;
385 u8 error;
386 u8 lbal;
387 u8 lbam;
388 u8 lbah;
389 u8 device;
390 u8 lbal_exp;
391 u8 lbam_exp;
392 u8 lbah_exp;
393 u8 _r_a;
394 u8 sector_count;
395 u8 sector_count_exp;
396 u8 _r_b;
397 u8 e_status;
398 u8 _r_c[2];
399 u8 transfer_count;
400 } __attribute__ ((packed));
403 * brief the data structure of SATA Completion Response
404 * use to describe the sata task response (64 bytes)
406 struct sata_completion_resp {
407 __le32 tag;
408 __le32 status;
409 __le32 param;
410 u32 sata_resp[12];
411 } __attribute__((packed, aligned(4)));
414 * brief the data structure of SAS HW Event Notification
415 * use to alert the host about the hardware event(64 bytes)
417 /* updated outbound struct for spcv */
419 struct hw_event_resp {
420 __le32 lr_status_evt_portid;
421 __le32 evt_param;
422 __le32 phyid_npip_portstate;
423 struct sas_identify_frame sas_identify;
424 struct dev_to_host_fis sata_fis;
425 } __attribute__((packed, aligned(4)));
428 * brief the data structure for thermal event notification
431 struct thermal_hw_event {
432 __le32 thermal_event;
433 __le32 rht_lht;
434 } __attribute__((packed, aligned(4)));
437 * brief the data structure of REGISTER DEVICE Command
438 * use to describe MPI REGISTER DEVICE Command (64 bytes)
441 struct reg_dev_req {
442 __le32 tag;
443 __le32 phyid_portid;
444 __le32 dtype_dlr_mcn_ir_retry;
445 __le32 firstburstsize_ITNexustimeout;
446 u8 sas_addr[SAS_ADDR_SIZE];
447 __le32 upper_device_id;
448 u32 reserved[24];
449 } __attribute__((packed, aligned(4)));
452 * brief the data structure of DEREGISTER DEVICE Command
453 * use to request spc to remove all internal resources associated
454 * with the device id (64 bytes)
457 struct dereg_dev_req {
458 __le32 tag;
459 __le32 device_id;
460 u32 reserved[29];
461 } __attribute__((packed, aligned(4)));
464 * brief the data structure of DEVICE_REGISTRATION Response
465 * use to notify the completion of the device registration (64 bytes)
467 struct dev_reg_resp {
468 __le32 tag;
469 __le32 status;
470 __le32 device_id;
471 u32 reserved[12];
472 } __attribute__((packed, aligned(4)));
475 * brief the data structure of Local PHY Control Command
476 * use to issue PHY CONTROL to local phy (64 bytes)
478 struct local_phy_ctl_req {
479 __le32 tag;
480 __le32 phyop_phyid;
481 u32 reserved1[29];
482 } __attribute__((packed, aligned(4)));
485 * brief the data structure of Local Phy Control Response
486 * use to describe MPI Local Phy Control Response (64 bytes)
488 struct local_phy_ctl_resp {
489 __le32 tag;
490 __le32 phyop_phyid;
491 __le32 status;
492 u32 reserved[12];
493 } __attribute__((packed, aligned(4)));
495 #define OP_BITS 0x0000FF00
496 #define ID_BITS 0x000000FF
499 * brief the data structure of PORT Control Command
500 * use to control port properties (64 bytes)
503 struct port_ctl_req {
504 __le32 tag;
505 __le32 portop_portid;
506 __le32 param0;
507 __le32 param1;
508 u32 reserved1[27];
509 } __attribute__((packed, aligned(4)));
512 * brief the data structure of HW Event Ack Command
513 * use to acknowledge receive HW event (64 bytes)
515 struct hw_event_ack_req {
516 __le32 tag;
517 __le32 phyid_sea_portid;
518 __le32 param0;
519 __le32 param1;
520 u32 reserved1[27];
521 } __attribute__((packed, aligned(4)));
524 * brief the data structure of PHY_START Response Command
525 * indicates the completion of PHY_START command (64 bytes)
527 struct phy_start_resp {
528 __le32 tag;
529 __le32 status;
530 __le32 phyid;
531 u32 reserved[12];
532 } __attribute__((packed, aligned(4)));
535 * brief the data structure of PHY_STOP Response Command
536 * indicates the completion of PHY_STOP command (64 bytes)
538 struct phy_stop_resp {
539 __le32 tag;
540 __le32 status;
541 __le32 phyid;
542 u32 reserved[12];
543 } __attribute__((packed, aligned(4)));
546 * brief the data structure of SSP Completion Response
547 * use to indicate a SSP Completion (n bytes)
549 struct ssp_completion_resp {
550 __le32 tag;
551 __le32 status;
552 __le32 param;
553 __le32 ssptag_rescv_rescpad;
554 struct ssp_response_iu ssp_resp_iu;
555 __le32 residual_count;
556 } __attribute__((packed, aligned(4)));
558 #define SSP_RESCV_BIT 0x00010000
561 * brief the data structure of SATA EVNET response
562 * use to indicate a SATA Completion (64 bytes)
564 struct sata_event_resp {
565 __le32 tag;
566 __le32 event;
567 __le32 port_id;
568 __le32 device_id;
569 u32 reserved;
570 __le32 event_param0;
571 __le32 event_param1;
572 __le32 sata_addr_h32;
573 __le32 sata_addr_l32;
574 __le32 e_udt1_udt0_crc;
575 __le32 e_udt5_udt4_udt3_udt2;
576 __le32 a_udt1_udt0_crc;
577 __le32 a_udt5_udt4_udt3_udt2;
578 __le32 hwdevid_diferr;
579 __le32 err_framelen_byteoffset;
580 __le32 err_dataframe;
581 } __attribute__((packed, aligned(4)));
584 * brief the data structure of SSP EVNET esponse
585 * use to indicate a SSP Completion (64 bytes)
587 struct ssp_event_resp {
588 __le32 tag;
589 __le32 event;
590 __le32 port_id;
591 __le32 device_id;
592 __le32 ssp_tag;
593 __le32 event_param0;
594 __le32 event_param1;
595 __le32 sas_addr_h32;
596 __le32 sas_addr_l32;
597 __le32 e_udt1_udt0_crc;
598 __le32 e_udt5_udt4_udt3_udt2;
599 __le32 a_udt1_udt0_crc;
600 __le32 a_udt5_udt4_udt3_udt2;
601 __le32 hwdevid_diferr;
602 __le32 err_framelen_byteoffset;
603 __le32 err_dataframe;
604 } __attribute__((packed, aligned(4)));
607 * brief the data structure of General Event Notification Response
608 * use to describe MPI General Event Notification Response (64 bytes)
610 struct general_event_resp {
611 __le32 status;
612 __le32 inb_IOMB_payload[14];
613 } __attribute__((packed, aligned(4)));
615 #define GENERAL_EVENT_PAYLOAD 14
616 #define OPCODE_BITS 0x00000fff
619 * brief the data structure of SMP Request Command
620 * use to describe MPI SMP REQUEST Command (64 bytes)
622 struct smp_req {
623 __le32 tag;
624 __le32 device_id;
625 __le32 len_ip_ir;
626 /* Bits [0] - Indirect response */
627 /* Bits [1] - Indirect Payload */
628 /* Bits [15:2] - Reserved */
629 /* Bits [23:16] - direct payload Len */
630 /* Bits [31:24] - Reserved */
631 u8 smp_req16[16];
632 union {
633 u8 smp_req[32];
634 struct {
635 __le64 long_req_addr;/* sg dma address, LE */
636 __le32 long_req_size;/* LE */
637 u32 _r_a;
638 __le64 long_resp_addr;/* sg dma address, LE */
639 __le32 long_resp_size;/* LE */
640 u32 _r_b;
641 } long_smp_req;/* sequencer extension */
643 __le32 rsvd[16];
644 } __attribute__((packed, aligned(4)));
646 * brief the data structure of SMP Completion Response
647 * use to describe MPI SMP Completion Response (64 bytes)
649 struct smp_completion_resp {
650 __le32 tag;
651 __le32 status;
652 __le32 param;
653 u8 _r_a[252];
654 } __attribute__((packed, aligned(4)));
657 *brief the data structure of SSP SMP SATA Abort Command
658 * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
660 struct task_abort_req {
661 __le32 tag;
662 __le32 device_id;
663 __le32 tag_to_abort;
664 __le32 abort_all;
665 u32 reserved[27];
666 } __attribute__((packed, aligned(4)));
668 /* These flags used for SSP SMP & SATA Abort */
669 #define ABORT_MASK 0x3
670 #define ABORT_SINGLE 0x0
671 #define ABORT_ALL 0x1
674 * brief the data structure of SSP SATA SMP Abort Response
675 * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
677 struct task_abort_resp {
678 __le32 tag;
679 __le32 status;
680 __le32 scp;
681 u32 reserved[12];
682 } __attribute__((packed, aligned(4)));
685 * brief the data structure of SAS Diagnostic Start/End Command
686 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
688 struct sas_diag_start_end_req {
689 __le32 tag;
690 __le32 operation_phyid;
691 u32 reserved[29];
692 } __attribute__((packed, aligned(4)));
695 * brief the data structure of SAS Diagnostic Execute Command
696 * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
698 struct sas_diag_execute_req {
699 __le32 tag;
700 __le32 cmdtype_cmddesc_phyid;
701 __le32 pat1_pat2;
702 __le32 threshold;
703 __le32 codepat_errmsk;
704 __le32 pmon;
705 __le32 pERF1CTL;
706 u32 reserved[24];
707 } __attribute__((packed, aligned(4)));
709 #define SAS_DIAG_PARAM_BYTES 24
712 * brief the data structure of Set Device State Command
713 * use to describe MPI Set Device State Command (64 bytes)
715 struct set_dev_state_req {
716 __le32 tag;
717 __le32 device_id;
718 __le32 nds;
719 u32 reserved[28];
720 } __attribute__((packed, aligned(4)));
723 * brief the data structure of SATA Start Command
724 * use to describe MPI SATA IO Start Command (64 bytes)
725 * Note: This structure is common for normal / encryption I/O
728 struct sata_start_req {
729 __le32 tag;
730 __le32 device_id;
731 __le32 data_len;
732 __le32 ncqtag_atap_dir_m_dad;
733 struct host_to_dev_fis sata_fis;
734 u32 reserved1;
735 u32 reserved2; /* dword 11. rsvd for normal I/O. */
736 /* EPLE Descl for enc I/O */
737 u32 addr_low; /* dword 12. rsvd for enc I/O */
738 u32 addr_high; /* dword 13. reserved for enc I/O */
739 __le32 len; /* dword 14: length for normal I/O. */
740 /* EPLE Desch for enc I/O */
741 __le32 esgl; /* dword 15. rsvd for enc I/O */
742 __le32 atapi_scsi_cdb[4]; /* dword 16-19. rsvd for enc I/O */
743 /* The below fields are reserved for normal I/O */
744 __le32 key_index_mode; /* dword 20 */
745 __le32 sector_cnt_enss;/* dword 21 */
746 __le32 keytagl; /* dword 22 */
747 __le32 keytagh; /* dword 23 */
748 __le32 twk_val0; /* dword 24 */
749 __le32 twk_val1; /* dword 25 */
750 __le32 twk_val2; /* dword 26 */
751 __le32 twk_val3; /* dword 27 */
752 __le32 enc_addr_low; /* dword 28. Encryption SGL address high */
753 __le32 enc_addr_high; /* dword 29. Encryption SGL address low */
754 __le32 enc_len; /* dword 30. Encryption length */
755 __le32 enc_esgl; /* dword 31. Encryption esgl bit */
756 } __attribute__((packed, aligned(4)));
759 * brief the data structure of SSP INI TM Start Command
760 * use to describe MPI SSP INI TM Start Command (64 bytes)
762 struct ssp_ini_tm_start_req {
763 __le32 tag;
764 __le32 device_id;
765 __le32 relate_tag;
766 __le32 tmf;
767 u8 lun[8];
768 __le32 ds_ads_m;
769 u32 reserved[24];
770 } __attribute__((packed, aligned(4)));
772 struct ssp_info_unit {
773 u8 lun[8];/* SCSI Logical Unit Number */
774 u8 reserved1;/* reserved */
775 u8 efb_prio_attr;
776 /* B7 : enabledFirstBurst */
777 /* B6-3 : taskPriority */
778 /* B2-0 : taskAttribute */
779 u8 reserved2; /* reserved */
780 u8 additional_cdb_len;
781 /* B7-2 : additional_cdb_len */
782 /* B1-0 : reserved */
783 u8 cdb[16];/* The SCSI CDB up to 16 bytes length */
784 } __attribute__((packed, aligned(4)));
787 * brief the data structure of SSP INI IO Start Command
788 * use to describe MPI SSP INI IO Start Command (64 bytes)
789 * Note: This structure is common for normal / encryption I/O
791 struct ssp_ini_io_start_req {
792 __le32 tag;
793 __le32 device_id;
794 __le32 data_len;
795 __le32 dad_dir_m_tlr;
796 struct ssp_info_unit ssp_iu;
797 __le32 addr_low; /* dword 12: sgl low for normal I/O. */
798 /* epl_descl for encryption I/O */
799 __le32 addr_high; /* dword 13: sgl hi for normal I/O */
800 /* dpl_descl for encryption I/O */
801 __le32 len; /* dword 14: len for normal I/O. */
802 /* edpl_desch for encryption I/O */
803 __le32 esgl; /* dword 15: ESGL bit for normal I/O. */
804 /* user defined tag mask for enc I/O */
805 /* The below fields are reserved for normal I/O */
806 u8 udt[12]; /* dword 16-18 */
807 __le32 sectcnt_ios; /* dword 19 */
808 __le32 key_cmode; /* dword 20 */
809 __le32 ks_enss; /* dword 21 */
810 __le32 keytagl; /* dword 22 */
811 __le32 keytagh; /* dword 23 */
812 __le32 twk_val0; /* dword 24 */
813 __le32 twk_val1; /* dword 25 */
814 __le32 twk_val2; /* dword 26 */
815 __le32 twk_val3; /* dword 27 */
816 __le32 enc_addr_low; /* dword 28: Encryption sgl addr low */
817 __le32 enc_addr_high; /* dword 29: Encryption sgl addr hi */
818 __le32 enc_len; /* dword 30: Encryption length */
819 __le32 enc_esgl; /* dword 31: ESGL bit for encryption */
820 } __attribute__((packed, aligned(4)));
823 * brief the data structure for SSP_INI_DIF_ENC_IO COMMAND
824 * use to initiate SSP I/O operation with optional DIF/ENC
826 struct ssp_dif_enc_io_req {
827 __le32 tag;
828 __le32 device_id;
829 __le32 data_len;
830 __le32 dirMTlr;
831 __le32 sspiu0;
832 __le32 sspiu1;
833 __le32 sspiu2;
834 __le32 sspiu3;
835 __le32 sspiu4;
836 __le32 sspiu5;
837 __le32 sspiu6;
838 __le32 epl_des;
839 __le32 dpl_desl_ndplr;
840 __le32 dpl_desh;
841 __le32 uum_uuv_bss_difbits;
842 u8 udt[12];
843 __le32 sectcnt_ios;
844 __le32 key_cmode;
845 __le32 ks_enss;
846 __le32 keytagl;
847 __le32 keytagh;
848 __le32 twk_val0;
849 __le32 twk_val1;
850 __le32 twk_val2;
851 __le32 twk_val3;
852 __le32 addr_low;
853 __le32 addr_high;
854 __le32 len;
855 __le32 esgl;
856 } __attribute__((packed, aligned(4)));
859 * brief the data structure of Firmware download
860 * use to describe MPI FW DOWNLOAD Command (64 bytes)
862 struct fw_flash_Update_req {
863 __le32 tag;
864 __le32 cur_image_offset;
865 __le32 cur_image_len;
866 __le32 total_image_len;
867 u32 reserved0[7];
868 __le32 sgl_addr_lo;
869 __le32 sgl_addr_hi;
870 __le32 len;
871 __le32 ext_reserved;
872 u32 reserved1[16];
873 } __attribute__((packed, aligned(4)));
875 #define FWFLASH_IOMB_RESERVED_LEN 0x07
877 * brief the data structure of FW_FLASH_UPDATE Response
878 * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
881 struct fw_flash_Update_resp {
882 __le32 tag;
883 __le32 status;
884 u32 reserved[13];
885 } __attribute__((packed, aligned(4)));
888 * brief the data structure of Get NVM Data Command
889 * use to get data from NVM in HBA(64 bytes)
891 struct get_nvm_data_req {
892 __le32 tag;
893 __le32 len_ir_vpdd;
894 __le32 vpd_offset;
895 u32 reserved[8];
896 __le32 resp_addr_lo;
897 __le32 resp_addr_hi;
898 __le32 resp_len;
899 u32 reserved1[17];
900 } __attribute__((packed, aligned(4)));
902 struct set_nvm_data_req {
903 __le32 tag;
904 __le32 len_ir_vpdd;
905 __le32 vpd_offset;
906 u32 reserved[8];
907 __le32 resp_addr_lo;
908 __le32 resp_addr_hi;
909 __le32 resp_len;
910 u32 reserved1[17];
911 } __attribute__((packed, aligned(4)));
914 * brief the data structure for SET CONTROLLER CONFIG COMMAND
915 * use to modify controller configuration
917 struct set_ctrl_cfg_req {
918 __le32 tag;
919 __le32 cfg_pg[14];
920 u32 reserved[16];
921 } __attribute__((packed, aligned(4)));
924 * brief the data structure for GET CONTROLLER CONFIG COMMAND
925 * use to get controller configuration page
927 struct get_ctrl_cfg_req {
928 __le32 tag;
929 __le32 pgcd;
930 __le32 int_vec;
931 u32 reserved[28];
932 } __attribute__((packed, aligned(4)));
935 * brief the data structure for KEK_MANAGEMENT COMMAND
936 * use for KEK management
938 struct kek_mgmt_req {
939 __le32 tag;
940 __le32 new_curidx_ksop;
941 u32 reserved;
942 __le32 kblob[12];
943 u32 reserved1[16];
944 } __attribute__((packed, aligned(4)));
947 * brief the data structure for DEK_MANAGEMENT COMMAND
948 * use for DEK management
950 struct dek_mgmt_req {
951 __le32 tag;
952 __le32 kidx_dsop;
953 __le32 dekidx;
954 __le32 addr_l;
955 __le32 addr_h;
956 __le32 nent;
957 __le32 dbf_tblsize;
958 u32 reserved[24];
959 } __attribute__((packed, aligned(4)));
962 * brief the data structure for SET PHY PROFILE COMMAND
963 * use to retrive phy specific information
965 struct set_phy_profile_req {
966 __le32 tag;
967 __le32 ppc_phyid;
968 u32 reserved[29];
969 } __attribute__((packed, aligned(4)));
972 * brief the data structure for GET PHY PROFILE COMMAND
973 * use to retrive phy specific information
975 struct get_phy_profile_req {
976 __le32 tag;
977 __le32 ppc_phyid;
978 __le32 profile[29];
979 } __attribute__((packed, aligned(4)));
982 * brief the data structure for EXT FLASH PARTITION
983 * use to manage ext flash partition
985 struct ext_flash_partition_req {
986 __le32 tag;
987 __le32 cmd;
988 __le32 offset;
989 __le32 len;
990 u32 reserved[7];
991 __le32 addr_low;
992 __le32 addr_high;
993 __le32 len1;
994 __le32 ext;
995 u32 reserved1[16];
996 } __attribute__((packed, aligned(4)));
998 #define TWI_DEVICE 0x0
999 #define C_SEEPROM 0x1
1000 #define VPD_FLASH 0x4
1001 #define AAP1_RDUMP 0x5
1002 #define IOP_RDUMP 0x6
1003 #define EXPAN_ROM 0x7
1005 #define IPMode 0x80000000
1006 #define NVMD_TYPE 0x0000000F
1007 #define NVMD_STAT 0x0000FFFF
1008 #define NVMD_LEN 0xFF000000
1010 * brief the data structure of Get NVMD Data Response
1011 * use to describe MPI Get NVMD Data Response (64 bytes)
1013 struct get_nvm_data_resp {
1014 __le32 tag;
1015 __le32 ir_tda_bn_dps_das_nvm;
1016 __le32 dlen_status;
1017 __le32 nvm_data[12];
1018 } __attribute__((packed, aligned(4)));
1021 * brief the data structure of SAS Diagnostic Start/End Response
1022 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
1025 struct sas_diag_start_end_resp {
1026 __le32 tag;
1027 __le32 status;
1028 u32 reserved[13];
1029 } __attribute__((packed, aligned(4)));
1032 * brief the data structure of SAS Diagnostic Execute Response
1033 * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
1036 struct sas_diag_execute_resp {
1037 __le32 tag;
1038 __le32 cmdtype_cmddesc_phyid;
1039 __le32 Status;
1040 __le32 ReportData;
1041 u32 reserved[11];
1042 } __attribute__((packed, aligned(4)));
1045 * brief the data structure of Set Device State Response
1046 * use to describe MPI Set Device State Response (64 bytes)
1049 struct set_dev_state_resp {
1050 __le32 tag;
1051 __le32 status;
1052 __le32 device_id;
1053 __le32 pds_nds;
1054 u32 reserved[11];
1055 } __attribute__((packed, aligned(4)));
1057 /* new outbound structure for spcv - begins */
1059 * brief the data structure for SET CONTROLLER CONFIG COMMAND
1060 * use to modify controller configuration
1062 struct set_ctrl_cfg_resp {
1063 __le32 tag;
1064 __le32 status;
1065 __le32 err_qlfr_pgcd;
1066 u32 reserved[12];
1067 } __attribute__((packed, aligned(4)));
1069 struct get_ctrl_cfg_resp {
1070 __le32 tag;
1071 __le32 status;
1072 __le32 err_qlfr;
1073 __le32 confg_page[12];
1074 } __attribute__((packed, aligned(4)));
1076 struct kek_mgmt_resp {
1077 __le32 tag;
1078 __le32 status;
1079 __le32 kidx_new_curr_ksop;
1080 __le32 err_qlfr;
1081 u32 reserved[11];
1082 } __attribute__((packed, aligned(4)));
1084 struct dek_mgmt_resp {
1085 __le32 tag;
1086 __le32 status;
1087 __le32 kekidx_tbls_dsop;
1088 __le32 dekidx;
1089 __le32 err_qlfr;
1090 u32 reserved[10];
1091 } __attribute__((packed, aligned(4)));
1093 struct get_phy_profile_resp {
1094 __le32 tag;
1095 __le32 status;
1096 __le32 ppc_phyid;
1097 __le32 ppc_specific_rsp[12];
1098 } __attribute__((packed, aligned(4)));
1100 struct flash_op_ext_resp {
1101 __le32 tag;
1102 __le32 cmd;
1103 __le32 status;
1104 __le32 epart_size;
1105 __le32 epart_sect_size;
1106 u32 reserved[10];
1107 } __attribute__((packed, aligned(4)));
1109 struct set_phy_profile_resp {
1110 __le32 tag;
1111 __le32 status;
1112 __le32 ppc_phyid;
1113 __le32 ppc_specific_rsp[12];
1114 } __attribute__((packed, aligned(4)));
1116 struct ssp_coalesced_comp_resp {
1117 __le32 coal_cnt;
1118 __le32 tag0;
1119 __le32 ssp_tag0;
1120 __le32 tag1;
1121 __le32 ssp_tag1;
1122 __le32 add_tag_ssp_tag[10];
1123 } __attribute__((packed, aligned(4)));
1125 /* new outbound structure for spcv - ends */
1127 /* brief data structure for SAS protocol timer configuration page.
1130 struct SASProtocolTimerConfig {
1131 __le32 pageCode; /* 0 */
1132 __le32 MST_MSI; /* 1 */
1133 __le32 STP_SSP_MCT_TMO; /* 2 */
1134 __le32 STP_FRM_TMO; /* 3 */
1135 __le32 STP_IDLE_TMO; /* 4 */
1136 __le32 OPNRJT_RTRY_INTVL; /* 5 */
1137 __le32 Data_Cmd_OPNRJT_RTRY_TMO; /* 6 */
1138 __le32 Data_Cmd_OPNRJT_RTRY_THR; /* 7 */
1139 __le32 MAX_AIP; /* 8 */
1140 } __attribute__((packed, aligned(4)));
1142 typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
1144 #define NDS_BITS 0x0F
1145 #define PDS_BITS 0xF0
1148 * HW Events type
1151 #define HW_EVENT_RESET_START 0x01
1152 #define HW_EVENT_CHIP_RESET_COMPLETE 0x02
1153 #define HW_EVENT_PHY_STOP_STATUS 0x03
1154 #define HW_EVENT_SAS_PHY_UP 0x04
1155 #define HW_EVENT_SATA_PHY_UP 0x05
1156 #define HW_EVENT_SATA_SPINUP_HOLD 0x06
1157 #define HW_EVENT_PHY_DOWN 0x07
1158 #define HW_EVENT_PORT_INVALID 0x08
1159 #define HW_EVENT_BROADCAST_CHANGE 0x09
1160 #define HW_EVENT_PHY_ERROR 0x0A
1161 #define HW_EVENT_BROADCAST_SES 0x0B
1162 #define HW_EVENT_INBOUND_CRC_ERROR 0x0C
1163 #define HW_EVENT_HARD_RESET_RECEIVED 0x0D
1164 #define HW_EVENT_MALFUNCTION 0x0E
1165 #define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
1166 #define HW_EVENT_BROADCAST_EXP 0x10
1167 #define HW_EVENT_PHY_START_STATUS 0x11
1168 #define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
1169 #define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
1170 #define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
1171 #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
1172 #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
1173 #define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
1174 #define HW_EVENT_PORT_RECOVER 0x18
1175 #define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
1176 #define HW_EVENT_PORT_RESET_COMPLETE 0x20
1177 #define EVENT_BROADCAST_ASYNCH_EVENT 0x21
1179 /* port state */
1180 #define PORT_NOT_ESTABLISHED 0x00
1181 #define PORT_VALID 0x01
1182 #define PORT_LOSTCOMM 0x02
1183 #define PORT_IN_RESET 0x04
1184 #define PORT_3RD_PARTY_RESET 0x07
1185 #define PORT_INVALID 0x08
1188 * SSP/SMP/SATA IO Completion Status values
1191 #define IO_SUCCESS 0x00
1192 #define IO_ABORTED 0x01
1193 #define IO_OVERFLOW 0x02
1194 #define IO_UNDERFLOW 0x03
1195 #define IO_FAILED 0x04
1196 #define IO_ABORT_RESET 0x05
1197 #define IO_NOT_VALID 0x06
1198 #define IO_NO_DEVICE 0x07
1199 #define IO_ILLEGAL_PARAMETER 0x08
1200 #define IO_LINK_FAILURE 0x09
1201 #define IO_PROG_ERROR 0x0A
1203 #define IO_EDC_IN_ERROR 0x0B
1204 #define IO_EDC_OUT_ERROR 0x0C
1205 #define IO_ERROR_HW_TIMEOUT 0x0D
1206 #define IO_XFER_ERROR_BREAK 0x0E
1207 #define IO_XFER_ERROR_PHY_NOT_READY 0x0F
1208 #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
1209 #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
1210 #define IO_OPEN_CNX_ERROR_BREAK 0x12
1211 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
1212 #define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
1213 #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
1214 #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
1215 #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
1216 /* This error code 0x18 is not used on SPCv */
1217 #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
1218 #define IO_XFER_ERROR_NAK_RECEIVED 0x19
1219 #define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
1220 #define IO_XFER_ERROR_PEER_ABORTED 0x1B
1221 #define IO_XFER_ERROR_RX_FRAME 0x1C
1222 #define IO_XFER_ERROR_DMA 0x1D
1223 #define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
1224 #define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
1225 #define IO_XFER_ERROR_SATA 0x20
1227 /* This error code 0x22 is not used on SPCv */
1228 #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
1229 #define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
1230 #define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
1231 #define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
1232 /* This error code 0x25 is not used on SPCv */
1233 #define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
1234 #define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
1235 #define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
1236 #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
1237 #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
1239 /* The following error code 0x31 and 0x32 are not using (obsolete) */
1240 #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
1241 #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
1243 #define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
1244 #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
1245 #define IO_XFER_CMD_FRAME_ISSUED 0x36
1246 #define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
1247 #define IO_PORT_IN_RESET 0x38
1248 #define IO_DS_NON_OPERATIONAL 0x39
1249 #define IO_DS_IN_RECOVERY 0x3A
1250 #define IO_TM_TAG_NOT_FOUND 0x3B
1251 #define IO_XFER_PIO_SETUP_ERROR 0x3C
1252 #define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
1253 #define IO_DS_IN_ERROR 0x3E
1254 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
1255 #define IO_ABORT_IN_PROGRESS 0x40
1256 #define IO_ABORT_DELAYED 0x41
1257 #define IO_INVALID_LENGTH 0x42
1259 /********** additional response event values *****************/
1261 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT 0x43
1262 #define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED 0x44
1263 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO 0x45
1264 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST 0x46
1265 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE 0x47
1266 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48
1267 #define IO_DS_INVALID 0x49
1268 /* WARNING: the value is not contiguous from here */
1269 #define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR 0x52
1270 #define IO_XFER_DMA_ACTIVATE_TIMEOUT 0x53
1271 #define IO_XFER_ERROR_INTERNAL_CRC_ERROR 0x54
1272 #define MPI_IO_RQE_BUSY_FULL 0x55
1273 #define IO_XFER_ERR_EOB_DATA_OVERRUN 0x56
1274 #define IO_XFER_ERROR_INVALID_SSP_RSP_FRAME 0x57
1275 #define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED 0x58
1277 #define MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004
1278 #define MPI_ERR_ATAPI_DEVICE_BUSY 0x1024
1280 #define IO_XFR_ERROR_DEK_KEY_CACHE_MISS 0x2040
1282 * An encryption IO request failed due to DEK Key Tag mismatch.
1283 * The key tag supplied in the encryption IOMB does not match with
1284 * the Key Tag in the referenced DEK Entry.
1286 #define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH 0x2041
1287 #define IO_XFR_ERROR_CIPHER_MODE_INVALID 0x2042
1289 * An encryption I/O request failed because the initial value (IV)
1290 * in the unwrapped DEK blob didn't match the IV used to unwrap it.
1292 #define IO_XFR_ERROR_DEK_IV_MISMATCH 0x2043
1293 /* An encryption I/O request failed due to an internal RAM ECC or
1294 * interface error while unwrapping the DEK. */
1295 #define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR 0x2044
1296 /* An encryption I/O request failed due to an internal RAM ECC or
1297 * interface error while unwrapping the DEK. */
1298 #define IO_XFR_ERROR_INTERNAL_RAM 0x2045
1300 * An encryption I/O request failed
1301 * because the DEK index specified in the I/O was outside the bounds of
1302 * the total number of entries in the host DEK table.
1304 #define IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046
1306 /* define DIF IO response error status code */
1307 #define IO_XFR_ERROR_DIF_MISMATCH 0x3000
1308 #define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001
1309 #define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002
1310 #define IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003
1312 /* define operator management response status and error qualifier code */
1313 #define OPR_MGMT_OP_NOT_SUPPORTED 0x2060
1314 #define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061
1315 #define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062
1316 #define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063
1317 #define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064
1318 #define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL 0x2022
1319 #define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE 0x2023
1320 /***************** additional response event values ***************/
1322 /* WARNING: This error code must always be the last number.
1323 * If you add error code, modify this code also
1324 * It is used as an index
1326 #define IO_ERROR_UNKNOWN_GENERIC 0x2023
1328 /* MSGU CONFIGURATION TABLE*/
1330 #define SPCv_MSGU_CFG_TABLE_UPDATE 0x001
1331 #define SPCv_MSGU_CFG_TABLE_RESET 0x002
1332 #define SPCv_MSGU_CFG_TABLE_FREEZE 0x004
1333 #define SPCv_MSGU_CFG_TABLE_UNFREEZE 0x008
1334 #define MSGU_IBDB_SET 0x00
1335 #define MSGU_HOST_INT_STATUS 0x08
1336 #define MSGU_HOST_INT_MASK 0x0C
1337 #define MSGU_IOPIB_INT_STATUS 0x18
1338 #define MSGU_IOPIB_INT_MASK 0x1C
1339 #define MSGU_IBDB_CLEAR 0x20
1341 #define MSGU_MSGU_CONTROL 0x24
1342 #define MSGU_ODR 0x20
1343 #define MSGU_ODCR 0x28
1345 #define MSGU_ODMR 0x30
1346 #define MSGU_ODMR_U 0x34
1347 #define MSGU_ODMR_CLR 0x38
1348 #define MSGU_ODMR_CLR_U 0x3C
1349 #define MSGU_OD_RSVD 0x40
1351 #define MSGU_SCRATCH_PAD_0 0x44
1352 #define MSGU_SCRATCH_PAD_1 0x48
1353 #define MSGU_SCRATCH_PAD_2 0x4C
1354 #define MSGU_SCRATCH_PAD_3 0x50
1355 #define MSGU_HOST_SCRATCH_PAD_0 0x54
1356 #define MSGU_HOST_SCRATCH_PAD_1 0x58
1357 #define MSGU_HOST_SCRATCH_PAD_2 0x5C
1358 #define MSGU_HOST_SCRATCH_PAD_3 0x60
1359 #define MSGU_HOST_SCRATCH_PAD_4 0x64
1360 #define MSGU_HOST_SCRATCH_PAD_5 0x68
1361 #define MSGU_HOST_SCRATCH_PAD_6 0x6C
1362 #define MSGU_HOST_SCRATCH_PAD_7 0x70
1364 /* bit definition for ODMR register */
1365 #define ODMR_MASK_ALL 0xFFFFFFFF/* mask all
1366 interrupt vector */
1367 #define ODMR_CLEAR_ALL 0 /* clear all
1368 interrupt vector */
1369 /* bit definition for ODCR register */
1370 #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all
1371 interrupt vector*/
1372 /* MSIX Interupts */
1373 #define MSIX_TABLE_OFFSET 0x2000
1374 #define MSIX_TABLE_ELEMENT_SIZE 0x10
1375 #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
1376 #define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + \
1377 MSIX_INTERRUPT_CONTROL_OFFSET)
1378 #define MSIX_INTERRUPT_DISABLE 0x1
1379 #define MSIX_INTERRUPT_ENABLE 0x0
1381 /* state definition for Scratch Pad1 register */
1382 #define SCRATCH_PAD_RAAE_READY 0x3
1383 #define SCRATCH_PAD_ILA_READY 0xC
1384 #define SCRATCH_PAD_BOOT_LOAD_SUCCESS 0x0
1385 #define SCRATCH_PAD_IOP0_READY 0xC00
1386 #define SCRATCH_PAD_IOP1_READY 0x3000
1388 /* boot loader state */
1389 #define SCRATCH_PAD1_BOOTSTATE_MASK 0x70 /* Bit 4-6 */
1390 #define SCRATCH_PAD1_BOOTSTATE_SUCESS 0x0 /* Load successful */
1391 #define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM 0x10 /* HDA SEEPROM */
1392 #define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP 0x20 /* HDA BootStrap Pins */
1393 #define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET 0x30 /* HDA Soft Reset */
1394 #define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR 0x40 /* HDA critical error */
1395 #define SCRATCH_PAD1_BOOTSTATE_R1 0x50 /* Reserved */
1396 #define SCRATCH_PAD1_BOOTSTATE_R2 0x60 /* Reserved */
1397 #define SCRATCH_PAD1_BOOTSTATE_FATAL 0x70 /* Fatal Error */
1399 /* state definition for Scratch Pad2 register */
1400 #define SCRATCH_PAD2_POR 0x00 /* power on state */
1401 #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
1402 #define SCRATCH_PAD2_ERR 0x02 /* error state */
1403 #define SCRATCH_PAD2_RDY 0x03 /* ready state */
1404 #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW rdy for soft reset flag */
1405 #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
1406 #define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2
1407 Mask, bit1-0 State */
1408 #define SCRATCH_PAD2_RESERVED 0x000003FC/* Scratch Pad1
1409 Reserved bit 2 to 9 */
1411 #define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */
1412 #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */
1414 /* main configuration offset - byte offset */
1415 #define MAIN_SIGNATURE_OFFSET 0x00 /* DWORD 0x00 */
1416 #define MAIN_INTERFACE_REVISION 0x04 /* DWORD 0x01 */
1417 #define MAIN_FW_REVISION 0x08 /* DWORD 0x02 */
1418 #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C /* DWORD 0x03 */
1419 #define MAIN_MAX_SGL_OFFSET 0x10 /* DWORD 0x04 */
1420 #define MAIN_CNTRL_CAP_OFFSET 0x14 /* DWORD 0x05 */
1421 #define MAIN_GST_OFFSET 0x18 /* DWORD 0x06 */
1422 #define MAIN_IBQ_OFFSET 0x1C /* DWORD 0x07 */
1423 #define MAIN_OBQ_OFFSET 0x20 /* DWORD 0x08 */
1424 #define MAIN_IQNPPD_HPPD_OFFSET 0x24 /* DWORD 0x09 */
1426 /* 0x28 - 0x4C - RSVD */
1427 #define MAIN_EVENT_CRC_CHECK 0x48 /* DWORD 0x12 */
1428 #define MAIN_EVENT_LOG_ADDR_HI 0x50 /* DWORD 0x14 */
1429 #define MAIN_EVENT_LOG_ADDR_LO 0x54 /* DWORD 0x15 */
1430 #define MAIN_EVENT_LOG_BUFF_SIZE 0x58 /* DWORD 0x16 */
1431 #define MAIN_EVENT_LOG_OPTION 0x5C /* DWORD 0x17 */
1432 #define MAIN_PCS_EVENT_LOG_ADDR_HI 0x60 /* DWORD 0x18 */
1433 #define MAIN_PCS_EVENT_LOG_ADDR_LO 0x64 /* DWORD 0x19 */
1434 #define MAIN_PCS_EVENT_LOG_BUFF_SIZE 0x68 /* DWORD 0x1A */
1435 #define MAIN_PCS_EVENT_LOG_OPTION 0x6C /* DWORD 0x1B */
1436 #define MAIN_FATAL_ERROR_INTERRUPT 0x70 /* DWORD 0x1C */
1437 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74 /* DWORD 0x1D */
1438 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78 /* DWORD 0x1E */
1439 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C /* DWORD 0x1F */
1440 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80 /* DWORD 0x20 */
1441 #define MAIN_GPIO_LED_FLAGS_OFFSET 0x84 /* DWORD 0x21 */
1442 #define MAIN_ANALOG_SETUP_OFFSET 0x88 /* DWORD 0x22 */
1444 #define MAIN_INT_VECTOR_TABLE_OFFSET 0x8C /* DWORD 0x23 */
1445 #define MAIN_SAS_PHY_ATTR_TABLE_OFFSET 0x90 /* DWORD 0x24 */
1446 #define MAIN_PORT_RECOVERY_TIMER 0x94 /* DWORD 0x25 */
1447 #define MAIN_INT_REASSERTION_DELAY 0x98 /* DWORD 0x26 */
1448 #define MAIN_MPI_ILA_RELEASE_TYPE 0xA4 /* DWORD 0x29 */
1449 #define MAIN_MPI_INACTIVE_FW_VERSION 0XB0 /* DWORD 0x2C */
1451 /* Gereral Status Table offset - byte offset */
1452 #define GST_GSTLEN_MPIS_OFFSET 0x00
1453 #define GST_IQ_FREEZE_STATE0_OFFSET 0x04
1454 #define GST_IQ_FREEZE_STATE1_OFFSET 0x08
1455 #define GST_MSGUTCNT_OFFSET 0x0C
1456 #define GST_IOPTCNT_OFFSET 0x10
1457 /* 0x14 - 0x34 - RSVD */
1458 #define GST_GPIO_INPUT_VAL 0x38
1459 /* 0x3c - 0x40 - RSVD */
1460 #define GST_RERRINFO_OFFSET0 0x44
1461 #define GST_RERRINFO_OFFSET1 0x48
1462 #define GST_RERRINFO_OFFSET2 0x4c
1463 #define GST_RERRINFO_OFFSET3 0x50
1464 #define GST_RERRINFO_OFFSET4 0x54
1465 #define GST_RERRINFO_OFFSET5 0x58
1466 #define GST_RERRINFO_OFFSET6 0x5c
1467 #define GST_RERRINFO_OFFSET7 0x60
1469 /* General Status Table - MPI state */
1470 #define GST_MPI_STATE_UNINIT 0x00
1471 #define GST_MPI_STATE_INIT 0x01
1472 #define GST_MPI_STATE_TERMINATION 0x02
1473 #define GST_MPI_STATE_ERROR 0x03
1474 #define GST_MPI_STATE_MASK 0x07
1476 /* Per SAS PHY Attributes */
1478 #define PSPA_PHYSTATE0_OFFSET 0x00 /* Dword V */
1479 #define PSPA_OB_HW_EVENT_PID0_OFFSET 0x04 /* DWORD V+1 */
1480 #define PSPA_PHYSTATE1_OFFSET 0x08 /* Dword V+2 */
1481 #define PSPA_OB_HW_EVENT_PID1_OFFSET 0x0C /* DWORD V+3 */
1482 #define PSPA_PHYSTATE2_OFFSET 0x10 /* Dword V+4 */
1483 #define PSPA_OB_HW_EVENT_PID2_OFFSET 0x14 /* DWORD V+5 */
1484 #define PSPA_PHYSTATE3_OFFSET 0x18 /* Dword V+6 */
1485 #define PSPA_OB_HW_EVENT_PID3_OFFSET 0x1C /* DWORD V+7 */
1486 #define PSPA_PHYSTATE4_OFFSET 0x20 /* Dword V+8 */
1487 #define PSPA_OB_HW_EVENT_PID4_OFFSET 0x24 /* DWORD V+9 */
1488 #define PSPA_PHYSTATE5_OFFSET 0x28 /* Dword V+10 */
1489 #define PSPA_OB_HW_EVENT_PID5_OFFSET 0x2C /* DWORD V+11 */
1490 #define PSPA_PHYSTATE6_OFFSET 0x30 /* Dword V+12 */
1491 #define PSPA_OB_HW_EVENT_PID6_OFFSET 0x34 /* DWORD V+13 */
1492 #define PSPA_PHYSTATE7_OFFSET 0x38 /* Dword V+14 */
1493 #define PSPA_OB_HW_EVENT_PID7_OFFSET 0x3C /* DWORD V+15 */
1494 #define PSPA_PHYSTATE8_OFFSET 0x40 /* DWORD V+16 */
1495 #define PSPA_OB_HW_EVENT_PID8_OFFSET 0x44 /* DWORD V+17 */
1496 #define PSPA_PHYSTATE9_OFFSET 0x48 /* DWORD V+18 */
1497 #define PSPA_OB_HW_EVENT_PID9_OFFSET 0x4C /* DWORD V+19 */
1498 #define PSPA_PHYSTATE10_OFFSET 0x50 /* DWORD V+20 */
1499 #define PSPA_OB_HW_EVENT_PID10_OFFSET 0x54 /* DWORD V+21 */
1500 #define PSPA_PHYSTATE11_OFFSET 0x58 /* DWORD V+22 */
1501 #define PSPA_OB_HW_EVENT_PID11_OFFSET 0x5C /* DWORD V+23 */
1502 #define PSPA_PHYSTATE12_OFFSET 0x60 /* DWORD V+24 */
1503 #define PSPA_OB_HW_EVENT_PID12_OFFSET 0x64 /* DWORD V+25 */
1504 #define PSPA_PHYSTATE13_OFFSET 0x68 /* DWORD V+26 */
1505 #define PSPA_OB_HW_EVENT_PID13_OFFSET 0x6c /* DWORD V+27 */
1506 #define PSPA_PHYSTATE14_OFFSET 0x70 /* DWORD V+28 */
1507 #define PSPA_OB_HW_EVENT_PID14_OFFSET 0x74 /* DWORD V+29 */
1508 #define PSPA_PHYSTATE15_OFFSET 0x78 /* DWORD V+30 */
1509 #define PSPA_OB_HW_EVENT_PID15_OFFSET 0x7c /* DWORD V+31 */
1510 /* end PSPA */
1512 /* inbound queue configuration offset - byte offset */
1513 #define IB_PROPERITY_OFFSET 0x00
1514 #define IB_BASE_ADDR_HI_OFFSET 0x04
1515 #define IB_BASE_ADDR_LO_OFFSET 0x08
1516 #define IB_CI_BASE_ADDR_HI_OFFSET 0x0C
1517 #define IB_CI_BASE_ADDR_LO_OFFSET 0x10
1518 #define IB_PIPCI_BAR 0x14
1519 #define IB_PIPCI_BAR_OFFSET 0x18
1520 #define IB_RESERVED_OFFSET 0x1C
1522 /* outbound queue configuration offset - byte offset */
1523 #define OB_PROPERITY_OFFSET 0x00
1524 #define OB_BASE_ADDR_HI_OFFSET 0x04
1525 #define OB_BASE_ADDR_LO_OFFSET 0x08
1526 #define OB_PI_BASE_ADDR_HI_OFFSET 0x0C
1527 #define OB_PI_BASE_ADDR_LO_OFFSET 0x10
1528 #define OB_CIPCI_BAR 0x14
1529 #define OB_CIPCI_BAR_OFFSET 0x18
1530 #define OB_INTERRUPT_COALES_OFFSET 0x1C
1531 #define OB_DYNAMIC_COALES_OFFSET 0x20
1532 #define OB_PROPERTY_INT_ENABLE 0x40000000
1534 #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
1535 #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
1536 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
1537 #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
1538 #define PCIE_EVENT_INTERRUPT 0x003044
1539 #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
1540 #define PCIE_ERROR_INTERRUPT 0x00304C
1542 /* SPCV soft reset */
1543 #define SPC_REG_SOFT_RESET 0x00001000
1544 #define SPCv_NORMAL_RESET_VALUE 0x1
1546 #define SPCv_SOFT_RESET_READ_MASK 0xC0
1547 #define SPCv_SOFT_RESET_NO_RESET 0x0
1548 #define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED 0x40
1549 #define SPCv_SOFT_RESET_HDA_MODE_OCCURED 0x80
1550 #define SPCv_SOFT_RESET_CHIP_RESET_OCCURED 0xC0
1552 /* signature definition for host scratch pad0 register */
1553 #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
1554 /* Signature for Soft Reset */
1556 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
1557 #define SPC_REG_RESET 0x000000/* reset register */
1559 /* bit definition for SPC_RESET register */
1560 #define SPC_REG_RESET_OSSP 0x00000001
1561 #define SPC_REG_RESET_RAAE 0x00000002
1562 #define SPC_REG_RESET_PCS_SPBC 0x00000004
1563 #define SPC_REG_RESET_PCS_IOP_SS 0x00000008
1564 #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
1565 #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
1566 #define SPC_REG_RESET_PCS_LM 0x00000040
1567 #define SPC_REG_RESET_PCS 0x00000080
1568 #define SPC_REG_RESET_GSM 0x00000100
1569 #define SPC_REG_RESET_DDR2 0x00010000
1570 #define SPC_REG_RESET_BDMA_CORE 0x00020000
1571 #define SPC_REG_RESET_BDMA_SXCBI 0x00040000
1572 #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
1573 #define SPC_REG_RESET_PCIE_PWR 0x00100000
1574 #define SPC_REG_RESET_PCIE_SFT 0x00200000
1575 #define SPC_REG_RESET_PCS_SXCBI 0x00400000
1576 #define SPC_REG_RESET_LMS_SXCBI 0x00800000
1577 #define SPC_REG_RESET_PMIC_SXCBI 0x01000000
1578 #define SPC_REG_RESET_PMIC_CORE 0x02000000
1579 #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
1580 #define SPC_REG_RESET_DEVICE 0x80000000
1582 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
1583 #define SPCV_IBW_AXI_TRANSLATION_LOW 0x001010
1585 #define MBIC_AAP1_ADDR_BASE 0x060000
1586 #define MBIC_IOP_ADDR_BASE 0x070000
1587 #define GSM_ADDR_BASE 0x0700000
1588 /* Dynamic map through Bar4 - 0x00700000 */
1589 #define GSM_CONFIG_RESET 0x00000000
1590 #define RAM_ECC_DB_ERR 0x00000018
1591 #define GSM_READ_ADDR_PARITY_INDIC 0x00000058
1592 #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
1593 #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
1594 #define GSM_READ_ADDR_PARITY_CHECK 0x00000038
1595 #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
1596 #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
1598 #define RB6_ACCESS_REG 0x6A0000
1599 #define HDAC_EXEC_CMD 0x0002
1600 #define HDA_C_PA 0xcb
1601 #define HDA_SEQ_ID_BITS 0x00ff0000
1602 #define HDA_GSM_OFFSET_BITS 0x00FFFFFF
1603 #define HDA_GSM_CMD_OFFSET_BITS 0x42C0
1604 #define HDA_GSM_RSP_OFFSET_BITS 0x42E0
1606 #define MBIC_AAP1_ADDR_BASE 0x060000
1607 #define MBIC_IOP_ADDR_BASE 0x070000
1608 #define GSM_ADDR_BASE 0x0700000
1609 #define SPC_TOP_LEVEL_ADDR_BASE 0x000000
1610 #define GSM_CONFIG_RESET_VALUE 0x00003b00
1611 #define GPIO_ADDR_BASE 0x00090000
1612 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
1614 /* RB6 offset */
1615 #define SPC_RB6_OFFSET 0x80C0
1616 /* Magic number of soft reset for RB6 */
1617 #define RB6_MAGIC_NUMBER_RST 0x1234
1619 /* Device Register status */
1620 #define DEVREG_SUCCESS 0x00
1621 #define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
1622 #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
1623 #define DEVREG_FAILURE_INVALID_PHY_ID 0x03
1624 #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
1625 #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
1626 #define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
1627 #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
1630 #define MEMBASE_II_SHIFT_REGISTER 0x1010
1631 #endif