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Linux 4.16.11
[linux/fpc-iii.git] / drivers / scsi / qla4xxx / ql4_mbx.c
blobbda2e64ee5ca4e3b528b7274bb2548f21638af11
1 /*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8 #include <linux/ctype.h>
9 #include "ql4_def.h"
10 #include "ql4_glbl.h"
11 #include "ql4_dbg.h"
12 #include "ql4_inline.h"
13 #include "ql4_version.h"
14
15 void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
16 int in_count)
17 {
18 int i;
19
20 /* Load all mailbox registers, except mailbox 0. */
21 for (i = 1; i < in_count; i++)
22 writel(mbx_cmd[i], &ha->reg->mailbox[i]);
23
24 /* Wakeup firmware */
25 writel(mbx_cmd[0], &ha->reg->mailbox[0]);
26 readl(&ha->reg->mailbox[0]);
27 writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
28 readl(&ha->reg->ctrl_status);
29 }
30
31 void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
32 {
33 int intr_status;
34
35 intr_status = readl(&ha->reg->ctrl_status);
36 if (intr_status & INTR_PENDING) {
37 /*
38 * Service the interrupt.
39 * The ISR will save the mailbox status registers
40 * to a temporary storage location in the adapter structure.
41 */
42 ha->mbox_status_count = out_count;
43 ha->isp_ops->interrupt_service_routine(ha, intr_status);
44 }
45 }
46
47 /**
48 * qla4xxx_is_intr_poll_mode – Are we allowed to poll for interrupts?
49 * @ha: Pointer to host adapter structure.
50 * @ret: 1=polling mode, 0=non-polling mode
51 **/
52 static int qla4xxx_is_intr_poll_mode(struct scsi_qla_host *ha)
53 {
54 int rval = 1;
55
56 if (is_qla8032(ha) || is_qla8042(ha)) {
57 if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
58 test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags))
59 rval = 0;
60 } else {
61 if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
62 test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
63 test_bit(AF_ONLINE, &ha->flags) &&
64 !test_bit(AF_HA_REMOVAL, &ha->flags))
65 rval = 0;
66 }
67
68 return rval;
69 }
70
71 /**
72 * qla4xxx_mailbox_command - issues mailbox commands
73 * @ha: Pointer to host adapter structure.
74 * @inCount: number of mailbox registers to load.
75 * @outCount: number of mailbox registers to return.
76 * @mbx_cmd: data pointer for mailbox in registers.
77 * @mbx_sts: data pointer for mailbox out registers.
78 *
79 * This routine issue mailbox commands and waits for completion.
80 * If outCount is 0, this routine completes successfully WITHOUT waiting
81 * for the mailbox command to complete.
82 **/
83 int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
84 uint8_t outCount, uint32_t *mbx_cmd,
85 uint32_t *mbx_sts)
86 {
87 int status = QLA_ERROR;
88 uint8_t i;
89 u_long wait_count;
90 unsigned long flags = 0;
91 uint32_t dev_state;
92
93 /* Make sure that pointers are valid */
94 if (!mbx_cmd || !mbx_sts) {
95 DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
96 "pointer\n", ha->host_no, __func__));
97 return status;
98 }
99
100 if (is_qla40XX(ha)) {
101 if (test_bit(AF_HA_REMOVAL, &ha->flags)) {
102 DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
103 "prematurely completing mbx cmd as "
104 "adapter removal detected\n",
105 ha->host_no, __func__));
106 return status;
107 }
108 }
109
110 if ((is_aer_supported(ha)) &&
111 (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
112 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
113 "timeout MBX Exiting.\n", ha->host_no, __func__));
114 return status;
115 }
116
117 /* Mailbox code active */
118 wait_count = MBOX_TOV * 100;
119
120 while (wait_count--) {
121 mutex_lock(&ha->mbox_sem);
122 if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
123 set_bit(AF_MBOX_COMMAND, &ha->flags);
124 mutex_unlock(&ha->mbox_sem);
125 break;
126 }
127 mutex_unlock(&ha->mbox_sem);
128 if (!wait_count) {
129 DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
130 ha->host_no, __func__));
131 return status;
132 }
133 msleep(10);
134 }
135
136 if (is_qla80XX(ha)) {
137 if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
138 DEBUG2(ql4_printk(KERN_WARNING, ha,
139 "scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n",
140 ha->host_no, __func__));
141 goto mbox_exit;
142 }
143 /* Do not send any mbx cmd if h/w is in failed state*/
144 ha->isp_ops->idc_lock(ha);
145 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
146 ha->isp_ops->idc_unlock(ha);
147 if (dev_state == QLA8XXX_DEV_FAILED) {
148 ql4_printk(KERN_WARNING, ha,
149 "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
150 ha->host_no, __func__);
151 goto mbox_exit;
152 }
153 }
154
155 spin_lock_irqsave(&ha->hardware_lock, flags);
156
157 ha->mbox_status_count = outCount;
158 for (i = 0; i < outCount; i++)
159 ha->mbox_status[i] = 0;
160
161 /* Queue the mailbox command to the firmware */
162 ha->isp_ops->queue_mailbox_command(ha, mbx_cmd, inCount);
163
164 spin_unlock_irqrestore(&ha->hardware_lock, flags);
165
166 /* Wait for completion */
167
168 /*
169 * If we don't want status, don't wait for the mailbox command to
170 * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
171 * you must poll the inbound Interrupt Mask for completion.
172 */
173 if (outCount == 0) {
174 status = QLA_SUCCESS;
175 goto mbox_exit;
176 }
177
178 /*
179 * Wait for completion: Poll or completion queue
180 */
181 if (qla4xxx_is_intr_poll_mode(ha)) {
182 /* Poll for command to complete */
183 wait_count = jiffies + MBOX_TOV * HZ;
184 while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
185 if (time_after_eq(jiffies, wait_count))
186 break;
187 /*
188 * Service the interrupt.
189 * The ISR will save the mailbox status registers
190 * to a temporary storage location in the adapter
191 * structure.
192 */
193 spin_lock_irqsave(&ha->hardware_lock, flags);
194 ha->isp_ops->process_mailbox_interrupt(ha, outCount);
195 spin_unlock_irqrestore(&ha->hardware_lock, flags);
196 msleep(10);
197 }
198 } else {
199 /* Do not poll for completion. Use completion queue */
200 set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
201 wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
202 clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
203 }
204
205 /* Check for mailbox timeout. */
206 if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
207 if (is_qla80XX(ha) &&
208 test_bit(AF_FW_RECOVERY, &ha->flags)) {
209 DEBUG2(ql4_printk(KERN_INFO, ha,
210 "scsi%ld: %s: prematurely completing mbx cmd as "
211 "firmware recovery detected\n",
212 ha->host_no, __func__));
213 goto mbox_exit;
214 }
215 ql4_printk(KERN_WARNING, ha, "scsi%ld: Mailbox Cmd 0x%08X timed out, Scheduling Adapter Reset\n",
216 ha->host_no, mbx_cmd[0]);
217 ha->mailbox_timeout_count++;
218 mbx_sts[0] = (-1);
219 set_bit(DPC_RESET_HA, &ha->dpc_flags);
220 if (is_qla8022(ha)) {
221 ql4_printk(KERN_INFO, ha,
222 "disabling pause transmit on port 0 & 1.\n");
223 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
224 CRB_NIU_XG_PAUSE_CTL_P0 |
225 CRB_NIU_XG_PAUSE_CTL_P1);
226 } else if (is_qla8032(ha) || is_qla8042(ha)) {
227 ql4_printk(KERN_INFO, ha, " %s: disabling pause transmit on port 0 & 1.\n",
228 __func__);
229 qla4_83xx_disable_pause(ha);
230 }
231 goto mbox_exit;
232 }
233
234 /*
235 * Copy the mailbox out registers to the caller's mailbox in/out
236 * structure.
237 */
238 spin_lock_irqsave(&ha->hardware_lock, flags);
239 for (i = 0; i < outCount; i++)
240 mbx_sts[i] = ha->mbox_status[i];
241
242 /* Set return status and error flags (if applicable). */
243 switch (ha->mbox_status[0]) {
244 case MBOX_STS_COMMAND_COMPLETE:
245 status = QLA_SUCCESS;
246 break;
247
248 case MBOX_STS_INTERMEDIATE_COMPLETION:
249 status = QLA_SUCCESS;
250 break;
251
252 case MBOX_STS_BUSY:
253 ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
254 ha->host_no, __func__, mbx_cmd[0]);
255 ha->mailbox_timeout_count++;
256 break;
257
258 default:
259 ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: FAILED, MBOX CMD = %08X, MBOX STS = %08X %08X %08X %08X %08X %08X %08X %08X\n",
260 ha->host_no, __func__, mbx_cmd[0], mbx_sts[0],
261 mbx_sts[1], mbx_sts[2], mbx_sts[3], mbx_sts[4],
262 mbx_sts[5], mbx_sts[6], mbx_sts[7]);
263 break;
264 }
265 spin_unlock_irqrestore(&ha->hardware_lock, flags);
266
267 mbox_exit:
268 mutex_lock(&ha->mbox_sem);
269 clear_bit(AF_MBOX_COMMAND, &ha->flags);
270 mutex_unlock(&ha->mbox_sem);
271 clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
272
273 return status;
274 }
275
276 /**
277 * qla4xxx_get_minidump_template - Get the firmware template
278 * @ha: Pointer to host adapter structure.
279 * @phys_addr: dma address for template
280 *
281 * Obtain the minidump template from firmware during initialization
282 * as it may not be available when minidump is desired.
283 **/
284 int qla4xxx_get_minidump_template(struct scsi_qla_host *ha,
285 dma_addr_t phys_addr)
286 {
287 uint32_t mbox_cmd[MBOX_REG_COUNT];
288 uint32_t mbox_sts[MBOX_REG_COUNT];
289 int status;
290
291 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
292 memset(&mbox_sts, 0, sizeof(mbox_sts));
293
294 mbox_cmd[0] = MBOX_CMD_MINIDUMP;
295 mbox_cmd[1] = MINIDUMP_GET_TMPLT_SUBCOMMAND;
296 mbox_cmd[2] = LSDW(phys_addr);
297 mbox_cmd[3] = MSDW(phys_addr);
298 mbox_cmd[4] = ha->fw_dump_tmplt_size;
299 mbox_cmd[5] = 0;
300
301 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
302 &mbox_sts[0]);
303 if (status != QLA_SUCCESS) {
304 DEBUG2(ql4_printk(KERN_INFO, ha,
305 "scsi%ld: %s: Cmd = %08X, mbx[0] = 0x%04x, mbx[1] = 0x%04x\n",
306 ha->host_no, __func__, mbox_cmd[0],
307 mbox_sts[0], mbox_sts[1]));
308 }
309 return status;
310 }
311
312 /**
313 * qla4xxx_req_template_size - Get minidump template size from firmware.
314 * @ha: Pointer to host adapter structure.
315 **/
316 int qla4xxx_req_template_size(struct scsi_qla_host *ha)
317 {
318 uint32_t mbox_cmd[MBOX_REG_COUNT];
319 uint32_t mbox_sts[MBOX_REG_COUNT];
320 int status;
321
322 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
323 memset(&mbox_sts, 0, sizeof(mbox_sts));
324
325 mbox_cmd[0] = MBOX_CMD_MINIDUMP;
326 mbox_cmd[1] = MINIDUMP_GET_SIZE_SUBCOMMAND;
327
328 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 8, &mbox_cmd[0],
329 &mbox_sts[0]);
330 if (status == QLA_SUCCESS) {
331 ha->fw_dump_tmplt_size = mbox_sts[1];
332 DEBUG2(ql4_printk(KERN_INFO, ha,
333 "%s: sts[0]=0x%04x, template size=0x%04x, size_cm_02=0x%04x, size_cm_04=0x%04x, size_cm_08=0x%04x, size_cm_10=0x%04x, size_cm_FF=0x%04x, version=0x%04x\n",
334 __func__, mbox_sts[0], mbox_sts[1],
335 mbox_sts[2], mbox_sts[3], mbox_sts[4],
336 mbox_sts[5], mbox_sts[6], mbox_sts[7]));
337 if (ha->fw_dump_tmplt_size == 0)
338 status = QLA_ERROR;
339 } else {
340 ql4_printk(KERN_WARNING, ha,
341 "%s: Error sts[0]=0x%04x, mbx[1]=0x%04x\n",
342 __func__, mbox_sts[0], mbox_sts[1]);
343 status = QLA_ERROR;
344 }
345
346 return status;
347 }
348
349 void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
350 {
351 set_bit(AF_FW_RECOVERY, &ha->flags);
352 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
353 ha->host_no, __func__);
354
355 if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
356 if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
357 complete(&ha->mbx_intr_comp);
358 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
359 "recovery, doing premature completion of "
360 "mbx cmd\n", ha->host_no, __func__);
361
362 } else {
363 set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
364 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
365 "recovery, doing premature completion of "
366 "polling mbx cmd\n", ha->host_no, __func__);
367 }
368 }
369 }
370
371 static uint8_t
372 qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
373 uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
374 {
375 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
376 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
377
378 if (is_qla8022(ha))
379 qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, 0);
380
381 mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
382 mbox_cmd[1] = 0;
383 mbox_cmd[2] = LSDW(init_fw_cb_dma);
384 mbox_cmd[3] = MSDW(init_fw_cb_dma);
385 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
386
387 if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
388 QLA_SUCCESS) {
389 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
390 "MBOX_CMD_INITIALIZE_FIRMWARE"
391 " failed w/ status %04X\n",
392 ha->host_no, __func__, mbox_sts[0]));
393 return QLA_ERROR;
394 }
395 return QLA_SUCCESS;
396 }
397
398 uint8_t
399 qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
400 uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
401 {
402 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
403 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
404 mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
405 mbox_cmd[2] = LSDW(init_fw_cb_dma);
406 mbox_cmd[3] = MSDW(init_fw_cb_dma);
407 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
408
409 if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
410 QLA_SUCCESS) {
411 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
412 "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
413 " failed w/ status %04X\n",
414 ha->host_no, __func__, mbox_sts[0]));
415 return QLA_ERROR;
416 }
417 return QLA_SUCCESS;
418 }
419
420 uint8_t qla4xxx_set_ipaddr_state(uint8_t fw_ipaddr_state)
421 {
422 uint8_t ipaddr_state;
423
424 switch (fw_ipaddr_state) {
425 case IP_ADDRSTATE_UNCONFIGURED:
426 ipaddr_state = ISCSI_IPDDRESS_STATE_UNCONFIGURED;
427 break;
428 case IP_ADDRSTATE_INVALID:
429 ipaddr_state = ISCSI_IPDDRESS_STATE_INVALID;
430 break;
431 case IP_ADDRSTATE_ACQUIRING:
432 ipaddr_state = ISCSI_IPDDRESS_STATE_ACQUIRING;
433 break;
434 case IP_ADDRSTATE_TENTATIVE:
435 ipaddr_state = ISCSI_IPDDRESS_STATE_TENTATIVE;
436 break;
437 case IP_ADDRSTATE_DEPRICATED:
438 ipaddr_state = ISCSI_IPDDRESS_STATE_DEPRECATED;
439 break;
440 case IP_ADDRSTATE_PREFERRED:
441 ipaddr_state = ISCSI_IPDDRESS_STATE_VALID;
442 break;
443 case IP_ADDRSTATE_DISABLING:
444 ipaddr_state = ISCSI_IPDDRESS_STATE_DISABLING;
445 break;
446 default:
447 ipaddr_state = ISCSI_IPDDRESS_STATE_UNCONFIGURED;
448 }
449 return ipaddr_state;
450 }
451
452 static void
453 qla4xxx_update_local_ip(struct scsi_qla_host *ha,
454 struct addr_ctrl_blk *init_fw_cb)
455 {
456 ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
457 ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
458 ha->ip_config.ipv4_addr_state =
459 qla4xxx_set_ipaddr_state(init_fw_cb->ipv4_addr_state);
460 ha->ip_config.eth_mtu_size =
461 le16_to_cpu(init_fw_cb->eth_mtu_size);
462 ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port);
463
464 if (ha->acb_version == ACB_SUPPORTED) {
465 ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
466 ha->ip_config.ipv6_addl_options =
467 le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
468 ha->ip_config.ipv6_tcp_options =
469 le16_to_cpu(init_fw_cb->ipv6_tcp_opts);
470 }
471
472 /* Save IPv4 Address Info */
473 memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
474 min(sizeof(ha->ip_config.ip_address),
475 sizeof(init_fw_cb->ipv4_addr)));
476 memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
477 min(sizeof(ha->ip_config.subnet_mask),
478 sizeof(init_fw_cb->ipv4_subnet)));
479 memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
480 min(sizeof(ha->ip_config.gateway),
481 sizeof(init_fw_cb->ipv4_gw_addr)));
482
483 ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
484 ha->ip_config.control = init_fw_cb->control;
485 ha->ip_config.tcp_wsf = init_fw_cb->ipv4_tcp_wsf;
486 ha->ip_config.ipv4_tos = init_fw_cb->ipv4_tos;
487 ha->ip_config.ipv4_cache_id = init_fw_cb->ipv4_cacheid;
488 ha->ip_config.ipv4_alt_cid_len = init_fw_cb->ipv4_dhcp_alt_cid_len;
489 memcpy(ha->ip_config.ipv4_alt_cid, init_fw_cb->ipv4_dhcp_alt_cid,
490 min(sizeof(ha->ip_config.ipv4_alt_cid),
491 sizeof(init_fw_cb->ipv4_dhcp_alt_cid)));
492 ha->ip_config.ipv4_vid_len = init_fw_cb->ipv4_dhcp_vid_len;
493 memcpy(ha->ip_config.ipv4_vid, init_fw_cb->ipv4_dhcp_vid,
494 min(sizeof(ha->ip_config.ipv4_vid),
495 sizeof(init_fw_cb->ipv4_dhcp_vid)));
496 ha->ip_config.ipv4_ttl = init_fw_cb->ipv4_ttl;
497 ha->ip_config.def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
498 ha->ip_config.abort_timer = init_fw_cb->abort_timer;
499 ha->ip_config.iscsi_options = le16_to_cpu(init_fw_cb->iscsi_opts);
500 ha->ip_config.iscsi_max_pdu_size =
501 le16_to_cpu(init_fw_cb->iscsi_max_pdu_size);
502 ha->ip_config.iscsi_first_burst_len =
503 le16_to_cpu(init_fw_cb->iscsi_fburst_len);
504 ha->ip_config.iscsi_max_outstnd_r2t =
505 le16_to_cpu(init_fw_cb->iscsi_max_outstnd_r2t);
506 ha->ip_config.iscsi_max_burst_len =
507 le16_to_cpu(init_fw_cb->iscsi_max_burst_len);
508 memcpy(ha->ip_config.iscsi_name, init_fw_cb->iscsi_name,
509 min(sizeof(ha->ip_config.iscsi_name),
510 sizeof(init_fw_cb->iscsi_name)));
511
512 if (is_ipv6_enabled(ha)) {
513 /* Save IPv6 Address */
514 ha->ip_config.ipv6_link_local_state =
515 qla4xxx_set_ipaddr_state(init_fw_cb->ipv6_lnk_lcl_addr_state);
516 ha->ip_config.ipv6_addr0_state =
517 qla4xxx_set_ipaddr_state(init_fw_cb->ipv6_addr0_state);
518 ha->ip_config.ipv6_addr1_state =
519 qla4xxx_set_ipaddr_state(init_fw_cb->ipv6_addr1_state);
520
521 switch (le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state)) {
522 case IPV6_RTRSTATE_UNKNOWN:
523 ha->ip_config.ipv6_default_router_state =
524 ISCSI_ROUTER_STATE_UNKNOWN;
525 break;
526 case IPV6_RTRSTATE_MANUAL:
527 ha->ip_config.ipv6_default_router_state =
528 ISCSI_ROUTER_STATE_MANUAL;
529 break;
530 case IPV6_RTRSTATE_ADVERTISED:
531 ha->ip_config.ipv6_default_router_state =
532 ISCSI_ROUTER_STATE_ADVERTISED;
533 break;
534 case IPV6_RTRSTATE_STALE:
535 ha->ip_config.ipv6_default_router_state =
536 ISCSI_ROUTER_STATE_STALE;
537 break;
538 default:
539 ha->ip_config.ipv6_default_router_state =
540 ISCSI_ROUTER_STATE_UNKNOWN;
541 }
542
543 ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
544 ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
545
546 memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
547 init_fw_cb->ipv6_if_id,
548 min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
549 sizeof(init_fw_cb->ipv6_if_id)));
550 memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
551 min(sizeof(ha->ip_config.ipv6_addr0),
552 sizeof(init_fw_cb->ipv6_addr0)));
553 memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
554 min(sizeof(ha->ip_config.ipv6_addr1),
555 sizeof(init_fw_cb->ipv6_addr1)));
556 memcpy(&ha->ip_config.ipv6_default_router_addr,
557 init_fw_cb->ipv6_dflt_rtr_addr,
558 min(sizeof(ha->ip_config.ipv6_default_router_addr),
559 sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
560 ha->ip_config.ipv6_vlan_tag =
561 be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
562 ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port);
563 ha->ip_config.ipv6_cache_id = init_fw_cb->ipv6_cache_id;
564 ha->ip_config.ipv6_flow_lbl =
565 le16_to_cpu(init_fw_cb->ipv6_flow_lbl);
566 ha->ip_config.ipv6_traffic_class =
567 init_fw_cb->ipv6_traffic_class;
568 ha->ip_config.ipv6_hop_limit = init_fw_cb->ipv6_hop_limit;
569 ha->ip_config.ipv6_nd_reach_time =
570 le32_to_cpu(init_fw_cb->ipv6_nd_reach_time);
571 ha->ip_config.ipv6_nd_rexmit_timer =
572 le32_to_cpu(init_fw_cb->ipv6_nd_rexmit_timer);
573 ha->ip_config.ipv6_nd_stale_timeout =
574 le32_to_cpu(init_fw_cb->ipv6_nd_stale_timeout);
575 ha->ip_config.ipv6_dup_addr_detect_count =
576 init_fw_cb->ipv6_dup_addr_detect_count;
577 ha->ip_config.ipv6_gw_advrt_mtu =
578 le32_to_cpu(init_fw_cb->ipv6_gw_advrt_mtu);
579 ha->ip_config.ipv6_tcp_wsf = init_fw_cb->ipv6_tcp_wsf;
580 }
581 }
582
583 uint8_t
584 qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
585 uint32_t *mbox_cmd,
586 uint32_t *mbox_sts,
587 struct addr_ctrl_blk *init_fw_cb,
588 dma_addr_t init_fw_cb_dma)
589 {
590 if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
591 != QLA_SUCCESS) {
592 DEBUG2(printk(KERN_WARNING
593 "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
594 ha->host_no, __func__));
595 return QLA_ERROR;
596 }
597
598 DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
599
600 /* Save some info in adapter structure. */
601 ha->acb_version = init_fw_cb->acb_version;
602 ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
603 ha->heartbeat_interval = init_fw_cb->hb_interval;
604 memcpy(ha->name_string, init_fw_cb->iscsi_name,
605 min(sizeof(ha->name_string),
606 sizeof(init_fw_cb->iscsi_name)));
607 ha->def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
608 /*memcpy(ha->alias, init_fw_cb->Alias,
609 min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
610
611 qla4xxx_update_local_ip(ha, init_fw_cb);
612
613 return QLA_SUCCESS;
614 }
615
616 /**
617 * qla4xxx_initialize_fw_cb - initializes firmware control block.
618 * @ha: Pointer to host adapter structure.
619 **/
620 int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
621 {
622 struct addr_ctrl_blk *init_fw_cb;
623 dma_addr_t init_fw_cb_dma;
624 uint32_t mbox_cmd[MBOX_REG_COUNT];
625 uint32_t mbox_sts[MBOX_REG_COUNT];
626 int status = QLA_ERROR;
627
628 init_fw_cb = dma_zalloc_coherent(&ha->pdev->dev,
629 sizeof(struct addr_ctrl_blk),
630 &init_fw_cb_dma, GFP_KERNEL);
631 if (init_fw_cb == NULL) {
632 DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
633 ha->host_no, __func__));
634 goto exit_init_fw_cb_no_free;
635 }
636
637 /* Get Initialize Firmware Control Block. */
638 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
639 memset(&mbox_sts, 0, sizeof(mbox_sts));
640
641 if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
642 QLA_SUCCESS) {
643 dma_free_coherent(&ha->pdev->dev,
644 sizeof(struct addr_ctrl_blk),
645 init_fw_cb, init_fw_cb_dma);
646 goto exit_init_fw_cb;
647 }
648
649 /* Fill in the request and response queue information. */
650 init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
651 init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
652 init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
653 init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
654 init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
655 init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
656 init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
657 init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
658 init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
659 init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
660
661 /* Set up required options. */
662 init_fw_cb->fw_options |=
663 __constant_cpu_to_le16(FWOPT_SESSION_MODE |
664 FWOPT_INITIATOR_MODE);
665
666 if (is_qla80XX(ha))
667 init_fw_cb->fw_options |=
668 __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
669
670 init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
671
672 init_fw_cb->add_fw_options = 0;
673 init_fw_cb->add_fw_options |=
674 __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
675 init_fw_cb->add_fw_options |=
676 __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
677
678 if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
679 != QLA_SUCCESS) {
680 DEBUG2(printk(KERN_WARNING
681 "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
682 ha->host_no, __func__));
683 goto exit_init_fw_cb;
684 }
685
686 if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
687 init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
688 DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
689 ha->host_no, __func__));
690 goto exit_init_fw_cb;
691 }
692 status = QLA_SUCCESS;
693
694 exit_init_fw_cb:
695 dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
696 init_fw_cb, init_fw_cb_dma);
697 exit_init_fw_cb_no_free:
698 return status;
699 }
700
701 /**
702 * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
703 * @ha: Pointer to host adapter structure.
704 **/
705 int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
706 {
707 struct addr_ctrl_blk *init_fw_cb;
708 dma_addr_t init_fw_cb_dma;
709 uint32_t mbox_cmd[MBOX_REG_COUNT];
710 uint32_t mbox_sts[MBOX_REG_COUNT];
711
712 init_fw_cb = dma_zalloc_coherent(&ha->pdev->dev,
713 sizeof(struct addr_ctrl_blk),
714 &init_fw_cb_dma, GFP_KERNEL);
715 if (init_fw_cb == NULL) {
716 printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
717 __func__);
718 return QLA_ERROR;
719 }
720
721 /* Get Initialize Firmware Control Block. */
722 if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
723 QLA_SUCCESS) {
724 DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
725 ha->host_no, __func__));
726 dma_free_coherent(&ha->pdev->dev,
727 sizeof(struct addr_ctrl_blk),
728 init_fw_cb, init_fw_cb_dma);
729 return QLA_ERROR;
730 }
731
732 /* Save IP Address. */
733 qla4xxx_update_local_ip(ha, init_fw_cb);
734 dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
735 init_fw_cb, init_fw_cb_dma);
736
737 return QLA_SUCCESS;
738 }
739
740 /**
741 * qla4xxx_get_firmware_state - gets firmware state of HBA
742 * @ha: Pointer to host adapter structure.
743 **/
744 int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
745 {
746 uint32_t mbox_cmd[MBOX_REG_COUNT];
747 uint32_t mbox_sts[MBOX_REG_COUNT];
748
749 /* Get firmware version */
750 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
751 memset(&mbox_sts, 0, sizeof(mbox_sts));
752
753 mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
754
755 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
756 QLA_SUCCESS) {
757 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
758 "status %04X\n", ha->host_no, __func__,
759 mbox_sts[0]));
760 return QLA_ERROR;
761 }
762 ha->firmware_state = mbox_sts[1];
763 ha->board_id = mbox_sts[2];
764 ha->addl_fw_state = mbox_sts[3];
765 DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
766 ha->host_no, __func__, ha->firmware_state);)
767
768 return QLA_SUCCESS;
769 }
770
771 /**
772 * qla4xxx_get_firmware_status - retrieves firmware status
773 * @ha: Pointer to host adapter structure.
774 **/
775 int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
776 {
777 uint32_t mbox_cmd[MBOX_REG_COUNT];
778 uint32_t mbox_sts[MBOX_REG_COUNT];
779
780 /* Get firmware version */
781 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
782 memset(&mbox_sts, 0, sizeof(mbox_sts));
783
784 mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
785
786 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
787 QLA_SUCCESS) {
788 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
789 "status %04X\n", ha->host_no, __func__,
790 mbox_sts[0]));
791 return QLA_ERROR;
792 }
793
794 /* High-water mark of IOCBs */
795 ha->iocb_hiwat = mbox_sts[2];
796 DEBUG2(ql4_printk(KERN_INFO, ha,
797 "%s: firmware IOCBs available = %d\n", __func__,
798 ha->iocb_hiwat));
799
800 if (ha->iocb_hiwat > IOCB_HIWAT_CUSHION)
801 ha->iocb_hiwat -= IOCB_HIWAT_CUSHION;
802
803 /* Ideally, we should not enter this code, as the # of firmware
804 * IOCBs is hard-coded in the firmware. We set a default
805 * iocb_hiwat here just in case */
806 if (ha->iocb_hiwat == 0) {
807 ha->iocb_hiwat = REQUEST_QUEUE_DEPTH / 4;
808 DEBUG2(ql4_printk(KERN_WARNING, ha,
809 "%s: Setting IOCB's to = %d\n", __func__,
810 ha->iocb_hiwat));
811 }
812
813 return QLA_SUCCESS;
814 }
815
816 /**
817 * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
818 * @ha: Pointer to host adapter structure.
819 * @fw_ddb_index: Firmware's device database index
820 * @fw_ddb_entry: Pointer to firmware's device database entry structure
821 * @num_valid_ddb_entries: Pointer to number of valid ddb entries
822 * @next_ddb_index: Pointer to next valid device database index
823 * @fw_ddb_device_state: Pointer to device state
824 **/
825 int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
826 uint16_t fw_ddb_index,
827 struct dev_db_entry *fw_ddb_entry,
828 dma_addr_t fw_ddb_entry_dma,
829 uint32_t *num_valid_ddb_entries,
830 uint32_t *next_ddb_index,
831 uint32_t *fw_ddb_device_state,
832 uint32_t *conn_err_detail,
833 uint16_t *tcp_source_port_num,
834 uint16_t *connection_id)
835 {
836 int status = QLA_ERROR;
837 uint16_t options;
838 uint32_t mbox_cmd[MBOX_REG_COUNT];
839 uint32_t mbox_sts[MBOX_REG_COUNT];
840
841 /* Make sure the device index is valid */
842 if (fw_ddb_index >= MAX_DDB_ENTRIES) {
843 DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
844 ha->host_no, __func__, fw_ddb_index));
845 goto exit_get_fwddb;
846 }
847 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
848 memset(&mbox_sts, 0, sizeof(mbox_sts));
849 if (fw_ddb_entry)
850 memset(fw_ddb_entry, 0, sizeof(struct dev_db_entry));
851
852 mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
853 mbox_cmd[1] = (uint32_t) fw_ddb_index;
854 mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
855 mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
856 mbox_cmd[4] = sizeof(struct dev_db_entry);
857
858 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
859 QLA_ERROR) {
860 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
861 " with status 0x%04X\n", ha->host_no, __func__,
862 mbox_sts[0]));
863 goto exit_get_fwddb;
864 }
865 if (fw_ddb_index != mbox_sts[1]) {
866 DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
867 ha->host_no, __func__, fw_ddb_index,
868 mbox_sts[1]));
869 goto exit_get_fwddb;
870 }
871 if (fw_ddb_entry) {
872 options = le16_to_cpu(fw_ddb_entry->options);
873 if (options & DDB_OPT_IPV6_DEVICE) {
874 ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
875 "Next %d State %04x ConnErr %08x %pI6 "
876 ":%04d \"%s\"\n", __func__, fw_ddb_index,
877 mbox_sts[0], mbox_sts[2], mbox_sts[3],
878 mbox_sts[4], mbox_sts[5],
879 fw_ddb_entry->ip_addr,
880 le16_to_cpu(fw_ddb_entry->port),
881 fw_ddb_entry->iscsi_name);
882 } else {
883 ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
884 "Next %d State %04x ConnErr %08x %pI4 "
885 ":%04d \"%s\"\n", __func__, fw_ddb_index,
886 mbox_sts[0], mbox_sts[2], mbox_sts[3],
887 mbox_sts[4], mbox_sts[5],
888 fw_ddb_entry->ip_addr,
889 le16_to_cpu(fw_ddb_entry->port),
890 fw_ddb_entry->iscsi_name);
891 }
892 }
893 if (num_valid_ddb_entries)
894 *num_valid_ddb_entries = mbox_sts[2];
895 if (next_ddb_index)
896 *next_ddb_index = mbox_sts[3];
897 if (fw_ddb_device_state)
898 *fw_ddb_device_state = mbox_sts[4];
899
900 /*
901 * RA: This mailbox has been changed to pass connection error and
902 * details. Its true for ISP4010 as per Version E - Not sure when it
903 * was changed. Get the time2wait from the fw_dd_entry field :
904 * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
905 * struct.
906 */
907 if (conn_err_detail)
908 *conn_err_detail = mbox_sts[5];
909 if (tcp_source_port_num)
910 *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
911 if (connection_id)
912 *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
913 status = QLA_SUCCESS;
914
915 exit_get_fwddb:
916 return status;
917 }
918
919 int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
920 {
921 uint32_t mbox_cmd[MBOX_REG_COUNT];
922 uint32_t mbox_sts[MBOX_REG_COUNT];
923 int status;
924
925 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
926 memset(&mbox_sts, 0, sizeof(mbox_sts));
927
928 mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
929 mbox_cmd[1] = fw_ddb_index;
930
931 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
932 &mbox_sts[0]);
933 DEBUG2(ql4_printk(KERN_INFO, ha,
934 "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
935 __func__, status, mbox_sts[0], mbox_sts[1]));
936 return status;
937 }
938
939 /**
940 * qla4xxx_set_fwddb_entry - sets a ddb entry.
941 * @ha: Pointer to host adapter structure.
942 * @fw_ddb_index: Firmware's device database index
943 * @fw_ddb_entry_dma: dma address of ddb entry
944 * @mbx_sts: mailbox 0 to be returned or NULL
945 *
946 * This routine initializes or updates the adapter's device database
947 * entry for the specified device.
948 **/
949 int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
950 dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
951 {
952 uint32_t mbox_cmd[MBOX_REG_COUNT];
953 uint32_t mbox_sts[MBOX_REG_COUNT];
954 int status;
955
956 /* Do not wait for completion. The firmware will send us an
957 * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
958 */
959 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
960 memset(&mbox_sts, 0, sizeof(mbox_sts));
961
962 mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
963 mbox_cmd[1] = (uint32_t) fw_ddb_index;
964 mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
965 mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
966 mbox_cmd[4] = sizeof(struct dev_db_entry);
967
968 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
969 &mbox_sts[0]);
970 if (mbx_sts)
971 *mbx_sts = mbox_sts[0];
972 DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
973 ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
974
975 return status;
976 }
977
978 int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
979 struct ddb_entry *ddb_entry, int options)
980 {
981 int status;
982 uint32_t mbox_cmd[MBOX_REG_COUNT];
983 uint32_t mbox_sts[MBOX_REG_COUNT];
984
985 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
986 memset(&mbox_sts, 0, sizeof(mbox_sts));
987
988 mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
989 mbox_cmd[1] = ddb_entry->fw_ddb_index;
990 mbox_cmd[3] = options;
991
992 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
993 &mbox_sts[0]);
994 if (status != QLA_SUCCESS) {
995 DEBUG2(ql4_printk(KERN_INFO, ha,
996 "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
997 "failed sts %04X %04X", __func__,
998 mbox_sts[0], mbox_sts[1]));
999 if ((mbox_sts[0] == MBOX_STS_COMMAND_ERROR) &&
1000 (mbox_sts[1] == DDB_NOT_LOGGED_IN)) {
1001 set_bit(DDB_CONN_CLOSE_FAILURE, &ddb_entry->flags);
1002 }
1003 }
1004
1005 return status;
1006 }
1007
1008 /**
1009 * qla4xxx_get_crash_record - retrieves crash record.
1010 * @ha: Pointer to host adapter structure.
1011 *
1012 * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
1013 **/
1014 void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
1015 {
1016 uint32_t mbox_cmd[MBOX_REG_COUNT];
1017 uint32_t mbox_sts[MBOX_REG_COUNT];
1018 struct crash_record *crash_record = NULL;
1019 dma_addr_t crash_record_dma = 0;
1020 uint32_t crash_record_size = 0;
1021
1022 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1023 memset(&mbox_sts, 0, sizeof(mbox_cmd));
1024
1025 /* Get size of crash record. */
1026 mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
1027
1028 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
1029 QLA_SUCCESS) {
1030 DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
1031 ha->host_no, __func__));
1032 goto exit_get_crash_record;
1033 }
1034 crash_record_size = mbox_sts[4];
1035 if (crash_record_size == 0) {
1036 DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
1037 ha->host_no, __func__));
1038 goto exit_get_crash_record;
1039 }
1040
1041 /* Alloc Memory for Crash Record. */
1042 crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
1043 &crash_record_dma, GFP_KERNEL);
1044 if (crash_record == NULL)
1045 goto exit_get_crash_record;
1046
1047 /* Get Crash Record. */
1048 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1049 memset(&mbox_sts, 0, sizeof(mbox_cmd));
1050
1051 mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
1052 mbox_cmd[2] = LSDW(crash_record_dma);
1053 mbox_cmd[3] = MSDW(crash_record_dma);
1054 mbox_cmd[4] = crash_record_size;
1055
1056 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
1057 QLA_SUCCESS)
1058 goto exit_get_crash_record;
1059
1060 /* Dump Crash Record. */
1061
1062 exit_get_crash_record:
1063 if (crash_record)
1064 dma_free_coherent(&ha->pdev->dev, crash_record_size,
1065 crash_record, crash_record_dma);
1066 }
1067
1068 /**
1069 * qla4xxx_get_conn_event_log - retrieves connection event log
1070 * @ha: Pointer to host adapter structure.
1071 **/
1072 void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
1073 {
1074 uint32_t mbox_cmd[MBOX_REG_COUNT];
1075 uint32_t mbox_sts[MBOX_REG_COUNT];
1076 struct conn_event_log_entry *event_log = NULL;
1077 dma_addr_t event_log_dma = 0;
1078 uint32_t event_log_size = 0;
1079 uint32_t num_valid_entries;
1080 uint32_t oldest_entry = 0;
1081 uint32_t max_event_log_entries;
1082 uint8_t i;
1083
1084 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1085 memset(&mbox_sts, 0, sizeof(mbox_cmd));
1086
1087 /* Get size of crash record. */
1088 mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
1089
1090 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
1091 QLA_SUCCESS)
1092 goto exit_get_event_log;
1093
1094 event_log_size = mbox_sts[4];
1095 if (event_log_size == 0)
1096 goto exit_get_event_log;
1097
1098 /* Alloc Memory for Crash Record. */
1099 event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
1100 &event_log_dma, GFP_KERNEL);
1101 if (event_log == NULL)
1102 goto exit_get_event_log;
1103
1104 /* Get Crash Record. */
1105 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1106 memset(&mbox_sts, 0, sizeof(mbox_cmd));
1107
1108 mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
1109 mbox_cmd[2] = LSDW(event_log_dma);
1110 mbox_cmd[3] = MSDW(event_log_dma);
1111
1112 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
1113 QLA_SUCCESS) {
1114 DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
1115 "log!\n", ha->host_no, __func__));
1116 goto exit_get_event_log;
1117 }
1118
1119 /* Dump Event Log. */
1120 num_valid_entries = mbox_sts[1];
1121
1122 max_event_log_entries = event_log_size /
1123 sizeof(struct conn_event_log_entry);
1124
1125 if (num_valid_entries > max_event_log_entries)
1126 oldest_entry = num_valid_entries % max_event_log_entries;
1127
1128 DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
1129 ha->host_no, num_valid_entries));
1130
1131 if (ql4xextended_error_logging == 3) {
1132 if (oldest_entry == 0) {
1133 /* Circular Buffer has not wrapped around */
1134 for (i=0; i < num_valid_entries; i++) {
1135 qla4xxx_dump_buffer((uint8_t *)event_log+
1136 (i*sizeof(*event_log)),
1137 sizeof(*event_log));
1138 }
1139 }
1140 else {
1141 /* Circular Buffer has wrapped around -
1142 * display accordingly*/
1143 for (i=oldest_entry; i < max_event_log_entries; i++) {
1144 qla4xxx_dump_buffer((uint8_t *)event_log+
1145 (i*sizeof(*event_log)),
1146 sizeof(*event_log));
1147 }
1148 for (i=0; i < oldest_entry; i++) {
1149 qla4xxx_dump_buffer((uint8_t *)event_log+
1150 (i*sizeof(*event_log)),
1151 sizeof(*event_log));
1152 }
1153 }
1154 }
1155
1156 exit_get_event_log:
1157 if (event_log)
1158 dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
1159 event_log_dma);
1160 }
1161
1162 /**
1163 * qla4xxx_abort_task - issues Abort Task
1164 * @ha: Pointer to host adapter structure.
1165 * @srb: Pointer to srb entry
1166 *
1167 * This routine performs a LUN RESET on the specified target/lun.
1168 * The caller must ensure that the ddb_entry and lun_entry pointers
1169 * are valid before calling this routine.
1170 **/
1171 int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
1172 {
1173 uint32_t mbox_cmd[MBOX_REG_COUNT];
1174 uint32_t mbox_sts[MBOX_REG_COUNT];
1175 struct scsi_cmnd *cmd = srb->cmd;
1176 int status = QLA_SUCCESS;
1177 unsigned long flags = 0;
1178 uint32_t index;
1179
1180 /*
1181 * Send abort task command to ISP, so that the ISP will return
1182 * request with ABORT status
1183 */
1184 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1185 memset(&mbox_sts, 0, sizeof(mbox_sts));
1186
1187 spin_lock_irqsave(&ha->hardware_lock, flags);
1188 index = (unsigned long)(unsigned char *)cmd->host_scribble;
1189 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1190
1191 /* Firmware already posted completion on response queue */
1192 if (index == MAX_SRBS)
1193 return status;
1194
1195 mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
1196 mbox_cmd[1] = srb->ddb->fw_ddb_index;
1197 mbox_cmd[2] = index;
1198 /* Immediate Command Enable */
1199 mbox_cmd[5] = 0x01;
1200
1201 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
1202 &mbox_sts[0]);
1203 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
1204 status = QLA_ERROR;
1205
1206 DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%llu: abort task FAILED: "
1207 "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
1208 ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
1209 mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
1210 }
1211
1212 return status;
1213 }
1214
1215 /**
1216 * qla4xxx_reset_lun - issues LUN Reset
1217 * @ha: Pointer to host adapter structure.
1218 * @ddb_entry: Pointer to device database entry
1219 * @lun: lun number
1220 *
1221 * This routine performs a LUN RESET on the specified target/lun.
1222 * The caller must ensure that the ddb_entry and lun_entry pointers
1223 * are valid before calling this routine.
1224 **/
1225 int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
1226 uint64_t lun)
1227 {
1228 uint32_t mbox_cmd[MBOX_REG_COUNT];
1229 uint32_t mbox_sts[MBOX_REG_COUNT];
1230 uint32_t scsi_lun[2];
1231 int status = QLA_SUCCESS;
1232
1233 DEBUG2(printk("scsi%ld:%d:%llu: lun reset issued\n", ha->host_no,
1234 ddb_entry->fw_ddb_index, lun));
1235
1236 /*
1237 * Send lun reset command to ISP, so that the ISP will return all
1238 * outstanding requests with RESET status
1239 */
1240 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1241 memset(&mbox_sts, 0, sizeof(mbox_sts));
1242 int_to_scsilun(lun, (struct scsi_lun *) scsi_lun);
1243
1244 mbox_cmd[0] = MBOX_CMD_LUN_RESET;
1245 mbox_cmd[1] = ddb_entry->fw_ddb_index;
1246 /* FW expects LUN bytes 0-3 in Incoming Mailbox 2
1247 * (LUN byte 0 is LSByte, byte 3 is MSByte) */
1248 mbox_cmd[2] = cpu_to_le32(scsi_lun[0]);
1249 /* FW expects LUN bytes 4-7 in Incoming Mailbox 3
1250 * (LUN byte 4 is LSByte, byte 7 is MSByte) */
1251 mbox_cmd[3] = cpu_to_le32(scsi_lun[1]);
1252 mbox_cmd[5] = 0x01; /* Immediate Command Enable */
1253
1254 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
1255 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
1256 mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
1257 status = QLA_ERROR;
1258
1259 return status;
1260 }
1261
1262 /**
1263 * qla4xxx_reset_target - issues target Reset
1264 * @ha: Pointer to host adapter structure.
1265 * @db_entry: Pointer to device database entry
1266 * @un_entry: Pointer to lun entry structure
1267 *
1268 * This routine performs a TARGET RESET on the specified target.
1269 * The caller must ensure that the ddb_entry pointers
1270 * are valid before calling this routine.
1271 **/
1272 int qla4xxx_reset_target(struct scsi_qla_host *ha,
1273 struct ddb_entry *ddb_entry)
1274 {
1275 uint32_t mbox_cmd[MBOX_REG_COUNT];
1276 uint32_t mbox_sts[MBOX_REG_COUNT];
1277 int status = QLA_SUCCESS;
1278
1279 DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
1280 ddb_entry->fw_ddb_index));
1281
1282 /*
1283 * Send target reset command to ISP, so that the ISP will return all
1284 * outstanding requests with RESET status
1285 */
1286 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1287 memset(&mbox_sts, 0, sizeof(mbox_sts));
1288
1289 mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
1290 mbox_cmd[1] = ddb_entry->fw_ddb_index;
1291 mbox_cmd[5] = 0x01; /* Immediate Command Enable */
1292
1293 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1294 &mbox_sts[0]);
1295 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
1296 mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
1297 status = QLA_ERROR;
1298
1299 return status;
1300 }
1301
1302 int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
1303 uint32_t offset, uint32_t len)
1304 {
1305 uint32_t mbox_cmd[MBOX_REG_COUNT];
1306 uint32_t mbox_sts[MBOX_REG_COUNT];
1307
1308 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1309 memset(&mbox_sts, 0, sizeof(mbox_sts));
1310
1311 mbox_cmd[0] = MBOX_CMD_READ_FLASH;
1312 mbox_cmd[1] = LSDW(dma_addr);
1313 mbox_cmd[2] = MSDW(dma_addr);
1314 mbox_cmd[3] = offset;
1315 mbox_cmd[4] = len;
1316
1317 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
1318 QLA_SUCCESS) {
1319 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
1320 "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
1321 __func__, mbox_sts[0], mbox_sts[1], offset, len));
1322 return QLA_ERROR;
1323 }
1324 return QLA_SUCCESS;
1325 }
1326
1327 /**
1328 * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
1329 * @ha: Pointer to host adapter structure.
1330 *
1331 * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
1332 * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
1333 * those mailboxes, if unused.
1334 **/
1335 int qla4xxx_about_firmware(struct scsi_qla_host *ha)
1336 {
1337 struct about_fw_info *about_fw = NULL;
1338 dma_addr_t about_fw_dma;
1339 uint32_t mbox_cmd[MBOX_REG_COUNT];
1340 uint32_t mbox_sts[MBOX_REG_COUNT];
1341 int status = QLA_ERROR;
1342
1343 about_fw = dma_zalloc_coherent(&ha->pdev->dev,
1344 sizeof(struct about_fw_info),
1345 &about_fw_dma, GFP_KERNEL);
1346 if (!about_fw) {
1347 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
1348 "for about_fw\n", __func__));
1349 return status;
1350 }
1351
1352 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1353 memset(&mbox_sts, 0, sizeof(mbox_sts));
1354
1355 mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
1356 mbox_cmd[2] = LSDW(about_fw_dma);
1357 mbox_cmd[3] = MSDW(about_fw_dma);
1358 mbox_cmd[4] = sizeof(struct about_fw_info);
1359
1360 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
1361 &mbox_cmd[0], &mbox_sts[0]);
1362 if (status != QLA_SUCCESS) {
1363 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
1364 "failed w/ status %04X\n", __func__,
1365 mbox_sts[0]));
1366 goto exit_about_fw;
1367 }
1368
1369 /* Save version information. */
1370 ha->fw_info.fw_major = le16_to_cpu(about_fw->fw_major);
1371 ha->fw_info.fw_minor = le16_to_cpu(about_fw->fw_minor);
1372 ha->fw_info.fw_patch = le16_to_cpu(about_fw->fw_patch);
1373 ha->fw_info.fw_build = le16_to_cpu(about_fw->fw_build);
1374 memcpy(ha->fw_info.fw_build_date, about_fw->fw_build_date,
1375 sizeof(about_fw->fw_build_date));
1376 memcpy(ha->fw_info.fw_build_time, about_fw->fw_build_time,
1377 sizeof(about_fw->fw_build_time));
1378 strcpy((char *)ha->fw_info.fw_build_user,
1379 skip_spaces((char *)about_fw->fw_build_user));
1380 ha->fw_info.fw_load_source = le16_to_cpu(about_fw->fw_load_source);
1381 ha->fw_info.iscsi_major = le16_to_cpu(about_fw->iscsi_major);
1382 ha->fw_info.iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
1383 ha->fw_info.bootload_major = le16_to_cpu(about_fw->bootload_major);
1384 ha->fw_info.bootload_minor = le16_to_cpu(about_fw->bootload_minor);
1385 ha->fw_info.bootload_patch = le16_to_cpu(about_fw->bootload_patch);
1386 ha->fw_info.bootload_build = le16_to_cpu(about_fw->bootload_build);
1387 strcpy((char *)ha->fw_info.extended_timestamp,
1388 skip_spaces((char *)about_fw->extended_timestamp));
1389
1390 ha->fw_uptime_secs = le32_to_cpu(mbox_sts[5]);
1391 ha->fw_uptime_msecs = le32_to_cpu(mbox_sts[6]);
1392 status = QLA_SUCCESS;
1393
1394 exit_about_fw:
1395 dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
1396 about_fw, about_fw_dma);
1397 return status;
1398 }
1399
1400 int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
1401 dma_addr_t dma_addr)
1402 {
1403 uint32_t mbox_cmd[MBOX_REG_COUNT];
1404 uint32_t mbox_sts[MBOX_REG_COUNT];
1405
1406 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1407 memset(&mbox_sts, 0, sizeof(mbox_sts));
1408
1409 mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
1410 mbox_cmd[1] = options;
1411 mbox_cmd[2] = LSDW(dma_addr);
1412 mbox_cmd[3] = MSDW(dma_addr);
1413
1414 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
1415 QLA_SUCCESS) {
1416 DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
1417 ha->host_no, __func__, mbox_sts[0]));
1418 return QLA_ERROR;
1419 }
1420 return QLA_SUCCESS;
1421 }
1422
1423 int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
1424 uint32_t *mbx_sts)
1425 {
1426 int status;
1427 uint32_t mbox_cmd[MBOX_REG_COUNT];
1428 uint32_t mbox_sts[MBOX_REG_COUNT];
1429
1430 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1431 memset(&mbox_sts, 0, sizeof(mbox_sts));
1432
1433 mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
1434 mbox_cmd[1] = ddb_index;
1435
1436 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1437 &mbox_sts[0]);
1438 if (status != QLA_SUCCESS) {
1439 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
1440 __func__, mbox_sts[0]));
1441 }
1442
1443 *mbx_sts = mbox_sts[0];
1444 return status;
1445 }
1446
1447 int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
1448 {
1449 int status;
1450 uint32_t mbox_cmd[MBOX_REG_COUNT];
1451 uint32_t mbox_sts[MBOX_REG_COUNT];
1452
1453 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1454 memset(&mbox_sts, 0, sizeof(mbox_sts));
1455
1456 mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
1457 mbox_cmd[1] = ddb_index;
1458
1459 status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
1460 &mbox_sts[0]);
1461 if (status != QLA_SUCCESS) {
1462 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
1463 __func__, mbox_sts[0]));
1464 }
1465
1466 return status;
1467 }
1468
1469 int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
1470 uint32_t offset, uint32_t length, uint32_t options)
1471 {
1472 uint32_t mbox_cmd[MBOX_REG_COUNT];
1473 uint32_t mbox_sts[MBOX_REG_COUNT];
1474 int status = QLA_SUCCESS;
1475
1476 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1477 memset(&mbox_sts, 0, sizeof(mbox_sts));
1478
1479 mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
1480 mbox_cmd[1] = LSDW(dma_addr);
1481 mbox_cmd[2] = MSDW(dma_addr);
1482 mbox_cmd[3] = offset;
1483 mbox_cmd[4] = length;
1484 mbox_cmd[5] = options;
1485
1486 status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
1487 if (status != QLA_SUCCESS) {
1488 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
1489 "failed w/ status %04X, mbx1 %04X\n",
1490 __func__, mbox_sts[0], mbox_sts[1]));
1491 }
1492 return status;
1493 }
1494
1495 int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
1496 struct dev_db_entry *fw_ddb_entry,
1497 dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
1498 {
1499 uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
1500 uint32_t dev_db_end_offset;
1501 int status = QLA_ERROR;
1502
1503 memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
1504
1505 dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
1506 dev_db_end_offset = FLASH_OFFSET_DB_END;
1507
1508 if (dev_db_start_offset > dev_db_end_offset) {
1509 DEBUG2(ql4_printk(KERN_ERR, ha,
1510 "%s:Invalid DDB index %d", __func__,
1511 ddb_index));
1512 goto exit_bootdb_failed;
1513 }
1514
1515 if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
1516 sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
1517 ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
1518 "failed\n", ha->host_no, __func__);
1519 goto exit_bootdb_failed;
1520 }
1521
1522 if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
1523 status = QLA_SUCCESS;
1524
1525 exit_bootdb_failed:
1526 return status;
1527 }
1528
1529 int qla4xxx_flashdb_by_index(struct scsi_qla_host *ha,
1530 struct dev_db_entry *fw_ddb_entry,
1531 dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
1532 {
1533 uint32_t dev_db_start_offset;
1534 uint32_t dev_db_end_offset;
1535 int status = QLA_ERROR;
1536
1537 memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
1538
1539 if (is_qla40XX(ha)) {
1540 dev_db_start_offset = FLASH_OFFSET_DB_INFO;
1541 dev_db_end_offset = FLASH_OFFSET_DB_END;
1542 } else {
1543 dev_db_start_offset = FLASH_RAW_ACCESS_ADDR +
1544 (ha->hw.flt_region_ddb << 2);
1545 /* flt_ddb_size is DDB table size for both ports
1546 * so divide it by 2 to calculate the offset for second port
1547 */
1548 if (ha->port_num == 1)
1549 dev_db_start_offset += (ha->hw.flt_ddb_size / 2);
1550
1551 dev_db_end_offset = dev_db_start_offset +
1552 (ha->hw.flt_ddb_size / 2);
1553 }
1554
1555 dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
1556
1557 if (dev_db_start_offset > dev_db_end_offset) {
1558 DEBUG2(ql4_printk(KERN_ERR, ha,
1559 "%s:Invalid DDB index %d", __func__,
1560 ddb_index));
1561 goto exit_fdb_failed;
1562 }
1563
1564 if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
1565 sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
1566 ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash failed\n",
1567 ha->host_no, __func__);
1568 goto exit_fdb_failed;
1569 }
1570
1571 if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
1572 status = QLA_SUCCESS;
1573
1574 exit_fdb_failed:
1575 return status;
1576 }
1577
1578 int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
1579 uint16_t idx)
1580 {
1581 int ret = 0;
1582 int rval = QLA_ERROR;
1583 uint32_t offset = 0, chap_size;
1584 struct ql4_chap_table *chap_table;
1585 dma_addr_t chap_dma;
1586
1587 chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
1588 if (chap_table == NULL)
1589 return -ENOMEM;
1590
1591 chap_size = sizeof(struct ql4_chap_table);
1592 memset(chap_table, 0, chap_size);
1593
1594 if (is_qla40XX(ha))
1595 offset = FLASH_CHAP_OFFSET | (idx * chap_size);
1596 else {
1597 offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
1598 /* flt_chap_size is CHAP table size for both ports
1599 * so divide it by 2 to calculate the offset for second port
1600 */
1601 if (ha->port_num == 1)
1602 offset += (ha->hw.flt_chap_size / 2);
1603 offset += (idx * chap_size);
1604 }
1605
1606 rval = qla4xxx_get_flash(ha, chap_dma, offset, chap_size);
1607 if (rval != QLA_SUCCESS) {
1608 ret = -EINVAL;
1609 goto exit_get_chap;
1610 }
1611
1612 DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
1613 __le16_to_cpu(chap_table->cookie)));
1614
1615 if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
1616 ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
1617 goto exit_get_chap;
1618 }
1619
1620 strlcpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
1621 strlcpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN);
1622 chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
1623
1624 exit_get_chap:
1625 dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
1626 return ret;
1627 }
1628
1629 /**
1630 * qla4xxx_set_chap - Make a chap entry at the given index
1631 * @ha: pointer to adapter structure
1632 * @username: CHAP username to set
1633 * @password: CHAP password to set
1634 * @idx: CHAP index at which to make the entry
1635 * @bidi: type of chap entry (chap_in or chap_out)
1636 *
1637 * Create chap entry at the given index with the information provided.
1638 *
1639 * Note: Caller should acquire the chap lock before getting here.
1640 **/
1641 int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username, char *password,
1642 uint16_t idx, int bidi)
1643 {
1644 int ret = 0;
1645 int rval = QLA_ERROR;
1646 uint32_t offset = 0;
1647 struct ql4_chap_table *chap_table;
1648 uint32_t chap_size = 0;
1649 dma_addr_t chap_dma;
1650
1651 chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
1652 if (chap_table == NULL) {
1653 ret = -ENOMEM;
1654 goto exit_set_chap;
1655 }
1656
1657 memset(chap_table, 0, sizeof(struct ql4_chap_table));
1658 if (bidi)
1659 chap_table->flags |= BIT_6; /* peer */
1660 else
1661 chap_table->flags |= BIT_7; /* local */
1662 chap_table->secret_len = strlen(password);
1663 strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN - 1);
1664 strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN - 1);
1665 chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
1666
1667 if (is_qla40XX(ha)) {
1668 chap_size = MAX_CHAP_ENTRIES_40XX * sizeof(*chap_table);
1669 offset = FLASH_CHAP_OFFSET;
1670 } else { /* Single region contains CHAP info for both ports which is
1671 * divided into half for each port.
1672 */
1673 chap_size = ha->hw.flt_chap_size / 2;
1674 offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
1675 if (ha->port_num == 1)
1676 offset += chap_size;
1677 }
1678
1679 offset += (idx * sizeof(struct ql4_chap_table));
1680 rval = qla4xxx_set_flash(ha, chap_dma, offset,
1681 sizeof(struct ql4_chap_table),
1682 FLASH_OPT_RMW_COMMIT);
1683
1684 if (rval == QLA_SUCCESS && ha->chap_list) {
1685 /* Update ha chap_list cache */
1686 memcpy((struct ql4_chap_table *)ha->chap_list + idx,
1687 chap_table, sizeof(struct ql4_chap_table));
1688 }
1689 dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
1690 if (rval != QLA_SUCCESS)
1691 ret = -EINVAL;
1692
1693 exit_set_chap:
1694 return ret;
1695 }
1696
1697
1698 int qla4xxx_get_uni_chap_at_index(struct scsi_qla_host *ha, char *username,
1699 char *password, uint16_t chap_index)
1700 {
1701 int rval = QLA_ERROR;
1702 struct ql4_chap_table *chap_table = NULL;
1703 int max_chap_entries;
1704
1705 if (!ha->chap_list) {
1706 ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
1707 rval = QLA_ERROR;
1708 goto exit_uni_chap;
1709 }
1710
1711 if (!username || !password) {
1712 ql4_printk(KERN_ERR, ha, "No memory for username & secret\n");
1713 rval = QLA_ERROR;
1714 goto exit_uni_chap;
1715 }
1716
1717 if (is_qla80XX(ha))
1718 max_chap_entries = (ha->hw.flt_chap_size / 2) /
1719 sizeof(struct ql4_chap_table);
1720 else
1721 max_chap_entries = MAX_CHAP_ENTRIES_40XX;
1722
1723 if (chap_index > max_chap_entries) {
1724 ql4_printk(KERN_ERR, ha, "Invalid Chap index\n");
1725 rval = QLA_ERROR;
1726 goto exit_uni_chap;
1727 }
1728
1729 mutex_lock(&ha->chap_sem);
1730 chap_table = (struct ql4_chap_table *)ha->chap_list + chap_index;
1731 if (chap_table->cookie != __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
1732 rval = QLA_ERROR;
1733 goto exit_unlock_uni_chap;
1734 }
1735
1736 if (!(chap_table->flags & BIT_7)) {
1737 ql4_printk(KERN_ERR, ha, "Unidirectional entry not set\n");
1738 rval = QLA_ERROR;
1739 goto exit_unlock_uni_chap;
1740 }
1741
1742 strlcpy(password, chap_table->secret, MAX_CHAP_SECRET_LEN);
1743 strlcpy(username, chap_table->name, MAX_CHAP_NAME_LEN);
1744
1745 rval = QLA_SUCCESS;
1746
1747 exit_unlock_uni_chap:
1748 mutex_unlock(&ha->chap_sem);
1749 exit_uni_chap:
1750 return rval;
1751 }
1752
1753 /**
1754 * qla4xxx_get_chap_index - Get chap index given username and secret
1755 * @ha: pointer to adapter structure
1756 * @username: CHAP username to be searched
1757 * @password: CHAP password to be searched
1758 * @bidi: Is this a BIDI CHAP
1759 * @chap_index: CHAP index to be returned
1760 *
1761 * Match the username and password in the chap_list, return the index if a
1762 * match is found. If a match is not found then add the entry in FLASH and
1763 * return the index at which entry is written in the FLASH.
1764 **/
1765 int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username,
1766 char *password, int bidi, uint16_t *chap_index)
1767 {
1768 int i, rval;
1769 int free_index = -1;
1770 int found_index = 0;
1771 int max_chap_entries = 0;
1772 struct ql4_chap_table *chap_table;
1773
1774 if (is_qla80XX(ha))
1775 max_chap_entries = (ha->hw.flt_chap_size / 2) /
1776 sizeof(struct ql4_chap_table);
1777 else
1778 max_chap_entries = MAX_CHAP_ENTRIES_40XX;
1779
1780 if (!ha->chap_list) {
1781 ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
1782 return QLA_ERROR;
1783 }
1784
1785 if (!username || !password) {
1786 ql4_printk(KERN_ERR, ha, "Do not have username and psw\n");
1787 return QLA_ERROR;
1788 }
1789
1790 mutex_lock(&ha->chap_sem);
1791 for (i = 0; i < max_chap_entries; i++) {
1792 chap_table = (struct ql4_chap_table *)ha->chap_list + i;
1793 if (chap_table->cookie !=
1794 __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
1795 if (i > MAX_RESRV_CHAP_IDX && free_index == -1)
1796 free_index = i;
1797 continue;
1798 }
1799 if (bidi) {
1800 if (chap_table->flags & BIT_7)
1801 continue;
1802 } else {
1803 if (chap_table->flags & BIT_6)
1804 continue;
1805 }
1806 if (!strncmp(chap_table->secret, password,
1807 MAX_CHAP_SECRET_LEN) &&
1808 !strncmp(chap_table->name, username,
1809 MAX_CHAP_NAME_LEN)) {
1810 *chap_index = i;
1811 found_index = 1;
1812 break;
1813 }
1814 }
1815
1816 /* If chap entry is not present and a free index is available then
1817 * write the entry in flash
1818 */
1819 if (!found_index && free_index != -1) {
1820 rval = qla4xxx_set_chap(ha, username, password,
1821 free_index, bidi);
1822 if (!rval) {
1823 *chap_index = free_index;
1824 found_index = 1;
1825 }
1826 }
1827
1828 mutex_unlock(&ha->chap_sem);
1829
1830 if (found_index)
1831 return QLA_SUCCESS;
1832 return QLA_ERROR;
1833 }
1834
1835 int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
1836 uint16_t fw_ddb_index,
1837 uint16_t connection_id,
1838 uint16_t option)
1839 {
1840 uint32_t mbox_cmd[MBOX_REG_COUNT];
1841 uint32_t mbox_sts[MBOX_REG_COUNT];
1842 int status = QLA_SUCCESS;
1843
1844 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1845 memset(&mbox_sts, 0, sizeof(mbox_sts));
1846
1847 mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
1848 mbox_cmd[1] = fw_ddb_index;
1849 mbox_cmd[2] = connection_id;
1850 mbox_cmd[3] = option;
1851
1852 status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
1853 if (status != QLA_SUCCESS) {
1854 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
1855 "option %04x failed w/ status %04X %04X\n",
1856 __func__, option, mbox_sts[0], mbox_sts[1]));
1857 }
1858 return status;
1859 }
1860
1861 /**
1862 * qla4_84xx_extend_idc_tmo - Extend IDC Timeout.
1863 * @ha: Pointer to host adapter structure.
1864 * @ext_tmo: idc timeout value
1865 *
1866 * Requests firmware to extend the idc timeout value.
1867 **/
1868 static int qla4_84xx_extend_idc_tmo(struct scsi_qla_host *ha, uint32_t ext_tmo)
1869 {
1870 uint32_t mbox_cmd[MBOX_REG_COUNT];
1871 uint32_t mbox_sts[MBOX_REG_COUNT];
1872 int status;
1873
1874 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1875 memset(&mbox_sts, 0, sizeof(mbox_sts));
1876 ext_tmo &= 0xf;
1877
1878 mbox_cmd[0] = MBOX_CMD_IDC_TIME_EXTEND;
1879 mbox_cmd[1] = ((ha->idc_info.request_desc & 0xfffff0ff) |
1880 (ext_tmo << 8)); /* new timeout */
1881 mbox_cmd[2] = ha->idc_info.info1;
1882 mbox_cmd[3] = ha->idc_info.info2;
1883 mbox_cmd[4] = ha->idc_info.info3;
1884
1885 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
1886 mbox_cmd, mbox_sts);
1887 if (status != QLA_SUCCESS) {
1888 DEBUG2(ql4_printk(KERN_INFO, ha,
1889 "scsi%ld: %s: failed status %04X\n",
1890 ha->host_no, __func__, mbox_sts[0]));
1891 return QLA_ERROR;
1892 } else {
1893 ql4_printk(KERN_INFO, ha, "%s: IDC timeout extended by %d secs\n",
1894 __func__, ext_tmo);
1895 }
1896
1897 return QLA_SUCCESS;
1898 }
1899
1900 int qla4xxx_disable_acb(struct scsi_qla_host *ha)
1901 {
1902 uint32_t mbox_cmd[MBOX_REG_COUNT];
1903 uint32_t mbox_sts[MBOX_REG_COUNT];
1904 int status = QLA_SUCCESS;
1905
1906 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1907 memset(&mbox_sts, 0, sizeof(mbox_sts));
1908
1909 mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
1910
1911 status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
1912 if (status != QLA_SUCCESS) {
1913 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
1914 "failed w/ status %04X %04X %04X", __func__,
1915 mbox_sts[0], mbox_sts[1], mbox_sts[2]));
1916 } else {
1917 if (is_qla8042(ha) &&
1918 test_bit(DPC_POST_IDC_ACK, &ha->dpc_flags) &&
1919 (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE)) {
1920 /*
1921 * Disable ACB mailbox command takes time to complete
1922 * based on the total number of targets connected.
1923 * For 512 targets, it took approximately 5 secs to
1924 * complete. Setting the timeout value to 8, with the 3
1925 * secs buffer.
1926 */
1927 qla4_84xx_extend_idc_tmo(ha, IDC_EXTEND_TOV);
1928 if (!wait_for_completion_timeout(&ha->disable_acb_comp,
1929 IDC_EXTEND_TOV * HZ)) {
1930 ql4_printk(KERN_WARNING, ha, "%s: Disable ACB Completion not received\n",
1931 __func__);
1932 }
1933 }
1934 }
1935 return status;
1936 }
1937
1938 int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
1939 uint32_t acb_type, uint32_t len)
1940 {
1941 uint32_t mbox_cmd[MBOX_REG_COUNT];
1942 uint32_t mbox_sts[MBOX_REG_COUNT];
1943 int status = QLA_SUCCESS;
1944
1945 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1946 memset(&mbox_sts, 0, sizeof(mbox_sts));
1947
1948 mbox_cmd[0] = MBOX_CMD_GET_ACB;
1949 mbox_cmd[1] = acb_type;
1950 mbox_cmd[2] = LSDW(acb_dma);
1951 mbox_cmd[3] = MSDW(acb_dma);
1952 mbox_cmd[4] = len;
1953
1954 status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
1955 if (status != QLA_SUCCESS) {
1956 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
1957 "failed w/ status %04X\n", __func__,
1958 mbox_sts[0]));
1959 }
1960 return status;
1961 }
1962
1963 int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
1964 uint32_t *mbox_sts, dma_addr_t acb_dma)
1965 {
1966 int status = QLA_SUCCESS;
1967
1968 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
1969 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
1970 mbox_cmd[0] = MBOX_CMD_SET_ACB;
1971 mbox_cmd[1] = 0; /* Primary ACB */
1972 mbox_cmd[2] = LSDW(acb_dma);
1973 mbox_cmd[3] = MSDW(acb_dma);
1974 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
1975
1976 status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
1977 if (status != QLA_SUCCESS) {
1978 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
1979 "failed w/ status %04X\n", __func__,
1980 mbox_sts[0]));
1981 }
1982 return status;
1983 }
1984
1985 int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
1986 struct ddb_entry *ddb_entry,
1987 struct iscsi_cls_conn *cls_conn,
1988 uint32_t *mbx_sts)
1989 {
1990 struct dev_db_entry *fw_ddb_entry;
1991 struct iscsi_conn *conn;
1992 struct iscsi_session *sess;
1993 struct qla_conn *qla_conn;
1994 struct sockaddr *dst_addr;
1995 dma_addr_t fw_ddb_entry_dma;
1996 int status = QLA_SUCCESS;
1997 int rval = 0;
1998 struct sockaddr_in *addr;
1999 struct sockaddr_in6 *addr6;
2000 char *ip;
2001 uint16_t iscsi_opts = 0;
2002 uint32_t options = 0;
2003 uint16_t idx, *ptid;
2004
2005 fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
2006 &fw_ddb_entry_dma, GFP_KERNEL);
2007 if (!fw_ddb_entry) {
2008 DEBUG2(ql4_printk(KERN_ERR, ha,
2009 "%s: Unable to allocate dma buffer.\n",
2010 __func__));
2011 rval = -ENOMEM;
2012 goto exit_set_param_no_free;
2013 }
2014
2015 conn = cls_conn->dd_data;
2016 qla_conn = conn->dd_data;
2017 sess = conn->session;
2018 dst_addr = (struct sockaddr *)&qla_conn->qla_ep->dst_addr;
2019
2020 if (dst_addr->sa_family == AF_INET6)
2021 options |= IPV6_DEFAULT_DDB_ENTRY;
2022
2023 status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
2024 if (status == QLA_ERROR) {
2025 rval = -EINVAL;
2026 goto exit_set_param;
2027 }
2028
2029 ptid = (uint16_t *)&fw_ddb_entry->isid[1];
2030 *ptid = cpu_to_le16((uint16_t)ddb_entry->sess->target_id);
2031
2032 DEBUG2(ql4_printk(KERN_INFO, ha, "ISID [%pmR]\n", fw_ddb_entry->isid));
2033
2034 iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
2035 memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
2036
2037 memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
2038
2039 if (sess->targetname != NULL) {
2040 memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
2041 min(strlen(sess->targetname),
2042 sizeof(fw_ddb_entry->iscsi_name)));
2043 }
2044
2045 memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
2046 memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
2047
2048 fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
2049
2050 if (dst_addr->sa_family == AF_INET) {
2051 addr = (struct sockaddr_in *)dst_addr;
2052 ip = (char *)&addr->sin_addr;
2053 memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
2054 fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
2055 DEBUG2(ql4_printk(KERN_INFO, ha,
2056 "%s: Destination Address [%pI4]: index [%d]\n",
2057 __func__, fw_ddb_entry->ip_addr,
2058 ddb_entry->fw_ddb_index));
2059 } else if (dst_addr->sa_family == AF_INET6) {
2060 addr6 = (struct sockaddr_in6 *)dst_addr;
2061 ip = (char *)&addr6->sin6_addr;
2062 memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
2063 fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
2064 fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
2065 DEBUG2(ql4_printk(KERN_INFO, ha,
2066 "%s: Destination Address [%pI6]: index [%d]\n",
2067 __func__, fw_ddb_entry->ip_addr,
2068 ddb_entry->fw_ddb_index));
2069 } else {
2070 ql4_printk(KERN_ERR, ha,
2071 "%s: Failed to get IP Address\n",
2072 __func__);
2073 rval = -EINVAL;
2074 goto exit_set_param;
2075 }
2076
2077 /* CHAP */
2078 if (sess->username != NULL && sess->password != NULL) {
2079 if (strlen(sess->username) && strlen(sess->password)) {
2080 iscsi_opts |= BIT_7;
2081
2082 rval = qla4xxx_get_chap_index(ha, sess->username,
2083 sess->password,
2084 LOCAL_CHAP, &idx);
2085 if (rval)
2086 goto exit_set_param;
2087
2088 fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
2089 }
2090 }
2091
2092 if (sess->username_in != NULL && sess->password_in != NULL) {
2093 /* Check if BIDI CHAP */
2094 if (strlen(sess->username_in) && strlen(sess->password_in)) {
2095 iscsi_opts |= BIT_4;
2096
2097 rval = qla4xxx_get_chap_index(ha, sess->username_in,
2098 sess->password_in,
2099 BIDI_CHAP, &idx);
2100 if (rval)
2101 goto exit_set_param;
2102 }
2103 }
2104
2105 if (sess->initial_r2t_en)
2106 iscsi_opts |= BIT_10;
2107
2108 if (sess->imm_data_en)
2109 iscsi_opts |= BIT_11;
2110
2111 fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
2112
2113 if (conn->max_recv_dlength)
2114 fw_ddb_entry->iscsi_max_rcv_data_seg_len =
2115 __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
2116
2117 if (sess->max_r2t)
2118 fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
2119
2120 if (sess->first_burst)
2121 fw_ddb_entry->iscsi_first_burst_len =
2122 __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
2123
2124 if (sess->max_burst)
2125 fw_ddb_entry->iscsi_max_burst_len =
2126 __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
2127
2128 if (sess->time2wait)
2129 fw_ddb_entry->iscsi_def_time2wait =
2130 cpu_to_le16(sess->time2wait);
2131
2132 if (sess->time2retain)
2133 fw_ddb_entry->iscsi_def_time2retain =
2134 cpu_to_le16(sess->time2retain);
2135
2136 status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
2137 fw_ddb_entry_dma, mbx_sts);
2138
2139 if (status != QLA_SUCCESS)
2140 rval = -EINVAL;
2141 exit_set_param:
2142 dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
2143 fw_ddb_entry, fw_ddb_entry_dma);
2144 exit_set_param_no_free:
2145 return rval;
2146 }
2147
2148 int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
2149 uint16_t stats_size, dma_addr_t stats_dma)
2150 {
2151 int status = QLA_SUCCESS;
2152 uint32_t mbox_cmd[MBOX_REG_COUNT];
2153 uint32_t mbox_sts[MBOX_REG_COUNT];
2154
2155 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
2156 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
2157 mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
2158 mbox_cmd[1] = fw_ddb_index;
2159 mbox_cmd[2] = LSDW(stats_dma);
2160 mbox_cmd[3] = MSDW(stats_dma);
2161 mbox_cmd[4] = stats_size;
2162
2163 status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
2164 if (status != QLA_SUCCESS) {
2165 DEBUG2(ql4_printk(KERN_WARNING, ha,
2166 "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
2167 "failed w/ status %04X\n", __func__,
2168 mbox_sts[0]));
2169 }
2170 return status;
2171 }
2172
2173 int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
2174 uint32_t ip_idx, uint32_t *sts)
2175 {
2176 uint32_t mbox_cmd[MBOX_REG_COUNT];
2177 uint32_t mbox_sts[MBOX_REG_COUNT];
2178 int status = QLA_SUCCESS;
2179
2180 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2181 memset(&mbox_sts, 0, sizeof(mbox_sts));
2182 mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
2183 mbox_cmd[1] = acb_idx;
2184 mbox_cmd[2] = ip_idx;
2185
2186 status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]);
2187 if (status != QLA_SUCCESS) {
2188 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
2189 "MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
2190 "status %04X\n", __func__, mbox_sts[0]));
2191 }
2192 memcpy(sts, mbox_sts, sizeof(mbox_sts));
2193 return status;
2194 }
2195
2196 int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
2197 uint32_t offset, uint32_t size)
2198 {
2199 int status = QLA_SUCCESS;
2200 uint32_t mbox_cmd[MBOX_REG_COUNT];
2201 uint32_t mbox_sts[MBOX_REG_COUNT];
2202
2203 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2204 memset(&mbox_sts, 0, sizeof(mbox_sts));
2205
2206 mbox_cmd[0] = MBOX_CMD_GET_NVRAM;
2207 mbox_cmd[1] = LSDW(nvram_dma);
2208 mbox_cmd[2] = MSDW(nvram_dma);
2209 mbox_cmd[3] = offset;
2210 mbox_cmd[4] = size;
2211
2212 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2213 &mbox_sts[0]);
2214 if (status != QLA_SUCCESS) {
2215 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
2216 "status %04X\n", ha->host_no, __func__,
2217 mbox_sts[0]));
2218 }
2219 return status;
2220 }
2221
2222 int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
2223 uint32_t offset, uint32_t size)
2224 {
2225 int status = QLA_SUCCESS;
2226 uint32_t mbox_cmd[MBOX_REG_COUNT];
2227 uint32_t mbox_sts[MBOX_REG_COUNT];
2228
2229 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2230 memset(&mbox_sts, 0, sizeof(mbox_sts));
2231
2232 mbox_cmd[0] = MBOX_CMD_SET_NVRAM;
2233 mbox_cmd[1] = LSDW(nvram_dma);
2234 mbox_cmd[2] = MSDW(nvram_dma);
2235 mbox_cmd[3] = offset;
2236 mbox_cmd[4] = size;
2237
2238 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2239 &mbox_sts[0]);
2240 if (status != QLA_SUCCESS) {
2241 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
2242 "status %04X\n", ha->host_no, __func__,
2243 mbox_sts[0]));
2244 }
2245 return status;
2246 }
2247
2248 int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha,
2249 uint32_t region, uint32_t field0,
2250 uint32_t field1)
2251 {
2252 int status = QLA_SUCCESS;
2253 uint32_t mbox_cmd[MBOX_REG_COUNT];
2254 uint32_t mbox_sts[MBOX_REG_COUNT];
2255
2256 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2257 memset(&mbox_sts, 0, sizeof(mbox_sts));
2258
2259 mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS;
2260 mbox_cmd[3] = region;
2261 mbox_cmd[4] = field0;
2262 mbox_cmd[5] = field1;
2263
2264 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0],
2265 &mbox_sts[0]);
2266 if (status != QLA_SUCCESS) {
2267 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
2268 "status %04X\n", ha->host_no, __func__,
2269 mbox_sts[0]));
2270 }
2271 return status;
2272 }
2273
2274 /**
2275 * qla4_8xxx_set_param - set driver version in firmware.
2276 * @ha: Pointer to host adapter structure.
2277 * @param: Parameter to set i.e driver version
2278 **/
2279 int qla4_8xxx_set_param(struct scsi_qla_host *ha, int param)
2280 {
2281 uint32_t mbox_cmd[MBOX_REG_COUNT];
2282 uint32_t mbox_sts[MBOX_REG_COUNT];
2283 uint32_t status;
2284
2285 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2286 memset(&mbox_sts, 0, sizeof(mbox_sts));
2287
2288 mbox_cmd[0] = MBOX_CMD_SET_PARAM;
2289 if (param == SET_DRVR_VERSION) {
2290 mbox_cmd[1] = SET_DRVR_VERSION;
2291 strncpy((char *)&mbox_cmd[2], QLA4XXX_DRIVER_VERSION,
2292 MAX_DRVR_VER_LEN - 1);
2293 } else {
2294 ql4_printk(KERN_ERR, ha, "%s: invalid parameter 0x%x\n",
2295 __func__, param);
2296 status = QLA_ERROR;
2297 goto exit_set_param;
2298 }
2299
2300 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, mbox_cmd,
2301 mbox_sts);
2302 if (status == QLA_ERROR)
2303 ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
2304 __func__, mbox_sts[0]);
2305
2306 exit_set_param:
2307 return status;
2308 }
2309
2310 /**
2311 * qla4_83xx_post_idc_ack - post IDC ACK
2312 * @ha: Pointer to host adapter structure.
2313 *
2314 * Posts IDC ACK for IDC Request Notification AEN.
2315 **/
2316 int qla4_83xx_post_idc_ack(struct scsi_qla_host *ha)
2317 {
2318 uint32_t mbox_cmd[MBOX_REG_COUNT];
2319 uint32_t mbox_sts[MBOX_REG_COUNT];
2320 int status;
2321
2322 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2323 memset(&mbox_sts, 0, sizeof(mbox_sts));
2324
2325 mbox_cmd[0] = MBOX_CMD_IDC_ACK;
2326 mbox_cmd[1] = ha->idc_info.request_desc;
2327 mbox_cmd[2] = ha->idc_info.info1;
2328 mbox_cmd[3] = ha->idc_info.info2;
2329 mbox_cmd[4] = ha->idc_info.info3;
2330
2331 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
2332 mbox_cmd, mbox_sts);
2333 if (status == QLA_ERROR)
2334 ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
2335 mbox_sts[0]);
2336 else
2337 ql4_printk(KERN_INFO, ha, "%s: IDC ACK posted\n", __func__);
2338
2339 return status;
2340 }
2341
2342 int qla4_84xx_config_acb(struct scsi_qla_host *ha, int acb_config)
2343 {
2344 uint32_t mbox_cmd[MBOX_REG_COUNT];
2345 uint32_t mbox_sts[MBOX_REG_COUNT];
2346 struct addr_ctrl_blk *acb = NULL;
2347 uint32_t acb_len = sizeof(struct addr_ctrl_blk);
2348 int rval = QLA_SUCCESS;
2349 dma_addr_t acb_dma;
2350
2351 acb = dma_alloc_coherent(&ha->pdev->dev,
2352 sizeof(struct addr_ctrl_blk),
2353 &acb_dma, GFP_KERNEL);
2354 if (!acb) {
2355 ql4_printk(KERN_ERR, ha, "%s: Unable to alloc acb\n", __func__);
2356 rval = QLA_ERROR;
2357 goto exit_config_acb;
2358 }
2359 memset(acb, 0, acb_len);
2360
2361 switch (acb_config) {
2362 case ACB_CONFIG_DISABLE:
2363 rval = qla4xxx_get_acb(ha, acb_dma, 0, acb_len);
2364 if (rval != QLA_SUCCESS)
2365 goto exit_free_acb;
2366
2367 rval = qla4xxx_disable_acb(ha);
2368 if (rval != QLA_SUCCESS)
2369 goto exit_free_acb;
2370
2371 if (!ha->saved_acb)
2372 ha->saved_acb = kzalloc(acb_len, GFP_KERNEL);
2373
2374 if (!ha->saved_acb) {
2375 ql4_printk(KERN_ERR, ha, "%s: Unable to alloc acb\n",
2376 __func__);
2377 rval = QLA_ERROR;
2378 goto exit_free_acb;
2379 }
2380 memcpy(ha->saved_acb, acb, acb_len);
2381 break;
2382 case ACB_CONFIG_SET:
2383
2384 if (!ha->saved_acb) {
2385 ql4_printk(KERN_ERR, ha, "%s: Can't set ACB, Saved ACB not available\n",
2386 __func__);
2387 rval = QLA_ERROR;
2388 goto exit_free_acb;
2389 }
2390
2391 memcpy(acb, ha->saved_acb, acb_len);
2392
2393 rval = qla4xxx_set_acb(ha, &mbox_cmd[0], &mbox_sts[0], acb_dma);
2394 if (rval != QLA_SUCCESS)
2395 goto exit_free_acb;
2396
2397 break;
2398 default:
2399 ql4_printk(KERN_ERR, ha, "%s: Invalid ACB Configuration\n",
2400 __func__);
2401 }
2402
2403 exit_free_acb:
2404 dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk), acb,
2405 acb_dma);
2406 exit_config_acb:
2407 if ((acb_config == ACB_CONFIG_SET) && ha->saved_acb) {
2408 kfree(ha->saved_acb);
2409 ha->saved_acb = NULL;
2410 }
2411 DEBUG2(ql4_printk(KERN_INFO, ha,
2412 "%s %s\n", __func__,
2413 rval == QLA_SUCCESS ? "SUCCEEDED" : "FAILED"));
2414 return rval;
2415 }
2416
2417 int qla4_83xx_get_port_config(struct scsi_qla_host *ha, uint32_t *config)
2418 {
2419 uint32_t mbox_cmd[MBOX_REG_COUNT];
2420 uint32_t mbox_sts[MBOX_REG_COUNT];
2421 int status;
2422
2423 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2424 memset(&mbox_sts, 0, sizeof(mbox_sts));
2425
2426 mbox_cmd[0] = MBOX_CMD_GET_PORT_CONFIG;
2427
2428 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
2429 mbox_cmd, mbox_sts);
2430 if (status == QLA_SUCCESS)
2431 *config = mbox_sts[1];
2432 else
2433 ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
2434 mbox_sts[0]);
2435
2436 return status;
2437 }
2438
2439 int qla4_83xx_set_port_config(struct scsi_qla_host *ha, uint32_t *config)
2440 {
2441 uint32_t mbox_cmd[MBOX_REG_COUNT];
2442 uint32_t mbox_sts[MBOX_REG_COUNT];
2443 int status;
2444
2445 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2446 memset(&mbox_sts, 0, sizeof(mbox_sts));
2447
2448 mbox_cmd[0] = MBOX_CMD_SET_PORT_CONFIG;
2449 mbox_cmd[1] = *config;
2450
2451 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
2452 mbox_cmd, mbox_sts);
2453 if (status != QLA_SUCCESS)
2454 ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
2455 mbox_sts[0]);
2456
2457 return status;
2458 }
Linux with added FPC-III support