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Linux 4.16.11
[linux/fpc-iii.git] / drivers / staging / rtlwifi / wifi.h
blobca0243fa2e664da19f776ef09b2698c2a16d94af
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #ifndef __RTL_WIFI_H__
27 #define __RTL_WIFI_H__
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sched.h>
32 #include <linux/firmware.h>
33 #include <linux/etherdevice.h>
34 #include <linux/vmalloc.h>
35 #include <linux/usb.h>
36 #include <net/mac80211.h>
37 #include <linux/completion.h>
38 #include "debug.h"
39
40 #define MASKBYTE0 0xff
41 #define MASKBYTE1 0xff00
42 #define MASKBYTE2 0xff0000
43 #define MASKBYTE3 0xff000000
44 #define MASKHWORD 0xffff0000
45 #define MASKLWORD 0x0000ffff
46 #define MASKDWORD 0xffffffff
47 #define MASK12BITS 0xfff
48 #define MASKH4BITS 0xf0000000
49 #define MASKOFDM_D 0xffc00000
50 #define MASKCCK 0x3f3f3f3f
51
52 #define MASK4BITS 0x0f
53 #define MASK20BITS 0xfffff
54 #define RFREG_OFFSET_MASK 0xfffff
55
56 #define MASKBYTE0 0xff
57 #define MASKBYTE1 0xff00
58 #define MASKBYTE2 0xff0000
59 #define MASKBYTE3 0xff000000
60 #define MASKHWORD 0xffff0000
61 #define MASKLWORD 0x0000ffff
62 #define MASKDWORD 0xffffffff
63 #define MASK12BITS 0xfff
64 #define MASKH4BITS 0xf0000000
65 #define MASKOFDM_D 0xffc00000
66 #define MASKCCK 0x3f3f3f3f
67
68 #define MASK4BITS 0x0f
69 #define MASK20BITS 0xfffff
70 #define RFREG_OFFSET_MASK 0xfffff
71
72 #define RF_CHANGE_BY_INIT 0
73 #define RF_CHANGE_BY_IPS BIT(28)
74 #define RF_CHANGE_BY_PS BIT(29)
75 #define RF_CHANGE_BY_HW BIT(30)
76 #define RF_CHANGE_BY_SW BIT(31)
77
78 #define IQK_ADDA_REG_NUM 16
79 #define IQK_MAC_REG_NUM 4
80 #define IQK_THRESHOLD 8
81
82 #define MAX_KEY_LEN 61
83 #define KEY_BUF_SIZE 5
84
85 /* QoS related. */
86 /*aci: 0x00 Best Effort*/
87 /*aci: 0x01 Background*/
88 /*aci: 0x10 Video*/
89 /*aci: 0x11 Voice*/
90 /*Max: define total number.*/
91 #define AC0_BE 0
92 #define AC1_BK 1
93 #define AC2_VI 2
94 #define AC3_VO 3
95 #define AC_MAX 4
96 #define QOS_QUEUE_NUM 4
97 #define RTL_MAC80211_NUM_QUEUE 5
98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
99 #define RTL_USB_MAX_RX_COUNT 100
100 #define QBSS_LOAD_SIZE 5
101 #define MAX_WMMELE_LENGTH 64
102
103 #define TOTAL_CAM_ENTRY 32
104
105 /*slot time for 11g. */
106 #define RTL_SLOT_TIME_9 9
107 #define RTL_SLOT_TIME_20 20
108
109 /*related to tcp/ip. */
110 #define SNAP_SIZE 6
111 #define PROTOC_TYPE_SIZE 2
112
113 /*related with 802.11 frame*/
114 #define MAC80211_3ADDR_LEN 24
115 #define MAC80211_4ADDR_LEN 30
116
117 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
118 #define CHANNEL_MAX_NUMBER_2G 14
119 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to
120 *"phy_GetChnlGroup8812A" and
121 * "Hal_ReadTxPowerInfo8812A"
122 */
123 #define CHANNEL_MAX_NUMBER_5G_80M 7
124 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
125 #define MAX_PG_GROUP 13
126 #define CHANNEL_GROUP_MAX_2G 3
127 #define CHANNEL_GROUP_IDX_5GL 3
128 #define CHANNEL_GROUP_IDX_5GM 6
129 #define CHANNEL_GROUP_IDX_5GH 9
130 #define CHANNEL_GROUP_MAX_5G 9
131 #define CHANNEL_MAX_NUMBER_2G 14
132 #define AVG_THERMAL_NUM 8
133 #define AVG_THERMAL_NUM_88E 4
134 #define AVG_THERMAL_NUM_8723BE 4
135 #define MAX_TID_COUNT 9
136
137 /* for early mode */
138 #define FCS_LEN 4
139 #define EM_HDR_LEN 8
140
141 enum rtl8192c_h2c_cmd {
142 H2C_AP_OFFLOAD = 0,
143 H2C_SETPWRMODE = 1,
144 H2C_JOINBSSRPT = 2,
145 H2C_RSVDPAGE = 3,
146 H2C_RSSI_REPORT = 5,
147 H2C_RA_MASK = 6,
148 H2C_MACID_PS_MODE = 7,
149 H2C_P2P_PS_OFFLOAD = 8,
150 H2C_MAC_MODE_SEL = 9,
151 H2C_PWRM = 15,
152 H2C_P2P_PS_CTW_CMD = 24,
153 MAX_H2CCMD
154 };
155
156 #define MAX_TX_COUNT 4
157 #define MAX_REGULATION_NUM 4
158 #define MAX_RF_PATH_NUM 4
159 #define MAX_RATE_SECTION_NUM 6 /* = MAX_RATE_SECTION */
160 #define MAX_2_4G_BANDWIDTH_NUM 4
161 #define MAX_5G_BANDWIDTH_NUM 4
162 #define MAX_RF_PATH 4
163 #define MAX_CHNL_GROUP_24G 6
164 #define MAX_CHNL_GROUP_5G 14
165
166 #define TX_PWR_BY_RATE_NUM_BAND 2
167 #define TX_PWR_BY_RATE_NUM_RF 4
168 #define TX_PWR_BY_RATE_NUM_SECTION 12
169 /* compatible with TX_PWR_BY_RATE_NUM_SECTION */
170 #define TX_PWR_BY_RATE_NUM_RATE 84
171 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 /* MAX_RATE_SECTION */
172 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 /* MAX_RATE_SECTION -1 */
173
174 #define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
175
176 #define DEL_SW_IDX_SZ 30
177
178 /* For now, it's just for 8192ee
179 * but not OK yet, keep it 0
180 */
181 #define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM
182 #define RTL8822BE_SEG_NUM BUFDESC_SEG_NUM
183
184 enum rf_tx_num {
185 RF_1TX = 0,
186 RF_2TX,
187 RF_MAX_TX_NUM,
188 RF_TX_NUM_NONIMPLEMENT,
189 };
190
191 #define PACKET_NORMAL 0
192 #define PACKET_DHCP 1
193 #define PACKET_ARP 2
194 #define PACKET_EAPOL 3
195
196 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
197 #define RSVD_WOL_PATTERN_NUM 1
198 #define WKFMCAM_ADDR_NUM 6
199 #define WKFMCAM_SIZE 24
200
201 #define MAX_WOL_BIT_MASK_SIZE 16
202 /* MIN LEN keeps 13 here */
203 #define MIN_WOL_PATTERN_SIZE 13
204 #define MAX_WOL_PATTERN_SIZE 128
205
206 #define WAKE_ON_MAGIC_PACKET BIT(0)
207 #define WAKE_ON_PATTERN_MATCH BIT(1)
208
209 #define WOL_REASON_PTK_UPDATE BIT(0)
210 #define WOL_REASON_GTK_UPDATE BIT(1)
211 #define WOL_REASON_DISASSOC BIT(2)
212 #define WOL_REASON_DEAUTH BIT(3)
213 #define WOL_REASON_AP_LOST BIT(4)
214 #define WOL_REASON_MAGIC_PKT BIT(5)
215 #define WOL_REASON_UNICAST_PKT BIT(6)
216 #define WOL_REASON_PATTERN_PKT BIT(7)
217 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
218 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
219 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
220
221 struct rtlwifi_firmware_header {
222 __le16 signature;
223 u8 category;
224 u8 function;
225 __le16 version;
226 u8 subversion;
227 u8 rsvd1;
228 u8 month;
229 u8 date;
230 u8 hour;
231 u8 minute;
232 __le16 ramcodesize;
233 __le16 rsvd2;
234 __le32 svnindex;
235 __le32 rsvd3;
236 __le32 rsvd4;
237 __le32 rsvd5;
238 };
239
240 struct txpower_info_2g {
241 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
242 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
243 /*If only one tx, only BW20 and OFDM are used.*/
244 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
245 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
246 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
247 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
248 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
249 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
250 };
251
252 struct txpower_info_5g {
253 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
254 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
255 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
256 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
257 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
258 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
259 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
260 };
261
262 enum rate_section {
263 CCK = 0,
264 OFDM,
265 HT_MCS0_MCS7,
266 HT_MCS8_MCS15,
267 VHT_1SSMCS0_1SSMCS9,
268 VHT_2SSMCS0_2SSMCS9,
269 MAX_RATE_SECTION,
270 };
271
272 enum intf_type {
273 INTF_PCI = 0,
274 INTF_USB = 1,
275 };
276
277 enum radio_path {
278 RF90_PATH_A = 0,
279 RF90_PATH_B = 1,
280 RF90_PATH_C = 2,
281 RF90_PATH_D = 3,
282 };
283
284 enum radio_mask {
285 RF_MASK_A = BIT(0),
286 RF_MASK_B = BIT(1),
287 RF_MASK_C = BIT(2),
288 RF_MASK_D = BIT(3),
289 };
290
291 enum regulation_txpwr_lmt {
292 TXPWR_LMT_FCC = 0,
293 TXPWR_LMT_MKK = 1,
294 TXPWR_LMT_ETSI = 2,
295 TXPWR_LMT_WW = 3,
296
297 TXPWR_LMT_MAX_REGULATION_NUM = 4
298 };
299
300 enum rt_eeprom_type {
301 EEPROM_93C46,
302 EEPROM_93C56,
303 EEPROM_BOOT_EFUSE,
304 };
305
306 enum ttl_status {
307 RTL_STATUS_INTERFACE_START = 0,
308 };
309
310 enum hardware_type {
311 HARDWARE_TYPE_RTL8192E,
312 HARDWARE_TYPE_RTL8192U,
313 HARDWARE_TYPE_RTL8192SE,
314 HARDWARE_TYPE_RTL8192SU,
315 HARDWARE_TYPE_RTL8192CE,
316 HARDWARE_TYPE_RTL8192CU,
317 HARDWARE_TYPE_RTL8192DE,
318 HARDWARE_TYPE_RTL8192DU,
319 HARDWARE_TYPE_RTL8723AE,
320 HARDWARE_TYPE_RTL8723U,
321 HARDWARE_TYPE_RTL8188EE,
322 HARDWARE_TYPE_RTL8723BE,
323 HARDWARE_TYPE_RTL8192EE,
324 HARDWARE_TYPE_RTL8821AE,
325 HARDWARE_TYPE_RTL8812AE,
326 HARDWARE_TYPE_RTL8822BE,
327
328 /* keep it last */
329 HARDWARE_TYPE_NUM
330 };
331
332 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type)
333 #define IS_NEW_GENERATION_IC(rtlpriv) \
334 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE)
335 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \
336 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE)
337 #define IS_HARDWARE_TYPE_8812(rtlpriv) \
338 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE)
339 #define IS_HARDWARE_TYPE_8821(rtlpriv) \
340 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE)
341 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \
342 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE)
343 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \
344 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE)
345 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \
346 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE)
347 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \
348 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE)
349
350 #define RX_HAL_IS_CCK_RATE(rxmcs) \
351 ((rxmcs) == DESC_RATE1M || \
352 (rxmcs) == DESC_RATE2M || \
353 (rxmcs) == DESC_RATE5_5M || \
354 (rxmcs) == DESC_RATE11M)
355
356 enum scan_operation_backup_opt {
357 SCAN_OPT_BACKUP = 0,
358 SCAN_OPT_BACKUP_BAND0 = 0,
359 SCAN_OPT_BACKUP_BAND1,
360 SCAN_OPT_RESTORE,
361 SCAN_OPT_MAX
362 };
363
364 /*RF state.*/
365 enum rf_pwrstate {
366 ERFON,
367 ERFSLEEP,
368 ERFOFF
369 };
370
371 struct bb_reg_def {
372 u32 rfintfs;
373 u32 rfintfi;
374 u32 rfintfo;
375 u32 rfintfe;
376 u32 rf3wire_offset;
377 u32 rflssi_select;
378 u32 rftxgain_stage;
379 u32 rfhssi_para1;
380 u32 rfhssi_para2;
381 u32 rfsw_ctrl;
382 u32 rfagc_control1;
383 u32 rfagc_control2;
384 u32 rfrxiq_imbal;
385 u32 rfrx_afe;
386 u32 rftxiq_imbal;
387 u32 rftx_afe;
388 u32 rf_rb; /* rflssi_readback */
389 u32 rf_rbpi; /* rflssi_readbackpi */
390 };
391
392 enum io_type {
393 IO_CMD_PAUSE_DM_BY_SCAN = 0,
394 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
395 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
396 IO_CMD_RESUME_DM_BY_SCAN = 2,
397 };
398
399 enum hw_variables {
400 HW_VAR_ETHER_ADDR = 0x0,
401 HW_VAR_MULTICAST_REG = 0x1,
402 HW_VAR_BASIC_RATE = 0x2,
403 HW_VAR_BSSID = 0x3,
404 HW_VAR_MEDIA_STATUS = 0x4,
405 HW_VAR_SECURITY_CONF = 0x5,
406 HW_VAR_BEACON_INTERVAL = 0x6,
407 HW_VAR_ATIM_WINDOW = 0x7,
408 HW_VAR_LISTEN_INTERVAL = 0x8,
409 HW_VAR_CS_COUNTER = 0x9,
410 HW_VAR_DEFAULTKEY0 = 0xa,
411 HW_VAR_DEFAULTKEY1 = 0xb,
412 HW_VAR_DEFAULTKEY2 = 0xc,
413 HW_VAR_DEFAULTKEY3 = 0xd,
414 HW_VAR_SIFS = 0xe,
415 HW_VAR_R2T_SIFS = 0xf,
416 HW_VAR_DIFS = 0x10,
417 HW_VAR_EIFS = 0x11,
418 HW_VAR_SLOT_TIME = 0x12,
419 HW_VAR_ACK_PREAMBLE = 0x13,
420 HW_VAR_CW_CONFIG = 0x14,
421 HW_VAR_CW_VALUES = 0x15,
422 HW_VAR_RATE_FALLBACK_CONTROL = 0x16,
423 HW_VAR_CONTENTION_WINDOW = 0x17,
424 HW_VAR_RETRY_COUNT = 0x18,
425 HW_VAR_TR_SWITCH = 0x19,
426 HW_VAR_COMMAND = 0x1a,
427 HW_VAR_WPA_CONFIG = 0x1b,
428 HW_VAR_AMPDU_MIN_SPACE = 0x1c,
429 HW_VAR_SHORTGI_DENSITY = 0x1d,
430 HW_VAR_AMPDU_FACTOR = 0x1e,
431 HW_VAR_MCS_RATE_AVAILABLE = 0x1f,
432 HW_VAR_AC_PARAM = 0x20,
433 HW_VAR_ACM_CTRL = 0x21,
434 HW_VAR_DIS_REQ_QSIZE = 0x22,
435 HW_VAR_CCX_CHNL_LOAD = 0x23,
436 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24,
437 HW_VAR_CCX_CLM_NHM = 0x25,
438 HW_VAR_TXOPLIMIT = 0x26,
439 HW_VAR_TURBO_MODE = 0x27,
440 HW_VAR_RF_STATE = 0x28,
441 HW_VAR_RF_OFF_BY_HW = 0x29,
442 HW_VAR_BUS_SPEED = 0x2a,
443 HW_VAR_SET_DEV_POWER = 0x2b,
444
445 HW_VAR_RCR = 0x2c,
446 HW_VAR_RATR_0 = 0x2d,
447 HW_VAR_RRSR = 0x2e,
448 HW_VAR_CPU_RST = 0x2f,
449 HW_VAR_CHECK_BSSID = 0x30,
450 HW_VAR_LBK_MODE = 0x31,
451 HW_VAR_AES_11N_FIX = 0x32,
452 HW_VAR_USB_RX_AGGR = 0x33,
453 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34,
454 HW_VAR_RETRY_LIMIT = 0x35,
455 HW_VAR_INIT_TX_RATE = 0x36,
456 HW_VAR_TX_RATE_REG = 0x37,
457 HW_VAR_EFUSE_USAGE = 0x38,
458 HW_VAR_EFUSE_BYTES = 0x39,
459 HW_VAR_AUTOLOAD_STATUS = 0x3a,
460 HW_VAR_RF_2R_DISABLE = 0x3b,
461 HW_VAR_SET_RPWM = 0x3c,
462 HW_VAR_H2C_FW_PWRMODE = 0x3d,
463 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e,
464 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f,
465 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40,
466 HW_VAR_FW_PSMODE_STATUS = 0x41,
467 HW_VAR_INIT_RTS_RATE = 0x42,
468 HW_VAR_RESUME_CLK_ON = 0x43,
469 HW_VAR_FW_LPS_ACTION = 0x44,
470 HW_VAR_1X1_RECV_COMBINE = 0x45,
471 HW_VAR_STOP_SEND_BEACON = 0x46,
472 HW_VAR_TSF_TIMER = 0x47,
473 HW_VAR_IO_CMD = 0x48,
474
475 HW_VAR_RF_RECOVERY = 0x49,
476 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a,
477 HW_VAR_WF_MASK = 0x4b,
478 HW_VAR_WF_CRC = 0x4c,
479 HW_VAR_WF_IS_MAC_ADDR = 0x4d,
480 HW_VAR_H2C_FW_OFFLOAD = 0x4e,
481 HW_VAR_RESET_WFCRC = 0x4f,
482
483 HW_VAR_HANDLE_FW_C2H = 0x50,
484 HW_VAR_DL_FW_RSVD_PAGE = 0x51,
485 HW_VAR_AID = 0x52,
486 HW_VAR_HW_SEQ_ENABLE = 0x53,
487 HW_VAR_CORRECT_TSF = 0x54,
488 HW_VAR_BCN_VALID = 0x55,
489 HW_VAR_FWLPS_RF_ON = 0x56,
490 HW_VAR_DUAL_TSF_RST = 0x57,
491 HW_VAR_SWITCH_EPHY_WOWLAN = 0x58,
492 HW_VAR_INT_MIGRATION = 0x59,
493 HW_VAR_INT_AC = 0x5a,
494 HW_VAR_RF_TIMING = 0x5b,
495
496 HAL_DEF_WOWLAN = 0x5c,
497 HW_VAR_MRC = 0x5d,
498 HW_VAR_KEEP_ALIVE = 0x5e,
499 HW_VAR_NAV_UPPER = 0x5f,
500
501 HW_VAR_MGT_FILTER = 0x60,
502 HW_VAR_CTRL_FILTER = 0x61,
503 HW_VAR_DATA_FILTER = 0x62,
504 };
505
506 enum rt_media_status {
507 RT_MEDIA_DISCONNECT = 0,
508 RT_MEDIA_CONNECT = 1
509 };
510
511 enum rt_oem_id {
512 RT_CID_DEFAULT = 0,
513 RT_CID_8187_ALPHA0 = 1,
514 RT_CID_8187_SERCOMM_PS = 2,
515 RT_CID_8187_HW_LED = 3,
516 RT_CID_8187_NETGEAR = 4,
517 RT_CID_WHQL = 5,
518 RT_CID_819X_CAMEO = 6,
519 RT_CID_819X_RUNTOP = 7,
520 RT_CID_819X_SENAO = 8,
521 RT_CID_TOSHIBA = 9,
522 RT_CID_819X_NETCORE = 10,
523 RT_CID_NETTRONIX = 11,
524 RT_CID_DLINK = 12,
525 RT_CID_PRONET = 13,
526 RT_CID_COREGA = 14,
527 RT_CID_819X_ALPHA = 15,
528 RT_CID_819X_SITECOM = 16,
529 RT_CID_CCX = 17,
530 RT_CID_819X_LENOVO = 18,
531 RT_CID_819X_QMI = 19,
532 RT_CID_819X_EDIMAX_BELKIN = 20,
533 RT_CID_819X_SERCOMM_BELKIN = 21,
534 RT_CID_819X_CAMEO1 = 22,
535 RT_CID_819X_MSI = 23,
536 RT_CID_819X_ACER = 24,
537 RT_CID_819X_HP = 27,
538 RT_CID_819X_CLEVO = 28,
539 RT_CID_819X_ARCADYAN_BELKIN = 29,
540 RT_CID_819X_SAMSUNG = 30,
541 RT_CID_819X_WNC_COREGA = 31,
542 RT_CID_819X_FOXCOON = 32,
543 RT_CID_819X_DELL = 33,
544 RT_CID_819X_PRONETS = 34,
545 RT_CID_819X_EDIMAX_ASUS = 35,
546 RT_CID_NETGEAR = 36,
547 RT_CID_PLANEX = 37,
548 RT_CID_CC_C = 38,
549 };
550
551 enum hw_descs {
552 HW_DESC_OWN,
553 HW_DESC_RXOWN,
554 HW_DESC_TX_NEXTDESC_ADDR,
555 HW_DESC_TXBUFF_ADDR,
556 HW_DESC_RXBUFF_ADDR,
557 HW_DESC_RXPKT_LEN,
558 HW_DESC_RXERO,
559 HW_DESC_RX_PREPARE,
560 };
561
562 enum prime_sc {
563 PRIME_CHNL_OFFSET_DONT_CARE = 0,
564 PRIME_CHNL_OFFSET_LOWER = 1,
565 PRIME_CHNL_OFFSET_UPPER = 2,
566 };
567
568 enum rf_type {
569 RF_1T1R = 0,
570 RF_1T2R = 1,
571 RF_2T2R = 2,
572 RF_2T2R_GREEN = 3,
573 RF_2T3R = 4,
574 RF_2T4R = 5,
575 RF_3T3R = 6,
576 RF_3T4R = 7,
577 RF_4T4R = 8,
578 };
579
580 enum ht_channel_width {
581 HT_CHANNEL_WIDTH_20 = 0,
582 HT_CHANNEL_WIDTH_20_40 = 1,
583 HT_CHANNEL_WIDTH_80 = 2,
584 HT_CHANNEL_WIDTH_MAX,
585 };
586
587 /* Ref: 802.11i spec D10.0 7.3.2.25.1
588 * Cipher Suites Encryption Algorithms
589 */
590 enum rt_enc_alg {
591 NO_ENCRYPTION = 0,
592 WEP40_ENCRYPTION = 1,
593 TKIP_ENCRYPTION = 2,
594 RSERVED_ENCRYPTION = 3,
595 AESCCMP_ENCRYPTION = 4,
596 WEP104_ENCRYPTION = 5,
597 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
598 };
599
600 enum rtl_hal_state {
601 _HAL_STATE_STOP = 0,
602 _HAL_STATE_START = 1,
603 };
604
605 enum rtl_desc_rate {
606 DESC_RATE1M = 0x00,
607 DESC_RATE2M = 0x01,
608 DESC_RATE5_5M = 0x02,
609 DESC_RATE11M = 0x03,
610
611 DESC_RATE6M = 0x04,
612 DESC_RATE9M = 0x05,
613 DESC_RATE12M = 0x06,
614 DESC_RATE18M = 0x07,
615 DESC_RATE24M = 0x08,
616 DESC_RATE36M = 0x09,
617 DESC_RATE48M = 0x0a,
618 DESC_RATE54M = 0x0b,
619
620 DESC_RATEMCS0 = 0x0c,
621 DESC_RATEMCS1 = 0x0d,
622 DESC_RATEMCS2 = 0x0e,
623 DESC_RATEMCS3 = 0x0f,
624 DESC_RATEMCS4 = 0x10,
625 DESC_RATEMCS5 = 0x11,
626 DESC_RATEMCS6 = 0x12,
627 DESC_RATEMCS7 = 0x13,
628 DESC_RATEMCS8 = 0x14,
629 DESC_RATEMCS9 = 0x15,
630 DESC_RATEMCS10 = 0x16,
631 DESC_RATEMCS11 = 0x17,
632 DESC_RATEMCS12 = 0x18,
633 DESC_RATEMCS13 = 0x19,
634 DESC_RATEMCS14 = 0x1a,
635 DESC_RATEMCS15 = 0x1b,
636 DESC_RATEMCS15_SG = 0x1c,
637 DESC_RATEMCS32 = 0x20,
638
639 DESC_RATEVHT1SS_MCS0 = 0x2c,
640 DESC_RATEVHT1SS_MCS1 = 0x2d,
641 DESC_RATEVHT1SS_MCS2 = 0x2e,
642 DESC_RATEVHT1SS_MCS3 = 0x2f,
643 DESC_RATEVHT1SS_MCS4 = 0x30,
644 DESC_RATEVHT1SS_MCS5 = 0x31,
645 DESC_RATEVHT1SS_MCS6 = 0x32,
646 DESC_RATEVHT1SS_MCS7 = 0x33,
647 DESC_RATEVHT1SS_MCS8 = 0x34,
648 DESC_RATEVHT1SS_MCS9 = 0x35,
649 DESC_RATEVHT2SS_MCS0 = 0x36,
650 DESC_RATEVHT2SS_MCS1 = 0x37,
651 DESC_RATEVHT2SS_MCS2 = 0x38,
652 DESC_RATEVHT2SS_MCS3 = 0x39,
653 DESC_RATEVHT2SS_MCS4 = 0x3a,
654 DESC_RATEVHT2SS_MCS5 = 0x3b,
655 DESC_RATEVHT2SS_MCS6 = 0x3c,
656 DESC_RATEVHT2SS_MCS7 = 0x3d,
657 DESC_RATEVHT2SS_MCS8 = 0x3e,
658 DESC_RATEVHT2SS_MCS9 = 0x3f,
659 };
660
661 enum rtl_var_map {
662 /*reg map */
663 SYS_ISO_CTRL = 0,
664 SYS_FUNC_EN,
665 SYS_CLK,
666 MAC_RCR_AM,
667 MAC_RCR_AB,
668 MAC_RCR_ACRC32,
669 MAC_RCR_ACF,
670 MAC_RCR_AAP,
671 MAC_HIMR,
672 MAC_HIMRE,
673 MAC_HSISR,
674
675 /*efuse map */
676 EFUSE_TEST,
677 EFUSE_CTRL,
678 EFUSE_CLK,
679 EFUSE_CLK_CTRL,
680 EFUSE_PWC_EV12V,
681 EFUSE_FEN_ELDR,
682 EFUSE_LOADER_CLK_EN,
683 EFUSE_ANA8M,
684 EFUSE_HWSET_MAX_SIZE,
685 EFUSE_MAX_SECTION_MAP,
686 EFUSE_REAL_CONTENT_SIZE,
687 EFUSE_OOB_PROTECT_BYTES_LEN,
688 EFUSE_ACCESS,
689
690 /*CAM map */
691 RWCAM,
692 WCAMI,
693 RCAMO,
694 CAMDBG,
695 SECR,
696 SEC_CAM_NONE,
697 SEC_CAM_WEP40,
698 SEC_CAM_TKIP,
699 SEC_CAM_AES,
700 SEC_CAM_WEP104,
701
702 /*IMR map */
703 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
704 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
705 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
706 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
707 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
708 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
709 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrupt 8 */
710 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrupt 7 */
711 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrupt 6 */
712 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrupt 5 */
713 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrupt 4 */
714 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrupt 3 */
715 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrupt 2 */
716 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrupt 1 */
717 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
718 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
719 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
720 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
721 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
722 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
723 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
724 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
725 RTL_IMR_H2CDOK, /*H2C Queue DMA OK Interrupt */
726 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrupt */
727 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
728 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
729 RTL_IMR_TBDOK, /*Transmit Beacon OK interrupt */
730 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
731 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
732 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
733 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
734 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
735 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
736 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
737 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
738 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
739 * RTL_IMR_TBDER)
740 */
741 RTL_IMR_C2HCMD, /*fw interrupt*/
742
743 /*CCK Rates, TxHT = 0 */
744 RTL_RC_CCK_RATE1M,
745 RTL_RC_CCK_RATE2M,
746 RTL_RC_CCK_RATE5_5M,
747 RTL_RC_CCK_RATE11M,
748
749 /*OFDM Rates, TxHT = 0 */
750 RTL_RC_OFDM_RATE6M,
751 RTL_RC_OFDM_RATE9M,
752 RTL_RC_OFDM_RATE12M,
753 RTL_RC_OFDM_RATE18M,
754 RTL_RC_OFDM_RATE24M,
755 RTL_RC_OFDM_RATE36M,
756 RTL_RC_OFDM_RATE48M,
757 RTL_RC_OFDM_RATE54M,
758
759 RTL_RC_HT_RATEMCS7,
760 RTL_RC_HT_RATEMCS15,
761
762 RTL_RC_VHT_RATE_1SS_MCS7,
763 RTL_RC_VHT_RATE_1SS_MCS8,
764 RTL_RC_VHT_RATE_1SS_MCS9,
765 RTL_RC_VHT_RATE_2SS_MCS7,
766 RTL_RC_VHT_RATE_2SS_MCS8,
767 RTL_RC_VHT_RATE_2SS_MCS9,
768
769 /*keep it last */
770 RTL_VAR_MAP_MAX,
771 };
772
773 /*Firmware PS mode for control LPS.*/
774 enum _fw_ps_mode {
775 FW_PS_ACTIVE_MODE = 0,
776 FW_PS_MIN_MODE = 1,
777 FW_PS_MAX_MODE = 2,
778 FW_PS_DTIM_MODE = 3,
779 FW_PS_VOIP_MODE = 4,
780 FW_PS_UAPSD_WMM_MODE = 5,
781 FW_PS_UAPSD_MODE = 6,
782 FW_PS_IBSS_MODE = 7,
783 FW_PS_WWLAN_MODE = 8,
784 FW_PS_PM_RADIO_OFF = 9,
785 FW_PS_PM_CARD_DISABLE = 10,
786 };
787
788 enum rt_psmode {
789 EACTIVE, /*Active/Continuous access. */
790 EMAXPS, /*Max power save mode. */
791 EFASTPS, /*Fast power save mode. */
792 EAUTOPS, /*Auto power save mode. */
793 };
794
795 /*LED related.*/
796 enum led_ctl_mode {
797 LED_CTL_POWER_ON = 1,
798 LED_CTL_LINK = 2,
799 LED_CTL_NO_LINK = 3,
800 LED_CTL_TX = 4,
801 LED_CTL_RX = 5,
802 LED_CTL_SITE_SURVEY = 6,
803 LED_CTL_POWER_OFF = 7,
804 LED_CTL_START_TO_LINK = 8,
805 LED_CTL_START_WPS = 9,
806 LED_CTL_STOP_WPS = 10,
807 };
808
809 enum rtl_led_pin {
810 LED_PIN_GPIO0,
811 LED_PIN_LED0,
812 LED_PIN_LED1,
813 LED_PIN_LED2
814 };
815
816 /* QoS related.*/
817 /* acm implementation method.*/
818 enum acm_method {
819 EACMWAY0_SWANDHW = 0,
820 EACMWAY1_HW = 1,
821 EACMWAY2_SW = 2,
822 };
823
824 enum macphy_mode {
825 SINGLEMAC_SINGLEPHY = 0,
826 DUALMAC_DUALPHY,
827 DUALMAC_SINGLEPHY,
828 };
829
830 enum band_type {
831 BAND_ON_2_4G = 0,
832 BAND_ON_5G,
833 BAND_ON_BOTH,
834 BANDMAX
835 };
836
837 /* aci/aifsn Field.
838 * Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
839 */
840 union aci_aifsn {
841 u8 char_data;
842
843 struct {
844 u8 aifsn:4;
845 u8 acm:1;
846 u8 aci:2;
847 u8 reserved:1;
848 } f; /* Field */
849 };
850
851 /*mlme related.*/
852 enum wireless_mode {
853 WIRELESS_MODE_UNKNOWN = 0x00,
854 WIRELESS_MODE_A = 0x01,
855 WIRELESS_MODE_B = 0x02,
856 WIRELESS_MODE_G = 0x04,
857 WIRELESS_MODE_AUTO = 0x08,
858 WIRELESS_MODE_N_24G = 0x10,
859 WIRELESS_MODE_N_5G = 0x20,
860 WIRELESS_MODE_AC_5G = 0x40,
861 WIRELESS_MODE_AC_24G = 0x80,
862 WIRELESS_MODE_AC_ONLY = 0x100,
863 WIRELESS_MODE_MAX = 0x800
864 };
865
866 #define IS_WIRELESS_MODE_A(wirelessmode) \
867 (wirelessmode == WIRELESS_MODE_A)
868 #define IS_WIRELESS_MODE_B(wirelessmode) \
869 (wirelessmode == WIRELESS_MODE_B)
870 #define IS_WIRELESS_MODE_G(wirelessmode) \
871 (wirelessmode == WIRELESS_MODE_G)
872 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
873 (wirelessmode == WIRELESS_MODE_N_24G)
874 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
875 (wirelessmode == WIRELESS_MODE_N_5G)
876
877 enum ratr_table_mode {
878 RATR_INX_WIRELESS_NGB = 0,
879 RATR_INX_WIRELESS_NG = 1,
880 RATR_INX_WIRELESS_NB = 2,
881 RATR_INX_WIRELESS_N = 3,
882 RATR_INX_WIRELESS_GB = 4,
883 RATR_INX_WIRELESS_G = 5,
884 RATR_INX_WIRELESS_B = 6,
885 RATR_INX_WIRELESS_MC = 7,
886 RATR_INX_WIRELESS_A = 8,
887 RATR_INX_WIRELESS_AC_5N = 8,
888 RATR_INX_WIRELESS_AC_24N = 9,
889 };
890
891 enum ratr_table_mode_new {
892 RATEID_IDX_BGN_40M_2SS = 0,
893 RATEID_IDX_BGN_40M_1SS = 1,
894 RATEID_IDX_BGN_20M_2SS_BN = 2,
895 RATEID_IDX_BGN_20M_1SS_BN = 3,
896 RATEID_IDX_GN_N2SS = 4,
897 RATEID_IDX_GN_N1SS = 5,
898 RATEID_IDX_BG = 6,
899 RATEID_IDX_G = 7,
900 RATEID_IDX_B = 8,
901 RATEID_IDX_VHT_2SS = 9,
902 RATEID_IDX_VHT_1SS = 10,
903 RATEID_IDX_MIX1 = 11,
904 RATEID_IDX_MIX2 = 12,
905 RATEID_IDX_VHT_3SS = 13,
906 RATEID_IDX_BGN_3SS = 14,
907 };
908
909 enum rtl_link_state {
910 MAC80211_NOLINK = 0,
911 MAC80211_LINKING = 1,
912 MAC80211_LINKED = 2,
913 MAC80211_LINKED_SCANNING = 3,
914 };
915
916 enum act_category {
917 ACT_CAT_QOS = 1,
918 ACT_CAT_DLS = 2,
919 ACT_CAT_BA = 3,
920 ACT_CAT_HT = 7,
921 ACT_CAT_WMM = 17,
922 };
923
924 enum ba_action {
925 ACT_ADDBAREQ = 0,
926 ACT_ADDBARSP = 1,
927 ACT_DELBA = 2,
928 };
929
930 enum rt_polarity_ctl {
931 RT_POLARITY_LOW_ACT = 0,
932 RT_POLARITY_HIGH_ACT = 1,
933 };
934
935 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
936 enum fw_wow_reason_v2 {
937 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
938 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
939 FW_WOW_V2_DISASSOC_EVENT = 0x04,
940 FW_WOW_V2_DEAUTH_EVENT = 0x08,
941 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
942 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
943 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
944 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
945 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
946 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
947 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
948 FW_WOW_V2_REASON_MAX = 0xff,
949 };
950
951 enum wolpattern_type {
952 UNICAST_PATTERN = 0,
953 MULTICAST_PATTERN = 1,
954 BROADCAST_PATTERN = 2,
955 DONT_CARE_DA = 3,
956 UNKNOWN_TYPE = 4,
957 };
958
959 enum package_type {
960 PACKAGE_DEFAULT,
961 PACKAGE_QFN68,
962 PACKAGE_TFBGA90,
963 PACKAGE_TFBGA80,
964 PACKAGE_TFBGA79
965 };
966
967 enum rtl_spec_ver {
968 RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */
969 RTL_SPEC_SUPPORT_VHT = BIT(1), /* support VHT */
970 RTL_SPEC_NEW_FW_C2H = BIT(2), /* new FW C2H (e.g. TX REPORT) */
971 };
972
973 struct octet_string {
974 u8 *octet;
975 u16 length;
976 };
977
978 struct rtl_hdr_3addr {
979 __le16 frame_ctl;
980 __le16 duration_id;
981 u8 addr1[ETH_ALEN];
982 u8 addr2[ETH_ALEN];
983 u8 addr3[ETH_ALEN];
984 __le16 seq_ctl;
985 u8 payload[0];
986 } __packed;
987
988 struct rtl_info_element {
989 u8 id;
990 u8 len;
991 u8 data[0];
992 } __packed;
993
994 struct rtl_probe_rsp {
995 struct rtl_hdr_3addr header;
996 u32 time_stamp[2];
997 __le16 beacon_interval;
998 __le16 capability;
999 /* SSID, supported rates, FH params, DS params,
1000 * CF params, IBSS params, TIM (if beacon), RSN
1001 */
1002 struct rtl_info_element info_element[0];
1003 } __packed;
1004
1005 struct rtl_beacon_keys {
1006 /*u8 ssid[32];*/
1007 /*u32 ssid_len;*/
1008 u8 bcn_channel;
1009 __le16 ht_cap_info;
1010 u8 ht_info_infos_0_sco; /* bit0 & bit1 in infos[0] is 2nd ch offset */
1011 bool valid;
1012 };
1013
1014 /*LED related.*/
1015 /*ledpin Identify how to implement this SW led.*/
1016 struct rtl_led {
1017 void *hw;
1018 enum rtl_led_pin ledpin;
1019 bool ledon;
1020 };
1021
1022 struct rtl_led_ctl {
1023 bool led_opendrain;
1024 struct rtl_led sw_led0;
1025 struct rtl_led sw_led1;
1026 };
1027
1028 struct rtl_qos_parameters {
1029 __le16 cw_min;
1030 __le16 cw_max;
1031 u8 aifs;
1032 u8 flag;
1033 __le16 tx_op;
1034 } __packed;
1035
1036 struct rt_smooth_data {
1037 u32 elements[100]; /*array to store values */
1038 u32 index; /*index to current array to store */
1039 u32 total_num; /*num of valid elements */
1040 u32 total_val; /*sum of valid elements */
1041 };
1042
1043 struct false_alarm_statistics {
1044 u32 cnt_parity_fail;
1045 u32 cnt_rate_illegal;
1046 u32 cnt_crc8_fail;
1047 u32 cnt_mcs_fail;
1048 u32 cnt_fast_fsync_fail;
1049 u32 cnt_sb_search_fail;
1050 u32 cnt_ofdm_fail;
1051 u32 cnt_cck_fail;
1052 u32 cnt_all;
1053 u32 cnt_ofdm_cca;
1054 u32 cnt_cck_cca;
1055 u32 cnt_cca_all;
1056 u32 cnt_bw_usc;
1057 u32 cnt_bw_lsc;
1058 };
1059
1060 struct init_gain {
1061 u8 xaagccore1;
1062 u8 xbagccore1;
1063 u8 xcagccore1;
1064 u8 xdagccore1;
1065 u8 cca;
1066
1067 };
1068
1069 struct wireless_stats {
1070 u64 txbytesunicast;
1071 u64 txbytesmulticast;
1072 u64 txbytesbroadcast;
1073 u64 rxbytesunicast;
1074
1075 u64 txbytesunicast_inperiod;
1076 u64 rxbytesunicast_inperiod;
1077 u32 txbytesunicast_inperiod_tp;
1078 u32 rxbytesunicast_inperiod_tp;
1079 u64 txbytesunicast_last;
1080 u64 rxbytesunicast_last;
1081
1082 long rx_snr_db[4];
1083 /* Correct smoothed ss in Dbm, only used
1084 * in driver to report real power now.
1085 */
1086 long recv_signal_power;
1087 long signal_quality;
1088 long last_sigstrength_inpercent;
1089
1090 u32 rssi_calculate_cnt;
1091 u32 pwdb_all_cnt;
1092
1093 /* Transformed, in dbm. Beautified signal
1094 * strength for UI, not correct.
1095 */
1096 long signal_strength;
1097
1098 u8 rx_rssi_percentage[4];
1099 u8 rx_evm_dbm[4];
1100 u8 rx_evm_percentage[2];
1101
1102 u16 rx_cfo_short[4];
1103 u16 rx_cfo_tail[4];
1104
1105 struct rt_smooth_data ui_rssi;
1106 struct rt_smooth_data ui_link_quality;
1107 };
1108
1109 struct rate_adaptive {
1110 u8 rate_adaptive_disabled;
1111 u8 ratr_state;
1112 u16 reserve;
1113
1114 u32 high_rssi_thresh_for_ra;
1115 u32 high2low_rssi_thresh_for_ra;
1116 u8 low2high_rssi_thresh_for_ra40m;
1117 u32 low_rssi_thresh_for_ra40m;
1118 u8 low2high_rssi_thresh_for_ra20m;
1119 u32 low_rssi_thresh_for_ra20m;
1120 u32 upper_rssi_threshold_ratr;
1121 u32 middleupper_rssi_threshold_ratr;
1122 u32 middle_rssi_threshold_ratr;
1123 u32 middlelow_rssi_threshold_ratr;
1124 u32 low_rssi_threshold_ratr;
1125 u32 ultralow_rssi_threshold_ratr;
1126 u32 low_rssi_threshold_ratr_40m;
1127 u32 low_rssi_threshold_ratr_20m;
1128 u8 ping_rssi_enable;
1129 u32 ping_rssi_ratr;
1130 u32 ping_rssi_thresh_for_ra;
1131 u32 last_ratr;
1132 u8 pre_ratr_state;
1133 u8 ldpc_thres;
1134 bool use_ldpc;
1135 bool lower_rts_rate;
1136 bool is_special_data;
1137 };
1138
1139 struct regd_pair_mapping {
1140 u16 reg_dmnenum;
1141 u16 reg_5ghz_ctl;
1142 u16 reg_2ghz_ctl;
1143 };
1144
1145 struct dynamic_primary_cca {
1146 u8 pricca_flag;
1147 u8 intf_flag;
1148 u8 intf_type;
1149 u8 dup_rts_flag;
1150 u8 monitor_flag;
1151 u8 ch_offset;
1152 u8 mf_state;
1153 };
1154
1155 struct rtl_regulatory {
1156 s8 alpha2[2];
1157 u16 country_code;
1158 u16 max_power_level;
1159 u32 tp_scale;
1160 u16 current_rd;
1161 u16 current_rd_ext;
1162 s16 power_limit;
1163 struct regd_pair_mapping *regpair;
1164 };
1165
1166 struct rtl_rfkill {
1167 bool rfkill_state; /*0 is off, 1 is on */
1168 };
1169
1170 /*for P2P PS**/
1171 #define P2P_MAX_NOA_NUM 2
1172
1173 enum p2p_role {
1174 P2P_ROLE_DISABLE = 0,
1175 P2P_ROLE_DEVICE = 1,
1176 P2P_ROLE_CLIENT = 2,
1177 P2P_ROLE_GO = 3
1178 };
1179
1180 enum p2p_ps_state {
1181 P2P_PS_DISABLE = 0,
1182 P2P_PS_ENABLE = 1,
1183 P2P_PS_SCAN = 2,
1184 P2P_PS_SCAN_DONE = 3,
1185 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1186 };
1187
1188 enum p2p_ps_mode {
1189 P2P_PS_NONE = 0,
1190 P2P_PS_CTWINDOW = 1,
1191 P2P_PS_NOA = 2,
1192 P2P_PS_MIX = 3, /* CTWindow and NoA */
1193 };
1194
1195 struct rtl_p2p_ps_info {
1196 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1197 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1198 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1199 /* Client traffic window. A period of time in TU after TBTT. */
1200 u8 ctwindow;
1201 u8 opp_ps; /* opportunistic power save. */
1202 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1203 /* Count for owner, Type of client. */
1204 u8 noa_count_type[P2P_MAX_NOA_NUM];
1205 /* Max duration for owner, preferred or min acceptable duration
1206 * for client.
1207 */
1208 u32 noa_duration[P2P_MAX_NOA_NUM];
1209 /* Length of interval for owner, preferred or max acceptable intervali
1210 * of client.
1211 */
1212 u32 noa_interval[P2P_MAX_NOA_NUM];
1213 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1214 u32 noa_start_time[P2P_MAX_NOA_NUM];
1215 };
1216
1217 struct p2p_ps_offload_t {
1218 u8 offload_en:1;
1219 u8 role:1; /* 1: Owner, 0: Client */
1220 u8 ctwindow_en:1;
1221 u8 noa0_en:1;
1222 u8 noa1_en:1;
1223 u8 allstasleep:1;
1224 u8 discovery:1;
1225 u8 reserved:1;
1226 };
1227
1228 #define IQK_MATRIX_REG_NUM 8
1229 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1230
1231 struct iqk_matrix_regs {
1232 bool iqk_done;
1233 long value[1][IQK_MATRIX_REG_NUM];
1234 };
1235
1236 struct phy_parameters {
1237 u16 length;
1238 u32 *pdata;
1239 };
1240
1241 enum hw_param_tab_index {
1242 PHY_REG_2T,
1243 PHY_REG_1T,
1244 PHY_REG_PG,
1245 RADIOA_2T,
1246 RADIOB_2T,
1247 RADIOA_1T,
1248 RADIOB_1T,
1249 MAC_REG,
1250 AGCTAB_2T,
1251 AGCTAB_1T,
1252 MAX_TAB
1253 };
1254
1255 struct rtl_phy {
1256 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1257 struct init_gain initgain_backup;
1258 enum io_type current_io_type;
1259
1260 u8 rf_mode;
1261 u8 rf_type;
1262 u8 current_chan_bw;
1263 u8 max_ht_chan_bw;
1264 u8 max_vht_chan_bw;
1265 u8 set_bwmode_inprogress;
1266 u8 sw_chnl_inprogress;
1267 u8 sw_chnl_stage;
1268 u8 sw_chnl_step;
1269 u8 current_channel;
1270 u8 h2c_box_num;
1271 u8 set_io_inprogress;
1272 u8 lck_inprogress;
1273
1274 /* record for power tracking */
1275 s32 reg_e94;
1276 s32 reg_e9c;
1277 s32 reg_ea4;
1278 s32 reg_eac;
1279 s32 reg_eb4;
1280 s32 reg_ebc;
1281 s32 reg_ec4;
1282 s32 reg_ecc;
1283 u8 rfpienable;
1284 u8 reserve_0;
1285 u16 reserve_1;
1286 u32 reg_c04, reg_c08, reg_874;
1287 u32 adda_backup[16];
1288 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1289 u32 iqk_bb_backup[10];
1290 bool iqk_initialized;
1291
1292 bool rfpath_rx_enable[MAX_RF_PATH];
1293 u8 reg_837;
1294 /* Dual mac */
1295 bool need_iqk;
1296 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1297
1298 bool rfpi_enable;
1299 bool iqk_in_progress;
1300
1301 u8 pwrgroup_cnt;
1302 u8 cck_high_power;
1303 /* this is for 88E & 8723A */
1304 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1305 /* MAX_PG_GROUP groups of pwr diff by rates */
1306 u32 mcs_offset[MAX_PG_GROUP][16];
1307 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1308 [TX_PWR_BY_RATE_NUM_RF]
1309 [TX_PWR_BY_RATE_NUM_RF]
1310 [TX_PWR_BY_RATE_NUM_RATE];
1311 /* compatible with TX_PWR_BY_RATE_NUM_SECTION*/
1312 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1313 [TX_PWR_BY_RATE_NUM_RF]
1314 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1315 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1316 [TX_PWR_BY_RATE_NUM_RF]
1317 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1318 u8 default_initialgain[4];
1319
1320 /* the current Tx power level */
1321 u8 cur_cck_txpwridx;
1322 u8 cur_ofdm24g_txpwridx;
1323 u8 cur_bw20_txpwridx;
1324 u8 cur_bw40_txpwridx;
1325
1326 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1327 [MAX_2_4G_BANDWIDTH_NUM]
1328 [MAX_RATE_SECTION_NUM]
1329 [CHANNEL_MAX_NUMBER_2G]
1330 [MAX_RF_PATH_NUM];
1331 s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1332 [MAX_5G_BANDWIDTH_NUM]
1333 [MAX_RATE_SECTION_NUM]
1334 [CHANNEL_MAX_NUMBER_5G]
1335 [MAX_RF_PATH_NUM];
1336
1337 u32 rfreg_chnlval[2];
1338 bool apk_done;
1339 u32 reg_rf3c[2]; /* pathA / pathB */
1340
1341 u32 backup_rf_0x1a;/*92ee*/
1342 /* bfsync */
1343 u8 framesync;
1344 u32 framesync_c34;
1345
1346 u8 num_total_rfpath;
1347 struct phy_parameters hwparam_tables[MAX_TAB];
1348 u16 rf_pathmap;
1349
1350 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1351 enum rt_polarity_ctl polarity_ctl;
1352 };
1353
1354 #define MAX_TID_COUNT 9
1355 #define RTL_AGG_STOP 0
1356 #define RTL_AGG_PROGRESS 1
1357 #define RTL_AGG_START 2
1358 #define RTL_AGG_OPERATIONAL 3
1359 #define RTL_AGG_OFF 0
1360 #define RTL_AGG_ON 1
1361 #define RTL_RX_AGG_START 1
1362 #define RTL_RX_AGG_STOP 0
1363 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1364 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1365
1366 struct rtl_ht_agg {
1367 u16 txq_id;
1368 u16 wait_for_ba;
1369 u16 start_idx;
1370 u64 bitmap;
1371 u32 rate_n_flags;
1372 u8 agg_state;
1373 u8 rx_agg_state;
1374 };
1375
1376 struct rssi_sta {
1377 /* for old dm */
1378 long undec_sm_pwdb;
1379 long undec_sm_cck;
1380
1381 /* for new phydm_mod */
1382 s32 undecorated_smoothed_pwdb;
1383 s32 undecorated_smoothed_cck;
1384 s32 undecorated_smoothed_ofdm;
1385 u8 ofdm_pkt;
1386 u8 cck_pkt;
1387 u16 cck_sum_power;
1388 u8 is_send_rssi;
1389 u64 packet_map;
1390 u8 valid_bit;
1391 };
1392
1393 struct rtl_tid_data {
1394 u16 seq_number;
1395 struct rtl_ht_agg agg;
1396 };
1397
1398 struct rtl_sta_info {
1399 struct list_head list;
1400 struct rtl_tid_data tids[MAX_TID_COUNT];
1401 /* just used for ap adhoc or mesh*/
1402 struct rssi_sta rssi_stat;
1403 u8 rssi_level;
1404 u16 wireless_mode;
1405 u8 ratr_index;
1406 u8 mimo_ps;
1407 u8 mac_addr[ETH_ALEN];
1408 } __packed;
1409
1410 struct rtl_priv;
1411 struct rtl_io {
1412 struct device *dev;
1413 struct mutex bb_mutex;
1414
1415 /*PCI MEM map */
1416 unsigned long pci_mem_end; /*shared mem end */
1417 unsigned long pci_mem_start; /*shared mem start */
1418
1419 /*PCI IO map */
1420 unsigned long pci_base_addr; /*device I/O address */
1421
1422 void (*write8_async)(struct rtl_priv *rtlpriv, u32 addr, u8 val);
1423 void (*write16_async)(struct rtl_priv *rtlpriv, u32 addr, u16 val);
1424 void (*write32_async)(struct rtl_priv *rtlpriv, u32 addr, u32 val);
1425 void (*writeN_sync)(struct rtl_priv *rtlpriv, u32 addr, void *buf,
1426 u16 len);
1427
1428 u8 (*read8_sync)(struct rtl_priv *rtlpriv, u32 addr);
1429 u16 (*read16_sync)(struct rtl_priv *rtlpriv, u32 addr);
1430 u32 (*read32_sync)(struct rtl_priv *rtlpriv, u32 addr);
1431
1432 };
1433
1434 struct rtl_mac {
1435 u8 mac_addr[ETH_ALEN];
1436 u8 mac80211_registered;
1437 u8 beacon_enabled;
1438
1439 u32 tx_ss_num;
1440 u32 rx_ss_num;
1441
1442 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1443 struct ieee80211_hw *hw;
1444 struct ieee80211_vif *vif;
1445 enum nl80211_iftype opmode;
1446
1447 /*Probe Beacon management */
1448 struct rtl_tid_data tids[MAX_TID_COUNT];
1449 enum rtl_link_state link_state;
1450 struct rtl_beacon_keys cur_beacon_keys;
1451 u8 new_beacon_cnt;
1452
1453 int n_channels;
1454 int n_bitrates;
1455
1456 bool offchan_delay;
1457 u8 p2p; /*using p2p role*/
1458 bool p2p_in_use;
1459
1460 /*filters */
1461 u32 rx_conf;
1462 u16 rx_mgt_filter;
1463 u16 rx_ctrl_filter;
1464 u16 rx_data_filter;
1465
1466 bool act_scanning;
1467 u8 cnt_after_linked;
1468 bool skip_scan;
1469
1470 /* early mode */
1471 /* skb wait queue */
1472 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1473
1474 u8 ht_stbc_cap;
1475 u8 ht_cur_stbc;
1476
1477 /*vht support*/
1478 u8 vht_enable;
1479 u8 bw_80;
1480 u8 vht_cur_ldpc;
1481 u8 vht_cur_stbc;
1482 u8 vht_stbc_cap;
1483 u8 vht_ldpc_cap;
1484
1485 /*RDG*/
1486 bool rdg_en;
1487
1488 /*AP*/
1489 u8 bssid[ETH_ALEN] __aligned(2);
1490 u32 vendor;
1491 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1492 u32 basic_rates; /* b/g rates */
1493 u8 ht_enable;
1494 u8 sgi_40;
1495 u8 sgi_20;
1496 u8 bw_40;
1497 u16 mode; /* wireless mode */
1498 u8 slot_time;
1499 u8 short_preamble;
1500 u8 use_cts_protect;
1501 u8 cur_40_prime_sc;
1502 u8 cur_40_prime_sc_bk;
1503 u8 cur_80_prime_sc;
1504 u64 tsf;
1505 u8 retry_short;
1506 u8 retry_long;
1507 u16 assoc_id;
1508 bool hiddenssid;
1509
1510 /*IBSS*/
1511 int beacon_interval;
1512
1513 /*AMPDU*/
1514 u8 min_space_cfg; /*For Min spacing configurations */
1515 u8 max_mss_density;
1516 u8 current_ampdu_factor;
1517 u8 current_ampdu_density;
1518
1519 /*QOS & EDCA */
1520 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1521 struct rtl_qos_parameters ac[AC_MAX];
1522
1523 /* counters */
1524 u64 last_txok_cnt;
1525 u64 last_rxok_cnt;
1526 u32 last_bt_edca_ul;
1527 u32 last_bt_edca_dl;
1528 };
1529
1530 struct btdm_8723 {
1531 bool all_off;
1532 bool agc_table_en;
1533 bool adc_back_off_on;
1534 bool b2_ant_hid_en;
1535 bool low_penalty_rate_adaptive;
1536 bool rf_rx_lpf_shrink;
1537 bool reject_aggre_pkt;
1538 bool tra_tdma_on;
1539 u8 tra_tdma_nav;
1540 u8 tra_tdma_ant;
1541 bool tdma_on;
1542 u8 tdma_ant;
1543 u8 tdma_nav;
1544 u8 tdma_dac_swing;
1545 u8 fw_dac_swing_lvl;
1546 bool ps_tdma_on;
1547 u8 ps_tdma_byte[5];
1548 bool pta_on;
1549 u32 val_0x6c0;
1550 u32 val_0x6c8;
1551 u32 val_0x6cc;
1552 bool sw_dac_swing_on;
1553 u32 sw_dac_swing_lvl;
1554 u32 wlan_act_hi;
1555 u32 wlan_act_lo;
1556 u32 bt_retry_index;
1557 bool dec_bt_pwr;
1558 bool ignore_wlan_act;
1559 };
1560
1561 struct bt_coexist_8723 {
1562 u32 high_priority_tx;
1563 u32 high_priority_rx;
1564 u32 low_priority_tx;
1565 u32 low_priority_rx;
1566 u8 c2h_bt_info;
1567 bool c2h_bt_info_req_sent;
1568 bool c2h_bt_inquiry_page;
1569 u32 bt_inq_page_start_time;
1570 u8 bt_retry_cnt;
1571 u8 c2h_bt_info_original;
1572 u8 bt_inquiry_page_cnt;
1573 struct btdm_8723 btdm;
1574 };
1575
1576 struct rtl_hal {
1577 struct ieee80211_hw *hw;
1578 bool driver_is_goingto_unload;
1579 bool up_first_time;
1580 bool first_init;
1581 bool being_init_adapter;
1582 bool bbrf_ready;
1583 bool mac_func_enable;
1584 bool pre_edcca_enable;
1585 struct bt_coexist_8723 hal_coex_8723;
1586
1587 enum intf_type interface;
1588 u16 hw_type; /*92c or 92d or 92s and so on */
1589 u8 ic_class;
1590 u8 oem_id;
1591 u32 version; /*version of chip */
1592 u8 state; /*stop 0, start 1 */
1593 u8 board_type;
1594 u8 package_type;
1595 u8 external_pa;
1596
1597 u8 pa_mode;
1598 u8 pa_type_2g;
1599 u8 pa_type_5g;
1600 u8 lna_type_2g;
1601 u8 lna_type_5g;
1602 u8 external_pa_2g;
1603 u8 external_lna_2g;
1604 u8 external_pa_5g;
1605 u8 external_lna_5g;
1606 u8 type_glna;
1607 u8 type_gpa;
1608 u8 type_alna;
1609 u8 type_apa;
1610 u8 rfe_type;
1611
1612 /*firmware */
1613 u32 fwsize;
1614 u8 *pfirmware;
1615 u16 fw_version;
1616 u16 fw_subversion;
1617 bool h2c_setinprogress;
1618 u8 last_hmeboxnum;
1619 bool fw_ready;
1620 /*Reserve page start offset except beacon in TxQ. */
1621 u8 fw_rsvdpage_startoffset;
1622 u8 h2c_txcmd_seq;
1623 u8 current_ra_rate;
1624
1625 /* FW Cmd IO related */
1626 u16 fwcmd_iomap;
1627 u32 fwcmd_ioparam;
1628 bool set_fwcmd_inprogress;
1629 u8 current_fwcmd_io;
1630
1631 struct p2p_ps_offload_t p2p_ps_offload;
1632 bool fw_clk_change_in_progress;
1633 bool allow_sw_to_change_hwclc;
1634 u8 fw_ps_state;
1635 /**/
1636 bool driver_going2unload;
1637
1638 /*AMPDU init min space*/
1639 u8 minspace_cfg; /*For Min spacing configurations */
1640
1641 /* Dual mac */
1642 enum macphy_mode macphymode;
1643 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1644 enum band_type current_bandtypebackup;
1645 enum band_type bandset;
1646 /* dual MAC 0--Mac0 1--Mac1 */
1647 u32 interfaceindex;
1648 /* just for DualMac S3S4 */
1649 u8 macphyctl_reg;
1650 bool earlymode_enable;
1651 u8 max_earlymode_num;
1652 /* Dual mac*/
1653 bool during_mac0init_radiob;
1654 bool during_mac1init_radioa;
1655 bool reloadtxpowerindex;
1656 /* True if IMR or IQK have done
1657 * for 2.4G in scan progress
1658 */
1659 bool load_imrandiqk_setting_for2g;
1660
1661 bool disable_amsdu_8k;
1662 bool master_of_dmsp;
1663 bool slave_of_dmsp;
1664
1665 u16 rx_tag;/*for 92ee*/
1666 u8 rts_en;
1667
1668 /*for wowlan*/
1669 bool wow_enable;
1670 bool enter_pnp_sleep;
1671 bool wake_from_pnp_sleep;
1672 bool wow_enabled;
1673 time64_t last_suspend_sec;
1674 u32 wowlan_fwsize;
1675 u8 *wowlan_firmware;
1676
1677 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1678
1679 bool real_wow_v2_enable;
1680 bool re_init_llt_table;
1681 };
1682
1683 struct rtl_security {
1684 /*default 0 */
1685 bool use_sw_sec;
1686
1687 bool being_setkey;
1688 bool use_defaultkey;
1689 /*Encryption Algorithm for Unicast Packet */
1690 enum rt_enc_alg pairwise_enc_algorithm;
1691 /*Encryption Algorithm for Brocast/Multicast */
1692 enum rt_enc_alg group_enc_algorithm;
1693 /*Cam Entry Bitmap */
1694 u32 hwsec_cam_bitmap;
1695 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1696 /* local Key buffer, indx 0 is for
1697 * pairwise key 1-4 is for agoup key.
1698 */
1699 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1700 u8 key_len[KEY_BUF_SIZE];
1701
1702 /* The pointer of Pairwise Key,
1703 * it always points to KeyBuf[4]
1704 */
1705 u8 *pairwise_key;
1706 };
1707
1708 #define ASSOCIATE_ENTRY_NUM 33
1709
1710 struct fast_ant_training {
1711 u8 bssid[6];
1712 u8 antsel_rx_keep_0;
1713 u8 antsel_rx_keep_1;
1714 u8 antsel_rx_keep_2;
1715 u32 ant_sum[7];
1716 u32 ant_cnt[7];
1717 u32 ant_ave[7];
1718 u8 fat_state;
1719 u32 train_idx;
1720 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1721 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1722 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1723 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1724 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1725 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1726 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1727 u8 rx_idle_ant;
1728 bool becomelinked;
1729 };
1730
1731 struct dm_phy_dbg_info {
1732 s8 rx_snrdb[4];
1733 u64 num_qry_phy_status;
1734 u64 num_qry_phy_status_cck;
1735 u64 num_qry_phy_status_ofdm;
1736 u16 num_qry_beacon_pkt;
1737 u16 num_non_be_pkt;
1738 s32 rx_evm[4];
1739 };
1740
1741 struct rtl_dm {
1742 /*PHY status for Dynamic Management */
1743 long entry_min_undec_sm_pwdb;
1744 long undec_sm_cck;
1745 long undec_sm_pwdb; /*out dm */
1746 long entry_max_undec_sm_pwdb;
1747 s32 ofdm_pkt_cnt;
1748 bool dm_initialgain_enable;
1749 bool dynamic_txpower_enable;
1750 bool current_turbo_edca;
1751 bool is_any_nonbepkts; /*out dm */
1752 bool is_cur_rdlstate;
1753 bool txpower_trackinginit;
1754 bool disable_framebursting;
1755 bool cck_inch14;
1756 bool txpower_tracking;
1757 bool useramask;
1758 bool rfpath_rxenable[4];
1759 bool inform_fw_driverctrldm;
1760 bool current_mrc_switch;
1761 u8 txpowercount;
1762 u8 powerindex_backup[6];
1763
1764 u8 thermalvalue_rxgain;
1765 u8 thermalvalue_iqk;
1766 u8 thermalvalue_lck;
1767 u8 thermalvalue;
1768 u8 last_dtp_lvl;
1769 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1770 u8 thermalvalue_avg_index;
1771 u8 tm_trigger;
1772 bool done_txpower;
1773 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1774 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1775 u8 dm_flag_tmp;
1776 u8 dm_type;
1777 u8 dm_rssi_sel;
1778 u8 txpower_track_control;
1779 bool interrupt_migration;
1780 bool disable_tx_int;
1781 s8 ofdm_index[MAX_RF_PATH];
1782 u8 default_ofdm_index;
1783 u8 default_cck_index;
1784 s8 cck_index;
1785 s8 delta_power_index[MAX_RF_PATH];
1786 s8 delta_power_index_last[MAX_RF_PATH];
1787 s8 power_index_offset[MAX_RF_PATH];
1788 s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
1789 s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
1790 s8 remnant_cck_idx;
1791 bool modify_txagc_flag_path_a;
1792 bool modify_txagc_flag_path_b;
1793
1794 bool one_entry_only;
1795 struct dm_phy_dbg_info dbginfo;
1796
1797 /* Dynamic ATC switch */
1798 bool atc_status;
1799 bool large_cfo_hit;
1800 bool is_freeze;
1801 int cfo_tail[2];
1802 int cfo_ave_pre;
1803 int crystal_cap;
1804 u8 cfo_threshold;
1805 u32 packet_count;
1806 u32 packet_count_pre;
1807 u8 tx_rate;
1808
1809 /*88e tx power tracking*/
1810 u8 swing_idx_ofdm[MAX_RF_PATH];
1811 u8 swing_idx_ofdm_cur;
1812 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1813 bool swing_flag_ofdm;
1814 u8 swing_idx_cck;
1815 u8 swing_idx_cck_cur;
1816 u8 swing_idx_cck_base;
1817 bool swing_flag_cck;
1818
1819 s8 swing_diff_2g;
1820 s8 swing_diff_5g;
1821
1822 /* DMSP */
1823 bool supp_phymode_switch;
1824
1825 /* DulMac */
1826 struct fast_ant_training fat_table;
1827
1828 u8 resp_tx_path;
1829 u8 path_sel;
1830 u32 patha_sum;
1831 u32 pathb_sum;
1832 u32 patha_cnt;
1833 u32 pathb_cnt;
1834
1835 u8 pre_channel;
1836 u8 *p_channel;
1837 u8 linked_interval;
1838
1839 u64 last_tx_ok_cnt;
1840 u64 last_rx_ok_cnt;
1841 };
1842
1843 #define EFUSE_MAX_LOGICAL_SIZE 512
1844
1845 struct rtl_efuse {
1846 bool autoload_ok;
1847 bool bootfromefuse;
1848 u16 max_physical_size;
1849
1850 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1851 u16 efuse_usedbytes;
1852 u8 efuse_usedpercentage;
1853 #ifdef EFUSE_REPG_WORKAROUND
1854 bool efuse_re_pg_sec1flag;
1855 u8 efuse_re_pg_data[8];
1856 #endif
1857
1858 u8 autoload_failflag;
1859 u8 autoload_status;
1860
1861 short epromtype;
1862 u16 eeprom_vid;
1863 u16 eeprom_did;
1864 u16 eeprom_svid;
1865 u16 eeprom_smid;
1866 u8 eeprom_oemid;
1867 u16 eeprom_channelplan;
1868 u8 eeprom_version;
1869 u8 board_type;
1870 u8 external_pa;
1871
1872 u8 dev_addr[6];
1873 u8 wowlan_enable;
1874 u8 antenna_div_cfg;
1875 u8 antenna_div_type;
1876
1877 bool txpwr_fromeprom;
1878 u8 eeprom_crystalcap;
1879 u8 eeprom_tssi[2];
1880 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1881 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1882 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1883 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1884 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1885 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1886
1887 u8 internal_pa_5g[2]; /* pathA / pathB */
1888 u8 eeprom_c9;
1889 u8 eeprom_cc;
1890
1891 /*For power group */
1892 u8 eeprom_pwrgroup[2][3];
1893 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1894 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1895
1896 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1897 /*For HT 40MHZ pwr */
1898 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1899 /*For HT 40MHZ pwr */
1900 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1901
1902 /*--------------------------------------------------------*
1903 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1904 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1905 * define new arrays in Windows code.
1906 * BUT, in linux code, we use the same array for all ICs.
1907 *
1908 * The Correspondance relation between two arrays is:
1909 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1910 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1911 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1912 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1913 *
1914 * Sizes of these arrays are decided by the larger ones.
1915 */
1916 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1917 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1918 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1919 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1920
1921 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1922 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1923 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1924 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1925 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1926 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1927
1928 u8 txpwr_safetyflag; /* Band edge enable flag */
1929 u16 eeprom_txpowerdiff;
1930 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1931 u8 antenna_txpwdiff[3];
1932
1933 u8 eeprom_regulatory;
1934 u8 eeprom_thermalmeter;
1935 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1936 u16 tssi_13dbm;
1937 u8 crystalcap; /* CrystalCap. */
1938 u8 delta_iqk;
1939 u8 delta_lck;
1940
1941 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1942 bool apk_thermalmeterignore;
1943
1944 bool b1x1_recvcombine;
1945 bool b1ss_support;
1946
1947 /*channel plan */
1948 u8 channel_plan;
1949 };
1950
1951 struct rtl_tx_report {
1952 atomic_t sn;
1953 u16 last_sent_sn;
1954 unsigned long last_sent_time;
1955 u16 last_recv_sn;
1956 };
1957
1958 struct rtl_ps_ctl {
1959 bool pwrdomain_protect;
1960 bool in_powersavemode;
1961 bool rfchange_inprogress;
1962 bool swrf_processing;
1963 bool hwradiooff;
1964 /* just for PCIE ASPM
1965 * If it supports ASPM, Offset[560h] = 0x40,
1966 * otherwise Offset[560h] = 0x00.
1967 */
1968 bool support_aspm;
1969 bool support_backdoor;
1970
1971 /*for LPS */
1972 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1973 bool swctrl_lps;
1974 bool leisure_ps;
1975 bool fwctrl_lps;
1976 u8 fwctrl_psmode;
1977 /*For Fw control LPS mode */
1978 u8 reg_fwctrl_lps;
1979 /*Record Fw PS mode status. */
1980 bool fw_current_inpsmode;
1981 u8 reg_max_lps_awakeintvl;
1982 bool report_linked;
1983 bool low_power_enable;/*for 32k*/
1984
1985 /*for IPS */
1986 bool inactiveps;
1987
1988 u32 rfoff_reason;
1989
1990 /*RF OFF Level */
1991 u32 cur_ps_level;
1992 u32 reg_rfps_level;
1993
1994 /*just for PCIE ASPM */
1995 u8 const_amdpci_aspm;
1996 bool pwrdown_mode;
1997
1998 enum rf_pwrstate inactive_pwrstate;
1999 enum rf_pwrstate rfpwr_state; /*cur power state */
2000
2001 /* for SW LPS*/
2002 bool sw_ps_enabled;
2003 bool state;
2004 bool state_inap;
2005 bool multi_buffered;
2006 u16 nullfunc_seq;
2007 unsigned int dtim_counter;
2008 unsigned int sleep_ms;
2009 unsigned long last_sleep_jiffies;
2010 unsigned long last_awake_jiffies;
2011 unsigned long last_delaylps_stamp_jiffies;
2012 unsigned long last_dtim;
2013 unsigned long last_beacon;
2014 unsigned long last_action;
2015 unsigned long last_slept;
2016
2017 /*For P2P PS */
2018 struct rtl_p2p_ps_info p2p_ps_info;
2019 u8 pwr_mode;
2020 u8 smart_ps;
2021
2022 /* wake up on line */
2023 u8 wo_wlan_mode;
2024 u8 arp_offload_enable;
2025 u8 gtk_offload_enable;
2026 /* Used for WOL, indicates the reason for waking event.*/
2027 u32 wakeup_reason;
2028 /* Record the last waking time for comparison with setting key. */
2029 u64 last_wakeup_time;
2030 };
2031
2032 struct rtl_stats {
2033 u8 psaddr[ETH_ALEN];
2034 u32 mac_time[2];
2035 s8 rssi;
2036 u8 signal;
2037 u8 noise;
2038 u8 rate; /* hw desc rate */
2039 u8 received_channel;
2040 u8 control;
2041 u8 mask;
2042 u8 freq;
2043 u16 len;
2044 u64 tsf;
2045 u32 beacon_time;
2046 u8 nic_type;
2047 u16 length;
2048 u8 signalquality; /*in 0-100 index. */
2049 /*
2050 * Real power in dBm for this packet,
2051 * no beautification and aggregation.
2052 */
2053 s32 recvsignalpower;
2054 s8 rxpower; /*in dBm Translate from PWdB */
2055 u8 signalstrength; /*in 0-100 index. */
2056 u16 hwerror:1;
2057 u16 crc:1;
2058 u16 icv:1;
2059 u16 shortpreamble:1;
2060 u16 antenna:1;
2061 u16 decrypted:1;
2062 u16 wakeup:1;
2063 u32 timestamp_low;
2064 u32 timestamp_high;
2065 bool shift;
2066
2067 u8 rx_drvinfo_size;
2068 u8 rx_bufshift;
2069 bool isampdu;
2070 bool isfirst_ampdu;
2071 bool rx_is40mhzpacket;
2072 u8 rx_packet_bw;
2073 u32 rx_pwdb_all;
2074 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
2075 s8 rx_mimo_signalquality[4];
2076 u8 rx_mimo_evm_dbm[4];
2077 u16 cfo_short[4]; /* per-path's Cfo_short */
2078 u16 cfo_tail[4];
2079
2080 s8 rx_mimo_sig_qual[4];
2081 u8 rx_pwr[4]; /* per-path's pwdb */
2082 u8 rx_snr[4]; /* per-path's SNR */
2083 u8 bandwidth;
2084 u8 bt_coex_pwr_adjust;
2085 bool packet_matchbssid;
2086 bool is_cck;
2087 bool is_ht;
2088 bool packet_toself;
2089 bool packet_beacon; /*for rssi */
2090 s8 cck_adc_pwdb[4]; /*for rx path selection */
2091
2092 bool is_vht;
2093 bool is_short_gi;
2094 u8 vht_nss;
2095
2096 u8 packet_report_type;
2097
2098 u32 macid;
2099 u8 wake_match;
2100 u32 bt_rx_rssi_percentage;
2101 u32 macid_valid_entry[2];
2102 };
2103
2104 struct rt_link_detect {
2105 /* count for roaming */
2106 u32 bcn_rx_inperiod;
2107 u32 roam_times;
2108
2109 u32 num_tx_in4period[4];
2110 u32 num_rx_in4period[4];
2111
2112 u32 num_tx_inperiod;
2113 u32 num_rx_inperiod;
2114
2115 bool busytraffic;
2116 bool tx_busy_traffic;
2117 bool rx_busy_traffic;
2118 bool higher_busytraffic;
2119 bool higher_busyrxtraffic;
2120
2121 u32 tidtx_in4period[MAX_TID_COUNT][4];
2122 u32 tidtx_inperiod[MAX_TID_COUNT];
2123 bool higher_busytxtraffic[MAX_TID_COUNT];
2124 };
2125
2126 struct rtl_tcb_desc {
2127 u8 packet_bw:2;
2128 u8 multicast:1;
2129 u8 broadcast:1;
2130
2131 u8 rts_stbc:1;
2132 u8 rts_enable:1;
2133 u8 cts_enable:1;
2134 u8 rts_use_shortpreamble:1;
2135 u8 rts_use_shortgi:1;
2136 u8 rts_sc:1;
2137 u8 rts_bw:1;
2138 u8 rts_rate;
2139
2140 u8 use_shortgi:1;
2141 u8 use_shortpreamble:1;
2142 u8 use_driver_rate:1;
2143 u8 disable_ratefallback:1;
2144
2145 u8 use_spe_rpt:1;
2146
2147 u8 ratr_index;
2148 u8 mac_id;
2149 u8 hw_rate;
2150
2151 u8 last_inipkt:1;
2152 u8 cmd_or_init:1;
2153 u8 queue_index;
2154
2155 /* early mode */
2156 u8 empkt_num;
2157 /* The max value by HW */
2158 u32 empkt_len[10];
2159 bool tx_enable_sw_calc_duration;
2160 };
2161
2162 struct rtl_wow_pattern {
2163 u8 type;
2164 u16 crc;
2165 u32 mask[4];
2166 };
2167
2168 struct rtl_hal_ops {
2169 int (*init_sw_vars)(struct ieee80211_hw *hw);
2170 void (*deinit_sw_vars)(struct ieee80211_hw *hw);
2171 void (*read_chip_version)(struct ieee80211_hw *hw);
2172 void (*read_eeprom_info)(struct ieee80211_hw *hw);
2173 void (*interrupt_recognized)(struct ieee80211_hw *hw,
2174 u32 *p_inta, u32 *p_intb,
2175 u32 *p_intc, u32 *p_intd);
2176 int (*hw_init)(struct ieee80211_hw *hw);
2177 void (*hw_disable)(struct ieee80211_hw *hw);
2178 void (*hw_suspend)(struct ieee80211_hw *hw);
2179 void (*hw_resume)(struct ieee80211_hw *hw);
2180 void (*enable_interrupt)(struct ieee80211_hw *hw);
2181 void (*disable_interrupt)(struct ieee80211_hw *hw);
2182 int (*set_network_type)(struct ieee80211_hw *hw,
2183 enum nl80211_iftype type);
2184 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2185 bool check_bssid);
2186 void (*set_bw_mode)(struct ieee80211_hw *hw,
2187 enum nl80211_channel_type ch_type);
2188 u8 (*switch_channel)(struct ieee80211_hw *hw);
2189 void (*set_qos)(struct ieee80211_hw *hw, int aci);
2190 void (*set_bcn_reg)(struct ieee80211_hw *hw);
2191 void (*set_bcn_intv)(struct ieee80211_hw *hw);
2192 void (*update_interrupt_mask)(struct ieee80211_hw *hw,
2193 u32 add_msr, u32 rm_msr);
2194 void (*get_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2195 void (*set_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2196 void (*update_rate_tbl)(struct ieee80211_hw *hw,
2197 struct ieee80211_sta *sta, u8 rssi_leve,
2198 bool update_bw);
2199 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2200 u8 *desc, u8 queue_index,
2201 struct sk_buff *skb, dma_addr_t addr);
2202 void (*update_rate_mask)(struct ieee80211_hw *hw, u8 rssi_level);
2203 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2204 u8 queue_index);
2205 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2206 u8 queue_index);
2207 void (*fill_tx_desc)(struct ieee80211_hw *hw,
2208 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2209 u8 *pbd_desc_tx,
2210 struct ieee80211_tx_info *info,
2211 struct ieee80211_sta *sta,
2212 struct sk_buff *skb, u8 hw_queue,
2213 struct rtl_tcb_desc *ptcb_desc);
2214 void (*fill_fake_txdesc)(struct ieee80211_hw *hw, u8 *pdesc,
2215 u32 buffer_len, bool bispspoll);
2216 void (*fill_tx_cmddesc)(struct ieee80211_hw *hw, u8 *pdesc,
2217 bool firstseg, bool lastseg,
2218 struct sk_buff *skb);
2219 void (*fill_tx_special_desc)(struct ieee80211_hw *hw,
2220 u8 *pdesc, u8 *pbd_desc,
2221 struct sk_buff *skb, u8 hw_queue);
2222 bool (*query_rx_desc)(struct ieee80211_hw *hw,
2223 struct rtl_stats *stats,
2224 struct ieee80211_rx_status *rx_status,
2225 u8 *pdesc, struct sk_buff *skb);
2226 void (*set_channel_access)(struct ieee80211_hw *hw);
2227 bool (*radio_onoff_checking)(struct ieee80211_hw *hw, u8 *valid);
2228 void (*dm_watchdog)(struct ieee80211_hw *hw);
2229 void (*scan_operation_backup)(struct ieee80211_hw *hw, u8 operation);
2230 bool (*set_rf_power_state)(struct ieee80211_hw *hw,
2231 enum rf_pwrstate rfpwr_state);
2232 void (*led_control)(struct ieee80211_hw *hw,
2233 enum led_ctl_mode ledaction);
2234 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2235 u8 desc_name, u8 *val);
2236 u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2237 u8 desc_name);
2238 bool (*is_tx_desc_closed)(struct ieee80211_hw *hw,
2239 u8 hw_queue, u16 index);
2240 void (*tx_polling)(struct ieee80211_hw *hw, u8 hw_queue);
2241 void (*enable_hw_sec)(struct ieee80211_hw *hw);
2242 void (*set_key)(struct ieee80211_hw *hw, u32 key_index,
2243 u8 *macaddr, bool is_group, u8 enc_algo,
2244 bool is_wepkey, bool clear_all);
2245 void (*init_sw_leds)(struct ieee80211_hw *hw);
2246 void (*deinit_sw_leds)(struct ieee80211_hw *hw);
2247 u32 (*get_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2248 void (*set_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2249 u32 data);
2250 u32 (*get_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2251 u32 regaddr, u32 bitmask);
2252 void (*set_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2253 u32 regaddr, u32 bitmask, u32 data);
2254 void (*linked_set_reg)(struct ieee80211_hw *hw);
2255 void (*chk_switch_dmdp)(struct ieee80211_hw *hw);
2256 void (*dualmac_easy_concurrent)(struct ieee80211_hw *hw);
2257 void (*dualmac_switch_to_dmdp)(struct ieee80211_hw *hw);
2258 bool (*phy_rf6052_config)(struct ieee80211_hw *hw);
2259 void (*phy_rf6052_set_cck_txpower)(struct ieee80211_hw *hw,
2260 u8 *powerlevel);
2261 void (*phy_rf6052_set_ofdm_txpower)(struct ieee80211_hw *hw,
2262 u8 *ppowerlevel, u8 channel);
2263 bool (*config_bb_with_headerfile)(struct ieee80211_hw *hw,
2264 u8 configtype);
2265 bool (*config_bb_with_pgheaderfile)(struct ieee80211_hw *hw,
2266 u8 configtype);
2267 void (*phy_lc_calibrate)(struct ieee80211_hw *hw, bool is2t);
2268 void (*phy_set_bw_mode_callback)(struct ieee80211_hw *hw);
2269 void (*dm_dynamic_txpower)(struct ieee80211_hw *hw);
2270 void (*c2h_command_handle)(struct ieee80211_hw *hw);
2271 void (*bt_wifi_media_status_notify)(struct ieee80211_hw *hw,
2272 bool mstate);
2273 void (*bt_coex_off_before_lps)(struct ieee80211_hw *hw);
2274 void (*fill_h2c_cmd)(struct ieee80211_hw *hw, u8 element_id,
2275 u32 cmd_len, u8 *p_cmdbuffer);
2276 void (*set_default_port_id_cmd)(struct ieee80211_hw *hw);
2277 bool (*get_btc_status)(void);
2278 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2279 u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2280 const struct rtl_stats *status,
2281 struct sk_buff *skb);
2282 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2283 struct rtl_wow_pattern *rtl_pattern,
2284 u8 index);
2285 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2286 void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len,
2287 u8 *val);
2288 /* ops for halmac cb */
2289 bool (*halmac_cb_init_mac_register)(struct rtl_priv *rtlpriv);
2290 bool (*halmac_cb_init_bb_rf_register)(struct rtl_priv *rtlpriv);
2291 bool (*halmac_cb_write_data_rsvd_page)(struct rtl_priv *rtlpriv,
2292 u8 *buf, u32 size);
2293 bool (*halmac_cb_write_data_h2c)(struct rtl_priv *rtlpriv, u8 *buf,
2294 u32 size);
2295 /* ops for phydm cb */
2296 u8 (*get_txpower_index)(struct ieee80211_hw *hw, u8 path,
2297 u8 rate, u8 bandwidth, u8 channel);
2298 void (*set_tx_power_index_by_rs)(struct ieee80211_hw *hw,
2299 u8 channel, u8 path,
2300 enum rate_section rs);
2301 void (*store_tx_power_by_rate)(struct ieee80211_hw *hw,
2302 u32 band, u32 rfpath,
2303 u32 txnum, u32 regaddr,
2304 u32 bitmask, u32 data);
2305 void (*phy_set_txpower_limit)(struct ieee80211_hw *hw, u8 *pregulation,
2306 u8 *pband, u8 *pbandwidth,
2307 u8 *prate_section, u8 *prf_path,
2308 u8 *pchannel, u8 *ppower_limit);
2309 };
2310
2311 struct rtl_intf_ops {
2312 /*com */
2313 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2314 int (*adapter_start)(struct ieee80211_hw *hw);
2315 void (*adapter_stop)(struct ieee80211_hw *hw);
2316 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2317 struct rtl_priv **buddy_priv);
2318
2319 int (*adapter_tx)(struct ieee80211_hw *hw,
2320 struct ieee80211_sta *sta,
2321 struct sk_buff *skb,
2322 struct rtl_tcb_desc *ptcb_desc);
2323 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2324 int (*reset_trx_ring)(struct ieee80211_hw *hw);
2325 bool (*waitq_insert)(struct ieee80211_hw *hw,
2326 struct ieee80211_sta *sta,
2327 struct sk_buff *skb);
2328
2329 /*pci */
2330 void (*disable_aspm)(struct ieee80211_hw *hw);
2331 void (*enable_aspm)(struct ieee80211_hw *hw);
2332
2333 /*usb */
2334 };
2335
2336 struct rtl_mod_params {
2337 /* default: 0,0 */
2338 u64 debug_mask;
2339 /* default: 0 = using hardware encryption */
2340 bool sw_crypto;
2341
2342 /* default: 0 = DBG_EMERG (0)*/
2343 int debug_level;
2344
2345 /* default: 1 = using no linked power save */
2346 bool inactiveps;
2347
2348 /* default: 1 = using linked sw power save */
2349 bool swctrl_lps;
2350
2351 /* default: 1 = using linked fw power save */
2352 bool fwctrl_lps;
2353
2354 /* default: 0 = not using MSI interrupts mode
2355 * submodules should set their own default value
2356 */
2357 bool msi_support;
2358
2359 /* default: 0 = dma 32 */
2360 bool dma64;
2361
2362 /* default: 1 = enable aspm */
2363 int aspm_support;
2364
2365 /* default 0: 1 means disable */
2366 bool disable_watchdog;
2367
2368 /* default 0: 1 means do not disable interrupts */
2369 bool int_clear;
2370
2371 /* select antenna */
2372 int ant_sel;
2373 };
2374
2375 struct rtl_hal_usbint_cfg {
2376 /* data - rx */
2377 u32 in_ep_num;
2378 u32 rx_urb_num;
2379 u32 rx_max_size;
2380
2381 /* op - rx */
2382 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2383 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2384 struct sk_buff_head *);
2385
2386 /* tx */
2387 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2388 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2389 struct sk_buff *);
2390 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2391 struct sk_buff_head *);
2392
2393 /* endpoint mapping */
2394 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2395 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2396 };
2397
2398 struct rtl_hal_cfg {
2399 u8 bar_id;
2400 bool write_readback;
2401 char *name;
2402 char *alt_fw_name;
2403 struct rtl_hal_ops *ops;
2404 struct rtl_mod_params *mod_params;
2405 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2406 enum rtl_spec_ver spec_ver;
2407
2408 /* this map used for some registers or vars
2409 * defined int HAL but used in MAIN
2410 */
2411 u32 maps[RTL_VAR_MAP_MAX];
2412
2413 };
2414
2415 struct rtl_locks {
2416 /* mutex */
2417 struct mutex conf_mutex;
2418 struct mutex ips_mutex; /* mutex for enter/leave IPS */
2419 struct mutex lps_mutex; /* mutex for enter/leave LPS */
2420
2421 /*spin lock */
2422 spinlock_t irq_th_lock;
2423 spinlock_t h2c_lock;
2424 spinlock_t rf_ps_lock;
2425 spinlock_t rf_lock;
2426 spinlock_t waitq_lock;
2427 spinlock_t entry_list_lock;
2428 spinlock_t usb_lock;
2429 spinlock_t c2hcmd_lock;
2430 spinlock_t scan_list_lock; /* lock for the scan list */
2431
2432 /*FW clock change */
2433 spinlock_t fw_ps_lock;
2434
2435 /*Dual mac*/
2436 spinlock_t cck_and_rw_pagea_lock;
2437
2438 spinlock_t iqk_lock;
2439 };
2440
2441 struct rtl_works {
2442 struct ieee80211_hw *hw;
2443
2444 /*timer */
2445 struct timer_list watchdog_timer;
2446 struct timer_list dualmac_easyconcurrent_retrytimer;
2447 struct timer_list fw_clockoff_timer;
2448 struct timer_list fast_antenna_training_timer;
2449 /*task */
2450 struct tasklet_struct irq_tasklet;
2451 struct tasklet_struct irq_prepare_bcn_tasklet;
2452
2453 /*work queue */
2454 struct workqueue_struct *rtl_wq;
2455 struct delayed_work watchdog_wq;
2456 struct delayed_work ips_nic_off_wq;
2457 struct delayed_work c2hcmd_wq;
2458
2459 /* For SW LPS */
2460 struct delayed_work ps_work;
2461 struct delayed_work ps_rfon_wq;
2462 struct delayed_work fwevt_wq;
2463
2464 struct work_struct lps_change_work;
2465 struct work_struct fill_h2c_cmd;
2466 };
2467
2468 struct rtl_debug {
2469 /* add for debug */
2470 struct dentry *debugfs_dir;
2471 char debugfs_name[20];
2472
2473 char *msg_buf;
2474 };
2475
2476 #define MIMO_PS_STATIC 0
2477 #define MIMO_PS_DYNAMIC 1
2478 #define MIMO_PS_NOLIMIT 3
2479
2480 struct rtl_dualmac_easy_concurrent_ctl {
2481 enum band_type currentbandtype_backfordmdp;
2482 bool close_bbandrf_for_dmsp;
2483 bool change_to_dmdp;
2484 bool change_to_dmsp;
2485 bool switch_in_process;
2486 };
2487
2488 struct rtl_dmsp_ctl {
2489 bool activescan_for_slaveofdmsp;
2490 bool scan_for_anothermac_fordmsp;
2491 bool scan_for_itself_fordmsp;
2492 bool writedig_for_anothermacofdmsp;
2493 u32 curdigvalue_for_anothermacofdmsp;
2494 bool changecckpdstate_for_anothermacofdmsp;
2495 u8 curcckpdstate_for_anothermacofdmsp;
2496 bool changetxhighpowerlvl_for_anothermacofdmsp;
2497 u8 curtxhighlvl_for_anothermacofdmsp;
2498 long rssivalmin_for_anothermacofdmsp;
2499 };
2500
2501 struct ps_t {
2502 u8 pre_ccastate;
2503 u8 cur_ccasate;
2504 u8 pre_rfstate;
2505 u8 cur_rfstate;
2506 u8 initialize;
2507 long rssi_val_min;
2508 };
2509
2510 struct dig_t {
2511 u32 rssi_lowthresh;
2512 u32 rssi_highthresh;
2513 u32 fa_lowthresh;
2514 u32 fa_highthresh;
2515 long last_min_undec_pwdb_for_dm;
2516 long rssi_highpower_lowthresh;
2517 long rssi_highpower_highthresh;
2518 u32 recover_cnt;
2519 u32 pre_igvalue;
2520 u32 cur_igvalue;
2521 long rssi_val;
2522 u8 dig_enable_flag;
2523 u8 dig_ext_port_stage;
2524 u8 dig_algorithm;
2525 u8 dig_twoport_algorithm;
2526 u8 dig_dbgmode;
2527 u8 dig_slgorithm_switch;
2528 u8 cursta_cstate;
2529 u8 presta_cstate;
2530 u8 curmultista_cstate;
2531 u8 stop_dig;
2532 s8 back_val;
2533 s8 back_range_max;
2534 s8 back_range_min;
2535 u8 rx_gain_max;
2536 u8 rx_gain_min;
2537 u8 min_undec_pwdb_for_dm;
2538 u8 rssi_val_min;
2539 u8 pre_cck_cca_thres;
2540 u8 cur_cck_cca_thres;
2541 u8 pre_cck_pd_state;
2542 u8 cur_cck_pd_state;
2543 u8 pre_cck_fa_state;
2544 u8 cur_cck_fa_state;
2545 u8 pre_ccastate;
2546 u8 cur_ccasate;
2547 u8 large_fa_hit;
2548 u8 forbidden_igi;
2549 u8 dig_state;
2550 u8 dig_highpwrstate;
2551 u8 cur_sta_cstate;
2552 u8 pre_sta_cstate;
2553 u8 cur_ap_cstate;
2554 u8 pre_ap_cstate;
2555 u8 cur_pd_thstate;
2556 u8 pre_pd_thstate;
2557 u8 cur_cs_ratiostate;
2558 u8 pre_cs_ratiostate;
2559 u8 backoff_enable_flag;
2560 s8 backoffval_range_max;
2561 s8 backoffval_range_min;
2562 u8 dig_min_0;
2563 u8 dig_min_1;
2564 u8 bt30_cur_igi;
2565 bool media_connect_0;
2566 bool media_connect_1;
2567
2568 u32 antdiv_rssi_max;
2569 u32 rssi_max;
2570 };
2571
2572 struct rtl_global_var {
2573 /* from this list we can get
2574 * other adapter's rtl_priv
2575 */
2576 struct list_head glb_priv_list;
2577 spinlock_t glb_list_lock;
2578 };
2579
2580 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */
2581
2582 struct rtl_btc_info {
2583 u8 bt_type;
2584 u8 btcoexist;
2585 u8 ant_num;
2586 u8 single_ant_path;
2587
2588 u8 ap_num;
2589 bool in_4way;
2590 unsigned long in_4way_ts;
2591 };
2592
2593 struct bt_coexist_info {
2594 struct rtl_btc_ops *btc_ops;
2595 struct rtl_btc_info btc_info;
2596 /* btc context */
2597 void *btc_context;
2598 void *wifi_only_context;
2599 /* EEPROM BT info. */
2600 u8 eeprom_bt_coexist;
2601 u8 eeprom_bt_type;
2602 u8 eeprom_bt_ant_num;
2603 u8 eeprom_bt_ant_isol;
2604 u8 eeprom_bt_radio_shared;
2605
2606 u8 bt_coexistence;
2607 u8 bt_ant_num;
2608 u8 bt_coexist_type;
2609 u8 bt_state;
2610 u8 bt_cur_state; /* 0:on, 1:off */
2611 u8 bt_ant_isolation; /* 0:good, 1:bad */
2612 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2613 u8 bt_service;
2614 u8 bt_radio_shared_type;
2615 u8 bt_rfreg_origin_1e;
2616 u8 bt_rfreg_origin_1f;
2617 u8 bt_rssi_state;
2618 u32 ratio_tx;
2619 u32 ratio_pri;
2620 u32 bt_edca_ul;
2621 u32 bt_edca_dl;
2622
2623 bool init_set;
2624 bool bt_busy_traffic;
2625 bool bt_traffic_mode_set;
2626 bool bt_non_traffic_mode_set;
2627
2628 bool fw_coexist_all_off;
2629 bool sw_coexist_all_off;
2630 bool hw_coexist_all_off;
2631 u32 cstate;
2632 u32 previous_state;
2633 u32 cstate_h;
2634 u32 previous_state_h;
2635
2636 u8 bt_pre_rssi_state;
2637 u8 bt_pre_rssi_state1;
2638
2639 u8 reg_bt_iso;
2640 u8 reg_bt_sco;
2641 bool balance_on;
2642 u8 bt_active_zero_cnt;
2643 bool cur_bt_disabled;
2644 bool pre_bt_disabled;
2645
2646 u8 bt_profile_case;
2647 u8 bt_profile_action;
2648 bool bt_busy;
2649 bool hold_for_bt_operation;
2650 u8 lps_counter;
2651 };
2652
2653 struct rtl_btc_ops {
2654 void (*btc_init_variables)(struct rtl_priv *rtlpriv);
2655 void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv);
2656 void (*btc_deinit_variables)(struct rtl_priv *rtlpriv);
2657 void (*btc_init_hal_vars)(struct rtl_priv *rtlpriv);
2658 void (*btc_power_on_setting)(struct rtl_priv *rtlpriv);
2659 void (*btc_init_hw_config)(struct rtl_priv *rtlpriv);
2660 void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv);
2661 void (*btc_ips_notify)(struct rtl_priv *rtlpriv, u8 type);
2662 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2663 void (*btc_scan_notify)(struct rtl_priv *rtlpriv, u8 scantype);
2664 void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv,
2665 u8 scantype);
2666 void (*btc_connect_notify)(struct rtl_priv *rtlpriv, u8 action);
2667 void (*btc_mediastatus_notify)(struct rtl_priv *rtlpriv,
2668 enum rt_media_status mstatus);
2669 void (*btc_periodical)(struct rtl_priv *rtlpriv);
2670 void (*btc_halt_notify)(struct rtl_priv *rtlpriv);
2671 void (*btc_btinfo_notify)(struct rtl_priv *rtlpriv,
2672 u8 *tmp_buf, u8 length);
2673 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv,
2674 u8 *tmp_buf, u8 length);
2675 bool (*btc_is_limited_dig)(struct rtl_priv *rtlpriv);
2676 bool (*btc_is_disable_edca_turbo)(struct rtl_priv *rtlpriv);
2677 bool (*btc_is_bt_disabled)(struct rtl_priv *rtlpriv);
2678 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2679 u8 pkt_type);
2680 void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type,
2681 bool scanning);
2682 void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv,
2683 u8 type, bool scanning);
2684 void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv,
2685 struct seq_file *m);
2686 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len);
2687 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv);
2688 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv);
2689 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv);
2690 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg,
2691 u8 *ctrl_agg_size, u8 *agg_size);
2692 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv);
2693 };
2694
2695 struct rtl_halmac_ops {
2696 int (*halmac_init_adapter)(struct rtl_priv *);
2697 int (*halmac_deinit_adapter)(struct rtl_priv *);
2698 int (*halmac_init_hal)(struct rtl_priv *);
2699 int (*halmac_deinit_hal)(struct rtl_priv *);
2700 int (*halmac_poweron)(struct rtl_priv *);
2701 int (*halmac_poweroff)(struct rtl_priv *);
2702
2703 int (*halmac_phy_power_switch)(struct rtl_priv *rtlpriv, u8 enable);
2704 int (*halmac_set_mac_address)(struct rtl_priv *rtlpriv, u8 hwport,
2705 u8 *addr);
2706 int (*halmac_set_bssid)(struct rtl_priv *rtlpriv, u8 hwport, u8 *addr);
2707
2708 int (*halmac_get_physical_efuse_size)(struct rtl_priv *rtlpriv,
2709 u32 *size);
2710 int (*halmac_read_physical_efuse_map)(struct rtl_priv *rtlpriv,
2711 u8 *map, u32 size);
2712 int (*halmac_get_logical_efuse_size)(struct rtl_priv *rtlpriv,
2713 u32 *size);
2714 int (*halmac_read_logical_efuse_map)(struct rtl_priv *rtlpriv, u8 *map,
2715 u32 size);
2716
2717 int (*halmac_set_bandwidth)(struct rtl_priv *rtlpriv, u8 channel,
2718 u8 pri_ch_idx, u8 bw);
2719
2720 int (*halmac_c2h_handle)(struct rtl_priv *rtlpriv, u8 *c2h, u32 size);
2721
2722 int (*halmac_chk_txdesc)(struct rtl_priv *rtlpriv, u8 *txdesc,
2723 u32 size);
2724 };
2725
2726 struct rtl_halmac_indicator {
2727 struct completion *comp;
2728 u32 wait_ms;
2729
2730 u8 *buffer;
2731 u32 buf_size;
2732 u32 ret_size;
2733 u32 status;
2734 };
2735
2736 struct rtl_halmac {
2737 struct rtl_halmac_ops *ops; /* halmac ops (halmac.ko own this object) */
2738 void *internal; /* internal context of halmac, i.e. PHALMAC_ADAPTER */
2739 struct rtl_halmac_indicator *indicator; /* size=10 */
2740
2741 /* flags */
2742 /*
2743 * send_general_info
2744 * 0: no need to call halmac_send_general_info()
2745 * 1: need to call halmac_send_general_info()
2746 */
2747 u8 send_general_info;
2748 };
2749
2750 struct rtl_phydm_params {
2751 u8 mp_chip; /* 1: MP chip, 0: test chip */
2752 u8 fab_ver; /* 0: TSMC, 1: UMC, ...*/
2753 u8 cut_ver; /* 0: A, 1: B, ..., 10: K */
2754 u8 efuse0x3d7; /* default: 0xff */
2755 u8 efuse0x3d8; /* default: 0xff */
2756 };
2757
2758 struct rtl_phydm_ops {
2759 /* init/deinit priv */
2760 int (*phydm_init_priv)(struct rtl_priv *rtlpriv,
2761 struct rtl_phydm_params *params);
2762 int (*phydm_deinit_priv)(struct rtl_priv *rtlpriv);
2763 bool (*phydm_load_txpower_by_rate)(struct rtl_priv *rtlpriv);
2764 bool (*phydm_load_txpower_limit)(struct rtl_priv *rtlpriv);
2765
2766 /* init hw */
2767 int (*phydm_init_dm)(struct rtl_priv *rtlpriv);
2768 int (*phydm_deinit_dm)(struct rtl_priv *rtlpriv);
2769 int (*phydm_reset_dm)(struct rtl_priv *rtlpriv);
2770 bool (*phydm_parameter_init)(struct rtl_priv *rtlpriv, bool post);
2771 bool (*phydm_phy_bb_config)(struct rtl_priv *rtlpriv);
2772 bool (*phydm_phy_rf_config)(struct rtl_priv *rtlpriv);
2773 bool (*phydm_phy_mac_config)(struct rtl_priv *rtlpriv);
2774 bool (*phydm_trx_mode)(struct rtl_priv *rtlpriv,
2775 enum radio_mask tx_path, enum radio_mask rx_path,
2776 bool is_tx2_path);
2777 /* watchdog */
2778 bool (*phydm_watchdog)(struct rtl_priv *rtlpriv);
2779
2780 /* channel */
2781 bool (*phydm_switch_band)(struct rtl_priv *rtlpriv, u8 central_ch);
2782 bool (*phydm_switch_channel)(struct rtl_priv *rtlpriv, u8 central_ch);
2783 bool (*phydm_switch_bandwidth)(struct rtl_priv *rtlpriv,
2784 u8 primary_ch_idx,
2785 enum ht_channel_width width);
2786 bool (*phydm_iq_calibrate)(struct rtl_priv *rtlpriv);
2787 bool (*phydm_clear_txpowertracking_state)(struct rtl_priv *rtlpriv);
2788 bool (*phydm_pause_dig)(struct rtl_priv *rtlpriv, bool pause);
2789
2790 /* read/write reg */
2791 u32 (*phydm_read_rf_reg)(struct rtl_priv *rtlpriv,
2792 enum radio_path rfpath,
2793 u32 addr, u32 mask);
2794 bool (*phydm_write_rf_reg)(struct rtl_priv *rtlpriv,
2795 enum radio_path rfpath,
2796 u32 addr, u32 mask, u32 data);
2797 u8 (*phydm_read_txagc)(struct rtl_priv *rtlpriv,
2798 enum radio_path rfpath, u8 hw_rate);
2799 bool (*phydm_write_txagc)(struct rtl_priv *rtlpriv, u32 power_index,
2800 enum radio_path rfpath, u8 hw_rate);
2801
2802 /* RX */
2803 bool (*phydm_c2h_content_parsing)(struct rtl_priv *rtlpriv, u8 cmd_id,
2804 u8 cmd_len, u8 *content);
2805 bool (*phydm_query_phy_status)(struct rtl_priv *rtlpriv, u8 *phystrpt,
2806 struct ieee80211_hdr *hdr,
2807 struct rtl_stats *pstatus);
2808
2809 /* TX */
2810 u8 (*phydm_rate_id_mapping)(struct rtl_priv *rtlpriv,
2811 enum wireless_mode wireless_mode,
2812 enum rf_type rf_type,
2813 enum ht_channel_width bw);
2814 bool (*phydm_get_ra_bitmap)(struct rtl_priv *rtlpriv,
2815 enum wireless_mode wireless_mode,
2816 enum rf_type rf_type,
2817 enum ht_channel_width bw,
2818 u8 tx_rate_level, /* 0~6 */
2819 u32 *tx_bitmap_msb,
2820 u32 *tx_bitmap_lsb);
2821
2822 /* STA */
2823 bool (*phydm_add_sta)(struct rtl_priv *rtlpriv,
2824 struct ieee80211_sta *sta);
2825 bool (*phydm_del_sta)(struct rtl_priv *rtlpriv,
2826 struct ieee80211_sta *sta);
2827
2828 /* BTC */
2829 u32 (*phydm_get_version)(struct rtl_priv *rtlpriv);
2830 bool (*phydm_modify_ra_pcr_threshold)(struct rtl_priv *rtlpriv,
2831 u8 ra_offset_direction,
2832 u8 ra_threshold_offset);
2833 u32 (*phydm_query_counter)(struct rtl_priv *rtlpriv,
2834 const char *info_type);
2835
2836 /* debug */
2837 bool (*phydm_debug_cmd)(struct rtl_priv *rtlpriv, char *in, u32 in_len,
2838 char *out, u32 out_len);
2839
2840 };
2841
2842 struct rtl_phydm {
2843 struct rtl_phydm_ops *ops;/* phydm ops (phydm_mod.ko own this object) */
2844 void *internal; /* internal context of phydm, i.e. PHY_DM_STRUCT */
2845
2846 u8 adaptivity_en;
2847 /* debug */
2848 u16 forced_data_rate;
2849 u8 forced_igi_lb;
2850 u8 antenna_test;
2851 };
2852
2853 struct proxim {
2854 bool proxim_on;
2855
2856 void *proximity_priv;
2857 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2858 struct sk_buff *skb);
2859 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2860 };
2861
2862 struct rtl_c2hcmd {
2863 struct list_head list;
2864 u8 tag;
2865 u8 len;
2866 u8 *val;
2867 };
2868
2869 struct rtl_bssid_entry {
2870 struct list_head list;
2871 u8 bssid[ETH_ALEN];
2872 u32 age;
2873 };
2874
2875 struct rtl_scan_list {
2876 int num;
2877 struct list_head list; /* sort by age */
2878 };
2879
2880 struct rtl_priv {
2881 struct ieee80211_hw *hw;
2882 struct completion firmware_loading_complete;
2883 struct list_head list;
2884 struct rtl_priv *buddy_priv;
2885 struct rtl_global_var *glb_var;
2886 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2887 struct rtl_dmsp_ctl dmsp_ctl;
2888 struct rtl_locks locks;
2889 struct rtl_works works;
2890 struct rtl_mac mac80211;
2891 struct rtl_hal rtlhal;
2892 struct rtl_regulatory regd;
2893 struct rtl_rfkill rfkill;
2894 struct rtl_io io;
2895 struct rtl_phy phy;
2896 struct rtl_dm dm;
2897 struct rtl_security sec;
2898 struct rtl_efuse efuse;
2899 struct rtl_led_ctl ledctl;
2900 struct rtl_tx_report tx_report;
2901 struct rtl_scan_list scan_list;
2902 struct rtl_ps_ctl psc;
2903 struct rate_adaptive ra;
2904 struct dynamic_primary_cca primarycca;
2905 struct wireless_stats stats;
2906 struct rt_link_detect link_info;
2907 struct false_alarm_statistics falsealm_cnt;
2908 struct rtl_rate_priv *rate_priv;
2909 /* sta entry list for ap adhoc or mesh */
2910 struct list_head entry_list;
2911 /* c2hcmd list for kthread level access */
2912 struct list_head c2hcmd_list;
2913 struct rtl_debug dbg;
2914 int max_fw_size;
2915
2916 /*hal_cfg : for diff cards
2917 *intf_ops : for diff interface usb/pcie
2918 */
2919 struct rtl_hal_cfg *cfg;
2920 const struct rtl_intf_ops *intf_ops;
2921
2922 /* this var will be set by set_bit,
2923 * and was used to indicate status of
2924 * interface or hardware
2925 */
2926 unsigned long status;
2927
2928 /* tables for dm */
2929 struct dig_t dm_digtable;
2930 struct ps_t dm_pstable;
2931
2932 u32 reg_874;
2933 u32 reg_c70;
2934 u32 reg_85c;
2935 u32 reg_a74;
2936 bool reg_init; /* true if regs saved */
2937 bool bt_operation_on;
2938 __le32 *usb_data;
2939 int usb_data_index;
2940 bool initialized;
2941 bool enter_ps; /* true when entering PS */
2942 u8 rate_mask[5];
2943
2944 /* intel Proximity, should be alloc mem
2945 * in intel Proximity module and can only
2946 * be used in intel Proximity mode
2947 */
2948 struct proxim proximity;
2949
2950 /*for bt coexist use*/
2951 struct bt_coexist_info btcoexist;
2952
2953 /* halmac for newer IC. (e.g. 8822B) */
2954 struct rtl_halmac halmac;
2955
2956 /* phydm for newer IC. (e.g. 8822B) */
2957 struct rtl_phydm phydm;
2958
2959 /* separate 92ee from other ICs,
2960 * 92ee use new trx flow.
2961 */
2962 bool use_new_trx_flow;
2963
2964 #ifdef CONFIG_PM
2965 struct wiphy_wowlan_support wowlan;
2966 #endif
2967 /* This must be the last item so
2968 * that it points to the data allocated
2969 * beyond this structure like:
2970 * rtl_pci_priv or rtl_usb_priv
2971 */
2972 u8 priv[0] __aligned(sizeof(void *));
2973 };
2974
2975 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2976 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2977 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2978 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2979 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2980
2981 /***************************************
2982 * Bluetooth Co-existence Related
2983 ***************************************/
2984
2985 enum bt_ant_num {
2986 ANT_X2 = 0,
2987 ANT_X1 = 1,
2988 };
2989
2990 enum bt_co_type {
2991 BT_2WIRE = 0,
2992 BT_ISSC_3WIRE = 1,
2993 BT_ACCEL = 2,
2994 BT_CSR_BC4 = 3,
2995 BT_CSR_BC8 = 4,
2996 BT_RTL8756 = 5,
2997 BT_RTL8723A = 6,
2998 BT_RTL8821A = 7,
2999 BT_RTL8723B = 8,
3000 BT_RTL8192E = 9,
3001 BT_RTL8812A = 11,
3002 BT_RTL8822B = 12,
3003 };
3004
3005 enum bt_total_ant_num {
3006 ANT_TOTAL_X2 = 0,
3007 ANT_TOTAL_X1 = 1
3008 };
3009
3010 enum bt_cur_state {
3011 BT_OFF = 0,
3012 BT_ON = 1,
3013 };
3014
3015 enum bt_service_type {
3016 BT_SCO = 0,
3017 BT_A2DP = 1,
3018 BT_HID = 2,
3019 BT_HID_IDLE = 3,
3020 BT_SCAN = 4,
3021 BT_IDLE = 5,
3022 BT_OTHER_ACTION = 6,
3023 BT_BUSY = 7,
3024 BT_OTHERBUSY = 8,
3025 BT_PAN = 9,
3026 };
3027
3028 enum bt_radio_shared {
3029 BT_RADIO_SHARED = 0,
3030 BT_RADIO_INDIVIDUAL = 1,
3031 };
3032
3033 /****************************************
3034 * mem access macro define start
3035 * Call endian free function when
3036 * 1. Read/write packet content.
3037 * 2. Before write integer to IO.
3038 * 3. After read integer from IO.
3039 ***************************************/
3040 /* Convert little data endian to host ordering */
3041 #define EF1BYTE(_val) \
3042 ((u8)(_val))
3043 #define EF2BYTE(_val) \
3044 (le16_to_cpu(_val))
3045 #define EF4BYTE(_val) \
3046 (le32_to_cpu(_val))
3047
3048 /* Read data from memory */
3049 #define READEF1BYTE(_ptr) \
3050 EF1BYTE(*((u8 *)(_ptr)))
3051 /* Read le16 data from memory and convert to host ordering */
3052 #define READEF2BYTE(_ptr) \
3053 EF2BYTE(*(_ptr))
3054 #define READEF4BYTE(_ptr) \
3055 EF4BYTE(*(_ptr))
3056
3057 /* Create a bit mask
3058 * Examples:
3059 * BIT_LEN_MASK_32(0) => 0x00000000
3060 * BIT_LEN_MASK_32(1) => 0x00000001
3061 * BIT_LEN_MASK_32(2) => 0x00000003
3062 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
3063 */
3064 #define BIT_LEN_MASK_32(__bitlen) \
3065 (0xFFFFFFFF >> (32 - (__bitlen)))
3066 #define BIT_LEN_MASK_16(__bitlen) \
3067 (0xFFFF >> (16 - (__bitlen)))
3068 #define BIT_LEN_MASK_8(__bitlen) \
3069 (0xFF >> (8 - (__bitlen)))
3070
3071 /* Create an offset bit mask
3072 * Examples:
3073 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
3074 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
3075 */
3076 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
3077 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
3078 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
3079 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
3080 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
3081 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
3082
3083 /*Description:
3084 * Return 4-byte value in host byte ordering from
3085 * 4-byte pointer in little-endian system.
3086 */
3087 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
3088 (EF4BYTE(*((__le32 *)(__pstart))))
3089 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
3090 (EF2BYTE(*((__le16 *)(__pstart))))
3091 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
3092 (EF1BYTE(*((u8 *)(__pstart))))
3093
3094 /* Description:
3095 * Translate subfield (continuous bits in little-endian) of 4-byte
3096 * value to host byte ordering.
3097 */
3098 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
3099 ( \
3100 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
3101 BIT_LEN_MASK_32(__bitlen) \
3102 )
3103 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
3104 ( \
3105 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
3106 BIT_LEN_MASK_16(__bitlen) \
3107 )
3108 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
3109 ( \
3110 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
3111 BIT_LEN_MASK_8(__bitlen) \
3112 )
3113
3114 /* Description:
3115 * Mask subfield (continuous bits in little-endian) of 4-byte value
3116 * and return the result in 4-byte value in host byte ordering.
3117 */
3118 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
3119 ( \
3120 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
3121 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
3122 )
3123 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
3124 ( \
3125 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
3126 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
3127 )
3128 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
3129 ( \
3130 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
3131 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
3132 )
3133
3134 /* Description:
3135 * Set subfield of little-endian 4-byte value to specified value.
3136 */
3137 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
3138 (*((__le32 *)(__pstart)) = \
3139 cpu_to_le32( \
3140 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
3141 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
3142 ))
3143 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
3144 (*((__le16 *)(__pstart)) = \
3145 cpu_to_le16( \
3146 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
3147 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
3148 ))
3149 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
3150 (*((u8 *)(__pstart)) = EF1BYTE \
3151 ( \
3152 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
3153 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
3154 ))
3155
3156 #define N_BYTE_ALIGNMENT(__value, __alignment) ((__alignment == 1) ? \
3157 (__value) : (((__value + __alignment - 1) / \
3158 __alignment) * __alignment))
3159
3160 /****************************************
3161 * mem access macro define end
3162 ****************************************/
3163
3164 #define byte(x, n) ((x >> (8 * n)) & 0xff)
3165
3166 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
3167 #define RTL_WATCH_DOG_TIME 2000
3168 #define MSECS(t) msecs_to_jiffies(t)
3169 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
3170 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
3171 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
3172 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
3173 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
3174
3175 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
3176 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
3177 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
3178 /*NIC halt, re-initialize hw parameters*/
3179 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
3180 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
3181 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
3182 /*Always enable ASPM and Clock Req in initialization.*/
3183 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
3184 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
3185 #define RT_PS_LEVEL_ASPM BIT(7)
3186 /*When LPS is on, disable 2R if no packet is received or transmitted.*/
3187 #define RT_RF_LPS_DISALBE_2R BIT(30)
3188 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
3189 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
3190 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
3191 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
3192 (ppsc->cur_ps_level &= (~(_ps_flg)))
3193 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
3194 (ppsc->cur_ps_level |= _ps_flg)
3195
3196 #define container_of_dwork_rtl(x, y, z) \
3197 container_of(to_delayed_work(x), y, z)
3198
3199 #define FILL_OCTET_STRING(_os, _octet, _len) \
3200 (_os).octet = (u8 *)(_octet); \
3201 (_os).length = (_len)
3202
3203 #define CP_MACADDR(des, src) \
3204 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
3205 (des)[2] = (src)[2], (des)[3] = (src)[3],\
3206 (des)[4] = (src)[4], (des)[5] = (src)[5])
3207
3208 #define LDPC_HT_ENABLE_RX BIT(0)
3209 #define LDPC_HT_ENABLE_TX BIT(1)
3210 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
3211 #define LDPC_HT_CAP_TX BIT(3)
3212
3213 #define STBC_HT_ENABLE_RX BIT(0)
3214 #define STBC_HT_ENABLE_TX BIT(1)
3215 #define STBC_HT_TEST_TX_ENABLE BIT(2)
3216 #define STBC_HT_CAP_TX BIT(3)
3217
3218 #define LDPC_VHT_ENABLE_RX BIT(0)
3219 #define LDPC_VHT_ENABLE_TX BIT(1)
3220 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
3221 #define LDPC_VHT_CAP_TX BIT(3)
3222
3223 #define STBC_VHT_ENABLE_RX BIT(0)
3224 #define STBC_VHT_ENABLE_TX BIT(1)
3225 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
3226 #define STBC_VHT_CAP_TX BIT(3)
3227
3228 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G];
3229
3230 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
3231
3232 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
3233 {
3234 return rtlpriv->io.read8_sync(rtlpriv, addr);
3235 }
3236
3237 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
3238 {
3239 return rtlpriv->io.read16_sync(rtlpriv, addr);
3240 }
3241
3242 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
3243 {
3244 return rtlpriv->io.read32_sync(rtlpriv, addr);
3245 }
3246
3247 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
3248 {
3249 rtlpriv->io.write8_async(rtlpriv, addr, val8);
3250
3251 if (rtlpriv->cfg->write_readback)
3252 rtlpriv->io.read8_sync(rtlpriv, addr);
3253 }
3254
3255 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw,
3256 u32 addr, u32 val8)
3257 {
3258 struct rtl_priv *rtlpriv = rtl_priv(hw);
3259
3260 rtl_write_byte(rtlpriv, addr, (u8)val8);
3261 }
3262
3263 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
3264 {
3265 rtlpriv->io.write16_async(rtlpriv, addr, val16);
3266
3267 if (rtlpriv->cfg->write_readback)
3268 rtlpriv->io.read16_sync(rtlpriv, addr);
3269 }
3270
3271 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
3272 u32 addr, u32 val32)
3273 {
3274 rtlpriv->io.write32_async(rtlpriv, addr, val32);
3275
3276 if (rtlpriv->cfg->write_readback)
3277 rtlpriv->io.read32_sync(rtlpriv, addr);
3278 }
3279
3280 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
3281 u32 regaddr, u32 bitmask)
3282 {
3283 struct rtl_priv *rtlpriv = hw->priv;
3284
3285 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
3286 }
3287
3288 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
3289 u32 bitmask, u32 data)
3290 {
3291 struct rtl_priv *rtlpriv = hw->priv;
3292
3293 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
3294 }
3295
3296 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw,
3297 u32 regaddr, u32 data)
3298 {
3299 rtl_set_bbreg(hw, regaddr, 0xffffffff, data);
3300 }
3301
3302 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
3303 enum radio_path rfpath, u32 regaddr,
3304 u32 bitmask)
3305 {
3306 struct rtl_priv *rtlpriv = hw->priv;
3307
3308 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
3309 }
3310
3311 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
3312 enum radio_path rfpath, u32 regaddr,
3313 u32 bitmask, u32 data)
3314 {
3315 struct rtl_priv *rtlpriv = hw->priv;
3316
3317 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
3318 }
3319
3320 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
3321 {
3322 return (rtlhal->state == _HAL_STATE_STOP);
3323 }
3324
3325 static inline void set_hal_start(struct rtl_hal *rtlhal)
3326 {
3327 rtlhal->state = _HAL_STATE_START;
3328 }
3329
3330 static inline void set_hal_stop(struct rtl_hal *rtlhal)
3331 {
3332 rtlhal->state = _HAL_STATE_STOP;
3333 }
3334
3335 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
3336 {
3337 return rtlphy->rf_type;
3338 }
3339
3340 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3341 {
3342 return (struct ieee80211_hdr *)(skb->data);
3343 }
3344
3345 static inline __le16 rtl_get_fc(struct sk_buff *skb)
3346 {
3347 return rtl_get_hdr(skb)->frame_control;
3348 }
3349
3350 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
3351 {
3352 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
3353 }
3354
3355 static inline u16 rtl_get_tid(struct sk_buff *skb)
3356 {
3357 return rtl_get_tid_h(rtl_get_hdr(skb));
3358 }
3359
3360 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3361 struct ieee80211_vif *vif,
3362 const u8 *bssid)
3363 {
3364 return ieee80211_find_sta(vif, bssid);
3365 }
3366
3367 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3368 u8 *mac_addr)
3369 {
3370 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3371
3372 return ieee80211_find_sta(mac->vif, mac_addr);
3373 }
3374
3375 #endif
Linux with added FPC-III support