| blob | f0b16347342659d80100c2df516ba06dd7f6da1e |
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
4 * All rights reserved.
5 *
6 * File: baseband.c
7 *
8 * Purpose: Implement functions to access baseband
9 *
10 * Author: Kyle Hsu
11 *
12 * Date: Aug.22, 2002
13 *
14 * Functions:
15 * BBuGetFrameTime - Calculate data frame transmitting time
16 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal
17 * parameter for baseband Tx
18 * BBbReadEmbedded - Embedded read baseband register via MAC
19 * BBbWriteEmbedded - Embedded write baseband register via MAC
20 * BBbVT3253Init - VIA VT3253 baseband chip init code
21 *
22 * Revision History:
23 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
24 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
25 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and
26 * BBvCalculateParameter().
27 * cancel the setting of MAC_REG_SOFTPWRCTL on
28 * BBbVT3253Init().
29 * Add the comments.
30 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
31 * Modified BBvLoopbackOn & BBvLoopbackOff().
32 *
33 *
34 */
42 /*--------------------- Static Classes ----------------------------*/
44 /*--------------------- Static Variables --------------------------*/
46 /*--------------------- Static Functions --------------------------*/
48 /*--------------------- Export Variables --------------------------*/
50 /*--------------------- Static Definitions -------------------------*/
52 /*--------------------- Static Classes ----------------------------*/
54 /*--------------------- Static Variables --------------------------*/
56 #define CB_VT3253_INIT_FOR_RFMD 446
504 };
506 #define CB_VT3253B0_INIT_FOR_RFMD 256
764 };
766 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
767 /* For RFMD2959 */
768 static
965 };
967 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
968 /* For AIROHA */
969 static
1227 };
1229 #define CB_VT3253B0_INIT_FOR_UW2451 256
1230 /* For UW2451 */
1488 };
1490 #define CB_VT3253B0_AGC 193
1491 /* For AIROHA */
1686 };
1690 };
1692 /*--------------------- Export Variables --------------------------*/
1693 /*
1694 * Description: Calculate data frame transmitting time
1695 *
1696 * Parameters:
1697 * In:
1698 * byPreambleType - Preamble Type
1699 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1700 * cbFrameLength - Baseband Type
1701 * wRate - Tx Rate
1702 * Out:
1703 *
1704 * Return Value: FrameTime
1705 *
1706 */
1707 unsigned int
1712 unsigned short wRate
1713 )
1714 {
1729 else
1735 uFrameTime++;
1738 }
1742 uFrameTime++;
1749 }
1751 /*
1752 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1753 *
1754 * Parameters:
1755 * In:
1756 * priv - Device Structure
1757 * frame_length - Tx Frame Length
1758 * tx_rate - Tx Rate
1759 * Out:
1760 * struct vnt_phy_field *phy
1761 * - pointer to Phy Length field
1762 * - pointer to Phy Service field
1763 * - pointer to Phy Signal field
1764 *
1765 * Return Value: none
1766 *
1767 */
1770 {
1771 u32 bit_count;
1773 u32 tmp;
1792 else
1801 count++;
1805 else
1814 count++;
1818 }
1822 else
1829 else
1836 else
1843 else
1850 else
1857 else
1864 else
1871 else
1878 else
1884 else
1887 }
1897 }
1898 }
1900 /*
1901 * Description: Read a byte from BASEBAND, by embedded programming
1902 *
1903 * Parameters:
1904 * In:
1905 * iobase - I/O base address
1906 * byBBAddr - address of register in Baseband
1907 * Out:
1908 * pbyData - data read
1909 *
1910 * Return Value: true if succeeded; false if failed.
1911 *
1912 */
1915 {
1920 /* BB reg offset */
1923 /* turn on REGR */
1925 /* W_MAX_TIMEOUT is the timeout period */
1930 }
1932 /* get BB data */
1938 }
1940 }
1942 /*
1943 * Description: Write a Byte to BASEBAND, by embedded programming
1944 *
1945 * Parameters:
1946 * In:
1947 * iobase - I/O base address
1948 * byBBAddr - address of register in Baseband
1949 * byData - data to write
1950 * Out:
1951 * none
1952 *
1953 * Return Value: true if succeeded; false if failed.
1954 *
1955 */
1958 {
1963 /* BB reg offset */
1965 /* set BB data */
1968 /* turn on BBREGCTL_REGW */
1970 /* W_MAX_TIMEOUT is the timeout period */
1975 }
1980 }
1982 }
1984 /*
1985 * Description: VIA VT3253 Baseband chip init function
1986 *
1987 * Parameters:
1988 * In:
1989 * iobase - I/O base address
1990 * byRevId - Revision ID
1991 * byRFType - RF type
1992 * Out:
1993 * none
1994 *
1995 * Return Value: true if succeeded; false if failed.
1996 *
1997 */
2000 {
2027 }
2082 /* Init ANT B select,
2083 * TX Config CR09 = 0x61->0x45,
2084 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2085 */
2087 /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/
2089 /* Init ANT B select,
2090 * RX Config CR10 = 0x28->0x2A,
2091 * 0x2A->0x28(VC1/VC2 define,
2092 * make the ANT_A, ANT_B inverted)
2093 */
2095 /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/
2096 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2099 /* {{RobertYu:20050125, request by Jack */
2102 /* }} */
2104 /* {{RobertYu:20050221, request by Jack */
2107 /* }} */
2122 /* }} RobertYu */
2142 /* Fix VT3226 DFC system timing issue */
2144 /* {{ RobertYu: 20050104 */
2151 /* {{ RobertYu:20050223, request by JerryChung */
2152 /* Init ANT B select,TX Config CR09 = 0x61->0x45,
2153 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2154 */
2155 /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/
2156 /* Init ANT B select,RX Config CR10 = 0x28->0x2A,
2157 * 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2158 */
2159 /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/
2160 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2162 /* }} */
2176 /* }} RobertYu */
2178 /* No VGA Table now */
2181 }
2186 }
2189 }
2191 /*
2192 * Description: Set ShortSlotTime mode
2193 *
2194 * Parameters:
2195 * In:
2196 * priv - Device Structure
2197 * Out:
2198 * none
2199 *
2200 * Return Value: none
2201 *
2202 */
2203 void
2205 {
2213 else
2216 /* patch for 3253B0 Baseband with Cardbus module */
2222 }
2225 {
2231 /* patch for 3253B0 Baseband with Cardbus module */
2236 else
2240 }
2242 /*
2243 * Description: Baseband SoftwareReset
2244 *
2245 * Parameters:
2246 * In:
2247 * iobase - I/O base address
2248 * Out:
2249 * none
2250 *
2251 * Return Value: none
2252 *
2253 */
2254 void
2256 {
2261 }
2263 /*
2264 * Description: Baseband Power Save Mode ON
2265 *
2266 * Parameters:
2267 * In:
2268 * iobase - I/O base address
2269 * Out:
2270 * none
2271 *
2272 * Return Value: none
2273 *
2274 */
2275 void
2277 {
2283 }
2285 /*
2286 * Description: Baseband Power Save Mode OFF
2287 *
2288 * Parameters:
2289 * In:
2290 * iobase - I/O base address
2291 * Out:
2292 * none
2293 *
2294 * Return Value: none
2295 *
2296 */
2297 void
2299 {
2305 }
2307 /*
2308 * Description: Set Tx Antenna mode
2309 *
2310 * Parameters:
2311 * In:
2312 * priv - Device Structure
2313 * byAntennaMode - Antenna Mode
2314 * Out:
2315 * none
2316 *
2317 * Return Value: none
2318 *
2319 */
2321 void
2323 {
2328 /* bit 1 is diversity */
2331 /* bit 2 is ANTSEL */
2336 }
2338 }
2340 /*
2341 * Description: Set Rx Antenna mode
2342 *
2343 * Parameters:
2344 * In:
2345 * priv - Device Structure
2346 * byAntennaMode - Antenna Mode
2347 * Out:
2348 * none
2349 *
2350 * Return Value: none
2351 *
2352 */
2354 void
2356 {
2368 }
2370 }
2372 /*
2373 * Description: BBvSetDeepSleep
2374 *
2375 * Parameters:
2376 * In:
2377 * priv - Device Structure
2378 * Out:
2379 * none
2380 *
2381 * Return Value: none
2382 *
2383 */
2384 void
2386 {
2389 }
2391 void
2393 {
2396 }