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Linux 4.16.11
[linux/fpc-iii.git] / drivers / tty / serial / bfin_uart.c
blob4755fa6963210c49fa7b100942f1738dd23d848c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Blackfin On-Chip Serial Driver
4 *
5 * Copyright 2006-2011 Analog Devices Inc.
6 *
7 * Enter bugs at http://blackfin.uclinux.org/
8 */
9
10 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
11 #define SUPPORT_SYSRQ
12 #endif
13
14 #define DRIVER_NAME "bfin-uart"
15 #define pr_fmt(fmt) DRIVER_NAME ": " fmt
16
17 #include <linux/module.h>
18 #include <linux/ioport.h>
19 #include <linux/gfp.h>
20 #include <linux/io.h>
21 #include <linux/init.h>
22 #include <linux/console.h>
23 #include <linux/sysrq.h>
24 #include <linux/platform_device.h>
25 #include <linux/tty.h>
26 #include <linux/tty_flip.h>
27 #include <linux/serial_core.h>
28 #include <linux/gpio.h>
29 #include <linux/irq.h>
30 #include <linux/kgdb.h>
31 #include <linux/slab.h>
32 #include <linux/dma-mapping.h>
33
34 #include <asm/portmux.h>
35 #include <asm/cacheflush.h>
36 #include <asm/dma.h>
37 #include <asm/bfin_serial.h>
38
39 #ifdef CONFIG_SERIAL_BFIN_MODULE
40 # undef CONFIG_EARLY_PRINTK
41 #endif
42
43 /* UART name and device definitions */
44 #define BFIN_SERIAL_DEV_NAME "ttyBF"
45 #define BFIN_SERIAL_MAJOR 204
46 #define BFIN_SERIAL_MINOR 64
47
48 static struct bfin_serial_port *bfin_serial_ports[BFIN_UART_NR_PORTS];
49
50 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
51 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
52
53 # ifndef CONFIG_SERIAL_BFIN_PIO
54 # error KGDB only support UART in PIO mode.
55 # endif
56
57 static int kgdboc_port_line;
58 static int kgdboc_break_enabled;
59 #endif
60 /*
61 * Setup for console. Argument comes from the menuconfig
62 */
63 #define DMA_RX_XCOUNT 512
64 #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
65
66 #define DMA_RX_FLUSH_JIFFIES (HZ / 50)
67
68 #ifdef CONFIG_SERIAL_BFIN_DMA
69 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
70 #else
71 static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
72 #endif
73
74 static void bfin_serial_reset_irda(struct uart_port *port);
75
76 #if defined(SERIAL_BFIN_CTSRTS) || \
77 defined(SERIAL_BFIN_HARD_CTSRTS)
78 static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
79 {
80 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
81 if (uart->cts_pin < 0)
82 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
83
84 /* CTS PIN is negative assertive. */
85 if (UART_GET_CTS(uart))
86 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
87 else
88 return TIOCM_DSR | TIOCM_CAR;
89 }
90
91 static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
92 {
93 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
94 if (uart->rts_pin < 0)
95 return;
96
97 /* RTS PIN is negative assertive. */
98 if (mctrl & TIOCM_RTS)
99 UART_ENABLE_RTS(uart);
100 else
101 UART_DISABLE_RTS(uart);
102 }
103
104 /*
105 * Handle any change of modem status signal.
106 */
107 static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
108 {
109 struct bfin_serial_port *uart = dev_id;
110 struct uart_port *uport = &uart->port;
111 unsigned int status = bfin_serial_get_mctrl(uport);
112 #ifdef SERIAL_BFIN_HARD_CTSRTS
113
114 UART_CLEAR_SCTS(uart);
115 if (uport->hw_stopped) {
116 if (status) {
117 uport->hw_stopped = 0;
118 uart_write_wakeup(uport);
119 }
120 } else {
121 if (!status)
122 uport->hw_stopped = 1;
123 }
124 #else
125 uart_handle_cts_change(uport, status & TIOCM_CTS);
126 #endif
127
128 return IRQ_HANDLED;
129 }
130 #else
131 static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
132 {
133 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
134 }
135
136 static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
137 {
138 }
139 #endif
140
141 /*
142 * interrupts are disabled on entry
143 */
144 static void bfin_serial_stop_tx(struct uart_port *port)
145 {
146 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
147 #ifdef CONFIG_SERIAL_BFIN_DMA
148 struct circ_buf *xmit = &uart->port.state->xmit;
149 #endif
150
151 while (!(UART_GET_LSR(uart) & TEMT))
152 cpu_relax();
153
154 #ifdef CONFIG_SERIAL_BFIN_DMA
155 disable_dma(uart->tx_dma_channel);
156 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
157 uart->port.icount.tx += uart->tx_count;
158 uart->tx_count = 0;
159 uart->tx_done = 1;
160 #else
161 #if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
162 /* Clear TFI bit */
163 UART_PUT_LSR(uart, TFI);
164 #endif
165 UART_CLEAR_IER(uart, ETBEI);
166 #endif
167 }
168
169 /*
170 * port is locked and interrupts are disabled
171 */
172 static void bfin_serial_start_tx(struct uart_port *port)
173 {
174 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
175 struct tty_struct *tty = uart->port.state->port.tty;
176
177 /*
178 * To avoid losting RX interrupt, we reset IR function
179 * before sending data.
180 */
181 if (tty->termios.c_line == N_IRDA)
182 bfin_serial_reset_irda(port);
183
184 #ifdef CONFIG_SERIAL_BFIN_DMA
185 if (uart->tx_done)
186 bfin_serial_dma_tx_chars(uart);
187 #else
188 UART_SET_IER(uart, ETBEI);
189 bfin_serial_tx_chars(uart);
190 #endif
191 }
192
193 /*
194 * Interrupts are enabled
195 */
196 static void bfin_serial_stop_rx(struct uart_port *port)
197 {
198 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
199
200 UART_CLEAR_IER(uart, ERBFI);
201 }
202
203 #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
204 # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
205 # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
206 #else
207 # define UART_GET_ANOMALY_THRESHOLD(uart) 0
208 # define UART_SET_ANOMALY_THRESHOLD(uart, v)
209 #endif
210
211 #ifdef CONFIG_SERIAL_BFIN_PIO
212 static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
213 {
214 unsigned int status, ch, flg;
215 static u64 anomaly_start;
216
217 status = UART_GET_LSR(uart);
218 UART_CLEAR_LSR(uart);
219
220 ch = UART_GET_CHAR(uart);
221 uart->port.icount.rx++;
222
223 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
224 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
225 if (kgdb_connected && kgdboc_port_line == uart->port.line
226 && kgdboc_break_enabled)
227 if (ch == 0x3) {/* Ctrl + C */
228 kgdb_breakpoint();
229 return;
230 }
231
232 if (!uart->port.state)
233 return;
234 #endif
235 if (ANOMALY_05000363) {
236 /* The BF533 (and BF561) family of processors have a nice anomaly
237 * where they continuously generate characters for a "single" break.
238 * We have to basically ignore this flood until the "next" valid
239 * character comes across. Due to the nature of the flood, it is
240 * not possible to reliably catch bytes that are sent too quickly
241 * after this break. So application code talking to the Blackfin
242 * which sends a break signal must allow at least 1.5 character
243 * times after the end of the break for things to stabilize. This
244 * timeout was picked as it must absolutely be larger than 1
245 * character time +/- some percent. So 1.5 sounds good. All other
246 * Blackfin families operate properly. Woo.
247 */
248 if (anomaly_start > 0) {
249 u64 curr, nsecs, threshold_ns;
250
251 if ((~ch & (~ch + 1)) & 0xff)
252 goto known_good_char;
253
254 curr = ktime_get_ns();
255 nsecs = curr - anomaly_start;
256 if (nsecs >> 32)
257 goto known_good_char;
258
259 threshold_ns = UART_GET_ANOMALY_THRESHOLD(uart)
260 * NSEC_PER_USEC;
261 if (nsecs > threshold_ns)
262 goto known_good_char;
263
264 if (ch)
265 anomaly_start = 0;
266 else
267 anomaly_start = curr;
268
269 return;
270
271 known_good_char:
272 status &= ~BI;
273 anomaly_start = 0;
274 }
275 }
276
277 if (status & BI) {
278 if (ANOMALY_05000363)
279 if (bfin_revid() < 5)
280 anomaly_start = ktime_get_ns();
281 uart->port.icount.brk++;
282 if (uart_handle_break(&uart->port))
283 goto ignore_char;
284 status &= ~(PE | FE);
285 }
286 if (status & PE)
287 uart->port.icount.parity++;
288 if (status & OE)
289 uart->port.icount.overrun++;
290 if (status & FE)
291 uart->port.icount.frame++;
292
293 status &= uart->port.read_status_mask;
294
295 if (status & BI)
296 flg = TTY_BREAK;
297 else if (status & PE)
298 flg = TTY_PARITY;
299 else if (status & FE)
300 flg = TTY_FRAME;
301 else
302 flg = TTY_NORMAL;
303
304 if (uart_handle_sysrq_char(&uart->port, ch))
305 goto ignore_char;
306
307 uart_insert_char(&uart->port, status, OE, ch, flg);
308
309 ignore_char:
310 tty_flip_buffer_push(&uart->port.state->port);
311 }
312
313 static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
314 {
315 struct circ_buf *xmit = &uart->port.state->xmit;
316
317 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
318 #if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
319 /* Clear TFI bit */
320 UART_PUT_LSR(uart, TFI);
321 #endif
322 /* Anomaly notes:
323 * 05000215 - we always clear ETBEI within last UART TX
324 * interrupt to end a string. It is always set
325 * when start a new tx.
326 */
327 UART_CLEAR_IER(uart, ETBEI);
328 return;
329 }
330
331 if (uart->port.x_char) {
332 UART_PUT_CHAR(uart, uart->port.x_char);
333 uart->port.icount.tx++;
334 uart->port.x_char = 0;
335 }
336
337 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
338 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
339 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
340 uart->port.icount.tx++;
341 }
342
343 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
344 uart_write_wakeup(&uart->port);
345 }
346
347 static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
348 {
349 struct bfin_serial_port *uart = dev_id;
350
351 while (UART_GET_LSR(uart) & DR)
352 bfin_serial_rx_chars(uart);
353
354 return IRQ_HANDLED;
355 }
356
357 static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
358 {
359 struct bfin_serial_port *uart = dev_id;
360
361 spin_lock(&uart->port.lock);
362 if (UART_GET_LSR(uart) & THRE)
363 bfin_serial_tx_chars(uart);
364 spin_unlock(&uart->port.lock);
365
366 return IRQ_HANDLED;
367 }
368 #endif
369
370 #ifdef CONFIG_SERIAL_BFIN_DMA
371 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
372 {
373 struct circ_buf *xmit = &uart->port.state->xmit;
374
375 uart->tx_done = 0;
376
377 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
378 uart->tx_count = 0;
379 uart->tx_done = 1;
380 return;
381 }
382
383 if (uart->port.x_char) {
384 UART_PUT_CHAR(uart, uart->port.x_char);
385 uart->port.icount.tx++;
386 uart->port.x_char = 0;
387 }
388
389 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
390 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
391 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
392 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
393 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
394 set_dma_config(uart->tx_dma_channel,
395 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
396 INTR_ON_BUF,
397 DIMENSION_LINEAR,
398 DATA_SIZE_8,
399 DMA_SYNC_RESTART));
400 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
401 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
402 set_dma_x_modify(uart->tx_dma_channel, 1);
403 SSYNC();
404 enable_dma(uart->tx_dma_channel);
405
406 UART_SET_IER(uart, ETBEI);
407 }
408
409 static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
410 {
411 int i, flg, status;
412
413 status = UART_GET_LSR(uart);
414 UART_CLEAR_LSR(uart);
415
416 uart->port.icount.rx +=
417 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
418 UART_XMIT_SIZE);
419
420 if (status & BI) {
421 uart->port.icount.brk++;
422 if (uart_handle_break(&uart->port))
423 goto dma_ignore_char;
424 status &= ~(PE | FE);
425 }
426 if (status & PE)
427 uart->port.icount.parity++;
428 if (status & OE)
429 uart->port.icount.overrun++;
430 if (status & FE)
431 uart->port.icount.frame++;
432
433 status &= uart->port.read_status_mask;
434
435 if (status & BI)
436 flg = TTY_BREAK;
437 else if (status & PE)
438 flg = TTY_PARITY;
439 else if (status & FE)
440 flg = TTY_FRAME;
441 else
442 flg = TTY_NORMAL;
443
444 for (i = uart->rx_dma_buf.tail; ; i++) {
445 if (i >= UART_XMIT_SIZE)
446 i = 0;
447 if (i == uart->rx_dma_buf.head)
448 break;
449 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
450 uart_insert_char(&uart->port, status, OE,
451 uart->rx_dma_buf.buf[i], flg);
452 }
453
454 dma_ignore_char:
455 tty_flip_buffer_push(&uart->port.state->port);
456 }
457
458 void bfin_serial_rx_dma_timeout(struct timer_list *t)
459 {
460 struct bfin_serial_port *uart = from_timer(uart, t, rx_dma_timer);
461 int x_pos, pos;
462 unsigned long flags;
463
464 dma_disable_irq_nosync(uart->rx_dma_channel);
465 spin_lock_irqsave(&uart->rx_lock, flags);
466
467 /* 2D DMA RX buffer ring is used. Because curr_y_count and
468 * curr_x_count can't be read as an atomic operation,
469 * curr_y_count should be read before curr_x_count. When
470 * curr_x_count is read, curr_y_count may already indicate
471 * next buffer line. But, the position calculated here is
472 * still indicate the old line. The wrong position data may
473 * be smaller than current buffer tail, which cause garbages
474 * are received if it is not prohibit.
475 */
476 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
477 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
478 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
479 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
480 uart->rx_dma_nrows = 0;
481 x_pos = DMA_RX_XCOUNT - x_pos;
482 if (x_pos == DMA_RX_XCOUNT)
483 x_pos = 0;
484
485 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
486 /* Ignore receiving data if new position is in the same line of
487 * current buffer tail and small.
488 */
489 if (pos > uart->rx_dma_buf.tail ||
490 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
491 uart->rx_dma_buf.head = pos;
492 bfin_serial_dma_rx_chars(uart);
493 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
494 }
495
496 spin_unlock_irqrestore(&uart->rx_lock, flags);
497 dma_enable_irq(uart->rx_dma_channel);
498
499 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
500 }
501
502 static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
503 {
504 struct bfin_serial_port *uart = dev_id;
505 struct circ_buf *xmit = &uart->port.state->xmit;
506
507 spin_lock(&uart->port.lock);
508 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
509 disable_dma(uart->tx_dma_channel);
510 clear_dma_irqstat(uart->tx_dma_channel);
511 /* Anomaly notes:
512 * 05000215 - we always clear ETBEI within last UART TX
513 * interrupt to end a string. It is always set
514 * when start a new tx.
515 */
516 UART_CLEAR_IER(uart, ETBEI);
517 uart->port.icount.tx += uart->tx_count;
518 if (!(xmit->tail == 0 && xmit->head == 0)) {
519 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
520
521 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
522 uart_write_wakeup(&uart->port);
523 }
524
525 bfin_serial_dma_tx_chars(uart);
526 }
527
528 spin_unlock(&uart->port.lock);
529 return IRQ_HANDLED;
530 }
531
532 static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
533 {
534 struct bfin_serial_port *uart = dev_id;
535 unsigned int irqstat;
536 int x_pos, pos;
537
538 spin_lock(&uart->rx_lock);
539 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
540 clear_dma_irqstat(uart->rx_dma_channel);
541
542 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
543 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
544 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
545 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
546 uart->rx_dma_nrows = 0;
547
548 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT;
549 if (pos > uart->rx_dma_buf.tail ||
550 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
551 uart->rx_dma_buf.head = pos;
552 bfin_serial_dma_rx_chars(uart);
553 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
554 }
555
556 spin_unlock(&uart->rx_lock);
557
558 return IRQ_HANDLED;
559 }
560 #endif
561
562 /*
563 * Return TIOCSER_TEMT when transmitter is not busy.
564 */
565 static unsigned int bfin_serial_tx_empty(struct uart_port *port)
566 {
567 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
568 unsigned int lsr;
569
570 lsr = UART_GET_LSR(uart);
571 if (lsr & TEMT)
572 return TIOCSER_TEMT;
573 else
574 return 0;
575 }
576
577 static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
578 {
579 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
580 u32 lcr = UART_GET_LCR(uart);
581 if (break_state)
582 lcr |= SB;
583 else
584 lcr &= ~SB;
585 UART_PUT_LCR(uart, lcr);
586 SSYNC();
587 }
588
589 static int bfin_serial_startup(struct uart_port *port)
590 {
591 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
592
593 #ifdef CONFIG_SERIAL_BFIN_DMA
594 dma_addr_t dma_handle;
595
596 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
597 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
598 return -EBUSY;
599 }
600
601 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
602 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
603 free_dma(uart->rx_dma_channel);
604 return -EBUSY;
605 }
606
607 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
608 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
609
610 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
611 uart->rx_dma_buf.head = 0;
612 uart->rx_dma_buf.tail = 0;
613 uart->rx_dma_nrows = 0;
614
615 set_dma_config(uart->rx_dma_channel,
616 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
617 INTR_ON_ROW, DIMENSION_2D,
618 DATA_SIZE_8,
619 DMA_SYNC_RESTART));
620 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
621 set_dma_x_modify(uart->rx_dma_channel, 1);
622 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
623 set_dma_y_modify(uart->rx_dma_channel, 1);
624 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
625 enable_dma(uart->rx_dma_channel);
626
627 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
628 add_timer(&(uart->rx_dma_timer));
629 #else
630 # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
631 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
632 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
633 kgdboc_break_enabled = 0;
634 else {
635 # endif
636 if (request_irq(uart->rx_irq, bfin_serial_rx_int, 0,
637 "BFIN_UART_RX", uart)) {
638 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
639 return -EBUSY;
640 }
641
642 if (request_irq
643 (uart->tx_irq, bfin_serial_tx_int, 0,
644 "BFIN_UART_TX", uart)) {
645 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
646 free_irq(uart->rx_irq, uart);
647 return -EBUSY;
648 }
649
650 # ifdef CONFIG_BF54x
651 {
652 /*
653 * UART2 and UART3 on BF548 share interrupt PINs and DMA
654 * controllers with SPORT2 and SPORT3. UART rx and tx
655 * interrupts are generated in PIO mode only when configure
656 * their peripheral mapping registers properly, which means
657 * request corresponding DMA channels in PIO mode as well.
658 */
659 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
660
661 switch (uart->rx_irq) {
662 case IRQ_UART3_RX:
663 uart_dma_ch_rx = CH_UART3_RX;
664 uart_dma_ch_tx = CH_UART3_TX;
665 break;
666 case IRQ_UART2_RX:
667 uart_dma_ch_rx = CH_UART2_RX;
668 uart_dma_ch_tx = CH_UART2_TX;
669 break;
670 default:
671 uart_dma_ch_rx = uart_dma_ch_tx = 0;
672 break;
673 }
674
675 if (uart_dma_ch_rx &&
676 request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
677 printk(KERN_NOTICE"Fail to attach UART interrupt\n");
678 free_irq(uart->rx_irq, uart);
679 free_irq(uart->tx_irq, uart);
680 return -EBUSY;
681 }
682 if (uart_dma_ch_tx &&
683 request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
684 printk(KERN_NOTICE "Fail to attach UART interrupt\n");
685 free_dma(uart_dma_ch_rx);
686 free_irq(uart->rx_irq, uart);
687 free_irq(uart->tx_irq, uart);
688 return -EBUSY;
689 }
690 }
691 # endif
692 # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
693 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
694 }
695 # endif
696 #endif
697
698 #ifdef SERIAL_BFIN_CTSRTS
699 if (uart->cts_pin >= 0) {
700 if (request_irq(gpio_to_irq(uart->cts_pin),
701 bfin_serial_mctrl_cts_int,
702 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
703 0, "BFIN_UART_CTS", uart)) {
704 uart->cts_pin = -1;
705 pr_info("Unable to attach BlackFin UART CTS interrupt. So, disable it.\n");
706 }
707 }
708 if (uart->rts_pin >= 0) {
709 if (gpio_request(uart->rts_pin, DRIVER_NAME)) {
710 pr_info("fail to request RTS PIN at GPIO_%d\n", uart->rts_pin);
711 uart->rts_pin = -1;
712 } else
713 gpio_direction_output(uart->rts_pin, 0);
714 }
715 #endif
716 #ifdef SERIAL_BFIN_HARD_CTSRTS
717 if (uart->cts_pin >= 0) {
718 if (request_irq(uart->status_irq, bfin_serial_mctrl_cts_int,
719 0, "BFIN_UART_MODEM_STATUS", uart)) {
720 uart->cts_pin = -1;
721 dev_info(port->dev, "Unable to attach BlackFin UART Modem Status interrupt.\n");
722 }
723
724 /* CTS RTS PINs are negative assertive. */
725 UART_PUT_MCR(uart, UART_GET_MCR(uart) | ACTS);
726 UART_SET_IER(uart, EDSSI);
727 }
728 #endif
729
730 UART_SET_IER(uart, ERBFI);
731 return 0;
732 }
733
734 static void bfin_serial_shutdown(struct uart_port *port)
735 {
736 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
737
738 #ifdef CONFIG_SERIAL_BFIN_DMA
739 disable_dma(uart->tx_dma_channel);
740 free_dma(uart->tx_dma_channel);
741 disable_dma(uart->rx_dma_channel);
742 free_dma(uart->rx_dma_channel);
743 del_timer(&(uart->rx_dma_timer));
744 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
745 #else
746 #ifdef CONFIG_BF54x
747 switch (uart->port.irq) {
748 case IRQ_UART3_RX:
749 free_dma(CH_UART3_RX);
750 free_dma(CH_UART3_TX);
751 break;
752 case IRQ_UART2_RX:
753 free_dma(CH_UART2_RX);
754 free_dma(CH_UART2_TX);
755 break;
756 default:
757 break;
758 }
759 #endif
760 free_irq(uart->rx_irq, uart);
761 free_irq(uart->tx_irq, uart);
762 #endif
763
764 #ifdef SERIAL_BFIN_CTSRTS
765 if (uart->cts_pin >= 0)
766 free_irq(gpio_to_irq(uart->cts_pin), uart);
767 if (uart->rts_pin >= 0)
768 gpio_free(uart->rts_pin);
769 #endif
770 #ifdef SERIAL_BFIN_HARD_CTSRTS
771 if (uart->cts_pin >= 0)
772 free_irq(uart->status_irq, uart);
773 #endif
774 }
775
776 static void
777 bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
778 struct ktermios *old)
779 {
780 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
781 unsigned long flags;
782 unsigned int baud, quot;
783 unsigned int ier, lcr = 0;
784 unsigned long timeout;
785
786 #ifdef SERIAL_BFIN_CTSRTS
787 if (old == NULL && uart->cts_pin != -1)
788 termios->c_cflag |= CRTSCTS;
789 else if (uart->cts_pin == -1)
790 termios->c_cflag &= ~CRTSCTS;
791 #endif
792
793 switch (termios->c_cflag & CSIZE) {
794 case CS8:
795 lcr = WLS(8);
796 break;
797 case CS7:
798 lcr = WLS(7);
799 break;
800 case CS6:
801 lcr = WLS(6);
802 break;
803 case CS5:
804 lcr = WLS(5);
805 break;
806 default:
807 printk(KERN_ERR "%s: word length not supported\n",
808 __func__);
809 }
810
811 /* Anomaly notes:
812 * 05000231 - STOP bit is always set to 1 whatever the user is set.
813 */
814 if (termios->c_cflag & CSTOPB) {
815 if (ANOMALY_05000231)
816 printk(KERN_WARNING "STOP bits other than 1 is not "
817 "supported in case of anomaly 05000231.\n");
818 else
819 lcr |= STB;
820 }
821 if (termios->c_cflag & PARENB)
822 lcr |= PEN;
823 if (!(termios->c_cflag & PARODD))
824 lcr |= EPS;
825 if (termios->c_cflag & CMSPAR)
826 lcr |= STP;
827
828 spin_lock_irqsave(&uart->port.lock, flags);
829
830 port->read_status_mask = OE;
831 if (termios->c_iflag & INPCK)
832 port->read_status_mask |= (FE | PE);
833 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
834 port->read_status_mask |= BI;
835
836 /*
837 * Characters to ignore
838 */
839 port->ignore_status_mask = 0;
840 if (termios->c_iflag & IGNPAR)
841 port->ignore_status_mask |= FE | PE;
842 if (termios->c_iflag & IGNBRK) {
843 port->ignore_status_mask |= BI;
844 /*
845 * If we're ignoring parity and break indicators,
846 * ignore overruns too (for real raw support).
847 */
848 if (termios->c_iflag & IGNPAR)
849 port->ignore_status_mask |= OE;
850 }
851
852 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
853 quot = uart_get_divisor(port, baud);
854
855 /* If discipline is not IRDA, apply ANOMALY_05000230 */
856 if (termios->c_line != N_IRDA)
857 quot -= ANOMALY_05000230;
858
859 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
860
861 /* Wait till the transfer buffer is empty */
862 timeout = jiffies + msecs_to_jiffies(10);
863 while (UART_GET_GCTL(uart) & UCEN && !(UART_GET_LSR(uart) & TEMT))
864 if (time_after(jiffies, timeout)) {
865 dev_warn(port->dev, "timeout waiting for TX buffer empty\n");
866 break;
867 }
868
869 /* Disable UART */
870 ier = UART_GET_IER(uart);
871 UART_PUT_GCTL(uart, UART_GET_GCTL(uart) & ~UCEN);
872 UART_DISABLE_INTS(uart);
873
874 /* Set DLAB in LCR to Access CLK */
875 UART_SET_DLAB(uart);
876
877 UART_PUT_CLK(uart, quot);
878 SSYNC();
879
880 /* Clear DLAB in LCR to Access THR RBR IER */
881 UART_CLEAR_DLAB(uart);
882
883 UART_PUT_LCR(uart, (UART_GET_LCR(uart) & ~LCR_MASK) | lcr);
884
885 /* Enable UART */
886 UART_ENABLE_INTS(uart, ier);
887 UART_PUT_GCTL(uart, UART_GET_GCTL(uart) | UCEN);
888
889 /* Port speed changed, update the per-port timeout. */
890 uart_update_timeout(port, termios->c_cflag, baud);
891
892 spin_unlock_irqrestore(&uart->port.lock, flags);
893 }
894
895 static const char *bfin_serial_type(struct uart_port *port)
896 {
897 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
898
899 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
900 }
901
902 /*
903 * Release the memory region(s) being used by 'port'.
904 */
905 static void bfin_serial_release_port(struct uart_port *port)
906 {
907 }
908
909 /*
910 * Request the memory region(s) being used by 'port'.
911 */
912 static int bfin_serial_request_port(struct uart_port *port)
913 {
914 return 0;
915 }
916
917 /*
918 * Configure/autoconfigure the port.
919 */
920 static void bfin_serial_config_port(struct uart_port *port, int flags)
921 {
922 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
923
924 if (flags & UART_CONFIG_TYPE &&
925 bfin_serial_request_port(&uart->port) == 0)
926 uart->port.type = PORT_BFIN;
927 }
928
929 /*
930 * Verify the new serial_struct (for TIOCSSERIAL).
931 * The only change we allow are to the flags and type, and
932 * even then only between PORT_BFIN and PORT_UNKNOWN
933 */
934 static int
935 bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
936 {
937 return 0;
938 }
939
940 /*
941 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
942 * In other cases, disable IrDA function.
943 */
944 static void bfin_serial_set_ldisc(struct uart_port *port,
945 struct ktermios *termios)
946 {
947 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
948 unsigned int val;
949
950 switch (termios->c_line) {
951 case N_IRDA:
952 val = UART_GET_GCTL(uart);
953 val |= (UMOD_IRDA | RPOLC);
954 UART_PUT_GCTL(uart, val);
955 break;
956 default:
957 val = UART_GET_GCTL(uart);
958 val &= ~(UMOD_MASK | RPOLC);
959 UART_PUT_GCTL(uart, val);
960 }
961 }
962
963 static void bfin_serial_reset_irda(struct uart_port *port)
964 {
965 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
966 unsigned int val;
967
968 val = UART_GET_GCTL(uart);
969 val &= ~(UMOD_MASK | RPOLC);
970 UART_PUT_GCTL(uart, val);
971 SSYNC();
972 val |= (UMOD_IRDA | RPOLC);
973 UART_PUT_GCTL(uart, val);
974 SSYNC();
975 }
976
977 #ifdef CONFIG_CONSOLE_POLL
978 /* Anomaly notes:
979 * 05000099 - Because we only use THRE in poll_put and DR in poll_get,
980 * losing other bits of UART_LSR is not a problem here.
981 */
982 static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
983 {
984 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
985
986 while (!(UART_GET_LSR(uart) & THRE))
987 cpu_relax();
988
989 UART_CLEAR_DLAB(uart);
990 UART_PUT_CHAR(uart, (unsigned char)chr);
991 }
992
993 static int bfin_serial_poll_get_char(struct uart_port *port)
994 {
995 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
996 unsigned char chr;
997
998 while (!(UART_GET_LSR(uart) & DR))
999 cpu_relax();
1000
1001 UART_CLEAR_DLAB(uart);
1002 chr = UART_GET_CHAR(uart);
1003
1004 return chr;
1005 }
1006 #endif
1007
1008 static struct uart_ops bfin_serial_pops = {
1009 .tx_empty = bfin_serial_tx_empty,
1010 .set_mctrl = bfin_serial_set_mctrl,
1011 .get_mctrl = bfin_serial_get_mctrl,
1012 .stop_tx = bfin_serial_stop_tx,
1013 .start_tx = bfin_serial_start_tx,
1014 .stop_rx = bfin_serial_stop_rx,
1015 .break_ctl = bfin_serial_break_ctl,
1016 .startup = bfin_serial_startup,
1017 .shutdown = bfin_serial_shutdown,
1018 .set_termios = bfin_serial_set_termios,
1019 .set_ldisc = bfin_serial_set_ldisc,
1020 .type = bfin_serial_type,
1021 .release_port = bfin_serial_release_port,
1022 .request_port = bfin_serial_request_port,
1023 .config_port = bfin_serial_config_port,
1024 .verify_port = bfin_serial_verify_port,
1025 #ifdef CONFIG_CONSOLE_POLL
1026 .poll_put_char = bfin_serial_poll_put_char,
1027 .poll_get_char = bfin_serial_poll_get_char,
1028 #endif
1029 };
1030
1031 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1032 /*
1033 * If the port was already initialised (eg, by a boot loader),
1034 * try to determine the current setup.
1035 */
1036 static void __init
1037 bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1038 int *parity, int *bits)
1039 {
1040 unsigned int status;
1041
1042 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1043 if (status == (ERBFI | ETBEI)) {
1044 /* ok, the port was enabled */
1045 u32 lcr, clk;
1046
1047 lcr = UART_GET_LCR(uart);
1048
1049 *parity = 'n';
1050 if (lcr & PEN) {
1051 if (lcr & EPS)
1052 *parity = 'e';
1053 else
1054 *parity = 'o';
1055 }
1056 *bits = ((lcr & WLS_MASK) >> WLS_OFFSET) + 5;
1057
1058 /* Set DLAB in LCR to Access CLK */
1059 UART_SET_DLAB(uart);
1060
1061 clk = UART_GET_CLK(uart);
1062
1063 /* Clear DLAB in LCR to Access THR RBR IER */
1064 UART_CLEAR_DLAB(uart);
1065
1066 *baud = get_sclk() / (16*clk);
1067 }
1068 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
1069 }
1070
1071 static struct uart_driver bfin_serial_reg;
1072
1073 static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1074 {
1075 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1076 while (!(UART_GET_LSR(uart) & THRE))
1077 barrier();
1078 UART_PUT_CHAR(uart, ch);
1079 }
1080
1081 #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1082 defined (CONFIG_EARLY_PRINTK) */
1083
1084 #ifdef CONFIG_SERIAL_BFIN_CONSOLE
1085 #define CLASS_BFIN_CONSOLE "bfin-console"
1086 /*
1087 * Interrupts are disabled on entering
1088 */
1089 static void
1090 bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1091 {
1092 struct bfin_serial_port *uart = bfin_serial_ports[co->index];
1093 unsigned long flags;
1094
1095 spin_lock_irqsave(&uart->port.lock, flags);
1096 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1097 spin_unlock_irqrestore(&uart->port.lock, flags);
1098
1099 }
1100
1101 static int __init
1102 bfin_serial_console_setup(struct console *co, char *options)
1103 {
1104 struct bfin_serial_port *uart;
1105 int baud = 57600;
1106 int bits = 8;
1107 int parity = 'n';
1108 # if defined(SERIAL_BFIN_CTSRTS) || \
1109 defined(SERIAL_BFIN_HARD_CTSRTS)
1110 int flow = 'r';
1111 # else
1112 int flow = 'n';
1113 # endif
1114
1115 /*
1116 * Check whether an invalid uart number has been specified, and
1117 * if so, search for the first available port that does have
1118 * console support.
1119 */
1120 if (co->index < 0 || co->index >= BFIN_UART_NR_PORTS)
1121 return -ENODEV;
1122
1123 uart = bfin_serial_ports[co->index];
1124 if (!uart)
1125 return -ENODEV;
1126
1127 if (options)
1128 uart_parse_options(options, &baud, &parity, &bits, &flow);
1129 else
1130 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1131
1132 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
1133 }
1134
1135 static struct console bfin_serial_console = {
1136 .name = BFIN_SERIAL_DEV_NAME,
1137 .write = bfin_serial_console_write,
1138 .device = uart_console_device,
1139 .setup = bfin_serial_console_setup,
1140 .flags = CON_PRINTBUFFER,
1141 .index = -1,
1142 .data = &bfin_serial_reg,
1143 };
1144 #define BFIN_SERIAL_CONSOLE (&bfin_serial_console)
1145 #else
1146 #define BFIN_SERIAL_CONSOLE NULL
1147 #endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1148
1149 #ifdef CONFIG_EARLY_PRINTK
1150 static struct bfin_serial_port bfin_earlyprintk_port;
1151 #define CLASS_BFIN_EARLYPRINTK "bfin-earlyprintk"
1152
1153 /*
1154 * Interrupts are disabled on entering
1155 */
1156 static void
1157 bfin_earlyprintk_console_write(struct console *co, const char *s, unsigned int count)
1158 {
1159 unsigned long flags;
1160
1161 if (bfin_earlyprintk_port.port.line != co->index)
1162 return;
1163
1164 spin_lock_irqsave(&bfin_earlyprintk_port.port.lock, flags);
1165 uart_console_write(&bfin_earlyprintk_port.port, s, count,
1166 bfin_serial_console_putchar);
1167 spin_unlock_irqrestore(&bfin_earlyprintk_port.port.lock, flags);
1168 }
1169
1170 /*
1171 * This should have a .setup or .early_setup in it, but then things get called
1172 * without the command line options, and the baud rate gets messed up - so
1173 * don't let the common infrastructure play with things. (see calls to setup
1174 * & earlysetup in ./kernel/printk.c:register_console()
1175 */
1176 static struct console bfin_early_serial_console __initdata = {
1177 .name = "early_BFuart",
1178 .write = bfin_earlyprintk_console_write,
1179 .device = uart_console_device,
1180 .flags = CON_PRINTBUFFER,
1181 .index = -1,
1182 .data = &bfin_serial_reg,
1183 };
1184 #endif
1185
1186 static struct uart_driver bfin_serial_reg = {
1187 .owner = THIS_MODULE,
1188 .driver_name = DRIVER_NAME,
1189 .dev_name = BFIN_SERIAL_DEV_NAME,
1190 .major = BFIN_SERIAL_MAJOR,
1191 .minor = BFIN_SERIAL_MINOR,
1192 .nr = BFIN_UART_NR_PORTS,
1193 .cons = BFIN_SERIAL_CONSOLE,
1194 };
1195
1196 static int bfin_serial_suspend(struct platform_device *pdev, pm_message_t state)
1197 {
1198 struct bfin_serial_port *uart = platform_get_drvdata(pdev);
1199
1200 return uart_suspend_port(&bfin_serial_reg, &uart->port);
1201 }
1202
1203 static int bfin_serial_resume(struct platform_device *pdev)
1204 {
1205 struct bfin_serial_port *uart = platform_get_drvdata(pdev);
1206
1207 return uart_resume_port(&bfin_serial_reg, &uart->port);
1208 }
1209
1210 static int bfin_serial_probe(struct platform_device *pdev)
1211 {
1212 struct resource *res;
1213 struct bfin_serial_port *uart = NULL;
1214 int ret = 0;
1215
1216 if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
1217 dev_err(&pdev->dev, "Wrong bfin uart platform device id.\n");
1218 return -ENOENT;
1219 }
1220
1221 if (bfin_serial_ports[pdev->id] == NULL) {
1222
1223 uart = kzalloc(sizeof(*uart), GFP_KERNEL);
1224 if (!uart) {
1225 dev_err(&pdev->dev,
1226 "fail to malloc bfin_serial_port\n");
1227 return -ENOMEM;
1228 }
1229 bfin_serial_ports[pdev->id] = uart;
1230
1231 #ifdef CONFIG_EARLY_PRINTK
1232 if (!(bfin_earlyprintk_port.port.membase
1233 && bfin_earlyprintk_port.port.line == pdev->id)) {
1234 /*
1235 * If the peripheral PINs of current port is allocated
1236 * in earlyprintk probe stage, don't do it again.
1237 */
1238 #endif
1239 ret = peripheral_request_list(
1240 dev_get_platdata(&pdev->dev),
1241 DRIVER_NAME);
1242 if (ret) {
1243 dev_err(&pdev->dev,
1244 "fail to request bfin serial peripherals\n");
1245 goto out_error_free_mem;
1246 }
1247 #ifdef CONFIG_EARLY_PRINTK
1248 }
1249 #endif
1250
1251 spin_lock_init(&uart->port.lock);
1252 uart->port.uartclk = get_sclk();
1253 uart->port.fifosize = BFIN_UART_TX_FIFO_SIZE;
1254 uart->port.ops = &bfin_serial_pops;
1255 uart->port.line = pdev->id;
1256 uart->port.iotype = UPIO_MEM;
1257 uart->port.flags = UPF_BOOT_AUTOCONF;
1258
1259 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1260 if (res == NULL) {
1261 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
1262 ret = -ENOENT;
1263 goto out_error_free_peripherals;
1264 }
1265
1266 uart->port.membase = ioremap(res->start, resource_size(res));
1267 if (!uart->port.membase) {
1268 dev_err(&pdev->dev, "Cannot map uart IO\n");
1269 ret = -ENXIO;
1270 goto out_error_free_peripherals;
1271 }
1272 uart->port.mapbase = res->start;
1273
1274 uart->tx_irq = platform_get_irq(pdev, 0);
1275 if (uart->tx_irq < 0) {
1276 dev_err(&pdev->dev, "No uart TX IRQ specified\n");
1277 ret = -ENOENT;
1278 goto out_error_unmap;
1279 }
1280
1281 uart->rx_irq = platform_get_irq(pdev, 1);
1282 if (uart->rx_irq < 0) {
1283 dev_err(&pdev->dev, "No uart RX IRQ specified\n");
1284 ret = -ENOENT;
1285 goto out_error_unmap;
1286 }
1287 uart->port.irq = uart->rx_irq;
1288
1289 uart->status_irq = platform_get_irq(pdev, 2);
1290 if (uart->status_irq < 0) {
1291 dev_err(&pdev->dev, "No uart status IRQ specified\n");
1292 ret = -ENOENT;
1293 goto out_error_unmap;
1294 }
1295
1296 #ifdef CONFIG_SERIAL_BFIN_DMA
1297 spin_lock_init(&uart->rx_lock);
1298 uart->tx_done = 1;
1299 uart->tx_count = 0;
1300
1301 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1302 if (res == NULL) {
1303 dev_err(&pdev->dev, "No uart TX DMA channel specified\n");
1304 ret = -ENOENT;
1305 goto out_error_unmap;
1306 }
1307 uart->tx_dma_channel = res->start;
1308
1309 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1310 if (res == NULL) {
1311 dev_err(&pdev->dev, "No uart RX DMA channel specified\n");
1312 ret = -ENOENT;
1313 goto out_error_unmap;
1314 }
1315 uart->rx_dma_channel = res->start;
1316
1317 timer_setup(&uart->rx_dma_timer, bfin_serial_rx_dma_timeout, 0);
1318 #endif
1319
1320 #if defined(SERIAL_BFIN_CTSRTS) || \
1321 defined(SERIAL_BFIN_HARD_CTSRTS)
1322 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1323 if (res == NULL)
1324 uart->cts_pin = -1;
1325 else
1326 uart->cts_pin = res->start;
1327
1328 res = platform_get_resource(pdev, IORESOURCE_IO, 1);
1329 if (res == NULL)
1330 uart->rts_pin = -1;
1331 else
1332 uart->rts_pin = res->start;
1333 #endif
1334 }
1335
1336 #ifdef CONFIG_SERIAL_BFIN_CONSOLE
1337 if (!is_early_platform_device(pdev)) {
1338 #endif
1339 uart = bfin_serial_ports[pdev->id];
1340 uart->port.dev = &pdev->dev;
1341 dev_set_drvdata(&pdev->dev, uart);
1342 ret = uart_add_one_port(&bfin_serial_reg, &uart->port);
1343 #ifdef CONFIG_SERIAL_BFIN_CONSOLE
1344 }
1345 #endif
1346
1347 if (!ret)
1348 return 0;
1349
1350 if (uart) {
1351 out_error_unmap:
1352 iounmap(uart->port.membase);
1353 out_error_free_peripherals:
1354 peripheral_free_list(dev_get_platdata(&pdev->dev));
1355 out_error_free_mem:
1356 kfree(uart);
1357 bfin_serial_ports[pdev->id] = NULL;
1358 }
1359
1360 return ret;
1361 }
1362
1363 static int bfin_serial_remove(struct platform_device *pdev)
1364 {
1365 struct bfin_serial_port *uart = platform_get_drvdata(pdev);
1366
1367 dev_set_drvdata(&pdev->dev, NULL);
1368
1369 if (uart) {
1370 uart_remove_one_port(&bfin_serial_reg, &uart->port);
1371 iounmap(uart->port.membase);
1372 peripheral_free_list(dev_get_platdata(&pdev->dev));
1373 kfree(uart);
1374 bfin_serial_ports[pdev->id] = NULL;
1375 }
1376
1377 return 0;
1378 }
1379
1380 static struct platform_driver bfin_serial_driver = {
1381 .probe = bfin_serial_probe,
1382 .remove = bfin_serial_remove,
1383 .suspend = bfin_serial_suspend,
1384 .resume = bfin_serial_resume,
1385 .driver = {
1386 .name = DRIVER_NAME,
1387 },
1388 };
1389
1390 #if defined(CONFIG_SERIAL_BFIN_CONSOLE)
1391 static struct early_platform_driver early_bfin_serial_driver __initdata = {
1392 .class_str = CLASS_BFIN_CONSOLE,
1393 .pdrv = &bfin_serial_driver,
1394 .requested_id = EARLY_PLATFORM_ID_UNSET,
1395 };
1396
1397 static int __init bfin_serial_rs_console_init(void)
1398 {
1399 early_platform_driver_register(&early_bfin_serial_driver, DRIVER_NAME);
1400
1401 early_platform_driver_probe(CLASS_BFIN_CONSOLE, BFIN_UART_NR_PORTS, 0);
1402
1403 register_console(&bfin_serial_console);
1404
1405 return 0;
1406 }
1407 console_initcall(bfin_serial_rs_console_init);
1408 #endif
1409
1410 #ifdef CONFIG_EARLY_PRINTK
1411 /*
1412 * Memory can't be allocated dynamically during earlyprink init stage.
1413 * So, do individual probe for earlyprink with a static uart port variable.
1414 */
1415 static int bfin_earlyprintk_probe(struct platform_device *pdev)
1416 {
1417 struct resource *res;
1418 int ret;
1419
1420 if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
1421 dev_err(&pdev->dev, "Wrong earlyprintk platform device id.\n");
1422 return -ENOENT;
1423 }
1424
1425 ret = peripheral_request_list(dev_get_platdata(&pdev->dev),
1426 DRIVER_NAME);
1427 if (ret) {
1428 dev_err(&pdev->dev,
1429 "fail to request bfin serial peripherals\n");
1430 return ret;
1431 }
1432
1433 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1434 if (res == NULL) {
1435 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
1436 ret = -ENOENT;
1437 goto out_error_free_peripherals;
1438 }
1439
1440 bfin_earlyprintk_port.port.membase = ioremap(res->start,
1441 resource_size(res));
1442 if (!bfin_earlyprintk_port.port.membase) {
1443 dev_err(&pdev->dev, "Cannot map uart IO\n");
1444 ret = -ENXIO;
1445 goto out_error_free_peripherals;
1446 }
1447 bfin_earlyprintk_port.port.mapbase = res->start;
1448 bfin_earlyprintk_port.port.line = pdev->id;
1449 bfin_earlyprintk_port.port.uartclk = get_sclk();
1450 bfin_earlyprintk_port.port.fifosize = BFIN_UART_TX_FIFO_SIZE;
1451 spin_lock_init(&bfin_earlyprintk_port.port.lock);
1452
1453 return 0;
1454
1455 out_error_free_peripherals:
1456 peripheral_free_list(dev_get_platdata(&pdev->dev));
1457
1458 return ret;
1459 }
1460
1461 static struct platform_driver bfin_earlyprintk_driver = {
1462 .probe = bfin_earlyprintk_probe,
1463 .driver = {
1464 .name = DRIVER_NAME,
1465 .owner = THIS_MODULE,
1466 },
1467 };
1468
1469 static struct early_platform_driver early_bfin_earlyprintk_driver __initdata = {
1470 .class_str = CLASS_BFIN_EARLYPRINTK,
1471 .pdrv = &bfin_earlyprintk_driver,
1472 .requested_id = EARLY_PLATFORM_ID_UNSET,
1473 };
1474
1475 struct console __init *bfin_earlyserial_init(unsigned int port,
1476 unsigned int cflag)
1477 {
1478 struct ktermios t;
1479 char port_name[20];
1480
1481 if (port < 0 || port >= BFIN_UART_NR_PORTS)
1482 return NULL;
1483
1484 /*
1485 * Only probe resource of the given port in earlyprintk boot arg.
1486 * The expected port id should be indicated in port name string.
1487 */
1488 snprintf(port_name, 20, DRIVER_NAME ".%d", port);
1489 early_platform_driver_register(&early_bfin_earlyprintk_driver,
1490 port_name);
1491 early_platform_driver_probe(CLASS_BFIN_EARLYPRINTK, 1, 0);
1492
1493 if (!bfin_earlyprintk_port.port.membase)
1494 return NULL;
1495
1496 #ifdef CONFIG_SERIAL_BFIN_CONSOLE
1497 /*
1498 * If we are using early serial, don't let the normal console rewind
1499 * log buffer, since that causes things to be printed multiple times
1500 */
1501 bfin_serial_console.flags &= ~CON_PRINTBUFFER;
1502 #endif
1503
1504 bfin_early_serial_console.index = port;
1505 t.c_cflag = cflag;
1506 t.c_iflag = 0;
1507 t.c_oflag = 0;
1508 t.c_lflag = ICANON;
1509 t.c_line = port;
1510 bfin_serial_set_termios(&bfin_earlyprintk_port.port, &t, &t);
1511
1512 return &bfin_early_serial_console;
1513 }
1514 #endif /* CONFIG_EARLY_PRINTK */
1515
1516 static int __init bfin_serial_init(void)
1517 {
1518 int ret;
1519
1520 pr_info("Blackfin serial driver\n");
1521
1522 ret = uart_register_driver(&bfin_serial_reg);
1523 if (ret) {
1524 pr_err("failed to register %s:%d\n",
1525 bfin_serial_reg.driver_name, ret);
1526 }
1527
1528 ret = platform_driver_register(&bfin_serial_driver);
1529 if (ret) {
1530 pr_err("fail to register bfin uart\n");
1531 uart_unregister_driver(&bfin_serial_reg);
1532 }
1533
1534 return ret;
1535 }
1536
1537 static void __exit bfin_serial_exit(void)
1538 {
1539 platform_driver_unregister(&bfin_serial_driver);
1540 uart_unregister_driver(&bfin_serial_reg);
1541 }
1542
1543
1544 module_init(bfin_serial_init);
1545 module_exit(bfin_serial_exit);
1546
1547 MODULE_AUTHOR("Sonic Zhang, Aubrey Li");
1548 MODULE_DESCRIPTION("Blackfin generic serial port driver");
1549 MODULE_LICENSE("GPL");
1550 MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
1551 MODULE_ALIAS("platform:bfin-uart");
Linux with added FPC-III support