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Linux 4.16.11
[linux/fpc-iii.git] / drivers / tty / serial / efm32-uart.c
blobd6b5e5463746ece5bd20232c7e00f1848f38b0b4
1 // SPDX-License-Identifier: GPL-2.0
2 #if defined(CONFIG_SERIAL_EFM32_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
3 #define SUPPORT_SYSRQ
4 #endif
5
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/io.h>
9 #include <linux/platform_device.h>
10 #include <linux/console.h>
11 #include <linux/sysrq.h>
12 #include <linux/serial_core.h>
13 #include <linux/tty_flip.h>
14 #include <linux/slab.h>
15 #include <linux/clk.h>
16 #include <linux/of.h>
17 #include <linux/of_device.h>
18
19 #include <linux/platform_data/efm32-uart.h>
20
21 #define DRIVER_NAME "efm32-uart"
22 #define DEV_NAME "ttyefm"
23
24 #define UARTn_CTRL 0x00
25 #define UARTn_CTRL_SYNC 0x0001
26 #define UARTn_CTRL_TXBIL 0x1000
27
28 #define UARTn_FRAME 0x04
29 #define UARTn_FRAME_DATABITS__MASK 0x000f
30 #define UARTn_FRAME_DATABITS(n) ((n) - 3)
31 #define UARTn_FRAME_PARITY__MASK 0x0300
32 #define UARTn_FRAME_PARITY_NONE 0x0000
33 #define UARTn_FRAME_PARITY_EVEN 0x0200
34 #define UARTn_FRAME_PARITY_ODD 0x0300
35 #define UARTn_FRAME_STOPBITS_HALF 0x0000
36 #define UARTn_FRAME_STOPBITS_ONE 0x1000
37 #define UARTn_FRAME_STOPBITS_TWO 0x3000
38
39 #define UARTn_CMD 0x0c
40 #define UARTn_CMD_RXEN 0x0001
41 #define UARTn_CMD_RXDIS 0x0002
42 #define UARTn_CMD_TXEN 0x0004
43 #define UARTn_CMD_TXDIS 0x0008
44
45 #define UARTn_STATUS 0x10
46 #define UARTn_STATUS_TXENS 0x0002
47 #define UARTn_STATUS_TXC 0x0020
48 #define UARTn_STATUS_TXBL 0x0040
49 #define UARTn_STATUS_RXDATAV 0x0080
50
51 #define UARTn_CLKDIV 0x14
52
53 #define UARTn_RXDATAX 0x18
54 #define UARTn_RXDATAX_RXDATA__MASK 0x01ff
55 #define UARTn_RXDATAX_PERR 0x4000
56 #define UARTn_RXDATAX_FERR 0x8000
57 /*
58 * This is a software only flag used for ignore_status_mask and
59 * read_status_mask! It's used for breaks that the hardware doesn't report
60 * explicitly.
61 */
62 #define SW_UARTn_RXDATAX_BERR 0x2000
63
64 #define UARTn_TXDATA 0x34
65
66 #define UARTn_IF 0x40
67 #define UARTn_IF_TXC 0x0001
68 #define UARTn_IF_TXBL 0x0002
69 #define UARTn_IF_RXDATAV 0x0004
70 #define UARTn_IF_RXOF 0x0010
71
72 #define UARTn_IFS 0x44
73 #define UARTn_IFC 0x48
74 #define UARTn_IEN 0x4c
75
76 #define UARTn_ROUTE 0x54
77 #define UARTn_ROUTE_LOCATION__MASK 0x0700
78 #define UARTn_ROUTE_LOCATION(n) (((n) << 8) & UARTn_ROUTE_LOCATION__MASK)
79 #define UARTn_ROUTE_RXPEN 0x0001
80 #define UARTn_ROUTE_TXPEN 0x0002
81
82 struct efm32_uart_port {
83 struct uart_port port;
84 unsigned int txirq;
85 struct clk *clk;
86 struct efm32_uart_pdata pdata;
87 };
88 #define to_efm_port(_port) container_of(_port, struct efm32_uart_port, port)
89 #define efm_debug(efm_port, format, arg...) \
90 dev_dbg(efm_port->port.dev, format, ##arg)
91
92 static void efm32_uart_write32(struct efm32_uart_port *efm_port,
93 u32 value, unsigned offset)
94 {
95 writel_relaxed(value, efm_port->port.membase + offset);
96 }
97
98 static u32 efm32_uart_read32(struct efm32_uart_port *efm_port,
99 unsigned offset)
100 {
101 return readl_relaxed(efm_port->port.membase + offset);
102 }
103
104 static unsigned int efm32_uart_tx_empty(struct uart_port *port)
105 {
106 struct efm32_uart_port *efm_port = to_efm_port(port);
107 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
108
109 if (status & UARTn_STATUS_TXC)
110 return TIOCSER_TEMT;
111 else
112 return 0;
113 }
114
115 static void efm32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
116 {
117 /* sorry, neither handshaking lines nor loop functionallity */
118 }
119
120 static unsigned int efm32_uart_get_mctrl(struct uart_port *port)
121 {
122 /* sorry, no handshaking lines available */
123 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
124 }
125
126 static void efm32_uart_stop_tx(struct uart_port *port)
127 {
128 struct efm32_uart_port *efm_port = to_efm_port(port);
129 u32 ien = efm32_uart_read32(efm_port, UARTn_IEN);
130
131 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
132 ien &= ~(UARTn_IF_TXC | UARTn_IF_TXBL);
133 efm32_uart_write32(efm_port, ien, UARTn_IEN);
134 }
135
136 static void efm32_uart_tx_chars(struct efm32_uart_port *efm_port)
137 {
138 struct uart_port *port = &efm_port->port;
139 struct circ_buf *xmit = &port->state->xmit;
140
141 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
142 UARTn_STATUS_TXBL) {
143 if (port->x_char) {
144 port->icount.tx++;
145 efm32_uart_write32(efm_port, port->x_char,
146 UARTn_TXDATA);
147 port->x_char = 0;
148 continue;
149 }
150 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
151 port->icount.tx++;
152 efm32_uart_write32(efm_port, xmit->buf[xmit->tail],
153 UARTn_TXDATA);
154 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
155 } else
156 break;
157 }
158
159 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
160 uart_write_wakeup(port);
161
162 if (!port->x_char && uart_circ_empty(xmit) &&
163 efm32_uart_read32(efm_port, UARTn_STATUS) &
164 UARTn_STATUS_TXC)
165 efm32_uart_stop_tx(port);
166 }
167
168 static void efm32_uart_start_tx(struct uart_port *port)
169 {
170 struct efm32_uart_port *efm_port = to_efm_port(port);
171 u32 ien;
172
173 efm32_uart_write32(efm_port,
174 UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IFC);
175 ien = efm32_uart_read32(efm_port, UARTn_IEN);
176 efm32_uart_write32(efm_port,
177 ien | UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IEN);
178 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
179
180 efm32_uart_tx_chars(efm_port);
181 }
182
183 static void efm32_uart_stop_rx(struct uart_port *port)
184 {
185 struct efm32_uart_port *efm_port = to_efm_port(port);
186
187 efm32_uart_write32(efm_port, UARTn_CMD_RXDIS, UARTn_CMD);
188 }
189
190 static void efm32_uart_break_ctl(struct uart_port *port, int ctl)
191 {
192 /* not possible without fiddling with gpios */
193 }
194
195 static void efm32_uart_rx_chars(struct efm32_uart_port *efm_port)
196 {
197 struct uart_port *port = &efm_port->port;
198
199 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
200 UARTn_STATUS_RXDATAV) {
201 u32 rxdata = efm32_uart_read32(efm_port, UARTn_RXDATAX);
202 int flag = 0;
203
204 /*
205 * This is a reserved bit and I only saw it read as 0. But to be
206 * sure not to be confused too much by new devices adhere to the
207 * warning in the reference manual that reserverd bits might
208 * read as 1 in the future.
209 */
210 rxdata &= ~SW_UARTn_RXDATAX_BERR;
211
212 port->icount.rx++;
213
214 if ((rxdata & UARTn_RXDATAX_FERR) &&
215 !(rxdata & UARTn_RXDATAX_RXDATA__MASK)) {
216 rxdata |= SW_UARTn_RXDATAX_BERR;
217 port->icount.brk++;
218 if (uart_handle_break(port))
219 continue;
220 } else if (rxdata & UARTn_RXDATAX_PERR)
221 port->icount.parity++;
222 else if (rxdata & UARTn_RXDATAX_FERR)
223 port->icount.frame++;
224
225 rxdata &= port->read_status_mask;
226
227 if (rxdata & SW_UARTn_RXDATAX_BERR)
228 flag = TTY_BREAK;
229 else if (rxdata & UARTn_RXDATAX_PERR)
230 flag = TTY_PARITY;
231 else if (rxdata & UARTn_RXDATAX_FERR)
232 flag = TTY_FRAME;
233 else if (uart_handle_sysrq_char(port,
234 rxdata & UARTn_RXDATAX_RXDATA__MASK))
235 continue;
236
237 if ((rxdata & port->ignore_status_mask) == 0)
238 tty_insert_flip_char(&port->state->port,
239 rxdata & UARTn_RXDATAX_RXDATA__MASK, flag);
240 }
241 }
242
243 static irqreturn_t efm32_uart_rxirq(int irq, void *data)
244 {
245 struct efm32_uart_port *efm_port = data;
246 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
247 int handled = IRQ_NONE;
248 struct uart_port *port = &efm_port->port;
249 struct tty_port *tport = &port->state->port;
250
251 spin_lock(&port->lock);
252
253 if (irqflag & UARTn_IF_RXDATAV) {
254 efm32_uart_write32(efm_port, UARTn_IF_RXDATAV, UARTn_IFC);
255 efm32_uart_rx_chars(efm_port);
256
257 handled = IRQ_HANDLED;
258 }
259
260 if (irqflag & UARTn_IF_RXOF) {
261 efm32_uart_write32(efm_port, UARTn_IF_RXOF, UARTn_IFC);
262 port->icount.overrun++;
263 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
264
265 handled = IRQ_HANDLED;
266 }
267
268 spin_unlock(&port->lock);
269
270 tty_flip_buffer_push(tport);
271
272 return handled;
273 }
274
275 static irqreturn_t efm32_uart_txirq(int irq, void *data)
276 {
277 struct efm32_uart_port *efm_port = data;
278 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
279
280 /* TXBL doesn't need to be cleared */
281 if (irqflag & UARTn_IF_TXC)
282 efm32_uart_write32(efm_port, UARTn_IF_TXC, UARTn_IFC);
283
284 if (irqflag & (UARTn_IF_TXC | UARTn_IF_TXBL)) {
285 efm32_uart_tx_chars(efm_port);
286 return IRQ_HANDLED;
287 } else
288 return IRQ_NONE;
289 }
290
291 static int efm32_uart_startup(struct uart_port *port)
292 {
293 struct efm32_uart_port *efm_port = to_efm_port(port);
294 int ret;
295
296 ret = clk_enable(efm_port->clk);
297 if (ret) {
298 efm_debug(efm_port, "failed to enable clk\n");
299 goto err_clk_enable;
300 }
301 port->uartclk = clk_get_rate(efm_port->clk);
302
303 /* Enable pins at configured location */
304 efm32_uart_write32(efm_port,
305 UARTn_ROUTE_LOCATION(efm_port->pdata.location) |
306 UARTn_ROUTE_RXPEN | UARTn_ROUTE_TXPEN,
307 UARTn_ROUTE);
308
309 ret = request_irq(port->irq, efm32_uart_rxirq, 0,
310 DRIVER_NAME, efm_port);
311 if (ret) {
312 efm_debug(efm_port, "failed to register rxirq\n");
313 goto err_request_irq_rx;
314 }
315
316 /* disable all irqs */
317 efm32_uart_write32(efm_port, 0, UARTn_IEN);
318
319 ret = request_irq(efm_port->txirq, efm32_uart_txirq, 0,
320 DRIVER_NAME, efm_port);
321 if (ret) {
322 efm_debug(efm_port, "failed to register txirq\n");
323 free_irq(port->irq, efm_port);
324 err_request_irq_rx:
325
326 clk_disable(efm_port->clk);
327 } else {
328 efm32_uart_write32(efm_port,
329 UARTn_IF_RXDATAV | UARTn_IF_RXOF, UARTn_IEN);
330 efm32_uart_write32(efm_port, UARTn_CMD_RXEN, UARTn_CMD);
331 }
332
333 err_clk_enable:
334 return ret;
335 }
336
337 static void efm32_uart_shutdown(struct uart_port *port)
338 {
339 struct efm32_uart_port *efm_port = to_efm_port(port);
340
341 efm32_uart_write32(efm_port, 0, UARTn_IEN);
342 free_irq(port->irq, efm_port);
343
344 clk_disable(efm_port->clk);
345 }
346
347 static void efm32_uart_set_termios(struct uart_port *port,
348 struct ktermios *new, struct ktermios *old)
349 {
350 struct efm32_uart_port *efm_port = to_efm_port(port);
351 unsigned long flags;
352 unsigned baud;
353 u32 clkdiv;
354 u32 frame = 0;
355
356 /* no modem control lines */
357 new->c_cflag &= ~(CRTSCTS | CMSPAR);
358
359 baud = uart_get_baud_rate(port, new, old,
360 DIV_ROUND_CLOSEST(port->uartclk, 16 * 8192),
361 DIV_ROUND_CLOSEST(port->uartclk, 16));
362
363 switch (new->c_cflag & CSIZE) {
364 case CS5:
365 frame |= UARTn_FRAME_DATABITS(5);
366 break;
367 case CS6:
368 frame |= UARTn_FRAME_DATABITS(6);
369 break;
370 case CS7:
371 frame |= UARTn_FRAME_DATABITS(7);
372 break;
373 case CS8:
374 frame |= UARTn_FRAME_DATABITS(8);
375 break;
376 }
377
378 if (new->c_cflag & CSTOPB)
379 /* the receiver only verifies the first stop bit */
380 frame |= UARTn_FRAME_STOPBITS_TWO;
381 else
382 frame |= UARTn_FRAME_STOPBITS_ONE;
383
384 if (new->c_cflag & PARENB) {
385 if (new->c_cflag & PARODD)
386 frame |= UARTn_FRAME_PARITY_ODD;
387 else
388 frame |= UARTn_FRAME_PARITY_EVEN;
389 } else
390 frame |= UARTn_FRAME_PARITY_NONE;
391
392 /*
393 * the 6 lowest bits of CLKDIV are dc, bit 6 has value 0.25.
394 * port->uartclk <= 14e6, so 4 * port->uartclk doesn't overflow.
395 */
396 clkdiv = (DIV_ROUND_CLOSEST(4 * port->uartclk, 16 * baud) - 4) << 6;
397
398 spin_lock_irqsave(&port->lock, flags);
399
400 efm32_uart_write32(efm_port,
401 UARTn_CMD_TXDIS | UARTn_CMD_RXDIS, UARTn_CMD);
402
403 port->read_status_mask = UARTn_RXDATAX_RXDATA__MASK;
404 if (new->c_iflag & INPCK)
405 port->read_status_mask |=
406 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
407 if (new->c_iflag & (IGNBRK | BRKINT | PARMRK))
408 port->read_status_mask |= SW_UARTn_RXDATAX_BERR;
409
410 port->ignore_status_mask = 0;
411 if (new->c_iflag & IGNPAR)
412 port->ignore_status_mask |=
413 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
414 if (new->c_iflag & IGNBRK)
415 port->ignore_status_mask |= SW_UARTn_RXDATAX_BERR;
416
417 uart_update_timeout(port, new->c_cflag, baud);
418
419 efm32_uart_write32(efm_port, UARTn_CTRL_TXBIL, UARTn_CTRL);
420 efm32_uart_write32(efm_port, frame, UARTn_FRAME);
421 efm32_uart_write32(efm_port, clkdiv, UARTn_CLKDIV);
422
423 efm32_uart_write32(efm_port, UARTn_CMD_TXEN | UARTn_CMD_RXEN,
424 UARTn_CMD);
425
426 spin_unlock_irqrestore(&port->lock, flags);
427 }
428
429 static const char *efm32_uart_type(struct uart_port *port)
430 {
431 return port->type == PORT_EFMUART ? "efm32-uart" : NULL;
432 }
433
434 static void efm32_uart_release_port(struct uart_port *port)
435 {
436 struct efm32_uart_port *efm_port = to_efm_port(port);
437
438 clk_unprepare(efm_port->clk);
439 clk_put(efm_port->clk);
440 iounmap(port->membase);
441 }
442
443 static int efm32_uart_request_port(struct uart_port *port)
444 {
445 struct efm32_uart_port *efm_port = to_efm_port(port);
446 int ret;
447
448 port->membase = ioremap(port->mapbase, 60);
449 if (!efm_port->port.membase) {
450 ret = -ENOMEM;
451 efm_debug(efm_port, "failed to remap\n");
452 goto err_ioremap;
453 }
454
455 efm_port->clk = clk_get(port->dev, NULL);
456 if (IS_ERR(efm_port->clk)) {
457 ret = PTR_ERR(efm_port->clk);
458 efm_debug(efm_port, "failed to get clock\n");
459 goto err_clk_get;
460 }
461
462 ret = clk_prepare(efm_port->clk);
463 if (ret) {
464 clk_put(efm_port->clk);
465 err_clk_get:
466
467 iounmap(port->membase);
468 err_ioremap:
469 return ret;
470 }
471 return 0;
472 }
473
474 static void efm32_uart_config_port(struct uart_port *port, int type)
475 {
476 if (type & UART_CONFIG_TYPE &&
477 !efm32_uart_request_port(port))
478 port->type = PORT_EFMUART;
479 }
480
481 static int efm32_uart_verify_port(struct uart_port *port,
482 struct serial_struct *serinfo)
483 {
484 int ret = 0;
485
486 if (serinfo->type != PORT_UNKNOWN && serinfo->type != PORT_EFMUART)
487 ret = -EINVAL;
488
489 return ret;
490 }
491
492 static const struct uart_ops efm32_uart_pops = {
493 .tx_empty = efm32_uart_tx_empty,
494 .set_mctrl = efm32_uart_set_mctrl,
495 .get_mctrl = efm32_uart_get_mctrl,
496 .stop_tx = efm32_uart_stop_tx,
497 .start_tx = efm32_uart_start_tx,
498 .stop_rx = efm32_uart_stop_rx,
499 .break_ctl = efm32_uart_break_ctl,
500 .startup = efm32_uart_startup,
501 .shutdown = efm32_uart_shutdown,
502 .set_termios = efm32_uart_set_termios,
503 .type = efm32_uart_type,
504 .release_port = efm32_uart_release_port,
505 .request_port = efm32_uart_request_port,
506 .config_port = efm32_uart_config_port,
507 .verify_port = efm32_uart_verify_port,
508 };
509
510 static struct efm32_uart_port *efm32_uart_ports[5];
511
512 #ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE
513 static void efm32_uart_console_putchar(struct uart_port *port, int ch)
514 {
515 struct efm32_uart_port *efm_port = to_efm_port(port);
516 unsigned int timeout = 0x400;
517 u32 status;
518
519 while (1) {
520 status = efm32_uart_read32(efm_port, UARTn_STATUS);
521
522 if (status & UARTn_STATUS_TXBL)
523 break;
524 if (!timeout--)
525 return;
526 }
527 efm32_uart_write32(efm_port, ch, UARTn_TXDATA);
528 }
529
530 static void efm32_uart_console_write(struct console *co, const char *s,
531 unsigned int count)
532 {
533 struct efm32_uart_port *efm_port = efm32_uart_ports[co->index];
534 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
535 unsigned int timeout = 0x400;
536
537 if (!(status & UARTn_STATUS_TXENS))
538 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
539
540 uart_console_write(&efm_port->port, s, count,
541 efm32_uart_console_putchar);
542
543 /* Wait for the transmitter to become empty */
544 while (1) {
545 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
546 if (status & UARTn_STATUS_TXC)
547 break;
548 if (!timeout--)
549 break;
550 }
551
552 if (!(status & UARTn_STATUS_TXENS))
553 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
554 }
555
556 static void efm32_uart_console_get_options(struct efm32_uart_port *efm_port,
557 int *baud, int *parity, int *bits)
558 {
559 u32 ctrl = efm32_uart_read32(efm_port, UARTn_CTRL);
560 u32 route, clkdiv, frame;
561
562 if (ctrl & UARTn_CTRL_SYNC)
563 /* not operating in async mode */
564 return;
565
566 route = efm32_uart_read32(efm_port, UARTn_ROUTE);
567 if (!(route & UARTn_ROUTE_TXPEN))
568 /* tx pin not routed */
569 return;
570
571 clkdiv = efm32_uart_read32(efm_port, UARTn_CLKDIV);
572
573 *baud = DIV_ROUND_CLOSEST(4 * efm_port->port.uartclk,
574 16 * (4 + (clkdiv >> 6)));
575
576 frame = efm32_uart_read32(efm_port, UARTn_FRAME);
577 switch (frame & UARTn_FRAME_PARITY__MASK) {
578 case UARTn_FRAME_PARITY_ODD:
579 *parity = 'o';
580 break;
581 case UARTn_FRAME_PARITY_EVEN:
582 *parity = 'e';
583 break;
584 default:
585 *parity = 'n';
586 }
587
588 *bits = (frame & UARTn_FRAME_DATABITS__MASK) -
589 UARTn_FRAME_DATABITS(4) + 4;
590
591 efm_debug(efm_port, "get_opts: options=%d%c%d\n",
592 *baud, *parity, *bits);
593 }
594
595 static int efm32_uart_console_setup(struct console *co, char *options)
596 {
597 struct efm32_uart_port *efm_port;
598 int baud = 115200;
599 int bits = 8;
600 int parity = 'n';
601 int flow = 'n';
602 int ret;
603
604 if (co->index < 0 || co->index >= ARRAY_SIZE(efm32_uart_ports)) {
605 unsigned i;
606 for (i = 0; i < ARRAY_SIZE(efm32_uart_ports); ++i) {
607 if (efm32_uart_ports[i]) {
608 pr_warn("efm32-console: fall back to console index %u (from %hhi)\n",
609 i, co->index);
610 co->index = i;
611 break;
612 }
613 }
614 }
615
616 efm_port = efm32_uart_ports[co->index];
617 if (!efm_port) {
618 pr_warn("efm32-console: No port at %d\n", co->index);
619 return -ENODEV;
620 }
621
622 ret = clk_prepare(efm_port->clk);
623 if (ret) {
624 dev_warn(efm_port->port.dev,
625 "console: clk_prepare failed: %d\n", ret);
626 return ret;
627 }
628
629 efm_port->port.uartclk = clk_get_rate(efm_port->clk);
630
631 if (options)
632 uart_parse_options(options, &baud, &parity, &bits, &flow);
633 else
634 efm32_uart_console_get_options(efm_port,
635 &baud, &parity, &bits);
636
637 return uart_set_options(&efm_port->port, co, baud, parity, bits, flow);
638 }
639
640 static struct uart_driver efm32_uart_reg;
641
642 static struct console efm32_uart_console = {
643 .name = DEV_NAME,
644 .write = efm32_uart_console_write,
645 .device = uart_console_device,
646 .setup = efm32_uart_console_setup,
647 .flags = CON_PRINTBUFFER,
648 .index = -1,
649 .data = &efm32_uart_reg,
650 };
651
652 #else
653 #define efm32_uart_console (*(struct console *)NULL)
654 #endif /* ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE / else */
655
656 static struct uart_driver efm32_uart_reg = {
657 .owner = THIS_MODULE,
658 .driver_name = DRIVER_NAME,
659 .dev_name = DEV_NAME,
660 .nr = ARRAY_SIZE(efm32_uart_ports),
661 .cons = &efm32_uart_console,
662 };
663
664 static int efm32_uart_probe_dt(struct platform_device *pdev,
665 struct efm32_uart_port *efm_port)
666 {
667 struct device_node *np = pdev->dev.of_node;
668 u32 location;
669 int ret;
670
671 if (!np)
672 return 1;
673
674 ret = of_property_read_u32(np, "energymicro,location", &location);
675
676 if (ret)
677 /* fall back to wrongly namespaced property */
678 ret = of_property_read_u32(np, "efm32,location", &location);
679
680 if (ret)
681 /* fall back to old and (wrongly) generic property "location" */
682 ret = of_property_read_u32(np, "location", &location);
683
684 if (!ret) {
685 if (location > 5) {
686 dev_err(&pdev->dev, "invalid location\n");
687 return -EINVAL;
688 }
689 efm_debug(efm_port, "using location %u\n", location);
690 efm_port->pdata.location = location;
691 } else {
692 efm_debug(efm_port, "fall back to location 0\n");
693 }
694
695 ret = of_alias_get_id(np, "serial");
696 if (ret < 0) {
697 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
698 return ret;
699 } else {
700 efm_port->port.line = ret;
701 return 0;
702 }
703
704 }
705
706 static int efm32_uart_probe(struct platform_device *pdev)
707 {
708 struct efm32_uart_port *efm_port;
709 struct resource *res;
710 unsigned int line;
711 int ret;
712
713 efm_port = kzalloc(sizeof(*efm_port), GFP_KERNEL);
714 if (!efm_port) {
715 dev_dbg(&pdev->dev, "failed to allocate private data\n");
716 return -ENOMEM;
717 }
718
719 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
720 if (!res) {
721 ret = -ENODEV;
722 dev_dbg(&pdev->dev, "failed to determine base address\n");
723 goto err_get_base;
724 }
725
726 if (resource_size(res) < 60) {
727 ret = -EINVAL;
728 dev_dbg(&pdev->dev, "memory resource too small\n");
729 goto err_too_small;
730 }
731
732 ret = platform_get_irq(pdev, 0);
733 if (ret <= 0) {
734 dev_dbg(&pdev->dev, "failed to get rx irq\n");
735 goto err_get_rxirq;
736 }
737
738 efm_port->port.irq = ret;
739
740 ret = platform_get_irq(pdev, 1);
741 if (ret <= 0)
742 ret = efm_port->port.irq + 1;
743
744 efm_port->txirq = ret;
745
746 efm_port->port.dev = &pdev->dev;
747 efm_port->port.mapbase = res->start;
748 efm_port->port.type = PORT_EFMUART;
749 efm_port->port.iotype = UPIO_MEM32;
750 efm_port->port.fifosize = 2;
751 efm_port->port.ops = &efm32_uart_pops;
752 efm_port->port.flags = UPF_BOOT_AUTOCONF;
753
754 ret = efm32_uart_probe_dt(pdev, efm_port);
755 if (ret > 0) {
756 /* not created by device tree */
757 const struct efm32_uart_pdata *pdata = dev_get_platdata(&pdev->dev);
758
759 efm_port->port.line = pdev->id;
760
761 if (pdata)
762 efm_port->pdata = *pdata;
763 } else if (ret < 0)
764 goto err_probe_dt;
765
766 line = efm_port->port.line;
767
768 if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
769 efm32_uart_ports[line] = efm_port;
770
771 ret = uart_add_one_port(&efm32_uart_reg, &efm_port->port);
772 if (ret) {
773 dev_dbg(&pdev->dev, "failed to add port: %d\n", ret);
774
775 if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
776 efm32_uart_ports[line] = NULL;
777 err_probe_dt:
778 err_get_rxirq:
779 err_too_small:
780 err_get_base:
781 kfree(efm_port);
782 } else {
783 platform_set_drvdata(pdev, efm_port);
784 dev_dbg(&pdev->dev, "\\o/\n");
785 }
786
787 return ret;
788 }
789
790 static int efm32_uart_remove(struct platform_device *pdev)
791 {
792 struct efm32_uart_port *efm_port = platform_get_drvdata(pdev);
793 unsigned int line = efm_port->port.line;
794
795 uart_remove_one_port(&efm32_uart_reg, &efm_port->port);
796
797 if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
798 efm32_uart_ports[line] = NULL;
799
800 kfree(efm_port);
801
802 return 0;
803 }
804
805 static const struct of_device_id efm32_uart_dt_ids[] = {
806 {
807 .compatible = "energymicro,efm32-uart",
808 }, {
809 /* doesn't follow the "vendor,device" scheme, don't use */
810 .compatible = "efm32,uart",
811 }, {
812 /* sentinel */
813 }
814 };
815 MODULE_DEVICE_TABLE(of, efm32_uart_dt_ids);
816
817 static struct platform_driver efm32_uart_driver = {
818 .probe = efm32_uart_probe,
819 .remove = efm32_uart_remove,
820
821 .driver = {
822 .name = DRIVER_NAME,
823 .of_match_table = efm32_uart_dt_ids,
824 },
825 };
826
827 static int __init efm32_uart_init(void)
828 {
829 int ret;
830
831 ret = uart_register_driver(&efm32_uart_reg);
832 if (ret)
833 return ret;
834
835 ret = platform_driver_register(&efm32_uart_driver);
836 if (ret)
837 uart_unregister_driver(&efm32_uart_reg);
838
839 pr_info("EFM32 UART/USART driver\n");
840
841 return ret;
842 }
843 module_init(efm32_uart_init);
844
845 static void __exit efm32_uart_exit(void)
846 {
847 platform_driver_unregister(&efm32_uart_driver);
848 uart_unregister_driver(&efm32_uart_reg);
849 }
850 module_exit(efm32_uart_exit);
851
852 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
853 MODULE_DESCRIPTION("EFM32 UART/USART driver");
854 MODULE_LICENSE("GPL v2");
855 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux with added FPC-III support