1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for msm7k serial device and console
5 * Copyright (C) 2007 Google, Inc.
6 * Author: Robert Love <rlove@google.com>
7 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
10 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
11 # define SUPPORT_SYSRQ
14 #include <linux/kernel.h>
15 #include <linux/atomic.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmaengine.h>
18 #include <linux/module.h>
20 #include <linux/ioport.h>
21 #include <linux/interrupt.h>
22 #include <linux/init.h>
23 #include <linux/console.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial_core.h>
27 #include <linux/slab.h>
28 #include <linux/clk.h>
29 #include <linux/platform_device.h>
30 #include <linux/delay.h>
32 #include <linux/of_device.h>
33 #include <linux/wait.h>
35 #define UART_MR1 0x0000
37 #define UART_MR1_AUTO_RFR_LEVEL0 0x3F
38 #define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
39 #define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
40 #define UART_MR1_RX_RDY_CTL BIT(7)
41 #define UART_MR1_CTS_CTL BIT(6)
43 #define UART_MR2 0x0004
44 #define UART_MR2_ERROR_MODE BIT(6)
45 #define UART_MR2_BITS_PER_CHAR 0x30
46 #define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
47 #define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
48 #define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
49 #define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
50 #define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
51 #define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
52 #define UART_MR2_PARITY_MODE_NONE 0x0
53 #define UART_MR2_PARITY_MODE_ODD 0x1
54 #define UART_MR2_PARITY_MODE_EVEN 0x2
55 #define UART_MR2_PARITY_MODE_SPACE 0x3
56 #define UART_MR2_PARITY_MODE 0x3
58 #define UART_CSR 0x0008
60 #define UART_TF 0x000C
61 #define UARTDM_TF 0x0070
63 #define UART_CR 0x0010
64 #define UART_CR_CMD_NULL (0 << 4)
65 #define UART_CR_CMD_RESET_RX (1 << 4)
66 #define UART_CR_CMD_RESET_TX (2 << 4)
67 #define UART_CR_CMD_RESET_ERR (3 << 4)
68 #define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
69 #define UART_CR_CMD_START_BREAK (5 << 4)
70 #define UART_CR_CMD_STOP_BREAK (6 << 4)
71 #define UART_CR_CMD_RESET_CTS (7 << 4)
72 #define UART_CR_CMD_RESET_STALE_INT (8 << 4)
73 #define UART_CR_CMD_PACKET_MODE (9 << 4)
74 #define UART_CR_CMD_MODE_RESET (12 << 4)
75 #define UART_CR_CMD_SET_RFR (13 << 4)
76 #define UART_CR_CMD_RESET_RFR (14 << 4)
77 #define UART_CR_CMD_PROTECTION_EN (16 << 4)
78 #define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
79 #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
80 #define UART_CR_CMD_FORCE_STALE (4 << 8)
81 #define UART_CR_CMD_RESET_TX_READY (3 << 8)
82 #define UART_CR_TX_DISABLE BIT(3)
83 #define UART_CR_TX_ENABLE BIT(2)
84 #define UART_CR_RX_DISABLE BIT(1)
85 #define UART_CR_RX_ENABLE BIT(0)
86 #define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
88 #define UART_IMR 0x0014
89 #define UART_IMR_TXLEV BIT(0)
90 #define UART_IMR_RXSTALE BIT(3)
91 #define UART_IMR_RXLEV BIT(4)
92 #define UART_IMR_DELTA_CTS BIT(5)
93 #define UART_IMR_CURRENT_CTS BIT(6)
94 #define UART_IMR_RXBREAK_START BIT(10)
96 #define UART_IPR_RXSTALE_LAST 0x20
97 #define UART_IPR_STALE_LSB 0x1F
98 #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
99 #define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
101 #define UART_IPR 0x0018
102 #define UART_TFWR 0x001C
103 #define UART_RFWR 0x0020
104 #define UART_HCR 0x0024
106 #define UART_MREG 0x0028
107 #define UART_NREG 0x002C
108 #define UART_DREG 0x0030
109 #define UART_MNDREG 0x0034
110 #define UART_IRDA 0x0038
111 #define UART_MISR_MODE 0x0040
112 #define UART_MISR_RESET 0x0044
113 #define UART_MISR_EXPORT 0x0048
114 #define UART_MISR_VAL 0x004C
115 #define UART_TEST_CTRL 0x0050
117 #define UART_SR 0x0008
118 #define UART_SR_HUNT_CHAR BIT(7)
119 #define UART_SR_RX_BREAK BIT(6)
120 #define UART_SR_PAR_FRAME_ERR BIT(5)
121 #define UART_SR_OVERRUN BIT(4)
122 #define UART_SR_TX_EMPTY BIT(3)
123 #define UART_SR_TX_READY BIT(2)
124 #define UART_SR_RX_FULL BIT(1)
125 #define UART_SR_RX_READY BIT(0)
127 #define UART_RF 0x000C
128 #define UARTDM_RF 0x0070
129 #define UART_MISR 0x0010
130 #define UART_ISR 0x0014
131 #define UART_ISR_TX_READY BIT(7)
133 #define UARTDM_RXFS 0x50
134 #define UARTDM_RXFS_BUF_SHIFT 0x7
135 #define UARTDM_RXFS_BUF_MASK 0x7
137 #define UARTDM_DMEN 0x3C
138 #define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
139 #define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
141 #define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */
142 #define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */
144 #define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */
145 #define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */
147 #define UARTDM_DMRX 0x34
148 #define UARTDM_NCF_TX 0x40
149 #define UARTDM_RX_TOTAL_SNAP 0x38
151 #define UARTDM_BURST_SIZE 16 /* in bytes */
152 #define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
153 #define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
154 #define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
164 struct dma_chan
*chan
;
165 enum dma_data_direction dir
;
171 struct dma_async_tx_descriptor
*desc
;
175 struct uart_port uart
;
181 unsigned int old_snap_state
;
183 struct msm_dma tx_dma
;
184 struct msm_dma rx_dma
;
187 #define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart)
190 void msm_write(struct uart_port
*port
, unsigned int val
, unsigned int off
)
192 writel_relaxed(val
, port
->membase
+ off
);
196 unsigned int msm_read(struct uart_port
*port
, unsigned int off
)
198 return readl_relaxed(port
->membase
+ off
);
202 * Setup the MND registers to use the TCXO clock.
204 static void msm_serial_set_mnd_regs_tcxo(struct uart_port
*port
)
206 msm_write(port
, 0x06, UART_MREG
);
207 msm_write(port
, 0xF1, UART_NREG
);
208 msm_write(port
, 0x0F, UART_DREG
);
209 msm_write(port
, 0x1A, UART_MNDREG
);
210 port
->uartclk
= 1843200;
214 * Setup the MND registers to use the TCXO clock divided by 4.
216 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port
*port
)
218 msm_write(port
, 0x18, UART_MREG
);
219 msm_write(port
, 0xF6, UART_NREG
);
220 msm_write(port
, 0x0F, UART_DREG
);
221 msm_write(port
, 0x0A, UART_MNDREG
);
222 port
->uartclk
= 1843200;
225 static void msm_serial_set_mnd_regs(struct uart_port
*port
)
227 struct msm_port
*msm_port
= UART_TO_MSM(port
);
230 * These registers don't exist so we change the clk input rate
231 * on uartdm hardware instead
233 if (msm_port
->is_uartdm
)
236 if (port
->uartclk
== 19200000)
237 msm_serial_set_mnd_regs_tcxo(port
);
238 else if (port
->uartclk
== 4800000)
239 msm_serial_set_mnd_regs_tcxoby4(port
);
242 static void msm_handle_tx(struct uart_port
*port
);
243 static void msm_start_rx_dma(struct msm_port
*msm_port
);
245 static void msm_stop_dma(struct uart_port
*port
, struct msm_dma
*dma
)
247 struct device
*dev
= port
->dev
;
254 dmaengine_terminate_all(dma
->chan
);
257 * DMA Stall happens if enqueue and flush command happens concurrently.
258 * For example before changing the baud rate/protocol configuration and
259 * sending flush command to ADM, disable the channel of UARTDM.
260 * Note: should not reset the receiver here immediately as it is not
261 * suggested to do disable/reset or reset/disable at the same time.
263 val
= msm_read(port
, UARTDM_DMEN
);
264 val
&= ~dma
->enable_bit
;
265 msm_write(port
, val
, UARTDM_DMEN
);
268 dma_unmap_single(dev
, dma
->phys
, mapped
, dma
->dir
);
271 static void msm_release_dma(struct msm_port
*msm_port
)
275 dma
= &msm_port
->tx_dma
;
277 msm_stop_dma(&msm_port
->uart
, dma
);
278 dma_release_channel(dma
->chan
);
281 memset(dma
, 0, sizeof(*dma
));
283 dma
= &msm_port
->rx_dma
;
285 msm_stop_dma(&msm_port
->uart
, dma
);
286 dma_release_channel(dma
->chan
);
290 memset(dma
, 0, sizeof(*dma
));
293 static void msm_request_tx_dma(struct msm_port
*msm_port
, resource_size_t base
)
295 struct device
*dev
= msm_port
->uart
.dev
;
296 struct dma_slave_config conf
;
301 dma
= &msm_port
->tx_dma
;
303 /* allocate DMA resources, if available */
304 dma
->chan
= dma_request_slave_channel_reason(dev
, "tx");
305 if (IS_ERR(dma
->chan
))
308 of_property_read_u32(dev
->of_node
, "qcom,tx-crci", &crci
);
310 memset(&conf
, 0, sizeof(conf
));
311 conf
.direction
= DMA_MEM_TO_DEV
;
312 conf
.device_fc
= true;
313 conf
.dst_addr
= base
+ UARTDM_TF
;
314 conf
.dst_maxburst
= UARTDM_BURST_SIZE
;
315 conf
.slave_id
= crci
;
317 ret
= dmaengine_slave_config(dma
->chan
, &conf
);
321 dma
->dir
= DMA_TO_DEVICE
;
323 if (msm_port
->is_uartdm
< UARTDM_1P4
)
324 dma
->enable_bit
= UARTDM_DMEN_TX_DM_ENABLE
;
326 dma
->enable_bit
= UARTDM_DMEN_TX_BAM_ENABLE
;
331 dma_release_channel(dma
->chan
);
333 memset(dma
, 0, sizeof(*dma
));
336 static void msm_request_rx_dma(struct msm_port
*msm_port
, resource_size_t base
)
338 struct device
*dev
= msm_port
->uart
.dev
;
339 struct dma_slave_config conf
;
344 dma
= &msm_port
->rx_dma
;
346 /* allocate DMA resources, if available */
347 dma
->chan
= dma_request_slave_channel_reason(dev
, "rx");
348 if (IS_ERR(dma
->chan
))
351 of_property_read_u32(dev
->of_node
, "qcom,rx-crci", &crci
);
353 dma
->virt
= kzalloc(UARTDM_RX_SIZE
, GFP_KERNEL
);
357 memset(&conf
, 0, sizeof(conf
));
358 conf
.direction
= DMA_DEV_TO_MEM
;
359 conf
.device_fc
= true;
360 conf
.src_addr
= base
+ UARTDM_RF
;
361 conf
.src_maxburst
= UARTDM_BURST_SIZE
;
362 conf
.slave_id
= crci
;
364 ret
= dmaengine_slave_config(dma
->chan
, &conf
);
368 dma
->dir
= DMA_FROM_DEVICE
;
370 if (msm_port
->is_uartdm
< UARTDM_1P4
)
371 dma
->enable_bit
= UARTDM_DMEN_RX_DM_ENABLE
;
373 dma
->enable_bit
= UARTDM_DMEN_RX_BAM_ENABLE
;
379 dma_release_channel(dma
->chan
);
381 memset(dma
, 0, sizeof(*dma
));
384 static inline void msm_wait_for_xmitr(struct uart_port
*port
)
386 while (!(msm_read(port
, UART_SR
) & UART_SR_TX_EMPTY
)) {
387 if (msm_read(port
, UART_ISR
) & UART_ISR_TX_READY
)
391 msm_write(port
, UART_CR_CMD_RESET_TX_READY
, UART_CR
);
394 static void msm_stop_tx(struct uart_port
*port
)
396 struct msm_port
*msm_port
= UART_TO_MSM(port
);
398 msm_port
->imr
&= ~UART_IMR_TXLEV
;
399 msm_write(port
, msm_port
->imr
, UART_IMR
);
402 static void msm_start_tx(struct uart_port
*port
)
404 struct msm_port
*msm_port
= UART_TO_MSM(port
);
405 struct msm_dma
*dma
= &msm_port
->tx_dma
;
407 /* Already started in DMA mode */
411 msm_port
->imr
|= UART_IMR_TXLEV
;
412 msm_write(port
, msm_port
->imr
, UART_IMR
);
415 static void msm_reset_dm_count(struct uart_port
*port
, int count
)
417 msm_wait_for_xmitr(port
);
418 msm_write(port
, count
, UARTDM_NCF_TX
);
419 msm_read(port
, UARTDM_NCF_TX
);
422 static void msm_complete_tx_dma(void *args
)
424 struct msm_port
*msm_port
= args
;
425 struct uart_port
*port
= &msm_port
->uart
;
426 struct circ_buf
*xmit
= &port
->state
->xmit
;
427 struct msm_dma
*dma
= &msm_port
->tx_dma
;
428 struct dma_tx_state state
;
429 enum dma_status status
;
434 spin_lock_irqsave(&port
->lock
, flags
);
436 /* Already stopped */
440 status
= dmaengine_tx_status(dma
->chan
, dma
->cookie
, &state
);
442 dma_unmap_single(port
->dev
, dma
->phys
, dma
->count
, dma
->dir
);
444 val
= msm_read(port
, UARTDM_DMEN
);
445 val
&= ~dma
->enable_bit
;
446 msm_write(port
, val
, UARTDM_DMEN
);
448 if (msm_port
->is_uartdm
> UARTDM_1P3
) {
449 msm_write(port
, UART_CR_CMD_RESET_TX
, UART_CR
);
450 msm_write(port
, UART_CR_TX_ENABLE
, UART_CR
);
453 count
= dma
->count
- state
.residue
;
454 port
->icount
.tx
+= count
;
458 xmit
->tail
&= UART_XMIT_SIZE
- 1;
460 /* Restore "Tx FIFO below watermark" interrupt */
461 msm_port
->imr
|= UART_IMR_TXLEV
;
462 msm_write(port
, msm_port
->imr
, UART_IMR
);
464 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
465 uart_write_wakeup(port
);
469 spin_unlock_irqrestore(&port
->lock
, flags
);
472 static int msm_handle_tx_dma(struct msm_port
*msm_port
, unsigned int count
)
474 struct circ_buf
*xmit
= &msm_port
->uart
.state
->xmit
;
475 struct uart_port
*port
= &msm_port
->uart
;
476 struct msm_dma
*dma
= &msm_port
->tx_dma
;
481 cpu_addr
= &xmit
->buf
[xmit
->tail
];
483 dma
->phys
= dma_map_single(port
->dev
, cpu_addr
, count
, dma
->dir
);
484 ret
= dma_mapping_error(port
->dev
, dma
->phys
);
488 dma
->desc
= dmaengine_prep_slave_single(dma
->chan
, dma
->phys
,
489 count
, DMA_MEM_TO_DEV
,
497 dma
->desc
->callback
= msm_complete_tx_dma
;
498 dma
->desc
->callback_param
= msm_port
;
500 dma
->cookie
= dmaengine_submit(dma
->desc
);
501 ret
= dma_submit_error(dma
->cookie
);
506 * Using DMA complete for Tx FIFO reload, no need for
507 * "Tx FIFO below watermark" one, disable it
509 msm_port
->imr
&= ~UART_IMR_TXLEV
;
510 msm_write(port
, msm_port
->imr
, UART_IMR
);
514 val
= msm_read(port
, UARTDM_DMEN
);
515 val
|= dma
->enable_bit
;
517 if (msm_port
->is_uartdm
< UARTDM_1P4
)
518 msm_write(port
, val
, UARTDM_DMEN
);
520 msm_reset_dm_count(port
, count
);
522 if (msm_port
->is_uartdm
> UARTDM_1P3
)
523 msm_write(port
, val
, UARTDM_DMEN
);
525 dma_async_issue_pending(dma
->chan
);
528 dma_unmap_single(port
->dev
, dma
->phys
, count
, dma
->dir
);
532 static void msm_complete_rx_dma(void *args
)
534 struct msm_port
*msm_port
= args
;
535 struct uart_port
*port
= &msm_port
->uart
;
536 struct tty_port
*tport
= &port
->state
->port
;
537 struct msm_dma
*dma
= &msm_port
->rx_dma
;
538 int count
= 0, i
, sysrq
;
542 spin_lock_irqsave(&port
->lock
, flags
);
544 /* Already stopped */
548 val
= msm_read(port
, UARTDM_DMEN
);
549 val
&= ~dma
->enable_bit
;
550 msm_write(port
, val
, UARTDM_DMEN
);
552 if (msm_read(port
, UART_SR
) & UART_SR_OVERRUN
) {
553 port
->icount
.overrun
++;
554 tty_insert_flip_char(tport
, 0, TTY_OVERRUN
);
555 msm_write(port
, UART_CR_CMD_RESET_ERR
, UART_CR
);
558 count
= msm_read(port
, UARTDM_RX_TOTAL_SNAP
);
560 port
->icount
.rx
+= count
;
564 dma_unmap_single(port
->dev
, dma
->phys
, UARTDM_RX_SIZE
, dma
->dir
);
566 for (i
= 0; i
< count
; i
++) {
567 char flag
= TTY_NORMAL
;
569 if (msm_port
->break_detected
&& dma
->virt
[i
] == 0) {
572 msm_port
->break_detected
= false;
573 if (uart_handle_break(port
))
577 if (!(port
->read_status_mask
& UART_SR_RX_BREAK
))
580 spin_unlock_irqrestore(&port
->lock
, flags
);
581 sysrq
= uart_handle_sysrq_char(port
, dma
->virt
[i
]);
582 spin_lock_irqsave(&port
->lock
, flags
);
584 tty_insert_flip_char(tport
, dma
->virt
[i
], flag
);
587 msm_start_rx_dma(msm_port
);
589 spin_unlock_irqrestore(&port
->lock
, flags
);
592 tty_flip_buffer_push(tport
);
595 static void msm_start_rx_dma(struct msm_port
*msm_port
)
597 struct msm_dma
*dma
= &msm_port
->rx_dma
;
598 struct uart_port
*uart
= &msm_port
->uart
;
605 dma
->phys
= dma_map_single(uart
->dev
, dma
->virt
,
606 UARTDM_RX_SIZE
, dma
->dir
);
607 ret
= dma_mapping_error(uart
->dev
, dma
->phys
);
611 dma
->desc
= dmaengine_prep_slave_single(dma
->chan
, dma
->phys
,
612 UARTDM_RX_SIZE
, DMA_DEV_TO_MEM
,
617 dma
->desc
->callback
= msm_complete_rx_dma
;
618 dma
->desc
->callback_param
= msm_port
;
620 dma
->cookie
= dmaengine_submit(dma
->desc
);
621 ret
= dma_submit_error(dma
->cookie
);
625 * Using DMA for FIFO off-load, no need for "Rx FIFO over
626 * watermark" or "stale" interrupts, disable them
628 msm_port
->imr
&= ~(UART_IMR_RXLEV
| UART_IMR_RXSTALE
);
631 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
632 * we need RXSTALE to flush input DMA fifo to memory
634 if (msm_port
->is_uartdm
< UARTDM_1P4
)
635 msm_port
->imr
|= UART_IMR_RXSTALE
;
637 msm_write(uart
, msm_port
->imr
, UART_IMR
);
639 dma
->count
= UARTDM_RX_SIZE
;
641 dma_async_issue_pending(dma
->chan
);
643 msm_write(uart
, UART_CR_CMD_RESET_STALE_INT
, UART_CR
);
644 msm_write(uart
, UART_CR_CMD_STALE_EVENT_ENABLE
, UART_CR
);
646 val
= msm_read(uart
, UARTDM_DMEN
);
647 val
|= dma
->enable_bit
;
649 if (msm_port
->is_uartdm
< UARTDM_1P4
)
650 msm_write(uart
, val
, UARTDM_DMEN
);
652 msm_write(uart
, UARTDM_RX_SIZE
, UARTDM_DMRX
);
654 if (msm_port
->is_uartdm
> UARTDM_1P3
)
655 msm_write(uart
, val
, UARTDM_DMEN
);
659 dma_unmap_single(uart
->dev
, dma
->phys
, UARTDM_RX_SIZE
, dma
->dir
);
662 static void msm_stop_rx(struct uart_port
*port
)
664 struct msm_port
*msm_port
= UART_TO_MSM(port
);
665 struct msm_dma
*dma
= &msm_port
->rx_dma
;
667 msm_port
->imr
&= ~(UART_IMR_RXLEV
| UART_IMR_RXSTALE
);
668 msm_write(port
, msm_port
->imr
, UART_IMR
);
671 msm_stop_dma(port
, dma
);
674 static void msm_enable_ms(struct uart_port
*port
)
676 struct msm_port
*msm_port
= UART_TO_MSM(port
);
678 msm_port
->imr
|= UART_IMR_DELTA_CTS
;
679 msm_write(port
, msm_port
->imr
, UART_IMR
);
682 static void msm_handle_rx_dm(struct uart_port
*port
, unsigned int misr
)
684 struct tty_port
*tport
= &port
->state
->port
;
687 struct msm_port
*msm_port
= UART_TO_MSM(port
);
689 if ((msm_read(port
, UART_SR
) & UART_SR_OVERRUN
)) {
690 port
->icount
.overrun
++;
691 tty_insert_flip_char(tport
, 0, TTY_OVERRUN
);
692 msm_write(port
, UART_CR_CMD_RESET_ERR
, UART_CR
);
695 if (misr
& UART_IMR_RXSTALE
) {
696 count
= msm_read(port
, UARTDM_RX_TOTAL_SNAP
) -
697 msm_port
->old_snap_state
;
698 msm_port
->old_snap_state
= 0;
700 count
= 4 * (msm_read(port
, UART_RFWR
));
701 msm_port
->old_snap_state
+= count
;
704 /* TODO: Precise error reporting */
706 port
->icount
.rx
+= count
;
709 unsigned char buf
[4];
710 int sysrq
, r_count
, i
;
712 sr
= msm_read(port
, UART_SR
);
713 if ((sr
& UART_SR_RX_READY
) == 0) {
714 msm_port
->old_snap_state
-= count
;
718 ioread32_rep(port
->membase
+ UARTDM_RF
, buf
, 1);
719 r_count
= min_t(int, count
, sizeof(buf
));
721 for (i
= 0; i
< r_count
; i
++) {
722 char flag
= TTY_NORMAL
;
724 if (msm_port
->break_detected
&& buf
[i
] == 0) {
727 msm_port
->break_detected
= false;
728 if (uart_handle_break(port
))
732 if (!(port
->read_status_mask
& UART_SR_RX_BREAK
))
735 spin_unlock(&port
->lock
);
736 sysrq
= uart_handle_sysrq_char(port
, buf
[i
]);
737 spin_lock(&port
->lock
);
739 tty_insert_flip_char(tport
, buf
[i
], flag
);
744 spin_unlock(&port
->lock
);
745 tty_flip_buffer_push(tport
);
746 spin_lock(&port
->lock
);
748 if (misr
& (UART_IMR_RXSTALE
))
749 msm_write(port
, UART_CR_CMD_RESET_STALE_INT
, UART_CR
);
750 msm_write(port
, 0xFFFFFF, UARTDM_DMRX
);
751 msm_write(port
, UART_CR_CMD_STALE_EVENT_ENABLE
, UART_CR
);
754 msm_start_rx_dma(msm_port
);
757 static void msm_handle_rx(struct uart_port
*port
)
759 struct tty_port
*tport
= &port
->state
->port
;
763 * Handle overrun. My understanding of the hardware is that overrun
764 * is not tied to the RX buffer, so we handle the case out of band.
766 if ((msm_read(port
, UART_SR
) & UART_SR_OVERRUN
)) {
767 port
->icount
.overrun
++;
768 tty_insert_flip_char(tport
, 0, TTY_OVERRUN
);
769 msm_write(port
, UART_CR_CMD_RESET_ERR
, UART_CR
);
772 /* and now the main RX loop */
773 while ((sr
= msm_read(port
, UART_SR
)) & UART_SR_RX_READY
) {
775 char flag
= TTY_NORMAL
;
778 c
= msm_read(port
, UART_RF
);
780 if (sr
& UART_SR_RX_BREAK
) {
782 if (uart_handle_break(port
))
784 } else if (sr
& UART_SR_PAR_FRAME_ERR
) {
785 port
->icount
.frame
++;
790 /* Mask conditions we're ignorning. */
791 sr
&= port
->read_status_mask
;
793 if (sr
& UART_SR_RX_BREAK
)
795 else if (sr
& UART_SR_PAR_FRAME_ERR
)
798 spin_unlock(&port
->lock
);
799 sysrq
= uart_handle_sysrq_char(port
, c
);
800 spin_lock(&port
->lock
);
802 tty_insert_flip_char(tport
, c
, flag
);
805 spin_unlock(&port
->lock
);
806 tty_flip_buffer_push(tport
);
807 spin_lock(&port
->lock
);
810 static void msm_handle_tx_pio(struct uart_port
*port
, unsigned int tx_count
)
812 struct circ_buf
*xmit
= &port
->state
->xmit
;
813 struct msm_port
*msm_port
= UART_TO_MSM(port
);
814 unsigned int num_chars
;
815 unsigned int tf_pointer
= 0;
818 if (msm_port
->is_uartdm
)
819 tf
= port
->membase
+ UARTDM_TF
;
821 tf
= port
->membase
+ UART_TF
;
823 if (tx_count
&& msm_port
->is_uartdm
)
824 msm_reset_dm_count(port
, tx_count
);
826 while (tf_pointer
< tx_count
) {
830 if (!(msm_read(port
, UART_SR
) & UART_SR_TX_READY
))
833 if (msm_port
->is_uartdm
)
834 num_chars
= min(tx_count
- tf_pointer
,
835 (unsigned int)sizeof(buf
));
839 for (i
= 0; i
< num_chars
; i
++) {
840 buf
[i
] = xmit
->buf
[xmit
->tail
+ i
];
844 iowrite32_rep(tf
, buf
, 1);
845 xmit
->tail
= (xmit
->tail
+ num_chars
) & (UART_XMIT_SIZE
- 1);
846 tf_pointer
+= num_chars
;
849 /* disable tx interrupts if nothing more to send */
850 if (uart_circ_empty(xmit
))
853 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
854 uart_write_wakeup(port
);
857 static void msm_handle_tx(struct uart_port
*port
)
859 struct msm_port
*msm_port
= UART_TO_MSM(port
);
860 struct circ_buf
*xmit
= &msm_port
->uart
.state
->xmit
;
861 struct msm_dma
*dma
= &msm_port
->tx_dma
;
862 unsigned int pio_count
, dma_count
, dma_min
;
867 if (msm_port
->is_uartdm
)
868 tf
= port
->membase
+ UARTDM_TF
;
870 tf
= port
->membase
+ UART_TF
;
872 if (msm_port
->is_uartdm
)
873 msm_reset_dm_count(port
, 1);
875 iowrite8_rep(tf
, &port
->x_char
, 1);
881 if (uart_circ_empty(xmit
) || uart_tx_stopped(port
)) {
886 pio_count
= CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
);
887 dma_count
= CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
);
889 dma_min
= 1; /* Always DMA */
890 if (msm_port
->is_uartdm
> UARTDM_1P3
) {
891 dma_count
= UARTDM_TX_AIGN(dma_count
);
892 dma_min
= UARTDM_BURST_SIZE
;
894 if (dma_count
> UARTDM_TX_MAX
)
895 dma_count
= UARTDM_TX_MAX
;
898 if (pio_count
> port
->fifosize
)
899 pio_count
= port
->fifosize
;
901 if (!dma
->chan
|| dma_count
< dma_min
)
902 msm_handle_tx_pio(port
, pio_count
);
904 err
= msm_handle_tx_dma(msm_port
, dma_count
);
906 if (err
) /* fall back to PIO mode */
907 msm_handle_tx_pio(port
, pio_count
);
910 static void msm_handle_delta_cts(struct uart_port
*port
)
912 msm_write(port
, UART_CR_CMD_RESET_CTS
, UART_CR
);
914 wake_up_interruptible(&port
->state
->port
.delta_msr_wait
);
917 static irqreturn_t
msm_uart_irq(int irq
, void *dev_id
)
919 struct uart_port
*port
= dev_id
;
920 struct msm_port
*msm_port
= UART_TO_MSM(port
);
921 struct msm_dma
*dma
= &msm_port
->rx_dma
;
926 spin_lock_irqsave(&port
->lock
, flags
);
927 misr
= msm_read(port
, UART_MISR
);
928 msm_write(port
, 0, UART_IMR
); /* disable interrupt */
930 if (misr
& UART_IMR_RXBREAK_START
) {
931 msm_port
->break_detected
= true;
932 msm_write(port
, UART_CR_CMD_RESET_RXBREAK_START
, UART_CR
);
935 if (misr
& (UART_IMR_RXLEV
| UART_IMR_RXSTALE
)) {
937 val
= UART_CR_CMD_STALE_EVENT_DISABLE
;
938 msm_write(port
, val
, UART_CR
);
939 val
= UART_CR_CMD_RESET_STALE_INT
;
940 msm_write(port
, val
, UART_CR
);
942 * Flush DMA input fifo to memory, this will also
943 * trigger DMA RX completion
945 dmaengine_terminate_all(dma
->chan
);
946 } else if (msm_port
->is_uartdm
) {
947 msm_handle_rx_dm(port
, misr
);
952 if (misr
& UART_IMR_TXLEV
)
954 if (misr
& UART_IMR_DELTA_CTS
)
955 msm_handle_delta_cts(port
);
957 msm_write(port
, msm_port
->imr
, UART_IMR
); /* restore interrupt */
958 spin_unlock_irqrestore(&port
->lock
, flags
);
963 static unsigned int msm_tx_empty(struct uart_port
*port
)
965 return (msm_read(port
, UART_SR
) & UART_SR_TX_EMPTY
) ? TIOCSER_TEMT
: 0;
968 static unsigned int msm_get_mctrl(struct uart_port
*port
)
970 return TIOCM_CAR
| TIOCM_CTS
| TIOCM_DSR
| TIOCM_RTS
;
973 static void msm_reset(struct uart_port
*port
)
975 struct msm_port
*msm_port
= UART_TO_MSM(port
);
977 /* reset everything */
978 msm_write(port
, UART_CR_CMD_RESET_RX
, UART_CR
);
979 msm_write(port
, UART_CR_CMD_RESET_TX
, UART_CR
);
980 msm_write(port
, UART_CR_CMD_RESET_ERR
, UART_CR
);
981 msm_write(port
, UART_CR_CMD_RESET_BREAK_INT
, UART_CR
);
982 msm_write(port
, UART_CR_CMD_RESET_CTS
, UART_CR
);
983 msm_write(port
, UART_CR_CMD_SET_RFR
, UART_CR
);
985 /* Disable DM modes */
986 if (msm_port
->is_uartdm
)
987 msm_write(port
, 0, UARTDM_DMEN
);
990 static void msm_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
994 mr
= msm_read(port
, UART_MR1
);
996 if (!(mctrl
& TIOCM_RTS
)) {
997 mr
&= ~UART_MR1_RX_RDY_CTL
;
998 msm_write(port
, mr
, UART_MR1
);
999 msm_write(port
, UART_CR_CMD_RESET_RFR
, UART_CR
);
1001 mr
|= UART_MR1_RX_RDY_CTL
;
1002 msm_write(port
, mr
, UART_MR1
);
1006 static void msm_break_ctl(struct uart_port
*port
, int break_ctl
)
1009 msm_write(port
, UART_CR_CMD_START_BREAK
, UART_CR
);
1011 msm_write(port
, UART_CR_CMD_STOP_BREAK
, UART_CR
);
1014 struct msm_baud_map
{
1020 static const struct msm_baud_map
*
1021 msm_find_best_baud(struct uart_port
*port
, unsigned int baud
,
1022 unsigned long *rate
)
1024 struct msm_port
*msm_port
= UART_TO_MSM(port
);
1025 unsigned int divisor
, result
;
1026 unsigned long target
, old
, best_rate
= 0, diff
, best_diff
= ULONG_MAX
;
1027 const struct msm_baud_map
*entry
, *end
, *best
;
1028 static const struct msm_baud_map table
[] = {
1047 best
= table
; /* Default to smallest divider */
1048 target
= clk_round_rate(msm_port
->clk
, 16 * baud
);
1049 divisor
= DIV_ROUND_CLOSEST(target
, 16 * baud
);
1051 end
= table
+ ARRAY_SIZE(table
);
1053 while (entry
< end
) {
1054 if (entry
->divisor
<= divisor
) {
1055 result
= target
/ entry
->divisor
/ 16;
1056 diff
= abs(result
- baud
);
1058 /* Keep track of best entry */
1059 if (diff
< best_diff
) {
1067 } else if (entry
->divisor
> divisor
) {
1069 target
= clk_round_rate(msm_port
->clk
, old
+ 1);
1071 * The rate didn't get any faster so we can't do
1072 * better at dividing it down
1077 /* Start the divisor search over at this new rate */
1079 divisor
= DIV_ROUND_CLOSEST(target
, 16 * baud
);
1089 static int msm_set_baud_rate(struct uart_port
*port
, unsigned int baud
,
1090 unsigned long *saved_flags
)
1092 unsigned int rxstale
, watermark
, mask
;
1093 struct msm_port
*msm_port
= UART_TO_MSM(port
);
1094 const struct msm_baud_map
*entry
;
1095 unsigned long flags
, rate
;
1097 flags
= *saved_flags
;
1098 spin_unlock_irqrestore(&port
->lock
, flags
);
1100 entry
= msm_find_best_baud(port
, baud
, &rate
);
1101 clk_set_rate(msm_port
->clk
, rate
);
1102 baud
= rate
/ 16 / entry
->divisor
;
1104 spin_lock_irqsave(&port
->lock
, flags
);
1105 *saved_flags
= flags
;
1106 port
->uartclk
= rate
;
1108 msm_write(port
, entry
->code
, UART_CSR
);
1110 /* RX stale watermark */
1111 rxstale
= entry
->rxstale
;
1112 watermark
= UART_IPR_STALE_LSB
& rxstale
;
1113 if (msm_port
->is_uartdm
) {
1114 mask
= UART_DM_IPR_STALE_TIMEOUT_MSB
;
1116 watermark
|= UART_IPR_RXSTALE_LAST
;
1117 mask
= UART_IPR_STALE_TIMEOUT_MSB
;
1120 watermark
|= mask
& (rxstale
<< 2);
1122 msm_write(port
, watermark
, UART_IPR
);
1124 /* set RX watermark */
1125 watermark
= (port
->fifosize
* 3) / 4;
1126 msm_write(port
, watermark
, UART_RFWR
);
1128 /* set TX watermark */
1129 msm_write(port
, 10, UART_TFWR
);
1131 msm_write(port
, UART_CR_CMD_PROTECTION_EN
, UART_CR
);
1134 /* Enable RX and TX */
1135 msm_write(port
, UART_CR_TX_ENABLE
| UART_CR_RX_ENABLE
, UART_CR
);
1137 /* turn on RX and CTS interrupts */
1138 msm_port
->imr
= UART_IMR_RXLEV
| UART_IMR_RXSTALE
|
1139 UART_IMR_CURRENT_CTS
| UART_IMR_RXBREAK_START
;
1141 msm_write(port
, msm_port
->imr
, UART_IMR
);
1143 if (msm_port
->is_uartdm
) {
1144 msm_write(port
, UART_CR_CMD_RESET_STALE_INT
, UART_CR
);
1145 msm_write(port
, 0xFFFFFF, UARTDM_DMRX
);
1146 msm_write(port
, UART_CR_CMD_STALE_EVENT_ENABLE
, UART_CR
);
1152 static void msm_init_clock(struct uart_port
*port
)
1154 struct msm_port
*msm_port
= UART_TO_MSM(port
);
1156 clk_prepare_enable(msm_port
->clk
);
1157 clk_prepare_enable(msm_port
->pclk
);
1158 msm_serial_set_mnd_regs(port
);
1161 static int msm_startup(struct uart_port
*port
)
1163 struct msm_port
*msm_port
= UART_TO_MSM(port
);
1164 unsigned int data
, rfr_level
, mask
;
1167 snprintf(msm_port
->name
, sizeof(msm_port
->name
),
1168 "msm_serial%d", port
->line
);
1170 msm_init_clock(port
);
1172 if (likely(port
->fifosize
> 12))
1173 rfr_level
= port
->fifosize
- 12;
1175 rfr_level
= port
->fifosize
;
1177 /* set automatic RFR level */
1178 data
= msm_read(port
, UART_MR1
);
1180 if (msm_port
->is_uartdm
)
1181 mask
= UART_DM_MR1_AUTO_RFR_LEVEL1
;
1183 mask
= UART_MR1_AUTO_RFR_LEVEL1
;
1186 data
&= ~UART_MR1_AUTO_RFR_LEVEL0
;
1187 data
|= mask
& (rfr_level
<< 2);
1188 data
|= UART_MR1_AUTO_RFR_LEVEL0
& rfr_level
;
1189 msm_write(port
, data
, UART_MR1
);
1191 if (msm_port
->is_uartdm
) {
1192 msm_request_tx_dma(msm_port
, msm_port
->uart
.mapbase
);
1193 msm_request_rx_dma(msm_port
, msm_port
->uart
.mapbase
);
1196 ret
= request_irq(port
->irq
, msm_uart_irq
, IRQF_TRIGGER_HIGH
,
1197 msm_port
->name
, port
);
1204 if (msm_port
->is_uartdm
)
1205 msm_release_dma(msm_port
);
1207 clk_disable_unprepare(msm_port
->pclk
);
1208 clk_disable_unprepare(msm_port
->clk
);
1213 static void msm_shutdown(struct uart_port
*port
)
1215 struct msm_port
*msm_port
= UART_TO_MSM(port
);
1218 msm_write(port
, 0, UART_IMR
); /* disable interrupts */
1220 if (msm_port
->is_uartdm
)
1221 msm_release_dma(msm_port
);
1223 clk_disable_unprepare(msm_port
->clk
);
1225 free_irq(port
->irq
, port
);
1228 static void msm_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1229 struct ktermios
*old
)
1231 struct msm_port
*msm_port
= UART_TO_MSM(port
);
1232 struct msm_dma
*dma
= &msm_port
->rx_dma
;
1233 unsigned long flags
;
1234 unsigned int baud
, mr
;
1236 spin_lock_irqsave(&port
->lock
, flags
);
1238 if (dma
->chan
) /* Terminate if any */
1239 msm_stop_dma(port
, dma
);
1241 /* calculate and set baud rate */
1242 baud
= uart_get_baud_rate(port
, termios
, old
, 300, 4000000);
1243 baud
= msm_set_baud_rate(port
, baud
, &flags
);
1244 if (tty_termios_baud_rate(termios
))
1245 tty_termios_encode_baud_rate(termios
, baud
, baud
);
1247 /* calculate parity */
1248 mr
= msm_read(port
, UART_MR2
);
1249 mr
&= ~UART_MR2_PARITY_MODE
;
1250 if (termios
->c_cflag
& PARENB
) {
1251 if (termios
->c_cflag
& PARODD
)
1252 mr
|= UART_MR2_PARITY_MODE_ODD
;
1253 else if (termios
->c_cflag
& CMSPAR
)
1254 mr
|= UART_MR2_PARITY_MODE_SPACE
;
1256 mr
|= UART_MR2_PARITY_MODE_EVEN
;
1259 /* calculate bits per char */
1260 mr
&= ~UART_MR2_BITS_PER_CHAR
;
1261 switch (termios
->c_cflag
& CSIZE
) {
1263 mr
|= UART_MR2_BITS_PER_CHAR_5
;
1266 mr
|= UART_MR2_BITS_PER_CHAR_6
;
1269 mr
|= UART_MR2_BITS_PER_CHAR_7
;
1273 mr
|= UART_MR2_BITS_PER_CHAR_8
;
1277 /* calculate stop bits */
1278 mr
&= ~(UART_MR2_STOP_BIT_LEN_ONE
| UART_MR2_STOP_BIT_LEN_TWO
);
1279 if (termios
->c_cflag
& CSTOPB
)
1280 mr
|= UART_MR2_STOP_BIT_LEN_TWO
;
1282 mr
|= UART_MR2_STOP_BIT_LEN_ONE
;
1284 /* set parity, bits per char, and stop bit */
1285 msm_write(port
, mr
, UART_MR2
);
1287 /* calculate and set hardware flow control */
1288 mr
= msm_read(port
, UART_MR1
);
1289 mr
&= ~(UART_MR1_CTS_CTL
| UART_MR1_RX_RDY_CTL
);
1290 if (termios
->c_cflag
& CRTSCTS
) {
1291 mr
|= UART_MR1_CTS_CTL
;
1292 mr
|= UART_MR1_RX_RDY_CTL
;
1294 msm_write(port
, mr
, UART_MR1
);
1296 /* Configure status bits to ignore based on termio flags. */
1297 port
->read_status_mask
= 0;
1298 if (termios
->c_iflag
& INPCK
)
1299 port
->read_status_mask
|= UART_SR_PAR_FRAME_ERR
;
1300 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1301 port
->read_status_mask
|= UART_SR_RX_BREAK
;
1303 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1305 /* Try to use DMA */
1306 msm_start_rx_dma(msm_port
);
1308 spin_unlock_irqrestore(&port
->lock
, flags
);
1311 static const char *msm_type(struct uart_port
*port
)
1316 static void msm_release_port(struct uart_port
*port
)
1318 struct platform_device
*pdev
= to_platform_device(port
->dev
);
1319 struct resource
*uart_resource
;
1320 resource_size_t size
;
1322 uart_resource
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1323 if (unlikely(!uart_resource
))
1325 size
= resource_size(uart_resource
);
1327 release_mem_region(port
->mapbase
, size
);
1328 iounmap(port
->membase
);
1329 port
->membase
= NULL
;
1332 static int msm_request_port(struct uart_port
*port
)
1334 struct platform_device
*pdev
= to_platform_device(port
->dev
);
1335 struct resource
*uart_resource
;
1336 resource_size_t size
;
1339 uart_resource
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1340 if (unlikely(!uart_resource
))
1343 size
= resource_size(uart_resource
);
1345 if (!request_mem_region(port
->mapbase
, size
, "msm_serial"))
1348 port
->membase
= ioremap(port
->mapbase
, size
);
1349 if (!port
->membase
) {
1351 goto fail_release_port
;
1357 release_mem_region(port
->mapbase
, size
);
1361 static void msm_config_port(struct uart_port
*port
, int flags
)
1365 if (flags
& UART_CONFIG_TYPE
) {
1366 port
->type
= PORT_MSM
;
1367 ret
= msm_request_port(port
);
1373 static int msm_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1375 if (unlikely(ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_MSM
))
1377 if (unlikely(port
->irq
!= ser
->irq
))
1382 static void msm_power(struct uart_port
*port
, unsigned int state
,
1383 unsigned int oldstate
)
1385 struct msm_port
*msm_port
= UART_TO_MSM(port
);
1389 clk_prepare_enable(msm_port
->clk
);
1390 clk_prepare_enable(msm_port
->pclk
);
1393 clk_disable_unprepare(msm_port
->clk
);
1394 clk_disable_unprepare(msm_port
->pclk
);
1397 pr_err("msm_serial: Unknown PM state %d\n", state
);
1401 #ifdef CONFIG_CONSOLE_POLL
1402 static int msm_poll_get_char_single(struct uart_port
*port
)
1404 struct msm_port
*msm_port
= UART_TO_MSM(port
);
1405 unsigned int rf_reg
= msm_port
->is_uartdm
? UARTDM_RF
: UART_RF
;
1407 if (!(msm_read(port
, UART_SR
) & UART_SR_RX_READY
))
1408 return NO_POLL_CHAR
;
1410 return msm_read(port
, rf_reg
) & 0xff;
1413 static int msm_poll_get_char_dm(struct uart_port
*port
)
1418 unsigned char *sp
= (unsigned char *)&slop
;
1420 /* Check if a previous read had more than one char */
1422 c
= sp
[sizeof(slop
) - count
];
1424 /* Or if FIFO is empty */
1425 } else if (!(msm_read(port
, UART_SR
) & UART_SR_RX_READY
)) {
1427 * If RX packing buffer has less than a word, force stale to
1428 * push contents into RX FIFO
1430 count
= msm_read(port
, UARTDM_RXFS
);
1431 count
= (count
>> UARTDM_RXFS_BUF_SHIFT
) & UARTDM_RXFS_BUF_MASK
;
1433 msm_write(port
, UART_CR_CMD_FORCE_STALE
, UART_CR
);
1434 slop
= msm_read(port
, UARTDM_RF
);
1437 msm_write(port
, UART_CR_CMD_RESET_STALE_INT
, UART_CR
);
1438 msm_write(port
, 0xFFFFFF, UARTDM_DMRX
);
1439 msm_write(port
, UART_CR_CMD_STALE_EVENT_ENABLE
,
1444 /* FIFO has a word */
1446 slop
= msm_read(port
, UARTDM_RF
);
1448 count
= sizeof(slop
) - 1;
1454 static int msm_poll_get_char(struct uart_port
*port
)
1458 struct msm_port
*msm_port
= UART_TO_MSM(port
);
1460 /* Disable all interrupts */
1461 imr
= msm_read(port
, UART_IMR
);
1462 msm_write(port
, 0, UART_IMR
);
1464 if (msm_port
->is_uartdm
)
1465 c
= msm_poll_get_char_dm(port
);
1467 c
= msm_poll_get_char_single(port
);
1469 /* Enable interrupts */
1470 msm_write(port
, imr
, UART_IMR
);
1475 static void msm_poll_put_char(struct uart_port
*port
, unsigned char c
)
1478 struct msm_port
*msm_port
= UART_TO_MSM(port
);
1480 /* Disable all interrupts */
1481 imr
= msm_read(port
, UART_IMR
);
1482 msm_write(port
, 0, UART_IMR
);
1484 if (msm_port
->is_uartdm
)
1485 msm_reset_dm_count(port
, 1);
1487 /* Wait until FIFO is empty */
1488 while (!(msm_read(port
, UART_SR
) & UART_SR_TX_READY
))
1491 /* Write a character */
1492 msm_write(port
, c
, msm_port
->is_uartdm
? UARTDM_TF
: UART_TF
);
1494 /* Wait until FIFO is empty */
1495 while (!(msm_read(port
, UART_SR
) & UART_SR_TX_READY
))
1498 /* Enable interrupts */
1499 msm_write(port
, imr
, UART_IMR
);
1503 static struct uart_ops msm_uart_pops
= {
1504 .tx_empty
= msm_tx_empty
,
1505 .set_mctrl
= msm_set_mctrl
,
1506 .get_mctrl
= msm_get_mctrl
,
1507 .stop_tx
= msm_stop_tx
,
1508 .start_tx
= msm_start_tx
,
1509 .stop_rx
= msm_stop_rx
,
1510 .enable_ms
= msm_enable_ms
,
1511 .break_ctl
= msm_break_ctl
,
1512 .startup
= msm_startup
,
1513 .shutdown
= msm_shutdown
,
1514 .set_termios
= msm_set_termios
,
1516 .release_port
= msm_release_port
,
1517 .request_port
= msm_request_port
,
1518 .config_port
= msm_config_port
,
1519 .verify_port
= msm_verify_port
,
1521 #ifdef CONFIG_CONSOLE_POLL
1522 .poll_get_char
= msm_poll_get_char
,
1523 .poll_put_char
= msm_poll_put_char
,
1527 static struct msm_port msm_uart_ports
[] = {
1531 .ops
= &msm_uart_pops
,
1532 .flags
= UPF_BOOT_AUTOCONF
,
1540 .ops
= &msm_uart_pops
,
1541 .flags
= UPF_BOOT_AUTOCONF
,
1549 .ops
= &msm_uart_pops
,
1550 .flags
= UPF_BOOT_AUTOCONF
,
1557 #define UART_NR ARRAY_SIZE(msm_uart_ports)
1559 static inline struct uart_port
*msm_get_port_from_line(unsigned int line
)
1561 return &msm_uart_ports
[line
].uart
;
1564 #ifdef CONFIG_SERIAL_MSM_CONSOLE
1565 static void __msm_console_write(struct uart_port
*port
, const char *s
,
1566 unsigned int count
, bool is_uartdm
)
1569 int num_newlines
= 0;
1570 bool replaced
= false;
1574 tf
= port
->membase
+ UARTDM_TF
;
1576 tf
= port
->membase
+ UART_TF
;
1578 /* Account for newlines that will get a carriage return added */
1579 for (i
= 0; i
< count
; i
++)
1582 count
+= num_newlines
;
1584 spin_lock(&port
->lock
);
1586 msm_reset_dm_count(port
, count
);
1591 unsigned int num_chars
;
1592 char buf
[4] = { 0 };
1595 num_chars
= min(count
- i
, (unsigned int)sizeof(buf
));
1599 for (j
= 0; j
< num_chars
; j
++) {
1602 if (c
== '\n' && !replaced
) {
1607 if (j
< num_chars
) {
1614 while (!(msm_read(port
, UART_SR
) & UART_SR_TX_READY
))
1617 iowrite32_rep(tf
, buf
, 1);
1620 spin_unlock(&port
->lock
);
1623 static void msm_console_write(struct console
*co
, const char *s
,
1626 struct uart_port
*port
;
1627 struct msm_port
*msm_port
;
1629 BUG_ON(co
->index
< 0 || co
->index
>= UART_NR
);
1631 port
= msm_get_port_from_line(co
->index
);
1632 msm_port
= UART_TO_MSM(port
);
1634 __msm_console_write(port
, s
, count
, msm_port
->is_uartdm
);
1637 static int __init
msm_console_setup(struct console
*co
, char *options
)
1639 struct uart_port
*port
;
1645 if (unlikely(co
->index
>= UART_NR
|| co
->index
< 0))
1648 port
= msm_get_port_from_line(co
->index
);
1650 if (unlikely(!port
->membase
))
1653 msm_init_clock(port
);
1656 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1658 pr_info("msm_serial: console setup on port #%d\n", port
->line
);
1660 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
1664 msm_serial_early_write(struct console
*con
, const char *s
, unsigned n
)
1666 struct earlycon_device
*dev
= con
->data
;
1668 __msm_console_write(&dev
->port
, s
, n
, false);
1672 msm_serial_early_console_setup(struct earlycon_device
*device
, const char *opt
)
1674 if (!device
->port
.membase
)
1677 device
->con
->write
= msm_serial_early_write
;
1680 OF_EARLYCON_DECLARE(msm_serial
, "qcom,msm-uart",
1681 msm_serial_early_console_setup
);
1684 msm_serial_early_write_dm(struct console
*con
, const char *s
, unsigned n
)
1686 struct earlycon_device
*dev
= con
->data
;
1688 __msm_console_write(&dev
->port
, s
, n
, true);
1692 msm_serial_early_console_setup_dm(struct earlycon_device
*device
,
1695 if (!device
->port
.membase
)
1698 device
->con
->write
= msm_serial_early_write_dm
;
1701 OF_EARLYCON_DECLARE(msm_serial_dm
, "qcom,msm-uartdm",
1702 msm_serial_early_console_setup_dm
);
1704 static struct uart_driver msm_uart_driver
;
1706 static struct console msm_console
= {
1708 .write
= msm_console_write
,
1709 .device
= uart_console_device
,
1710 .setup
= msm_console_setup
,
1711 .flags
= CON_PRINTBUFFER
,
1713 .data
= &msm_uart_driver
,
1716 #define MSM_CONSOLE (&msm_console)
1719 #define MSM_CONSOLE NULL
1722 static struct uart_driver msm_uart_driver
= {
1723 .owner
= THIS_MODULE
,
1724 .driver_name
= "msm_serial",
1725 .dev_name
= "ttyMSM",
1727 .cons
= MSM_CONSOLE
,
1730 static atomic_t msm_uart_next_id
= ATOMIC_INIT(0);
1732 static const struct of_device_id msm_uartdm_table
[] = {
1733 { .compatible
= "qcom,msm-uartdm-v1.1", .data
= (void *)UARTDM_1P1
},
1734 { .compatible
= "qcom,msm-uartdm-v1.2", .data
= (void *)UARTDM_1P2
},
1735 { .compatible
= "qcom,msm-uartdm-v1.3", .data
= (void *)UARTDM_1P3
},
1736 { .compatible
= "qcom,msm-uartdm-v1.4", .data
= (void *)UARTDM_1P4
},
1740 static int msm_serial_probe(struct platform_device
*pdev
)
1742 struct msm_port
*msm_port
;
1743 struct resource
*resource
;
1744 struct uart_port
*port
;
1745 const struct of_device_id
*id
;
1748 if (pdev
->dev
.of_node
)
1749 line
= of_alias_get_id(pdev
->dev
.of_node
, "serial");
1754 line
= atomic_inc_return(&msm_uart_next_id
) - 1;
1756 if (unlikely(line
< 0 || line
>= UART_NR
))
1759 dev_info(&pdev
->dev
, "msm_serial: detected port #%d\n", line
);
1761 port
= msm_get_port_from_line(line
);
1762 port
->dev
= &pdev
->dev
;
1763 msm_port
= UART_TO_MSM(port
);
1765 id
= of_match_device(msm_uartdm_table
, &pdev
->dev
);
1767 msm_port
->is_uartdm
= (unsigned long)id
->data
;
1769 msm_port
->is_uartdm
= 0;
1771 msm_port
->clk
= devm_clk_get(&pdev
->dev
, "core");
1772 if (IS_ERR(msm_port
->clk
))
1773 return PTR_ERR(msm_port
->clk
);
1775 if (msm_port
->is_uartdm
) {
1776 msm_port
->pclk
= devm_clk_get(&pdev
->dev
, "iface");
1777 if (IS_ERR(msm_port
->pclk
))
1778 return PTR_ERR(msm_port
->pclk
);
1781 port
->uartclk
= clk_get_rate(msm_port
->clk
);
1782 dev_info(&pdev
->dev
, "uartclk = %d\n", port
->uartclk
);
1784 resource
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1785 if (unlikely(!resource
))
1787 port
->mapbase
= resource
->start
;
1789 irq
= platform_get_irq(pdev
, 0);
1790 if (unlikely(irq
< 0))
1794 platform_set_drvdata(pdev
, port
);
1796 return uart_add_one_port(&msm_uart_driver
, port
);
1799 static int msm_serial_remove(struct platform_device
*pdev
)
1801 struct uart_port
*port
= platform_get_drvdata(pdev
);
1803 uart_remove_one_port(&msm_uart_driver
, port
);
1808 static const struct of_device_id msm_match_table
[] = {
1809 { .compatible
= "qcom,msm-uart" },
1810 { .compatible
= "qcom,msm-uartdm" },
1813 MODULE_DEVICE_TABLE(of
, msm_match_table
);
1815 static struct platform_driver msm_platform_driver
= {
1816 .remove
= msm_serial_remove
,
1817 .probe
= msm_serial_probe
,
1819 .name
= "msm_serial",
1820 .of_match_table
= msm_match_table
,
1824 static int __init
msm_serial_init(void)
1828 ret
= uart_register_driver(&msm_uart_driver
);
1832 ret
= platform_driver_register(&msm_platform_driver
);
1834 uart_unregister_driver(&msm_uart_driver
);
1836 pr_info("msm_serial: driver initialized\n");
1841 static void __exit
msm_serial_exit(void)
1843 platform_driver_unregister(&msm_platform_driver
);
1844 uart_unregister_driver(&msm_uart_driver
);
1847 module_init(msm_serial_init
);
1848 module_exit(msm_serial_exit
);
1850 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1851 MODULE_DESCRIPTION("Driver for msm7x serial device");
1852 MODULE_LICENSE("GPL");