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Linux 4.16.11
[linux/fpc-iii.git] / drivers / usb / dwc3 / core.c
blobdf4569df7eaff0fb44433542f6a580c3b68cafb9
1 // SPDX-License-Identifier: GPL-2.0
2 /**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/version.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/io.h>
21 #include <linux/list.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/of.h>
25 #include <linux/acpi.h>
26 #include <linux/pinctrl/consumer.h>
27
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
30 #include <linux/usb/of.h>
31 #include <linux/usb/otg.h>
32
33 #include "core.h"
34 #include "gadget.h"
35 #include "io.h"
36
37 #include "debug.h"
38
39 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
40
41 /**
42 * dwc3_get_dr_mode - Validates and sets dr_mode
43 * @dwc: pointer to our context structure
44 */
45 static int dwc3_get_dr_mode(struct dwc3 *dwc)
46 {
47 enum usb_dr_mode mode;
48 struct device *dev = dwc->dev;
49 unsigned int hw_mode;
50
51 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
52 dwc->dr_mode = USB_DR_MODE_OTG;
53
54 mode = dwc->dr_mode;
55 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
56
57 switch (hw_mode) {
58 case DWC3_GHWPARAMS0_MODE_GADGET:
59 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
60 dev_err(dev,
61 "Controller does not support host mode.\n");
62 return -EINVAL;
63 }
64 mode = USB_DR_MODE_PERIPHERAL;
65 break;
66 case DWC3_GHWPARAMS0_MODE_HOST:
67 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
68 dev_err(dev,
69 "Controller does not support device mode.\n");
70 return -EINVAL;
71 }
72 mode = USB_DR_MODE_HOST;
73 break;
74 default:
75 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
76 mode = USB_DR_MODE_HOST;
77 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
78 mode = USB_DR_MODE_PERIPHERAL;
79 }
80
81 if (mode != dwc->dr_mode) {
82 dev_warn(dev,
83 "Configuration mismatch. dr_mode forced to %s\n",
84 mode == USB_DR_MODE_HOST ? "host" : "gadget");
85
86 dwc->dr_mode = mode;
87 }
88
89 return 0;
90 }
91
92 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
93 static int dwc3_event_buffers_setup(struct dwc3 *dwc);
94
95 static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
96 {
97 u32 reg;
98
99 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
100 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
101 reg |= DWC3_GCTL_PRTCAPDIR(mode);
102 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
103
104 dwc->current_dr_role = mode;
105 }
106
107 static void __dwc3_set_mode(struct work_struct *work)
108 {
109 struct dwc3 *dwc = work_to_dwc(work);
110 unsigned long flags;
111 int ret;
112
113 if (!dwc->desired_dr_role)
114 return;
115
116 if (dwc->desired_dr_role == dwc->current_dr_role)
117 return;
118
119 if (dwc->dr_mode != USB_DR_MODE_OTG)
120 return;
121
122 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG)
123 return;
124
125 switch (dwc->current_dr_role) {
126 case DWC3_GCTL_PRTCAP_HOST:
127 dwc3_host_exit(dwc);
128 break;
129 case DWC3_GCTL_PRTCAP_DEVICE:
130 dwc3_gadget_exit(dwc);
131 dwc3_event_buffers_cleanup(dwc);
132 break;
133 default:
134 break;
135 }
136
137 spin_lock_irqsave(&dwc->lock, flags);
138
139 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
140
141 spin_unlock_irqrestore(&dwc->lock, flags);
142
143 switch (dwc->desired_dr_role) {
144 case DWC3_GCTL_PRTCAP_HOST:
145 ret = dwc3_host_init(dwc);
146 if (ret) {
147 dev_err(dwc->dev, "failed to initialize host\n");
148 } else {
149 if (dwc->usb2_phy)
150 otg_set_vbus(dwc->usb2_phy->otg, true);
151 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
152 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
153 phy_calibrate(dwc->usb2_generic_phy);
154 }
155 break;
156 case DWC3_GCTL_PRTCAP_DEVICE:
157 dwc3_event_buffers_setup(dwc);
158
159 if (dwc->usb2_phy)
160 otg_set_vbus(dwc->usb2_phy->otg, false);
161 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
162 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
163
164 ret = dwc3_gadget_init(dwc);
165 if (ret)
166 dev_err(dwc->dev, "failed to initialize peripheral\n");
167 break;
168 default:
169 break;
170 }
171 }
172
173 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
174 {
175 unsigned long flags;
176
177 spin_lock_irqsave(&dwc->lock, flags);
178 dwc->desired_dr_role = mode;
179 spin_unlock_irqrestore(&dwc->lock, flags);
180
181 queue_work(system_freezable_wq, &dwc->drd_work);
182 }
183
184 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
185 {
186 struct dwc3 *dwc = dep->dwc;
187 u32 reg;
188
189 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
190 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
191 DWC3_GDBGFIFOSPACE_TYPE(type));
192
193 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
194
195 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
196 }
197
198 /**
199 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
200 * @dwc: pointer to our context structure
201 */
202 static int dwc3_core_soft_reset(struct dwc3 *dwc)
203 {
204 u32 reg;
205 int retries = 1000;
206 int ret;
207
208 usb_phy_init(dwc->usb2_phy);
209 usb_phy_init(dwc->usb3_phy);
210 ret = phy_init(dwc->usb2_generic_phy);
211 if (ret < 0)
212 return ret;
213
214 ret = phy_init(dwc->usb3_generic_phy);
215 if (ret < 0) {
216 phy_exit(dwc->usb2_generic_phy);
217 return ret;
218 }
219
220 /*
221 * We're resetting only the device side because, if we're in host mode,
222 * XHCI driver will reset the host block. If dwc3 was configured for
223 * host-only mode, then we can return early.
224 */
225 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
226 return 0;
227
228 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
229 reg |= DWC3_DCTL_CSFTRST;
230 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
231
232 do {
233 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
234 if (!(reg & DWC3_DCTL_CSFTRST))
235 return 0;
236
237 udelay(1);
238 } while (--retries);
239
240 phy_exit(dwc->usb3_generic_phy);
241 phy_exit(dwc->usb2_generic_phy);
242
243 return -ETIMEDOUT;
244 }
245
246 /*
247 * dwc3_frame_length_adjustment - Adjusts frame length if required
248 * @dwc3: Pointer to our controller context structure
249 */
250 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
251 {
252 u32 reg;
253 u32 dft;
254
255 if (dwc->revision < DWC3_REVISION_250A)
256 return;
257
258 if (dwc->fladj == 0)
259 return;
260
261 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
262 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
263 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
264 "request value same as default, ignoring\n")) {
265 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
266 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
267 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
268 }
269 }
270
271 /**
272 * dwc3_free_one_event_buffer - Frees one event buffer
273 * @dwc: Pointer to our controller context structure
274 * @evt: Pointer to event buffer to be freed
275 */
276 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
277 struct dwc3_event_buffer *evt)
278 {
279 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
280 }
281
282 /**
283 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
284 * @dwc: Pointer to our controller context structure
285 * @length: size of the event buffer
286 *
287 * Returns a pointer to the allocated event buffer structure on success
288 * otherwise ERR_PTR(errno).
289 */
290 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
291 unsigned length)
292 {
293 struct dwc3_event_buffer *evt;
294
295 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
296 if (!evt)
297 return ERR_PTR(-ENOMEM);
298
299 evt->dwc = dwc;
300 evt->length = length;
301 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
302 if (!evt->cache)
303 return ERR_PTR(-ENOMEM);
304
305 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
306 &evt->dma, GFP_KERNEL);
307 if (!evt->buf)
308 return ERR_PTR(-ENOMEM);
309
310 return evt;
311 }
312
313 /**
314 * dwc3_free_event_buffers - frees all allocated event buffers
315 * @dwc: Pointer to our controller context structure
316 */
317 static void dwc3_free_event_buffers(struct dwc3 *dwc)
318 {
319 struct dwc3_event_buffer *evt;
320
321 evt = dwc->ev_buf;
322 if (evt)
323 dwc3_free_one_event_buffer(dwc, evt);
324 }
325
326 /**
327 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
328 * @dwc: pointer to our controller context structure
329 * @length: size of event buffer
330 *
331 * Returns 0 on success otherwise negative errno. In the error case, dwc
332 * may contain some buffers allocated but not all which were requested.
333 */
334 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
335 {
336 struct dwc3_event_buffer *evt;
337
338 evt = dwc3_alloc_one_event_buffer(dwc, length);
339 if (IS_ERR(evt)) {
340 dev_err(dwc->dev, "can't allocate event buffer\n");
341 return PTR_ERR(evt);
342 }
343 dwc->ev_buf = evt;
344
345 return 0;
346 }
347
348 /**
349 * dwc3_event_buffers_setup - setup our allocated event buffers
350 * @dwc: pointer to our controller context structure
351 *
352 * Returns 0 on success otherwise negative errno.
353 */
354 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
355 {
356 struct dwc3_event_buffer *evt;
357
358 evt = dwc->ev_buf;
359 evt->lpos = 0;
360 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
361 lower_32_bits(evt->dma));
362 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
363 upper_32_bits(evt->dma));
364 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
365 DWC3_GEVNTSIZ_SIZE(evt->length));
366 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
367
368 return 0;
369 }
370
371 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
372 {
373 struct dwc3_event_buffer *evt;
374
375 evt = dwc->ev_buf;
376
377 evt->lpos = 0;
378
379 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
380 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
381 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
382 | DWC3_GEVNTSIZ_SIZE(0));
383 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
384 }
385
386 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
387 {
388 if (!dwc->has_hibernation)
389 return 0;
390
391 if (!dwc->nr_scratch)
392 return 0;
393
394 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
395 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
396 if (!dwc->scratchbuf)
397 return -ENOMEM;
398
399 return 0;
400 }
401
402 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
403 {
404 dma_addr_t scratch_addr;
405 u32 param;
406 int ret;
407
408 if (!dwc->has_hibernation)
409 return 0;
410
411 if (!dwc->nr_scratch)
412 return 0;
413
414 /* should never fall here */
415 if (!WARN_ON(dwc->scratchbuf))
416 return 0;
417
418 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
419 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
420 DMA_BIDIRECTIONAL);
421 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
422 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
423 ret = -EFAULT;
424 goto err0;
425 }
426
427 dwc->scratch_addr = scratch_addr;
428
429 param = lower_32_bits(scratch_addr);
430
431 ret = dwc3_send_gadget_generic_command(dwc,
432 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
433 if (ret < 0)
434 goto err1;
435
436 param = upper_32_bits(scratch_addr);
437
438 ret = dwc3_send_gadget_generic_command(dwc,
439 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
440 if (ret < 0)
441 goto err1;
442
443 return 0;
444
445 err1:
446 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
447 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
448
449 err0:
450 return ret;
451 }
452
453 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
454 {
455 if (!dwc->has_hibernation)
456 return;
457
458 if (!dwc->nr_scratch)
459 return;
460
461 /* should never fall here */
462 if (!WARN_ON(dwc->scratchbuf))
463 return;
464
465 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
466 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
467 kfree(dwc->scratchbuf);
468 }
469
470 static void dwc3_core_num_eps(struct dwc3 *dwc)
471 {
472 struct dwc3_hwparams *parms = &dwc->hwparams;
473
474 dwc->num_eps = DWC3_NUM_EPS(parms);
475 }
476
477 static void dwc3_cache_hwparams(struct dwc3 *dwc)
478 {
479 struct dwc3_hwparams *parms = &dwc->hwparams;
480
481 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
482 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
483 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
484 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
485 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
486 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
487 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
488 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
489 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
490 }
491
492 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
493 {
494 int intf;
495 int ret = 0;
496
497 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
498
499 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
500 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
501 dwc->hsphy_interface &&
502 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
503 ret = dwc3_ulpi_init(dwc);
504
505 return ret;
506 }
507
508 /**
509 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
510 * @dwc: Pointer to our controller context structure
511 *
512 * Returns 0 on success. The USB PHY interfaces are configured but not
513 * initialized. The PHY interfaces and the PHYs get initialized together with
514 * the core in dwc3_core_init.
515 */
516 static int dwc3_phy_setup(struct dwc3 *dwc)
517 {
518 u32 reg;
519
520 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
521
522 /*
523 * Make sure UX_EXIT_PX is cleared as that causes issues with some
524 * PHYs. Also, this bit is not supposed to be used in normal operation.
525 */
526 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
527
528 /*
529 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
530 * to '0' during coreConsultant configuration. So default value
531 * will be '0' when the core is reset. Application needs to set it
532 * to '1' after the core initialization is completed.
533 */
534 if (dwc->revision > DWC3_REVISION_194A)
535 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
536
537 if (dwc->u2ss_inp3_quirk)
538 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
539
540 if (dwc->dis_rxdet_inp3_quirk)
541 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
542
543 if (dwc->req_p1p2p3_quirk)
544 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
545
546 if (dwc->del_p1p2p3_quirk)
547 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
548
549 if (dwc->del_phy_power_chg_quirk)
550 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
551
552 if (dwc->lfps_filter_quirk)
553 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
554
555 if (dwc->rx_detect_poll_quirk)
556 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
557
558 if (dwc->tx_de_emphasis_quirk)
559 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
560
561 if (dwc->dis_u3_susphy_quirk)
562 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
563
564 if (dwc->dis_del_phy_power_chg_quirk)
565 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
566
567 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
568
569 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
570
571 /* Select the HS PHY interface */
572 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
573 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
574 if (dwc->hsphy_interface &&
575 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
576 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
577 break;
578 } else if (dwc->hsphy_interface &&
579 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
580 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
581 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
582 } else {
583 /* Relying on default value. */
584 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
585 break;
586 }
587 /* FALLTHROUGH */
588 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
589 /* FALLTHROUGH */
590 default:
591 break;
592 }
593
594 switch (dwc->hsphy_mode) {
595 case USBPHY_INTERFACE_MODE_UTMI:
596 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
597 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
598 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
599 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
600 break;
601 case USBPHY_INTERFACE_MODE_UTMIW:
602 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
603 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
604 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
605 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
606 break;
607 default:
608 break;
609 }
610
611 /*
612 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
613 * '0' during coreConsultant configuration. So default value will
614 * be '0' when the core is reset. Application needs to set it to
615 * '1' after the core initialization is completed.
616 */
617 if (dwc->revision > DWC3_REVISION_194A)
618 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
619
620 if (dwc->dis_u2_susphy_quirk)
621 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
622
623 if (dwc->dis_enblslpm_quirk)
624 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
625
626 if (dwc->dis_u2_freeclk_exists_quirk)
627 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
628
629 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
630
631 return 0;
632 }
633
634 static void dwc3_core_exit(struct dwc3 *dwc)
635 {
636 dwc3_event_buffers_cleanup(dwc);
637
638 usb_phy_shutdown(dwc->usb2_phy);
639 usb_phy_shutdown(dwc->usb3_phy);
640 phy_exit(dwc->usb2_generic_phy);
641 phy_exit(dwc->usb3_generic_phy);
642
643 usb_phy_set_suspend(dwc->usb2_phy, 1);
644 usb_phy_set_suspend(dwc->usb3_phy, 1);
645 phy_power_off(dwc->usb2_generic_phy);
646 phy_power_off(dwc->usb3_generic_phy);
647 }
648
649 static bool dwc3_core_is_valid(struct dwc3 *dwc)
650 {
651 u32 reg;
652
653 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
654
655 /* This should read as U3 followed by revision number */
656 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
657 /* Detected DWC_usb3 IP */
658 dwc->revision = reg;
659 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
660 /* Detected DWC_usb31 IP */
661 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
662 dwc->revision |= DWC3_REVISION_IS_DWC31;
663 } else {
664 return false;
665 }
666
667 return true;
668 }
669
670 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
671 {
672 u32 hwparams4 = dwc->hwparams.hwparams4;
673 u32 reg;
674
675 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
676 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
677
678 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
679 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
680 /**
681 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
682 * issue which would cause xHCI compliance tests to fail.
683 *
684 * Because of that we cannot enable clock gating on such
685 * configurations.
686 *
687 * Refers to:
688 *
689 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
690 * SOF/ITP Mode Used
691 */
692 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
693 dwc->dr_mode == USB_DR_MODE_OTG) &&
694 (dwc->revision >= DWC3_REVISION_210A &&
695 dwc->revision <= DWC3_REVISION_250A))
696 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
697 else
698 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
699 break;
700 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
701 /* enable hibernation here */
702 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
703
704 /*
705 * REVISIT Enabling this bit so that host-mode hibernation
706 * will work. Device-mode hibernation is not yet implemented.
707 */
708 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
709 break;
710 default:
711 /* nothing */
712 break;
713 }
714
715 /* check if current dwc3 is on simulation board */
716 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
717 dev_info(dwc->dev, "Running with FPGA optmizations\n");
718 dwc->is_fpga = true;
719 }
720
721 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
722 "disable_scramble cannot be used on non-FPGA builds\n");
723
724 if (dwc->disable_scramble_quirk && dwc->is_fpga)
725 reg |= DWC3_GCTL_DISSCRAMBLE;
726 else
727 reg &= ~DWC3_GCTL_DISSCRAMBLE;
728
729 if (dwc->u2exit_lfps_quirk)
730 reg |= DWC3_GCTL_U2EXIT_LFPS;
731
732 /*
733 * WORKAROUND: DWC3 revisions <1.90a have a bug
734 * where the device can fail to connect at SuperSpeed
735 * and falls back to high-speed mode which causes
736 * the device to enter a Connect/Disconnect loop
737 */
738 if (dwc->revision < DWC3_REVISION_190A)
739 reg |= DWC3_GCTL_U2RSTECN;
740
741 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
742 }
743
744 static int dwc3_core_get_phy(struct dwc3 *dwc);
745 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
746
747 /**
748 * dwc3_core_init - Low-level initialization of DWC3 Core
749 * @dwc: Pointer to our controller context structure
750 *
751 * Returns 0 on success otherwise negative errno.
752 */
753 static int dwc3_core_init(struct dwc3 *dwc)
754 {
755 u32 reg;
756 int ret;
757
758 if (!dwc3_core_is_valid(dwc)) {
759 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
760 ret = -ENODEV;
761 goto err0;
762 }
763
764 /*
765 * Write Linux Version Code to our GUID register so it's easy to figure
766 * out which kernel version a bug was found.
767 */
768 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
769
770 /* Handle USB2.0-only core configuration */
771 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
772 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
773 if (dwc->maximum_speed == USB_SPEED_SUPER)
774 dwc->maximum_speed = USB_SPEED_HIGH;
775 }
776
777 ret = dwc3_phy_setup(dwc);
778 if (ret)
779 goto err0;
780
781 if (!dwc->ulpi_ready) {
782 ret = dwc3_core_ulpi_init(dwc);
783 if (ret)
784 goto err0;
785 dwc->ulpi_ready = true;
786 }
787
788 if (!dwc->phys_ready) {
789 ret = dwc3_core_get_phy(dwc);
790 if (ret)
791 goto err0a;
792 dwc->phys_ready = true;
793 }
794
795 ret = dwc3_core_soft_reset(dwc);
796 if (ret)
797 goto err0a;
798
799 dwc3_core_setup_global_control(dwc);
800 dwc3_core_num_eps(dwc);
801
802 ret = dwc3_setup_scratch_buffers(dwc);
803 if (ret)
804 goto err1;
805
806 /* Adjust Frame Length */
807 dwc3_frame_length_adjustment(dwc);
808
809 usb_phy_set_suspend(dwc->usb2_phy, 0);
810 usb_phy_set_suspend(dwc->usb3_phy, 0);
811 ret = phy_power_on(dwc->usb2_generic_phy);
812 if (ret < 0)
813 goto err2;
814
815 ret = phy_power_on(dwc->usb3_generic_phy);
816 if (ret < 0)
817 goto err3;
818
819 ret = dwc3_event_buffers_setup(dwc);
820 if (ret) {
821 dev_err(dwc->dev, "failed to setup event buffers\n");
822 goto err4;
823 }
824
825 /*
826 * ENDXFER polling is available on version 3.10a and later of
827 * the DWC_usb3 controller. It is NOT available in the
828 * DWC_usb31 controller.
829 */
830 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
831 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
832 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
833 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
834 }
835
836 if (dwc->revision >= DWC3_REVISION_250A) {
837 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
838
839 /*
840 * Enable hardware control of sending remote wakeup
841 * in HS when the device is in the L1 state.
842 */
843 if (dwc->revision >= DWC3_REVISION_290A)
844 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
845
846 if (dwc->dis_tx_ipgap_linecheck_quirk)
847 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
848
849 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
850 }
851
852 return 0;
853
854 err4:
855 phy_power_off(dwc->usb3_generic_phy);
856
857 err3:
858 phy_power_off(dwc->usb2_generic_phy);
859
860 err2:
861 usb_phy_set_suspend(dwc->usb2_phy, 1);
862 usb_phy_set_suspend(dwc->usb3_phy, 1);
863
864 err1:
865 usb_phy_shutdown(dwc->usb2_phy);
866 usb_phy_shutdown(dwc->usb3_phy);
867 phy_exit(dwc->usb2_generic_phy);
868 phy_exit(dwc->usb3_generic_phy);
869
870 err0a:
871 dwc3_ulpi_exit(dwc);
872
873 err0:
874 return ret;
875 }
876
877 static int dwc3_core_get_phy(struct dwc3 *dwc)
878 {
879 struct device *dev = dwc->dev;
880 struct device_node *node = dev->of_node;
881 int ret;
882
883 if (node) {
884 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
885 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
886 } else {
887 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
888 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
889 }
890
891 if (IS_ERR(dwc->usb2_phy)) {
892 ret = PTR_ERR(dwc->usb2_phy);
893 if (ret == -ENXIO || ret == -ENODEV) {
894 dwc->usb2_phy = NULL;
895 } else if (ret == -EPROBE_DEFER) {
896 return ret;
897 } else {
898 dev_err(dev, "no usb2 phy configured\n");
899 return ret;
900 }
901 }
902
903 if (IS_ERR(dwc->usb3_phy)) {
904 ret = PTR_ERR(dwc->usb3_phy);
905 if (ret == -ENXIO || ret == -ENODEV) {
906 dwc->usb3_phy = NULL;
907 } else if (ret == -EPROBE_DEFER) {
908 return ret;
909 } else {
910 dev_err(dev, "no usb3 phy configured\n");
911 return ret;
912 }
913 }
914
915 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
916 if (IS_ERR(dwc->usb2_generic_phy)) {
917 ret = PTR_ERR(dwc->usb2_generic_phy);
918 if (ret == -ENOSYS || ret == -ENODEV) {
919 dwc->usb2_generic_phy = NULL;
920 } else if (ret == -EPROBE_DEFER) {
921 return ret;
922 } else {
923 dev_err(dev, "no usb2 phy configured\n");
924 return ret;
925 }
926 }
927
928 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
929 if (IS_ERR(dwc->usb3_generic_phy)) {
930 ret = PTR_ERR(dwc->usb3_generic_phy);
931 if (ret == -ENOSYS || ret == -ENODEV) {
932 dwc->usb3_generic_phy = NULL;
933 } else if (ret == -EPROBE_DEFER) {
934 return ret;
935 } else {
936 dev_err(dev, "no usb3 phy configured\n");
937 return ret;
938 }
939 }
940
941 return 0;
942 }
943
944 static int dwc3_core_init_mode(struct dwc3 *dwc)
945 {
946 struct device *dev = dwc->dev;
947 int ret;
948
949 switch (dwc->dr_mode) {
950 case USB_DR_MODE_PERIPHERAL:
951 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
952
953 if (dwc->usb2_phy)
954 otg_set_vbus(dwc->usb2_phy->otg, false);
955 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
956 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
957
958 ret = dwc3_gadget_init(dwc);
959 if (ret) {
960 if (ret != -EPROBE_DEFER)
961 dev_err(dev, "failed to initialize gadget\n");
962 return ret;
963 }
964 break;
965 case USB_DR_MODE_HOST:
966 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
967
968 if (dwc->usb2_phy)
969 otg_set_vbus(dwc->usb2_phy->otg, true);
970 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
971 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
972
973 ret = dwc3_host_init(dwc);
974 if (ret) {
975 if (ret != -EPROBE_DEFER)
976 dev_err(dev, "failed to initialize host\n");
977 return ret;
978 }
979 phy_calibrate(dwc->usb2_generic_phy);
980 break;
981 case USB_DR_MODE_OTG:
982 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
983 ret = dwc3_drd_init(dwc);
984 if (ret) {
985 if (ret != -EPROBE_DEFER)
986 dev_err(dev, "failed to initialize dual-role\n");
987 return ret;
988 }
989 break;
990 default:
991 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
992 return -EINVAL;
993 }
994
995 return 0;
996 }
997
998 static void dwc3_core_exit_mode(struct dwc3 *dwc)
999 {
1000 switch (dwc->dr_mode) {
1001 case USB_DR_MODE_PERIPHERAL:
1002 dwc3_gadget_exit(dwc);
1003 break;
1004 case USB_DR_MODE_HOST:
1005 dwc3_host_exit(dwc);
1006 break;
1007 case USB_DR_MODE_OTG:
1008 dwc3_drd_exit(dwc);
1009 break;
1010 default:
1011 /* do nothing */
1012 break;
1013 }
1014 }
1015
1016 static void dwc3_get_properties(struct dwc3 *dwc)
1017 {
1018 struct device *dev = dwc->dev;
1019 u8 lpm_nyet_threshold;
1020 u8 tx_de_emphasis;
1021 u8 hird_threshold;
1022
1023 /* default to highest possible threshold */
1024 lpm_nyet_threshold = 0xff;
1025
1026 /* default to -3.5dB de-emphasis */
1027 tx_de_emphasis = 1;
1028
1029 /*
1030 * default to assert utmi_sleep_n and use maximum allowed HIRD
1031 * threshold value of 0b1100
1032 */
1033 hird_threshold = 12;
1034
1035 dwc->maximum_speed = usb_get_maximum_speed(dev);
1036 dwc->dr_mode = usb_get_dr_mode(dev);
1037 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1038
1039 dwc->sysdev_is_parent = device_property_read_bool(dev,
1040 "linux,sysdev_is_parent");
1041 if (dwc->sysdev_is_parent)
1042 dwc->sysdev = dwc->dev->parent;
1043 else
1044 dwc->sysdev = dwc->dev;
1045
1046 dwc->has_lpm_erratum = device_property_read_bool(dev,
1047 "snps,has-lpm-erratum");
1048 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1049 &lpm_nyet_threshold);
1050 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1051 "snps,is-utmi-l1-suspend");
1052 device_property_read_u8(dev, "snps,hird-threshold",
1053 &hird_threshold);
1054 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1055 "snps,usb3_lpm_capable");
1056
1057 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1058 "snps,disable_scramble_quirk");
1059 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1060 "snps,u2exit_lfps_quirk");
1061 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1062 "snps,u2ss_inp3_quirk");
1063 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1064 "snps,req_p1p2p3_quirk");
1065 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1066 "snps,del_p1p2p3_quirk");
1067 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1068 "snps,del_phy_power_chg_quirk");
1069 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1070 "snps,lfps_filter_quirk");
1071 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1072 "snps,rx_detect_poll_quirk");
1073 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1074 "snps,dis_u3_susphy_quirk");
1075 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1076 "snps,dis_u2_susphy_quirk");
1077 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1078 "snps,dis_enblslpm_quirk");
1079 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1080 "snps,dis_rxdet_inp3_quirk");
1081 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1082 "snps,dis-u2-freeclk-exists-quirk");
1083 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1084 "snps,dis-del-phy-power-chg-quirk");
1085 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1086 "snps,dis-tx-ipgap-linecheck-quirk");
1087
1088 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1089 "snps,tx_de_emphasis_quirk");
1090 device_property_read_u8(dev, "snps,tx_de_emphasis",
1091 &tx_de_emphasis);
1092 device_property_read_string(dev, "snps,hsphy_interface",
1093 &dwc->hsphy_interface);
1094 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1095 &dwc->fladj);
1096
1097 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1098 "snps,dis_metastability_quirk");
1099
1100 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1101 dwc->tx_de_emphasis = tx_de_emphasis;
1102
1103 dwc->hird_threshold = hird_threshold
1104 | (dwc->is_utmi_l1_suspend << 4);
1105
1106 dwc->imod_interval = 0;
1107 }
1108
1109 /* check whether the core supports IMOD */
1110 bool dwc3_has_imod(struct dwc3 *dwc)
1111 {
1112 return ((dwc3_is_usb3(dwc) &&
1113 dwc->revision >= DWC3_REVISION_300A) ||
1114 (dwc3_is_usb31(dwc) &&
1115 dwc->revision >= DWC3_USB31_REVISION_120A));
1116 }
1117
1118 static void dwc3_check_params(struct dwc3 *dwc)
1119 {
1120 struct device *dev = dwc->dev;
1121
1122 /* Check for proper value of imod_interval */
1123 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1124 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1125 dwc->imod_interval = 0;
1126 }
1127
1128 /*
1129 * Workaround for STAR 9000961433 which affects only version
1130 * 3.00a of the DWC_usb3 core. This prevents the controller
1131 * interrupt from being masked while handling events. IMOD
1132 * allows us to work around this issue. Enable it for the
1133 * affected version.
1134 */
1135 if (!dwc->imod_interval &&
1136 (dwc->revision == DWC3_REVISION_300A))
1137 dwc->imod_interval = 1;
1138
1139 /* Check the maximum_speed parameter */
1140 switch (dwc->maximum_speed) {
1141 case USB_SPEED_LOW:
1142 case USB_SPEED_FULL:
1143 case USB_SPEED_HIGH:
1144 case USB_SPEED_SUPER:
1145 case USB_SPEED_SUPER_PLUS:
1146 break;
1147 default:
1148 dev_err(dev, "invalid maximum_speed parameter %d\n",
1149 dwc->maximum_speed);
1150 /* fall through */
1151 case USB_SPEED_UNKNOWN:
1152 /* default to superspeed */
1153 dwc->maximum_speed = USB_SPEED_SUPER;
1154
1155 /*
1156 * default to superspeed plus if we are capable.
1157 */
1158 if (dwc3_is_usb31(dwc) &&
1159 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1160 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1161 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1162
1163 break;
1164 }
1165 }
1166
1167 static int dwc3_probe(struct platform_device *pdev)
1168 {
1169 struct device *dev = &pdev->dev;
1170 struct resource *res;
1171 struct dwc3 *dwc;
1172
1173 int ret;
1174
1175 void __iomem *regs;
1176
1177 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1178 if (!dwc)
1179 return -ENOMEM;
1180
1181 dwc->dev = dev;
1182
1183 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1184 if (!res) {
1185 dev_err(dev, "missing memory resource\n");
1186 return -ENODEV;
1187 }
1188
1189 dwc->xhci_resources[0].start = res->start;
1190 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1191 DWC3_XHCI_REGS_END;
1192 dwc->xhci_resources[0].flags = res->flags;
1193 dwc->xhci_resources[0].name = res->name;
1194
1195 res->start += DWC3_GLOBALS_REGS_START;
1196
1197 /*
1198 * Request memory region but exclude xHCI regs,
1199 * since it will be requested by the xhci-plat driver.
1200 */
1201 regs = devm_ioremap_resource(dev, res);
1202 if (IS_ERR(regs)) {
1203 ret = PTR_ERR(regs);
1204 goto err0;
1205 }
1206
1207 dwc->regs = regs;
1208 dwc->regs_size = resource_size(res);
1209
1210 dwc3_get_properties(dwc);
1211
1212 platform_set_drvdata(pdev, dwc);
1213 dwc3_cache_hwparams(dwc);
1214
1215 spin_lock_init(&dwc->lock);
1216
1217 pm_runtime_set_active(dev);
1218 pm_runtime_use_autosuspend(dev);
1219 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1220 pm_runtime_enable(dev);
1221 ret = pm_runtime_get_sync(dev);
1222 if (ret < 0)
1223 goto err1;
1224
1225 pm_runtime_forbid(dev);
1226
1227 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1228 if (ret) {
1229 dev_err(dwc->dev, "failed to allocate event buffers\n");
1230 ret = -ENOMEM;
1231 goto err2;
1232 }
1233
1234 ret = dwc3_get_dr_mode(dwc);
1235 if (ret)
1236 goto err3;
1237
1238 ret = dwc3_alloc_scratch_buffers(dwc);
1239 if (ret)
1240 goto err3;
1241
1242 ret = dwc3_core_init(dwc);
1243 if (ret) {
1244 dev_err(dev, "failed to initialize core\n");
1245 goto err4;
1246 }
1247
1248 dwc3_check_params(dwc);
1249
1250 ret = dwc3_core_init_mode(dwc);
1251 if (ret)
1252 goto err5;
1253
1254 dwc3_debugfs_init(dwc);
1255 pm_runtime_put(dev);
1256
1257 return 0;
1258
1259 err5:
1260 dwc3_event_buffers_cleanup(dwc);
1261
1262 err4:
1263 dwc3_free_scratch_buffers(dwc);
1264
1265 err3:
1266 dwc3_free_event_buffers(dwc);
1267
1268 err2:
1269 pm_runtime_allow(&pdev->dev);
1270
1271 err1:
1272 pm_runtime_put_sync(&pdev->dev);
1273 pm_runtime_disable(&pdev->dev);
1274
1275 err0:
1276 /*
1277 * restore res->start back to its original value so that, in case the
1278 * probe is deferred, we don't end up getting error in request the
1279 * memory region the next time probe is called.
1280 */
1281 res->start -= DWC3_GLOBALS_REGS_START;
1282
1283 return ret;
1284 }
1285
1286 static int dwc3_remove(struct platform_device *pdev)
1287 {
1288 struct dwc3 *dwc = platform_get_drvdata(pdev);
1289 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1290
1291 pm_runtime_get_sync(&pdev->dev);
1292 /*
1293 * restore res->start back to its original value so that, in case the
1294 * probe is deferred, we don't end up getting error in request the
1295 * memory region the next time probe is called.
1296 */
1297 res->start -= DWC3_GLOBALS_REGS_START;
1298
1299 dwc3_debugfs_exit(dwc);
1300 dwc3_core_exit_mode(dwc);
1301
1302 dwc3_core_exit(dwc);
1303 dwc3_ulpi_exit(dwc);
1304
1305 pm_runtime_put_sync(&pdev->dev);
1306 pm_runtime_allow(&pdev->dev);
1307 pm_runtime_disable(&pdev->dev);
1308
1309 dwc3_free_event_buffers(dwc);
1310 dwc3_free_scratch_buffers(dwc);
1311
1312 return 0;
1313 }
1314
1315 #ifdef CONFIG_PM
1316 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1317 {
1318 unsigned long flags;
1319
1320 switch (dwc->current_dr_role) {
1321 case DWC3_GCTL_PRTCAP_DEVICE:
1322 spin_lock_irqsave(&dwc->lock, flags);
1323 dwc3_gadget_suspend(dwc);
1324 spin_unlock_irqrestore(&dwc->lock, flags);
1325 dwc3_core_exit(dwc);
1326 break;
1327 case DWC3_GCTL_PRTCAP_HOST:
1328 /* do nothing during host runtime_suspend */
1329 if (!PMSG_IS_AUTO(msg))
1330 dwc3_core_exit(dwc);
1331 break;
1332 default:
1333 /* do nothing */
1334 break;
1335 }
1336
1337 return 0;
1338 }
1339
1340 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1341 {
1342 unsigned long flags;
1343 int ret;
1344
1345 switch (dwc->current_dr_role) {
1346 case DWC3_GCTL_PRTCAP_DEVICE:
1347 ret = dwc3_core_init(dwc);
1348 if (ret)
1349 return ret;
1350
1351 spin_lock_irqsave(&dwc->lock, flags);
1352 dwc3_gadget_resume(dwc);
1353 spin_unlock_irqrestore(&dwc->lock, flags);
1354 break;
1355 case DWC3_GCTL_PRTCAP_HOST:
1356 /* nothing to do on host runtime_resume */
1357 if (!PMSG_IS_AUTO(msg)) {
1358 ret = dwc3_core_init(dwc);
1359 if (ret)
1360 return ret;
1361 }
1362 break;
1363 default:
1364 /* do nothing */
1365 break;
1366 }
1367
1368 return 0;
1369 }
1370
1371 static int dwc3_runtime_checks(struct dwc3 *dwc)
1372 {
1373 switch (dwc->current_dr_role) {
1374 case DWC3_GCTL_PRTCAP_DEVICE:
1375 if (dwc->connected)
1376 return -EBUSY;
1377 break;
1378 case DWC3_GCTL_PRTCAP_HOST:
1379 default:
1380 /* do nothing */
1381 break;
1382 }
1383
1384 return 0;
1385 }
1386
1387 static int dwc3_runtime_suspend(struct device *dev)
1388 {
1389 struct dwc3 *dwc = dev_get_drvdata(dev);
1390 int ret;
1391
1392 if (dwc3_runtime_checks(dwc))
1393 return -EBUSY;
1394
1395 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1396 if (ret)
1397 return ret;
1398
1399 device_init_wakeup(dev, true);
1400
1401 return 0;
1402 }
1403
1404 static int dwc3_runtime_resume(struct device *dev)
1405 {
1406 struct dwc3 *dwc = dev_get_drvdata(dev);
1407 int ret;
1408
1409 device_init_wakeup(dev, false);
1410
1411 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1412 if (ret)
1413 return ret;
1414
1415 switch (dwc->current_dr_role) {
1416 case DWC3_GCTL_PRTCAP_DEVICE:
1417 dwc3_gadget_process_pending_events(dwc);
1418 break;
1419 case DWC3_GCTL_PRTCAP_HOST:
1420 default:
1421 /* do nothing */
1422 break;
1423 }
1424
1425 pm_runtime_mark_last_busy(dev);
1426
1427 return 0;
1428 }
1429
1430 static int dwc3_runtime_idle(struct device *dev)
1431 {
1432 struct dwc3 *dwc = dev_get_drvdata(dev);
1433
1434 switch (dwc->current_dr_role) {
1435 case DWC3_GCTL_PRTCAP_DEVICE:
1436 if (dwc3_runtime_checks(dwc))
1437 return -EBUSY;
1438 break;
1439 case DWC3_GCTL_PRTCAP_HOST:
1440 default:
1441 /* do nothing */
1442 break;
1443 }
1444
1445 pm_runtime_mark_last_busy(dev);
1446 pm_runtime_autosuspend(dev);
1447
1448 return 0;
1449 }
1450 #endif /* CONFIG_PM */
1451
1452 #ifdef CONFIG_PM_SLEEP
1453 static int dwc3_suspend(struct device *dev)
1454 {
1455 struct dwc3 *dwc = dev_get_drvdata(dev);
1456 int ret;
1457
1458 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1459 if (ret)
1460 return ret;
1461
1462 pinctrl_pm_select_sleep_state(dev);
1463
1464 return 0;
1465 }
1466
1467 static int dwc3_resume(struct device *dev)
1468 {
1469 struct dwc3 *dwc = dev_get_drvdata(dev);
1470 int ret;
1471
1472 pinctrl_pm_select_default_state(dev);
1473
1474 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1475 if (ret)
1476 return ret;
1477
1478 pm_runtime_disable(dev);
1479 pm_runtime_set_active(dev);
1480 pm_runtime_enable(dev);
1481
1482 return 0;
1483 }
1484 #endif /* CONFIG_PM_SLEEP */
1485
1486 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1487 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1488 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1489 dwc3_runtime_idle)
1490 };
1491
1492 #ifdef CONFIG_OF
1493 static const struct of_device_id of_dwc3_match[] = {
1494 {
1495 .compatible = "snps,dwc3"
1496 },
1497 {
1498 .compatible = "synopsys,dwc3"
1499 },
1500 { },
1501 };
1502 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1503 #endif
1504
1505 #ifdef CONFIG_ACPI
1506
1507 #define ACPI_ID_INTEL_BSW "808622B7"
1508
1509 static const struct acpi_device_id dwc3_acpi_match[] = {
1510 { ACPI_ID_INTEL_BSW, 0 },
1511 { },
1512 };
1513 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1514 #endif
1515
1516 static struct platform_driver dwc3_driver = {
1517 .probe = dwc3_probe,
1518 .remove = dwc3_remove,
1519 .driver = {
1520 .name = "dwc3",
1521 .of_match_table = of_match_ptr(of_dwc3_match),
1522 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1523 .pm = &dwc3_dev_pm_ops,
1524 },
1525 };
1526
1527 module_platform_driver(dwc3_driver);
1528
1529 MODULE_ALIAS("platform:dwc3");
1530 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1531 MODULE_LICENSE("GPL v2");
1532 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux with added FPC-III support