drivers/usb/host/xhci-ext-caps.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10 /* Up to 16 ms to halt an HC */
  11 #define XHCI_MAX_HALT_USEC      (16*1000)
  12 /* HC not running - set to 1 when run/stop bit is cleared. */
  13 #define XHCI_STS_HALT           (1<<0)
  14
  15 /* HCCPARAMS offset from PCI base address */
  16 #define XHCI_HCC_PARAMS_OFFSET  0x10
  17 /* HCCPARAMS contains the first extended capability pointer */
  18 #define XHCI_HCC_EXT_CAPS(p)    (((p)>>16)&0xffff)
  19
  20 /* Command and Status registers offset from the Operational Registers address */
  21 #define XHCI_CMD_OFFSET         0x00
  22 #define XHCI_STS_OFFSET         0x04
  23
  24 #define XHCI_MAX_EXT_CAPS               50
  25
  26 /* Capability Register */
  27 /* bits 7:0 - how long is the Capabilities register */
  28 #define XHCI_HC_LENGTH(p)       (((p)>>00)&0x00ff)
  29
  30 /* Extended capability register fields */
  31 #define XHCI_EXT_CAPS_ID(p)     (((p)>>0)&0xff)
  32 #define XHCI_EXT_CAPS_NEXT(p)   (((p)>>8)&0xff)
  33 #define XHCI_EXT_CAPS_VAL(p)    ((p)>>16)
  34 /* Extended capability IDs - ID 0 reserved */
  35 #define XHCI_EXT_CAPS_LEGACY    1
  36 #define XHCI_EXT_CAPS_PROTOCOL  2
  37 #define XHCI_EXT_CAPS_PM        3
  38 #define XHCI_EXT_CAPS_VIRT      4
  39 #define XHCI_EXT_CAPS_ROUTE     5
  40 /* IDs 6-9 reserved */
  41 #define XHCI_EXT_CAPS_DEBUG     10
  42 /* USB Legacy Support Capability - section 7.1.1 */
  43 #define XHCI_HC_BIOS_OWNED      (1 << 16)
  44 #define XHCI_HC_OS_OWNED        (1 << 24)
  45
  46 /* USB Legacy Support Capability - section 7.1.1 */
  47 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
  48 #define XHCI_LEGACY_SUPPORT_OFFSET      (0x00)
  49
  50 /* USB Legacy Support Control and Status Register  - section 7.1.2 */
  51 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
  52 #define XHCI_LEGACY_CONTROL_OFFSET      (0x04)
  53 /* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
  54 #define XHCI_LEGACY_DISABLE_SMI         ((0x7 << 1) + (0xff << 5) + (0x7 << 17))
  55 #define XHCI_LEGACY_SMI_EVENTS          (0x7 << 29)
  56
  57 /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
  58 #define XHCI_L1C               (1 << 16)
  59
  60 /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
  61 #define XHCI_HLC               (1 << 19)
  62 #define XHCI_BLC               (1 << 20)
  63
  64 /* command register values to disable interrupts and halt the HC */
  65 /* start/stop HC execution - do not write unless HC is halted*/
  66 #define XHCI_CMD_RUN            (1 << 0)
  67 /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
  68 #define XHCI_CMD_EIE            (1 << 2)
  69 /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
  70 #define XHCI_CMD_HSEIE          (1 << 3)
  71 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
  72 #define XHCI_CMD_EWE            (1 << 10)
  73
  74 #define XHCI_IRQS               (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
  75
  76 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
  77 #define XHCI_STS_CNR            (1 << 11)
  78
  79 #include <linux/io.h>
  80
  81 /**
  82  * Find the offset of the extended capabilities with capability ID id.
  83  *
  84  * @base        PCI MMIO registers base address.
  85  * @start       address at which to start looking, (0 or HCC_PARAMS to start at
  86  *              beginning of list)
  87  * @id          Extended capability ID to search for.
  88  *
  89  * Returns the offset of the next matching extended capability structure.
  90  * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
  91  * and this provides a way to find them all.
  92  */
  93
  94 static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
  95 {
  96         u32 val;
  97         u32 next;
  98         u32 offset;
  99
 100         offset = start;
 101         if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
 102                 val = readl(base + XHCI_HCC_PARAMS_OFFSET);
 103                 if (val == ~0)
 104                         return 0;
 105                 offset = XHCI_HCC_EXT_CAPS(val) << 2;
 106                 if (!offset)
 107                         return 0;
 108         }
 109         do {
 110                 val = readl(base + offset);
 111                 if (val == ~0)
 112                         return 0;
 113                 if (XHCI_EXT_CAPS_ID(val) == id && offset != start)
 114                         return offset;
 115
 116                 next = XHCI_EXT_CAPS_NEXT(val);
 117                 offset += next << 2;
 118         } while (next);
 119
 120         return 0;
 121 }