1 /* linux/drivers/video/s3c2410fb.c
2 * Copyright (c) 2004,2005 Arnaud Patard
3 * Copyright (c) 2004-2008 Ben Dooks
5 * S3C2410 LCD Framebuffer Driver
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
11 * Driver based on skeletonfb.c, sa1100fb.c and others.
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <linux/string.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/interrupt.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/cpufreq.h>
33 #include <asm/div64.h>
35 #include <asm/mach/map.h>
36 #include <mach/regs-lcd.h>
37 #include <mach/regs-gpio.h>
44 #include "s3c2410fb.h"
47 #ifdef CONFIG_FB_S3C2410_DEBUG
53 #define dprintk(msg...) \
59 /* useful functions */
61 static int is_s3c2412(struct s3c2410fb_info
*fbi
)
63 return (fbi
->drv_type
== DRV_S3C2412
);
66 /* s3c2410fb_set_lcdaddr
68 * initialise lcd controller address pointers
70 static void s3c2410fb_set_lcdaddr(struct fb_info
*info
)
72 unsigned long saddr1
, saddr2
, saddr3
;
73 struct s3c2410fb_info
*fbi
= info
->par
;
74 void __iomem
*regs
= fbi
->io
;
76 saddr1
= info
->fix
.smem_start
>> 1;
77 saddr2
= info
->fix
.smem_start
;
78 saddr2
+= info
->fix
.line_length
* info
->var
.yres
;
81 saddr3
= S3C2410_OFFSIZE(0) |
82 S3C2410_PAGEWIDTH((info
->fix
.line_length
/ 2) & 0x3ff);
84 dprintk("LCDSADDR1 = 0x%08lx\n", saddr1
);
85 dprintk("LCDSADDR2 = 0x%08lx\n", saddr2
);
86 dprintk("LCDSADDR3 = 0x%08lx\n", saddr3
);
88 writel(saddr1
, regs
+ S3C2410_LCDSADDR1
);
89 writel(saddr2
, regs
+ S3C2410_LCDSADDR2
);
90 writel(saddr3
, regs
+ S3C2410_LCDSADDR3
);
93 /* s3c2410fb_calc_pixclk()
95 * calculate divisor for clk->pixclk
97 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info
*fbi
,
100 unsigned long clk
= fbi
->clk_rate
;
101 unsigned long long div
;
103 /* pixclk is in picoseconds, our clock is in Hz
105 * Hz -> picoseconds is / 10^-12
108 div
= (unsigned long long)clk
* pixclk
;
109 div
>>= 12; /* div / 2^12 */
110 do_div(div
, 625 * 625UL * 625); /* div / 5^12 */
112 dprintk("pixclk %ld, divisor is %ld\n", pixclk
, (long)div
);
117 * s3c2410fb_check_var():
118 * Get the video params out of 'var'. If a value doesn't fit, round it up,
119 * if it's too big, return -EINVAL.
122 static int s3c2410fb_check_var(struct fb_var_screeninfo
*var
,
123 struct fb_info
*info
)
125 struct s3c2410fb_info
*fbi
= info
->par
;
126 struct s3c2410fb_mach_info
*mach_info
= dev_get_platdata(fbi
->dev
);
127 struct s3c2410fb_display
*display
= NULL
;
128 struct s3c2410fb_display
*default_display
= mach_info
->displays
+
129 mach_info
->default_display
;
130 int type
= default_display
->type
;
133 dprintk("check_var(var=%p, info=%p)\n", var
, info
);
135 /* validate x/y resolution */
136 /* choose default mode if possible */
137 if (var
->yres
== default_display
->yres
&&
138 var
->xres
== default_display
->xres
&&
139 var
->bits_per_pixel
== default_display
->bpp
)
140 display
= default_display
;
142 for (i
= 0; i
< mach_info
->num_displays
; i
++)
143 if (type
== mach_info
->displays
[i
].type
&&
144 var
->yres
== mach_info
->displays
[i
].yres
&&
145 var
->xres
== mach_info
->displays
[i
].xres
&&
146 var
->bits_per_pixel
== mach_info
->displays
[i
].bpp
) {
147 display
= mach_info
->displays
+ i
;
152 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
153 var
->xres
, var
->yres
, var
->bits_per_pixel
);
157 /* it is always the size as the display */
158 var
->xres_virtual
= display
->xres
;
159 var
->yres_virtual
= display
->yres
;
160 var
->height
= display
->height
;
161 var
->width
= display
->width
;
163 /* copy lcd settings */
164 var
->pixclock
= display
->pixclock
;
165 var
->left_margin
= display
->left_margin
;
166 var
->right_margin
= display
->right_margin
;
167 var
->upper_margin
= display
->upper_margin
;
168 var
->lower_margin
= display
->lower_margin
;
169 var
->vsync_len
= display
->vsync_len
;
170 var
->hsync_len
= display
->hsync_len
;
172 fbi
->regs
.lcdcon5
= display
->lcdcon5
;
173 /* set display type */
174 fbi
->regs
.lcdcon1
= display
->type
;
176 var
->transp
.offset
= 0;
177 var
->transp
.length
= 0;
178 /* set r/g/b positions */
179 switch (var
->bits_per_pixel
) {
184 var
->red
.length
= var
->bits_per_pixel
;
185 var
->green
= var
->red
;
186 var
->blue
= var
->red
;
189 if (display
->type
!= S3C2410_LCDCON1_TFT
) {
193 var
->green
.length
= 3;
194 var
->green
.offset
= 2;
195 var
->blue
.length
= 2;
196 var
->blue
.offset
= 0;
200 var
->green
= var
->red
;
201 var
->blue
= var
->red
;
208 var
->green
.length
= 4;
209 var
->green
.offset
= 4;
210 var
->blue
.length
= 4;
211 var
->blue
.offset
= 0;
216 if (display
->lcdcon5
& S3C2410_LCDCON5_FRM565
) {
217 /* 16 bpp, 565 format */
218 var
->red
.offset
= 11;
219 var
->green
.offset
= 5;
220 var
->blue
.offset
= 0;
222 var
->green
.length
= 6;
223 var
->blue
.length
= 5;
225 /* 16 bpp, 5551 format */
226 var
->red
.offset
= 11;
227 var
->green
.offset
= 6;
228 var
->blue
.offset
= 1;
230 var
->green
.length
= 5;
231 var
->blue
.length
= 5;
235 /* 24 bpp 888 and 8 dummy */
237 var
->red
.offset
= 16;
238 var
->green
.length
= 8;
239 var
->green
.offset
= 8;
240 var
->blue
.length
= 8;
241 var
->blue
.offset
= 0;
247 /* s3c2410fb_calculate_stn_lcd_regs
249 * calculate register values from var settings
251 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info
*info
,
252 struct s3c2410fb_hw
*regs
)
254 const struct s3c2410fb_info
*fbi
= info
->par
;
255 const struct fb_var_screeninfo
*var
= &info
->var
;
256 int type
= regs
->lcdcon1
& ~S3C2410_LCDCON1_TFT
;
257 int hs
= var
->xres
>> 2;
258 unsigned wdly
= (var
->left_margin
>> 4) - 1;
259 unsigned wlh
= (var
->hsync_len
>> 4) - 1;
261 if (type
!= S3C2410_LCDCON1_STN4
)
264 switch (var
->bits_per_pixel
) {
266 regs
->lcdcon1
|= S3C2410_LCDCON1_STN1BPP
;
269 regs
->lcdcon1
|= S3C2410_LCDCON1_STN2GREY
;
272 regs
->lcdcon1
|= S3C2410_LCDCON1_STN4GREY
;
275 regs
->lcdcon1
|= S3C2410_LCDCON1_STN8BPP
;
279 regs
->lcdcon1
|= S3C2410_LCDCON1_STN12BPP
;
284 /* invalid pixel depth */
285 dev_err(fbi
->dev
, "invalid bpp %d\n",
286 var
->bits_per_pixel
);
288 /* update X/Y info */
289 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
290 var
->left_margin
, var
->right_margin
, var
->hsync_len
);
292 regs
->lcdcon2
= S3C2410_LCDCON2_LINEVAL(var
->yres
- 1);
300 regs
->lcdcon3
= S3C2410_LCDCON3_WDLY(wdly
) |
301 S3C2410_LCDCON3_LINEBLANK(var
->right_margin
/ 8) |
302 S3C2410_LCDCON3_HOZVAL(hs
- 1);
304 regs
->lcdcon4
= S3C2410_LCDCON4_WLH(wlh
);
307 /* s3c2410fb_calculate_tft_lcd_regs
309 * calculate register values from var settings
311 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info
*info
,
312 struct s3c2410fb_hw
*regs
)
314 const struct s3c2410fb_info
*fbi
= info
->par
;
315 const struct fb_var_screeninfo
*var
= &info
->var
;
317 switch (var
->bits_per_pixel
) {
319 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT1BPP
;
322 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT2BPP
;
325 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT4BPP
;
328 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT8BPP
;
329 regs
->lcdcon5
|= S3C2410_LCDCON5_BSWP
|
330 S3C2410_LCDCON5_FRM565
;
331 regs
->lcdcon5
&= ~S3C2410_LCDCON5_HWSWP
;
334 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT16BPP
;
335 regs
->lcdcon5
&= ~S3C2410_LCDCON5_BSWP
;
336 regs
->lcdcon5
|= S3C2410_LCDCON5_HWSWP
;
339 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT24BPP
;
340 regs
->lcdcon5
&= ~(S3C2410_LCDCON5_BSWP
|
341 S3C2410_LCDCON5_HWSWP
|
342 S3C2410_LCDCON5_BPP24BL
);
345 /* invalid pixel depth */
346 dev_err(fbi
->dev
, "invalid bpp %d\n",
347 var
->bits_per_pixel
);
349 /* update X/Y info */
350 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
351 var
->upper_margin
, var
->lower_margin
, var
->vsync_len
);
353 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
354 var
->left_margin
, var
->right_margin
, var
->hsync_len
);
356 regs
->lcdcon2
= S3C2410_LCDCON2_LINEVAL(var
->yres
- 1) |
357 S3C2410_LCDCON2_VBPD(var
->upper_margin
- 1) |
358 S3C2410_LCDCON2_VFPD(var
->lower_margin
- 1) |
359 S3C2410_LCDCON2_VSPW(var
->vsync_len
- 1);
361 regs
->lcdcon3
= S3C2410_LCDCON3_HBPD(var
->right_margin
- 1) |
362 S3C2410_LCDCON3_HFPD(var
->left_margin
- 1) |
363 S3C2410_LCDCON3_HOZVAL(var
->xres
- 1);
365 regs
->lcdcon4
= S3C2410_LCDCON4_HSPW(var
->hsync_len
- 1);
368 /* s3c2410fb_activate_var
370 * activate (set) the controller from the given framebuffer
373 static void s3c2410fb_activate_var(struct fb_info
*info
)
375 struct s3c2410fb_info
*fbi
= info
->par
;
376 void __iomem
*regs
= fbi
->io
;
377 int type
= fbi
->regs
.lcdcon1
& S3C2410_LCDCON1_TFT
;
378 struct fb_var_screeninfo
*var
= &info
->var
;
381 clkdiv
= DIV_ROUND_UP(s3c2410fb_calc_pixclk(fbi
, var
->pixclock
), 2);
383 dprintk("%s: var->xres = %d\n", __func__
, var
->xres
);
384 dprintk("%s: var->yres = %d\n", __func__
, var
->yres
);
385 dprintk("%s: var->bpp = %d\n", __func__
, var
->bits_per_pixel
);
387 if (type
== S3C2410_LCDCON1_TFT
) {
388 s3c2410fb_calculate_tft_lcd_regs(info
, &fbi
->regs
);
393 s3c2410fb_calculate_stn_lcd_regs(info
, &fbi
->regs
);
398 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_CLKVAL(clkdiv
);
400 /* write new registers */
402 dprintk("new register set:\n");
403 dprintk("lcdcon[1] = 0x%08lx\n", fbi
->regs
.lcdcon1
);
404 dprintk("lcdcon[2] = 0x%08lx\n", fbi
->regs
.lcdcon2
);
405 dprintk("lcdcon[3] = 0x%08lx\n", fbi
->regs
.lcdcon3
);
406 dprintk("lcdcon[4] = 0x%08lx\n", fbi
->regs
.lcdcon4
);
407 dprintk("lcdcon[5] = 0x%08lx\n", fbi
->regs
.lcdcon5
);
409 writel(fbi
->regs
.lcdcon1
& ~S3C2410_LCDCON1_ENVID
,
410 regs
+ S3C2410_LCDCON1
);
411 writel(fbi
->regs
.lcdcon2
, regs
+ S3C2410_LCDCON2
);
412 writel(fbi
->regs
.lcdcon3
, regs
+ S3C2410_LCDCON3
);
413 writel(fbi
->regs
.lcdcon4
, regs
+ S3C2410_LCDCON4
);
414 writel(fbi
->regs
.lcdcon5
, regs
+ S3C2410_LCDCON5
);
416 /* set lcd address pointers */
417 s3c2410fb_set_lcdaddr(info
);
419 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_ENVID
,
420 writel(fbi
->regs
.lcdcon1
, regs
+ S3C2410_LCDCON1
);
424 * s3c2410fb_set_par - Alters the hardware state.
425 * @info: frame buffer structure that represents a single frame buffer
428 static int s3c2410fb_set_par(struct fb_info
*info
)
430 struct fb_var_screeninfo
*var
= &info
->var
;
432 switch (var
->bits_per_pixel
) {
436 info
->fix
.visual
= FB_VISUAL_TRUECOLOR
;
439 info
->fix
.visual
= FB_VISUAL_MONO01
;
442 info
->fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
446 info
->fix
.line_length
= (var
->xres_virtual
* var
->bits_per_pixel
) / 8;
448 /* activate this new configuration */
450 s3c2410fb_activate_var(info
);
454 static void schedule_palette_update(struct s3c2410fb_info
*fbi
,
455 unsigned int regno
, unsigned int val
)
459 void __iomem
*irq_base
= fbi
->irq_base
;
461 local_irq_save(flags
);
463 fbi
->palette_buffer
[regno
] = val
;
465 if (!fbi
->palette_ready
) {
466 fbi
->palette_ready
= 1;
469 irqen
= readl(irq_base
+ S3C24XX_LCDINTMSK
);
470 irqen
&= ~S3C2410_LCDINT_FRSYNC
;
471 writel(irqen
, irq_base
+ S3C24XX_LCDINTMSK
);
474 local_irq_restore(flags
);
478 static inline unsigned int chan_to_field(unsigned int chan
,
479 struct fb_bitfield
*bf
)
482 chan
>>= 16 - bf
->length
;
483 return chan
<< bf
->offset
;
486 static int s3c2410fb_setcolreg(unsigned regno
,
487 unsigned red
, unsigned green
, unsigned blue
,
488 unsigned transp
, struct fb_info
*info
)
490 struct s3c2410fb_info
*fbi
= info
->par
;
491 void __iomem
*regs
= fbi
->io
;
494 /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
495 regno, red, green, blue); */
497 switch (info
->fix
.visual
) {
498 case FB_VISUAL_TRUECOLOR
:
499 /* true-colour, use pseudo-palette */
502 u32
*pal
= info
->pseudo_palette
;
504 val
= chan_to_field(red
, &info
->var
.red
);
505 val
|= chan_to_field(green
, &info
->var
.green
);
506 val
|= chan_to_field(blue
, &info
->var
.blue
);
512 case FB_VISUAL_PSEUDOCOLOR
:
514 /* currently assume RGB 5-6-5 mode */
516 val
= (red
>> 0) & 0xf800;
517 val
|= (green
>> 5) & 0x07e0;
518 val
|= (blue
>> 11) & 0x001f;
520 writel(val
, regs
+ S3C2410_TFTPAL(regno
));
521 schedule_palette_update(fbi
, regno
, val
);
527 return 1; /* unknown type */
533 /* s3c2410fb_lcd_enable
535 * shutdown the lcd controller
537 static void s3c2410fb_lcd_enable(struct s3c2410fb_info
*fbi
, int enable
)
541 local_irq_save(flags
);
544 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_ENVID
;
546 fbi
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_ENVID
;
548 writel(fbi
->regs
.lcdcon1
, fbi
->io
+ S3C2410_LCDCON1
);
550 local_irq_restore(flags
);
556 * @blank_mode: the blank mode we want.
557 * @info: frame buffer structure that represents a single frame buffer
559 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
560 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
561 * video mode which doesn't support it. Implements VESA suspend
562 * and powerdown modes on hardware that supports disabling hsync/vsync:
564 * Returns negative errno on error, or zero on success.
567 static int s3c2410fb_blank(int blank_mode
, struct fb_info
*info
)
569 struct s3c2410fb_info
*fbi
= info
->par
;
570 void __iomem
*tpal_reg
= fbi
->io
;
572 dprintk("blank(mode=%d, info=%p)\n", blank_mode
, info
);
574 tpal_reg
+= is_s3c2412(fbi
) ? S3C2412_TPAL
: S3C2410_TPAL
;
576 if (blank_mode
== FB_BLANK_POWERDOWN
)
577 s3c2410fb_lcd_enable(fbi
, 0);
579 s3c2410fb_lcd_enable(fbi
, 1);
581 if (blank_mode
== FB_BLANK_UNBLANK
)
582 writel(0x0, tpal_reg
);
584 dprintk("setting TPAL to output 0x000000\n");
585 writel(S3C2410_TPAL_EN
, tpal_reg
);
591 static int s3c2410fb_debug_show(struct device
*dev
,
592 struct device_attribute
*attr
, char *buf
)
594 return snprintf(buf
, PAGE_SIZE
, "%s\n", debug
? "on" : "off");
597 static int s3c2410fb_debug_store(struct device
*dev
,
598 struct device_attribute
*attr
,
599 const char *buf
, size_t len
)
604 if (strncasecmp(buf
, "on", 2) == 0 ||
605 strncasecmp(buf
, "1", 1) == 0) {
607 dev_dbg(dev
, "s3c2410fb: Debug On");
608 } else if (strncasecmp(buf
, "off", 3) == 0 ||
609 strncasecmp(buf
, "0", 1) == 0) {
611 dev_dbg(dev
, "s3c2410fb: Debug Off");
619 static DEVICE_ATTR(debug
, 0664, s3c2410fb_debug_show
, s3c2410fb_debug_store
);
621 static struct fb_ops s3c2410fb_ops
= {
622 .owner
= THIS_MODULE
,
623 .fb_check_var
= s3c2410fb_check_var
,
624 .fb_set_par
= s3c2410fb_set_par
,
625 .fb_blank
= s3c2410fb_blank
,
626 .fb_setcolreg
= s3c2410fb_setcolreg
,
627 .fb_fillrect
= cfb_fillrect
,
628 .fb_copyarea
= cfb_copyarea
,
629 .fb_imageblit
= cfb_imageblit
,
633 * s3c2410fb_map_video_memory():
634 * Allocates the DRAM memory for the frame buffer. This buffer is
635 * remapped into a non-cached, non-buffered, memory region to
636 * allow palette and pixel writes to occur without flushing the
637 * cache. Once this area is remapped, all virtual memory
638 * access to the video memory should occur at the new region.
640 static int s3c2410fb_map_video_memory(struct fb_info
*info
)
642 struct s3c2410fb_info
*fbi
= info
->par
;
644 unsigned map_size
= PAGE_ALIGN(info
->fix
.smem_len
);
646 dprintk("map_video_memory(fbi=%p) map_size %u\n", fbi
, map_size
);
648 info
->screen_base
= dma_alloc_wc(fbi
->dev
, map_size
, &map_dma
,
651 if (info
->screen_base
) {
652 /* prevent initial garbage on screen */
653 dprintk("map_video_memory: clear %p:%08x\n",
654 info
->screen_base
, map_size
);
655 memset(info
->screen_base
, 0x00, map_size
);
657 info
->fix
.smem_start
= map_dma
;
659 dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
660 info
->fix
.smem_start
, info
->screen_base
, map_size
);
663 return info
->screen_base
? 0 : -ENOMEM
;
666 static inline void s3c2410fb_unmap_video_memory(struct fb_info
*info
)
668 struct s3c2410fb_info
*fbi
= info
->par
;
670 dma_free_wc(fbi
->dev
, PAGE_ALIGN(info
->fix
.smem_len
),
671 info
->screen_base
, info
->fix
.smem_start
);
674 static inline void modify_gpio(void __iomem
*reg
,
675 unsigned long set
, unsigned long mask
)
679 tmp
= readl(reg
) & ~mask
;
680 writel(tmp
| set
, reg
);
684 * s3c2410fb_init_registers - Initialise all LCD-related registers
686 static int s3c2410fb_init_registers(struct fb_info
*info
)
688 struct s3c2410fb_info
*fbi
= info
->par
;
689 struct s3c2410fb_mach_info
*mach_info
= dev_get_platdata(fbi
->dev
);
691 void __iomem
*regs
= fbi
->io
;
693 void __iomem
*lpcsel
;
695 if (is_s3c2412(fbi
)) {
696 tpal
= regs
+ S3C2412_TPAL
;
697 lpcsel
= regs
+ S3C2412_TCONSEL
;
699 tpal
= regs
+ S3C2410_TPAL
;
700 lpcsel
= regs
+ S3C2410_LPCSEL
;
703 /* Initialise LCD with values from haret */
705 local_irq_save(flags
);
707 /* modify the gpio(s) with interrupts set (bjd) */
709 modify_gpio(S3C2410_GPCUP
, mach_info
->gpcup
, mach_info
->gpcup_mask
);
710 modify_gpio(S3C2410_GPCCON
, mach_info
->gpccon
, mach_info
->gpccon_mask
);
711 modify_gpio(S3C2410_GPDUP
, mach_info
->gpdup
, mach_info
->gpdup_mask
);
712 modify_gpio(S3C2410_GPDCON
, mach_info
->gpdcon
, mach_info
->gpdcon_mask
);
714 local_irq_restore(flags
);
716 dprintk("LPCSEL = 0x%08lx\n", mach_info
->lpcsel
);
717 writel(mach_info
->lpcsel
, lpcsel
);
719 dprintk("replacing TPAL %08x\n", readl(tpal
));
721 /* ensure temporary palette disabled */
727 static void s3c2410fb_write_palette(struct s3c2410fb_info
*fbi
)
730 void __iomem
*regs
= fbi
->io
;
732 fbi
->palette_ready
= 0;
734 for (i
= 0; i
< 256; i
++) {
735 unsigned long ent
= fbi
->palette_buffer
[i
];
736 if (ent
== PALETTE_BUFF_CLEAR
)
739 writel(ent
, regs
+ S3C2410_TFTPAL(i
));
741 /* it seems the only way to know exactly
742 * if the palette wrote ok, is to check
743 * to see if the value verifies ok
746 if (readw(regs
+ S3C2410_TFTPAL(i
)) == ent
)
747 fbi
->palette_buffer
[i
] = PALETTE_BUFF_CLEAR
;
749 fbi
->palette_ready
= 1; /* retry */
753 static irqreturn_t
s3c2410fb_irq(int irq
, void *dev_id
)
755 struct s3c2410fb_info
*fbi
= dev_id
;
756 void __iomem
*irq_base
= fbi
->irq_base
;
757 unsigned long lcdirq
= readl(irq_base
+ S3C24XX_LCDINTPND
);
759 if (lcdirq
& S3C2410_LCDINT_FRSYNC
) {
760 if (fbi
->palette_ready
)
761 s3c2410fb_write_palette(fbi
);
763 writel(S3C2410_LCDINT_FRSYNC
, irq_base
+ S3C24XX_LCDINTPND
);
764 writel(S3C2410_LCDINT_FRSYNC
, irq_base
+ S3C24XX_LCDSRCPND
);
770 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
772 static int s3c2410fb_cpufreq_transition(struct notifier_block
*nb
,
773 unsigned long val
, void *data
)
775 struct s3c2410fb_info
*info
;
776 struct fb_info
*fbinfo
;
779 info
= container_of(nb
, struct s3c2410fb_info
, freq_transition
);
780 fbinfo
= platform_get_drvdata(to_platform_device(info
->dev
));
782 /* work out change, <0 for speed-up */
783 delta_f
= info
->clk_rate
- clk_get_rate(info
->clk
);
785 if ((val
== CPUFREQ_POSTCHANGE
&& delta_f
> 0) ||
786 (val
== CPUFREQ_PRECHANGE
&& delta_f
< 0)) {
787 info
->clk_rate
= clk_get_rate(info
->clk
);
788 s3c2410fb_activate_var(fbinfo
);
794 static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info
*info
)
796 info
->freq_transition
.notifier_call
= s3c2410fb_cpufreq_transition
;
798 return cpufreq_register_notifier(&info
->freq_transition
,
799 CPUFREQ_TRANSITION_NOTIFIER
);
802 static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info
*info
)
804 cpufreq_unregister_notifier(&info
->freq_transition
,
805 CPUFREQ_TRANSITION_NOTIFIER
);
809 static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info
*info
)
814 static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info
*info
)
820 static const char driver_name
[] = "s3c2410fb";
822 static int s3c24xxfb_probe(struct platform_device
*pdev
,
823 enum s3c_drv_type drv_type
)
825 struct s3c2410fb_info
*info
;
826 struct s3c2410fb_display
*display
;
827 struct fb_info
*fbinfo
;
828 struct s3c2410fb_mach_info
*mach_info
;
829 struct resource
*res
;
836 mach_info
= dev_get_platdata(&pdev
->dev
);
837 if (mach_info
== NULL
) {
839 "no platform data for lcd, cannot attach\n");
843 if (mach_info
->default_display
>= mach_info
->num_displays
) {
844 dev_err(&pdev
->dev
, "default is %d but only %d displays\n",
845 mach_info
->default_display
, mach_info
->num_displays
);
849 display
= mach_info
->displays
+ mach_info
->default_display
;
851 irq
= platform_get_irq(pdev
, 0);
853 dev_err(&pdev
->dev
, "no irq for device\n");
857 fbinfo
= framebuffer_alloc(sizeof(struct s3c2410fb_info
), &pdev
->dev
);
861 platform_set_drvdata(pdev
, fbinfo
);
864 info
->dev
= &pdev
->dev
;
865 info
->drv_type
= drv_type
;
867 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
869 dev_err(&pdev
->dev
, "failed to get memory registers\n");
874 size
= resource_size(res
);
875 info
->mem
= request_mem_region(res
->start
, size
, pdev
->name
);
876 if (info
->mem
== NULL
) {
877 dev_err(&pdev
->dev
, "failed to get memory region\n");
882 info
->io
= ioremap(res
->start
, size
);
883 if (info
->io
== NULL
) {
884 dev_err(&pdev
->dev
, "ioremap() of registers failed\n");
889 if (drv_type
== DRV_S3C2412
)
890 info
->irq_base
= info
->io
+ S3C2412_LCDINTBASE
;
892 info
->irq_base
= info
->io
+ S3C2410_LCDINTBASE
;
894 dprintk("devinit\n");
896 strcpy(fbinfo
->fix
.id
, driver_name
);
899 lcdcon1
= readl(info
->io
+ S3C2410_LCDCON1
);
900 writel(lcdcon1
& ~S3C2410_LCDCON1_ENVID
, info
->io
+ S3C2410_LCDCON1
);
902 fbinfo
->fix
.type
= FB_TYPE_PACKED_PIXELS
;
903 fbinfo
->fix
.type_aux
= 0;
904 fbinfo
->fix
.xpanstep
= 0;
905 fbinfo
->fix
.ypanstep
= 0;
906 fbinfo
->fix
.ywrapstep
= 0;
907 fbinfo
->fix
.accel
= FB_ACCEL_NONE
;
909 fbinfo
->var
.nonstd
= 0;
910 fbinfo
->var
.activate
= FB_ACTIVATE_NOW
;
911 fbinfo
->var
.accel_flags
= 0;
912 fbinfo
->var
.vmode
= FB_VMODE_NONINTERLACED
;
914 fbinfo
->fbops
= &s3c2410fb_ops
;
915 fbinfo
->flags
= FBINFO_FLAG_DEFAULT
;
916 fbinfo
->pseudo_palette
= &info
->pseudo_pal
;
918 for (i
= 0; i
< 256; i
++)
919 info
->palette_buffer
[i
] = PALETTE_BUFF_CLEAR
;
921 ret
= request_irq(irq
, s3c2410fb_irq
, 0, pdev
->name
, info
);
923 dev_err(&pdev
->dev
, "cannot get irq %d - err %d\n", irq
, ret
);
928 info
->clk
= clk_get(NULL
, "lcd");
929 if (IS_ERR(info
->clk
)) {
930 dev_err(&pdev
->dev
, "failed to get lcd clock source\n");
931 ret
= PTR_ERR(info
->clk
);
935 clk_prepare_enable(info
->clk
);
936 dprintk("got and enabled clock\n");
938 usleep_range(1000, 1100);
940 info
->clk_rate
= clk_get_rate(info
->clk
);
942 /* find maximum required memory size for display */
943 for (i
= 0; i
< mach_info
->num_displays
; i
++) {
944 unsigned long smem_len
= mach_info
->displays
[i
].xres
;
946 smem_len
*= mach_info
->displays
[i
].yres
;
947 smem_len
*= mach_info
->displays
[i
].bpp
;
949 if (fbinfo
->fix
.smem_len
< smem_len
)
950 fbinfo
->fix
.smem_len
= smem_len
;
953 /* Initialize video memory */
954 ret
= s3c2410fb_map_video_memory(fbinfo
);
956 dev_err(&pdev
->dev
, "Failed to allocate video RAM: %d\n", ret
);
961 dprintk("got video memory\n");
963 fbinfo
->var
.xres
= display
->xres
;
964 fbinfo
->var
.yres
= display
->yres
;
965 fbinfo
->var
.bits_per_pixel
= display
->bpp
;
967 s3c2410fb_init_registers(fbinfo
);
969 s3c2410fb_check_var(&fbinfo
->var
, fbinfo
);
971 ret
= s3c2410fb_cpufreq_register(info
);
973 dev_err(&pdev
->dev
, "Failed to register cpufreq\n");
974 goto free_video_memory
;
977 ret
= register_framebuffer(fbinfo
);
979 dev_err(&pdev
->dev
, "Failed to register framebuffer device: %d\n",
984 /* create device files */
985 ret
= device_create_file(&pdev
->dev
, &dev_attr_debug
);
987 dev_err(&pdev
->dev
, "failed to add debug attribute\n");
989 dev_info(&pdev
->dev
, "fb%d: %s frame buffer device\n",
990 fbinfo
->node
, fbinfo
->fix
.id
);
995 s3c2410fb_cpufreq_deregister(info
);
997 s3c2410fb_unmap_video_memory(fbinfo
);
999 clk_disable_unprepare(info
->clk
);
1002 free_irq(irq
, info
);
1006 release_mem_region(res
->start
, size
);
1008 framebuffer_release(fbinfo
);
1012 static int s3c2410fb_probe(struct platform_device
*pdev
)
1014 return s3c24xxfb_probe(pdev
, DRV_S3C2410
);
1017 static int s3c2412fb_probe(struct platform_device
*pdev
)
1019 return s3c24xxfb_probe(pdev
, DRV_S3C2412
);
1026 static int s3c2410fb_remove(struct platform_device
*pdev
)
1028 struct fb_info
*fbinfo
= platform_get_drvdata(pdev
);
1029 struct s3c2410fb_info
*info
= fbinfo
->par
;
1032 unregister_framebuffer(fbinfo
);
1033 s3c2410fb_cpufreq_deregister(info
);
1035 s3c2410fb_lcd_enable(info
, 0);
1036 usleep_range(1000, 1100);
1038 s3c2410fb_unmap_video_memory(fbinfo
);
1041 clk_disable_unprepare(info
->clk
);
1046 irq
= platform_get_irq(pdev
, 0);
1047 free_irq(irq
, info
);
1051 release_mem_region(info
->mem
->start
, resource_size(info
->mem
));
1053 framebuffer_release(fbinfo
);
1060 /* suspend and resume support for the lcd controller */
1061 static int s3c2410fb_suspend(struct platform_device
*dev
, pm_message_t state
)
1063 struct fb_info
*fbinfo
= platform_get_drvdata(dev
);
1064 struct s3c2410fb_info
*info
= fbinfo
->par
;
1066 s3c2410fb_lcd_enable(info
, 0);
1068 /* sleep before disabling the clock, we need to ensure
1069 * the LCD DMA engine is not going to get back on the bus
1070 * before the clock goes off again (bjd) */
1072 usleep_range(1000, 1100);
1073 clk_disable_unprepare(info
->clk
);
1078 static int s3c2410fb_resume(struct platform_device
*dev
)
1080 struct fb_info
*fbinfo
= platform_get_drvdata(dev
);
1081 struct s3c2410fb_info
*info
= fbinfo
->par
;
1083 clk_prepare_enable(info
->clk
);
1084 usleep_range(1000, 1100);
1086 s3c2410fb_init_registers(fbinfo
);
1088 /* re-activate our display after resume */
1089 s3c2410fb_activate_var(fbinfo
);
1090 s3c2410fb_blank(FB_BLANK_UNBLANK
, fbinfo
);
1096 #define s3c2410fb_suspend NULL
1097 #define s3c2410fb_resume NULL
1100 static struct platform_driver s3c2410fb_driver
= {
1101 .probe
= s3c2410fb_probe
,
1102 .remove
= s3c2410fb_remove
,
1103 .suspend
= s3c2410fb_suspend
,
1104 .resume
= s3c2410fb_resume
,
1106 .name
= "s3c2410-lcd",
1110 static struct platform_driver s3c2412fb_driver
= {
1111 .probe
= s3c2412fb_probe
,
1112 .remove
= s3c2410fb_remove
,
1113 .suspend
= s3c2410fb_suspend
,
1114 .resume
= s3c2410fb_resume
,
1116 .name
= "s3c2412-lcd",
1120 int __init
s3c2410fb_init(void)
1122 int ret
= platform_driver_register(&s3c2410fb_driver
);
1125 ret
= platform_driver_register(&s3c2412fb_driver
);
1130 static void __exit
s3c2410fb_cleanup(void)
1132 platform_driver_unregister(&s3c2410fb_driver
);
1133 platform_driver_unregister(&s3c2412fb_driver
);
1136 module_init(s3c2410fb_init
);
1137 module_exit(s3c2410fb_cleanup
);
1139 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
1140 MODULE_AUTHOR("Ben Dooks <ben-linux@fluff.org>");
1141 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1142 MODULE_LICENSE("GPL");
1143 MODULE_ALIAS("platform:s3c2410-lcd");
1144 MODULE_ALIAS("platform:s3c2412-lcd");