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Linux 4.16.11
[linux/fpc-iii.git] / drivers / video / fbdev / sstfb.c
blobf0cb279ef333e8d5acd45a98a301af0345639b83
1 /*
2 * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer
3 *
4 * Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net>
5 *
6 * Created 15 Jan 2000 by Ghozlane Toumi
7 *
8 * Contributions (and many thanks) :
9 *
10 * 03/2001 James Simmons <jsimmons@infradead.org>
11 * 04/2001 Paul Mundt <lethal@chaoticdreams.org>
12 * 05/2001 Urs Ganse <ursg@uni.de>
13 * (initial work on voodoo2 port, interlace)
14 * 09/2002 Helge Deller <deller@gmx.de>
15 * (enable driver on big-endian machines (hppa), ioctl fixes)
16 * 12/2002 Helge Deller <deller@gmx.de>
17 * (port driver to new frambuffer infrastructure)
18 * 01/2003 Helge Deller <deller@gmx.de>
19 * (initial work on fb hardware acceleration for voodoo2)
20 * 08/2006 Alan Cox <alan@redhat.com>
21 * Remove never finished and bogus 24/32bit support
22 * Clean up macro abuse
23 * Minor tidying for format.
24 * 12/2006 Helge Deller <deller@gmx.de>
25 * add /sys/class/graphics/fbX/vgapass sysfs-interface
26 * add module option "mode_option" to set initial screen mode
27 * use fbdev default videomode database
28 * remove debug functions from ioctl
29 */
30
31 /*
32 * The voodoo1 has the following memory mapped address space:
33 * 0x000000 - 0x3fffff : registers (4MB)
34 * 0x400000 - 0x7fffff : linear frame buffer (4MB)
35 * 0x800000 - 0xffffff : texture memory (8MB)
36 */
37
38 /*
39 * misc notes, TODOs, toASKs, and deep thoughts
40
41 -TODO: at one time or another test that the mode is acceptable by the monitor
42 -ASK: Can I choose different ordering for the color bitfields (rgba argb ...)
43 which one should i use ? is there any preferred one ? It seems ARGB is
44 the one ...
45 -TODO: in set_var check the validity of timings (hsync vsync)...
46 -TODO: check and recheck the use of sst_wait_idle : we don't flush the fifo via
47 a nop command. so it's ok as long as the commands we pass don't go
48 through the fifo. warning: issuing a nop command seems to need pci_fifo
49 -FIXME: in case of failure in the init sequence, be sure we return to a safe
50 state.
51 - FIXME: Use accelerator for 2D scroll
52 -FIXME: 4MB boards have banked memory (FbiInit2 bits 1 & 20)
53 */
54
55 /*
56 * debug info
57 * SST_DEBUG : enable debugging
58 * SST_DEBUG_REG : debug registers
59 * 0 : no debug
60 * 1 : dac calls, [un]set_bits, FbiInit
61 * 2 : insane debug level (log every register read/write)
62 * SST_DEBUG_FUNC : functions
63 * 0 : no debug
64 * 1 : function call / debug ioctl
65 * 2 : variables
66 * 3 : flood . you don't want to do that. trust me.
67 * SST_DEBUG_VAR : debug display/var structs
68 * 0 : no debug
69 * 1 : dumps display, fb_var
70 *
71 * sstfb specific ioctls:
72 * toggle vga (0x46db) : toggle vga_pass_through
73 */
74
75 #undef SST_DEBUG
76
77
78 /*
79 * Includes
80 */
81
82 #include <linux/string.h>
83 #include <linux/kernel.h>
84 #include <linux/module.h>
85 #include <linux/fb.h>
86 #include <linux/pci.h>
87 #include <linux/delay.h>
88 #include <linux/init.h>
89 #include <asm/io.h>
90 #include <linux/uaccess.h>
91 #include <video/sstfb.h>
92
93
94 /* initialized by setup */
95
96 static bool vgapass; /* enable VGA passthrough cable */
97 static int mem; /* mem size in MB, 0 = autodetect */
98 static bool clipping = 1; /* use clipping (slower, safer) */
99 static int gfxclk; /* force FBI freq in Mhz . Dangerous */
100 static bool slowpci; /* slow PCI settings */
101
102 /*
103 Possible default video modes: 800x600@60, 640x480@75, 1024x768@76, 640x480@60
104 */
105 #define DEFAULT_VIDEO_MODE "640x480@60"
106
107 static char *mode_option = DEFAULT_VIDEO_MODE;
108
109 enum {
110 ID_VOODOO1 = 0,
111 ID_VOODOO2 = 1,
112 };
113
114 #define IS_VOODOO2(par) ((par)->type == ID_VOODOO2)
115
116 static struct sst_spec voodoo_spec[] = {
117 { .name = "Voodoo Graphics", .default_gfx_clock = 50000, .max_gfxclk = 60 },
118 { .name = "Voodoo2", .default_gfx_clock = 75000, .max_gfxclk = 85 },
119 };
120
121
122 /*
123 * debug functions
124 */
125
126 #if (SST_DEBUG_REG > 0)
127 static void sst_dbg_print_read_reg(u32 reg, u32 val) {
128 const char *regname;
129 switch (reg) {
130 case FBIINIT0: regname = "FbiInit0"; break;
131 case FBIINIT1: regname = "FbiInit1"; break;
132 case FBIINIT2: regname = "FbiInit2"; break;
133 case FBIINIT3: regname = "FbiInit3"; break;
134 case FBIINIT4: regname = "FbiInit4"; break;
135 case FBIINIT5: regname = "FbiInit5"; break;
136 case FBIINIT6: regname = "FbiInit6"; break;
137 default: regname = NULL; break;
138 }
139 if (regname == NULL)
140 r_ddprintk("sst_read(%#x): %#x\n", reg, val);
141 else
142 r_dprintk(" sst_read(%s): %#x\n", regname, val);
143 }
144
145 static void sst_dbg_print_write_reg(u32 reg, u32 val) {
146 const char *regname;
147 switch (reg) {
148 case FBIINIT0: regname = "FbiInit0"; break;
149 case FBIINIT1: regname = "FbiInit1"; break;
150 case FBIINIT2: regname = "FbiInit2"; break;
151 case FBIINIT3: regname = "FbiInit3"; break;
152 case FBIINIT4: regname = "FbiInit4"; break;
153 case FBIINIT5: regname = "FbiInit5"; break;
154 case FBIINIT6: regname = "FbiInit6"; break;
155 default: regname = NULL; break;
156 }
157 if (regname == NULL)
158 r_ddprintk("sst_write(%#x, %#x)\n", reg, val);
159 else
160 r_dprintk(" sst_write(%s, %#x)\n", regname, val);
161 }
162 #else /* (SST_DEBUG_REG > 0) */
163 # define sst_dbg_print_read_reg(reg, val) do {} while(0)
164 # define sst_dbg_print_write_reg(reg, val) do {} while(0)
165 #endif /* (SST_DEBUG_REG > 0) */
166
167 /*
168 * hardware access functions
169 */
170
171 /* register access */
172 #define sst_read(reg) __sst_read(par->mmio_vbase, reg)
173 #define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val)
174 #define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val)
175 #define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val)
176 #define sst_dac_read(reg) __sst_dac_read(par->mmio_vbase, reg)
177 #define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val)
178 #define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg)
179 #define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val)
180
181 static inline u32 __sst_read(u8 __iomem *vbase, u32 reg)
182 {
183 u32 ret = readl(vbase + reg);
184 sst_dbg_print_read_reg(reg, ret);
185 return ret;
186 }
187
188 static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val)
189 {
190 sst_dbg_print_write_reg(reg, val);
191 writel(val, vbase + reg);
192 }
193
194 static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val)
195 {
196 r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val);
197 __sst_write(vbase, reg, __sst_read(vbase, reg) | val);
198 }
199
200 static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val)
201 {
202 r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val);
203 __sst_write(vbase, reg, __sst_read(vbase, reg) & ~val);
204 }
205
206 /*
207 * wait for the fbi chip. ASK: what happens if the fbi is stuck ?
208 *
209 * the FBI is supposed to be ready if we receive 5 time
210 * in a row a "idle" answer to our requests
211 */
212
213 #define sst_wait_idle() __sst_wait_idle(par->mmio_vbase)
214
215 static int __sst_wait_idle(u8 __iomem *vbase)
216 {
217 int count = 0;
218
219 /* if (doFBINOP) __sst_write(vbase, NOPCMD, 0); */
220
221 while(1) {
222 if (__sst_read(vbase, STATUS) & STATUS_FBI_BUSY) {
223 f_dddprintk("status: busy\n");
224 /* FIXME basically, this is a busy wait. maybe not that good. oh well;
225 * this is a small loop after all.
226 * Or maybe we should use mdelay() or udelay() here instead ? */
227 count = 0;
228 } else {
229 count++;
230 f_dddprintk("status: idle(%d)\n", count);
231 }
232 if (count >= 5) return 1;
233 /* XXX do something to avoid hanging the machine if the voodoo is out */
234 }
235 }
236
237
238 /* dac access */
239 /* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */
240 static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg)
241 {
242 u8 ret;
243
244 reg &= 0x07;
245 __sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD );
246 __sst_wait_idle(vbase);
247 /* udelay(10); */
248 ret = __sst_read(vbase, DAC_READ) & 0xff;
249 r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret);
250
251 return ret;
252 }
253
254 static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val)
255 {
256 r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val);
257 reg &= 0x07;
258 __sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val);
259 __sst_wait_idle(vbase);
260 }
261
262 /* indexed access to ti/att dacs */
263 static u32 __dac_i_read(u8 __iomem *vbase, u8 reg)
264 {
265 u32 ret;
266
267 __sst_dac_write(vbase, DACREG_ADDR_I, reg);
268 ret = __sst_dac_read(vbase, DACREG_DATA_I);
269 r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret);
270 return ret;
271 }
272 static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val)
273 {
274 r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val);
275 __sst_dac_write(vbase, DACREG_ADDR_I, reg);
276 __sst_dac_write(vbase, DACREG_DATA_I, val);
277 }
278
279 /* compute the m,n,p , returns the real freq
280 * (ics datasheet : N <-> N1 , P <-> N2)
281 *
282 * Fout= Fref * (M+2)/( 2^P * (N+2))
283 * we try to get close to the asked freq
284 * with P as high, and M as low as possible
285 * range:
286 * ti/att : 0 <= M <= 255; 0 <= P <= 3; 0<= N <= 63
287 * ics : 1 <= M <= 127; 0 <= P <= 3; 1<= N <= 31
288 * we'll use the lowest limitation, should be precise enouth
289 */
290 static int sst_calc_pll(const int freq, int *freq_out, struct pll_timing *t)
291 {
292 int m, m2, n, p, best_err, fout;
293 int best_n = -1;
294 int best_m = -1;
295
296 best_err = freq;
297 p = 3;
298 /* f * 2^P = vco should be less than VCOmax ~ 250 MHz for ics*/
299 while (((1 << p) * freq > VCO_MAX) && (p >= 0))
300 p--;
301 if (p == -1)
302 return -EINVAL;
303 for (n = 1; n < 32; n++) {
304 /* calc 2 * m so we can round it later*/
305 m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ;
306
307 m = (m2 % 2 ) ? m2/2+1 : m2/2 ;
308 if (m >= 128)
309 break;
310 fout = (DAC_FREF * (m + 2)) / ((1 << p) * (n + 2));
311 if ((abs(fout - freq) < best_err) && (m > 0)) {
312 best_n = n;
313 best_m = m;
314 best_err = abs(fout - freq);
315 /* we get the lowest m , allowing 0.5% error in freq*/
316 if (200*best_err < freq) break;
317 }
318 }
319 if (best_n == -1) /* unlikely, but who knows ? */
320 return -EINVAL;
321 t->p = p;
322 t->n = best_n;
323 t->m = best_m;
324 *freq_out = (DAC_FREF * (t->m + 2)) / ((1 << t->p) * (t->n + 2));
325 f_ddprintk ("m: %d, n: %d, p: %d, F: %dKhz\n",
326 t->m, t->n, t->p, *freq_out);
327 return 0;
328 }
329
330 /*
331 * clear lfb screen
332 */
333 static void sstfb_clear_screen(struct fb_info *info)
334 {
335 /* clear screen */
336 fb_memset(info->screen_base, 0, info->fix.smem_len);
337 }
338
339
340 /**
341 * sstfb_check_var - Optional function. Validates a var passed in.
342 * @var: frame buffer variable screen structure
343 * @info: frame buffer structure that represents a single frame buffer
344 *
345 * Limit to the abilities of a single chip as SLI is not supported
346 * by this driver.
347 */
348
349 static int sstfb_check_var(struct fb_var_screeninfo *var,
350 struct fb_info *info)
351 {
352 struct sstfb_par *par = info->par;
353 int hSyncOff = var->xres + var->right_margin + var->left_margin;
354 int vSyncOff = var->yres + var->lower_margin + var->upper_margin;
355 int vBackPorch = var->left_margin, yDim = var->yres;
356 int vSyncOn = var->vsync_len;
357 int tiles_in_X, real_length;
358 unsigned int freq;
359
360 if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) {
361 printk(KERN_ERR "sstfb: Pixclock at %ld KHZ out of range\n",
362 PICOS2KHZ(var->pixclock));
363 return -EINVAL;
364 }
365 var->pixclock = KHZ2PICOS(freq);
366
367 if (var->vmode & FB_VMODE_INTERLACED)
368 vBackPorch += (vBackPorch % 2);
369 if (var->vmode & FB_VMODE_DOUBLE) {
370 vBackPorch <<= 1;
371 yDim <<=1;
372 vSyncOn <<=1;
373 vSyncOff <<=1;
374 }
375
376 switch (var->bits_per_pixel) {
377 case 0 ... 16 :
378 var->bits_per_pixel = 16;
379 break;
380 default :
381 printk(KERN_ERR "sstfb: Unsupported bpp %d\n", var->bits_per_pixel);
382 return -EINVAL;
383 }
384
385 /* validity tests */
386 if (var->xres <= 1 || yDim <= 0 || var->hsync_len <= 1 ||
387 hSyncOff <= 1 || var->left_margin <= 2 || vSyncOn <= 0 ||
388 vSyncOff <= 0 || vBackPorch <= 0) {
389 return -EINVAL;
390 }
391
392 if (IS_VOODOO2(par)) {
393 /* Voodoo 2 limits */
394 tiles_in_X = (var->xres + 63 ) / 64 * 2;
395
396 if (var->xres > POW2(11) || yDim >= POW2(11)) {
397 printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n",
398 var->xres, var->yres);
399 return -EINVAL;
400 }
401
402 if (var->hsync_len > POW2(9) || hSyncOff > POW2(11) ||
403 var->left_margin - 2 >= POW2(9) || vSyncOn >= POW2(13) ||
404 vSyncOff >= POW2(13) || vBackPorch >= POW2(9) ||
405 tiles_in_X >= POW2(6) || tiles_in_X <= 0) {
406 printk(KERN_ERR "sstfb: Unsupported timings\n");
407 return -EINVAL;
408 }
409 } else {
410 /* Voodoo limits */
411 tiles_in_X = (var->xres + 63 ) / 64;
412
413 if (var->vmode) {
414 printk(KERN_ERR "sstfb: Interlace/doublescan not supported %#x\n",
415 var->vmode);
416 return -EINVAL;
417 }
418 if (var->xres > POW2(10) || var->yres >= POW2(10)) {
419 printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n",
420 var->xres, var->yres);
421 return -EINVAL;
422 }
423 if (var->hsync_len > POW2(8) || hSyncOff - 1 > POW2(10) ||
424 var->left_margin - 2 >= POW2(8) || vSyncOn >= POW2(12) ||
425 vSyncOff >= POW2(12) || vBackPorch >= POW2(8) ||
426 tiles_in_X >= POW2(4) || tiles_in_X <= 0) {
427 printk(KERN_ERR "sstfb: Unsupported timings\n");
428 return -EINVAL;
429 }
430 }
431
432 /* it seems that the fbi uses tiles of 64x16 pixels to "map" the mem */
433 /* FIXME: i don't like this... looks wrong */
434 real_length = tiles_in_X * (IS_VOODOO2(par) ? 32 : 64 )
435 * ((var->bits_per_pixel == 16) ? 2 : 4);
436
437 if (real_length * yDim > info->fix.smem_len) {
438 printk(KERN_ERR "sstfb: Not enough video memory\n");
439 return -ENOMEM;
440 }
441
442 var->sync &= (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT);
443 var->vmode &= (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE);
444 var->xoffset = 0;
445 var->yoffset = 0;
446 var->height = -1;
447 var->width = -1;
448
449 /*
450 * correct the color bit fields
451 */
452 /* var->{red|green|blue}.msb_right = 0; */
453
454 switch (var->bits_per_pixel) {
455 case 16: /* RGB 565 LfbMode 0 */
456 var->red.length = 5;
457 var->green.length = 6;
458 var->blue.length = 5;
459 var->transp.length = 0;
460
461 var->red.offset = 11;
462 var->green.offset = 5;
463 var->blue.offset = 0;
464 var->transp.offset = 0;
465 break;
466 default:
467 return -EINVAL;
468 }
469 return 0;
470 }
471
472 /**
473 * sstfb_set_par - Optional function. Alters the hardware state.
474 * @info: frame buffer structure that represents a single frame buffer
475 */
476 static int sstfb_set_par(struct fb_info *info)
477 {
478 struct sstfb_par *par = info->par;
479 u32 lfbmode, fbiinit1, fbiinit2, fbiinit3, fbiinit5, fbiinit6=0;
480 struct pci_dev *sst_dev = par->dev;
481 unsigned int freq;
482 int ntiles;
483
484 par->hSyncOff = info->var.xres + info->var.right_margin + info->var.left_margin;
485
486 par->yDim = info->var.yres;
487 par->vSyncOn = info->var.vsync_len;
488 par->vSyncOff = info->var.yres + info->var.lower_margin + info->var.upper_margin;
489 par->vBackPorch = info->var.upper_margin;
490
491 /* We need par->pll */
492 sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll);
493
494 if (info->var.vmode & FB_VMODE_INTERLACED)
495 par->vBackPorch += (par->vBackPorch % 2);
496 if (info->var.vmode & FB_VMODE_DOUBLE) {
497 par->vBackPorch <<= 1;
498 par->yDim <<=1;
499 par->vSyncOn <<=1;
500 par->vSyncOff <<=1;
501 }
502
503 if (IS_VOODOO2(par)) {
504 /* voodoo2 has 32 pixel wide tiles , BUT strange things
505 happen with odd number of tiles */
506 par->tiles_in_X = (info->var.xres + 63 ) / 64 * 2;
507 } else {
508 /* voodoo1 has 64 pixels wide tiles. */
509 par->tiles_in_X = (info->var.xres + 63 ) / 64;
510 }
511
512 f_ddprintk("hsync_len hSyncOff vsync_len vSyncOff\n");
513 f_ddprintk("%-7d %-8d %-7d %-8d\n",
514 info->var.hsync_len, par->hSyncOff,
515 par->vSyncOn, par->vSyncOff);
516 f_ddprintk("left_margin upper_margin xres yres Freq\n");
517 f_ddprintk("%-10d %-10d %-4d %-4d %-8ld\n",
518 info->var.left_margin, info->var.upper_margin,
519 info->var.xres, info->var.yres, PICOS2KHZ(info->var.pixclock));
520
521 sst_write(NOPCMD, 0);
522 sst_wait_idle();
523 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
524 sst_set_bits(FBIINIT1, VIDEO_RESET);
525 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
526 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
527 sst_wait_idle();
528
529 /*sst_unset_bits (FBIINIT0, FBI_RESET); / reenable FBI ? */
530
531 sst_write(BACKPORCH, par->vBackPorch << 16 | (info->var.left_margin - 2));
532 sst_write(VIDEODIMENSIONS, par->yDim << 16 | (info->var.xres - 1));
533 sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1));
534 sst_write(VSYNC, par->vSyncOff << 16 | par->vSyncOn);
535
536 fbiinit2 = sst_read(FBIINIT2);
537 fbiinit3 = sst_read(FBIINIT3);
538
539 /* everything is reset. we enable fbiinit2/3 remap : dac access ok */
540 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
541 PCI_EN_INIT_WR | PCI_REMAP_DAC );
542
543 par->dac_sw.set_vidmod(info, info->var.bits_per_pixel);
544
545 /* set video clock */
546 par->dac_sw.set_pll(info, &par->pll, VID_CLOCK);
547
548 /* disable fbiinit2/3 remap */
549 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
550 PCI_EN_INIT_WR);
551
552 /* restore fbiinit2/3 */
553 sst_write(FBIINIT2,fbiinit2);
554 sst_write(FBIINIT3,fbiinit3);
555
556 fbiinit1 = (sst_read(FBIINIT1) & VIDEO_MASK)
557 | EN_DATA_OE
558 | EN_BLANK_OE
559 | EN_HVSYNC_OE
560 | EN_DCLK_OE
561 /* | (15 << TILES_IN_X_SHIFT) */
562 | SEL_INPUT_VCLK_2X
563 /* | (2 << VCLK_2X_SEL_DEL_SHIFT)
564 | (2 << VCLK_DEL_SHIFT) */;
565 /* try with vclk_in_delay =0 (bits 29:30) , vclk_out_delay =0 (bits(27:28)
566 in (near) future set them accordingly to revision + resolution (cf glide)
567 first understand what it stands for :)
568 FIXME: there are some artefacts... check for the vclk_in_delay
569 lets try with 6ns delay in both vclk_out & in...
570 doh... they're still there :\
571 */
572
573 ntiles = par->tiles_in_X;
574 if (IS_VOODOO2(par)) {
575 fbiinit1 |= ((ntiles & 0x20) >> 5) << TILES_IN_X_MSB_SHIFT
576 | ((ntiles & 0x1e) >> 1) << TILES_IN_X_SHIFT;
577 /* as the only value of importance for us in fbiinit6 is tiles in X (lsb),
578 and as reading fbinit 6 will return crap (see FBIINIT6_DEFAULT) we just
579 write our value. BTW due to the dac unable to read odd number of tiles, this
580 field is always null ... */
581 fbiinit6 = (ntiles & 0x1) << TILES_IN_X_LSB_SHIFT;
582 }
583 else
584 fbiinit1 |= ntiles << TILES_IN_X_SHIFT;
585
586 switch (info->var.bits_per_pixel) {
587 case 16:
588 fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL;
589 break;
590 default:
591 return -EINVAL;
592 }
593 sst_write(FBIINIT1, fbiinit1);
594 if (IS_VOODOO2(par)) {
595 sst_write(FBIINIT6, fbiinit6);
596 fbiinit5=sst_read(FBIINIT5) & FBIINIT5_MASK ;
597 if (info->var.vmode & FB_VMODE_INTERLACED)
598 fbiinit5 |= INTERLACE;
599 if (info->var.vmode & FB_VMODE_DOUBLE)
600 fbiinit5 |= VDOUBLESCAN;
601 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
602 fbiinit5 |= HSYNC_HIGH;
603 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
604 fbiinit5 |= VSYNC_HIGH;
605 sst_write(FBIINIT5, fbiinit5);
606 }
607 sst_wait_idle();
608 sst_unset_bits(FBIINIT1, VIDEO_RESET);
609 sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
610 sst_set_bits(FBIINIT2, EN_DRAM_REFRESH);
611 /* disables fbiinit writes */
612 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
613
614 /* set lfbmode : set mode + front buffer for reads/writes
615 + disable pipeline */
616 switch (info->var.bits_per_pixel) {
617 case 16:
618 lfbmode = LFB_565;
619 break;
620 default:
621 return -EINVAL;
622 }
623
624 #if defined(__BIG_ENDIAN)
625 /* Enable byte-swizzle functionality in hardware.
626 * With this enabled, all our read- and write-accesses to
627 * the voodoo framebuffer can be done in native format, and
628 * the hardware will automatically convert it to little-endian.
629 * - tested on HP-PARISC, Helge Deller <deller@gmx.de> */
630 lfbmode |= ( LFB_WORD_SWIZZLE_WR | LFB_BYTE_SWIZZLE_WR |
631 LFB_WORD_SWIZZLE_RD | LFB_BYTE_SWIZZLE_RD );
632 #endif
633
634 if (clipping) {
635 sst_write(LFBMODE, lfbmode | EN_PXL_PIPELINE);
636 /*
637 * Set "clipping" dimensions. If clipping is disabled and
638 * writes to offscreen areas of the framebuffer are performed,
639 * the "behaviour is undefined" (_very_ undefined) - Urs
640 */
641 /* btw, it requires enabling pixel pipeline in LFBMODE .
642 off screen read/writes will just wrap and read/print pixels
643 on screen. Ugly but not that dangerous */
644 f_ddprintk("setting clipping dimensions 0..%d, 0..%d\n",
645 info->var.xres - 1, par->yDim - 1);
646
647 sst_write(CLIP_LEFT_RIGHT, info->var.xres);
648 sst_write(CLIP_LOWY_HIGHY, par->yDim);
649 sst_set_bits(FBZMODE, EN_CLIPPING | EN_RGB_WRITE);
650 } else {
651 /* no clipping : direct access, no pipeline */
652 sst_write(LFBMODE, lfbmode);
653 }
654 return 0;
655 }
656
657 /**
658 * sstfb_setcolreg - Optional function. Sets a color register.
659 * @regno: hardware colormap register
660 * @red: frame buffer colormap structure
661 * @green: The green value which can be up to 16 bits wide
662 * @blue: The blue value which can be up to 16 bits wide.
663 * @transp: If supported the alpha value which can be up to 16 bits wide.
664 * @info: frame buffer info structure
665 */
666 static int sstfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
667 u_int transp, struct fb_info *info)
668 {
669 struct sstfb_par *par = info->par;
670 u32 col;
671
672 f_dddprintk("sstfb_setcolreg\n");
673 f_dddprintk("%-2d rgbt: %#x, %#x, %#x, %#x\n",
674 regno, red, green, blue, transp);
675 if (regno > 15)
676 return 0;
677
678 red >>= (16 - info->var.red.length);
679 green >>= (16 - info->var.green.length);
680 blue >>= (16 - info->var.blue.length);
681 transp >>= (16 - info->var.transp.length);
682 col = (red << info->var.red.offset)
683 | (green << info->var.green.offset)
684 | (blue << info->var.blue.offset)
685 | (transp << info->var.transp.offset);
686
687 par->palette[regno] = col;
688
689 return 0;
690 }
691
692 static void sstfb_setvgapass( struct fb_info *info, int enable )
693 {
694 struct sstfb_par *par = info->par;
695 struct pci_dev *sst_dev = par->dev;
696 u32 fbiinit0, tmp;
697
698 enable = enable ? 1:0;
699 if (par->vgapass == enable)
700 return;
701 par->vgapass = enable;
702
703 pci_read_config_dword(sst_dev, PCI_INIT_ENABLE, &tmp);
704 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
705 tmp | PCI_EN_INIT_WR );
706 fbiinit0 = sst_read (FBIINIT0);
707 if (par->vgapass) {
708 sst_write(FBIINIT0, fbiinit0 & ~DIS_VGA_PASSTHROUGH);
709 fb_info(info, "Enabling VGA pass-through\n");
710 } else {
711 sst_write(FBIINIT0, fbiinit0 | DIS_VGA_PASSTHROUGH);
712 fb_info(info, "Disabling VGA pass-through\n");
713 }
714 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp);
715 }
716
717 static ssize_t store_vgapass(struct device *device, struct device_attribute *attr,
718 const char *buf, size_t count)
719 {
720 struct fb_info *info = dev_get_drvdata(device);
721 char ** last = NULL;
722 int val;
723
724 val = simple_strtoul(buf, last, 0);
725 sstfb_setvgapass(info, val);
726
727 return count;
728 }
729
730 static ssize_t show_vgapass(struct device *device, struct device_attribute *attr,
731 char *buf)
732 {
733 struct fb_info *info = dev_get_drvdata(device);
734 struct sstfb_par *par = info->par;
735 return snprintf(buf, PAGE_SIZE, "%d\n", par->vgapass);
736 }
737
738 static struct device_attribute device_attrs[] = {
739 __ATTR(vgapass, S_IRUGO|S_IWUSR, show_vgapass, store_vgapass)
740 };
741
742 static int sstfb_ioctl(struct fb_info *info, unsigned int cmd,
743 unsigned long arg)
744 {
745 struct sstfb_par *par;
746 u32 val;
747
748 switch (cmd) {
749 /* set/get VGA pass_through mode */
750 case SSTFB_SET_VGAPASS:
751 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
752 return -EFAULT;
753 sstfb_setvgapass(info, val);
754 return 0;
755 case SSTFB_GET_VGAPASS:
756 par = info->par;
757 val = par->vgapass;
758 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
759 return -EFAULT;
760 return 0;
761 }
762
763 return -EINVAL;
764 }
765
766
767 /*
768 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) - Voodoo2 only
769 */
770 #if 0
771 static void sstfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
772 {
773 struct sstfb_par *par = info->par;
774 u32 stride = info->fix.line_length;
775
776 if (!IS_VOODOO2(par))
777 return;
778
779 sst_write(BLTSRCBASEADDR, 0);
780 sst_write(BLTDSTBASEADDR, 0);
781 sst_write(BLTROP, BLTROP_COPY);
782 sst_write(BLTXYSTRIDES, stride | (stride << 16));
783 sst_write(BLTSRCXY, area->sx | (area->sy << 16));
784 sst_write(BLTDSTXY, area->dx | (area->dy << 16));
785 sst_write(BLTSIZE, area->width | (area->height << 16));
786 sst_write(BLTCOMMAND, BLT_SCR2SCR_BITBLT | LAUNCH_BITBLT |
787 (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) );
788 sst_wait_idle();
789 }
790 #endif
791
792
793 /*
794 * FillRect 2D command (solidfill or invert (via ROP_XOR)) - Voodoo2 only
795 */
796 #if 0
797 static void sstfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
798 {
799 struct sstfb_par *par = info->par;
800 u32 stride = info->fix.line_length;
801
802 if (!IS_VOODOO2(par))
803 return;
804
805 sst_write(BLTCLIPX, info->var.xres);
806 sst_write(BLTCLIPY, info->var.yres);
807
808 sst_write(BLTDSTBASEADDR, 0);
809 sst_write(BLTCOLOR, rect->color);
810 sst_write(BLTROP, rect->rop == ROP_COPY ? BLTROP_COPY : BLTROP_XOR);
811 sst_write(BLTXYSTRIDES, stride | (stride << 16));
812 sst_write(BLTDSTXY, rect->dx | (rect->dy << 16));
813 sst_write(BLTSIZE, rect->width | (rect->height << 16));
814 sst_write(BLTCOMMAND, BLT_RECFILL_BITBLT | LAUNCH_BITBLT
815 | (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) | BIT(16) );
816 sst_wait_idle();
817 }
818 #endif
819
820
821
822 /*
823 * get lfb size
824 */
825 static int sst_get_memsize(struct fb_info *info, __u32 *memsize)
826 {
827 u8 __iomem *fbbase_virt = info->screen_base;
828
829 /* force memsize */
830 if (mem >= 1 && mem <= 4) {
831 *memsize = (mem * 0x100000);
832 printk(KERN_INFO "supplied memsize: %#x\n", *memsize);
833 return 1;
834 }
835
836 writel(0xdeadbeef, fbbase_virt);
837 writel(0xdeadbeef, fbbase_virt+0x100000);
838 writel(0xdeadbeef, fbbase_virt+0x200000);
839 f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
840 readl(fbbase_virt), readl(fbbase_virt + 0x100000),
841 readl(fbbase_virt + 0x200000));
842
843 writel(0xabcdef01, fbbase_virt);
844
845 f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
846 readl(fbbase_virt), readl(fbbase_virt + 0x100000),
847 readl(fbbase_virt + 0x200000));
848
849 /* checks for 4mb lfb, then 2, then defaults to 1 */
850 if (readl(fbbase_virt + 0x200000) == 0xdeadbeef)
851 *memsize = 0x400000;
852 else if (readl(fbbase_virt + 0x100000) == 0xdeadbeef)
853 *memsize = 0x200000;
854 else
855 *memsize = 0x100000;
856 f_ddprintk("detected memsize: %dMB\n", *memsize >> 20);
857 return 1;
858 }
859
860
861 /*
862 * DAC detection routines
863 */
864
865 /* fbi should be idle, and fifo emty and mem disabled */
866 /* supposed to detect AT&T ATT20C409 and Ti TVP3409 ramdacs */
867
868 static int sst_detect_att(struct fb_info *info)
869 {
870 struct sstfb_par *par = info->par;
871 int i, mir, dir;
872
873 for (i = 0; i < 3; i++) {
874 sst_dac_write(DACREG_WMA, 0); /* backdoor */
875 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
876 sst_dac_read(DACREG_RMR);
877 sst_dac_read(DACREG_RMR);
878 sst_dac_read(DACREG_RMR);
879 /* the fifth time, CR0 is read */
880 sst_dac_read(DACREG_RMR);
881 /* the 6th, manufacturer id register */
882 mir = sst_dac_read(DACREG_RMR);
883 /*the 7th, device ID register */
884 dir = sst_dac_read(DACREG_RMR);
885 f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
886 if (mir == DACREG_MIR_ATT && dir == DACREG_DIR_ATT) {
887 return 1;
888 }
889 }
890 return 0;
891 }
892
893 static int sst_detect_ti(struct fb_info *info)
894 {
895 struct sstfb_par *par = info->par;
896 int i, mir, dir;
897
898 for (i = 0; i<3; i++) {
899 sst_dac_write(DACREG_WMA, 0); /* backdoor */
900 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
901 sst_dac_read(DACREG_RMR);
902 sst_dac_read(DACREG_RMR);
903 sst_dac_read(DACREG_RMR);
904 /* the fifth time, CR0 is read */
905 sst_dac_read(DACREG_RMR);
906 /* the 6th, manufacturer id register */
907 mir = sst_dac_read(DACREG_RMR);
908 /*the 7th, device ID register */
909 dir = sst_dac_read(DACREG_RMR);
910 f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
911 if ((mir == DACREG_MIR_TI ) && (dir == DACREG_DIR_TI)) {
912 return 1;
913 }
914 }
915 return 0;
916 }
917
918 /*
919 * try to detect ICS5342 ramdac
920 * we get the 1st byte (M value) of preset f1,f7 and fB
921 * why those 3 ? mmmh... for now, i'll do it the glide way...
922 * and ask questions later. anyway, it seems that all the freq registers are
923 * really at their default state (cf specs) so i ask again, why those 3 regs ?
924 * mmmmh.. it seems that's much more ugly than i thought. we use f0 and fA for
925 * pll programming, so in fact, we *hope* that the f1, f7 & fB won't be
926 * touched...
927 * is it really safe ? how can i reset this ramdac ? geee...
928 */
929 static int sst_detect_ics(struct fb_info *info)
930 {
931 struct sstfb_par *par = info->par;
932 int m_clk0_1, m_clk0_7, m_clk1_b;
933 int n_clk0_1, n_clk0_7, n_clk1_b;
934 int i;
935
936 for (i = 0; i<5; i++ ) {
937 sst_dac_write(DACREG_ICS_PLLRMA, 0x1); /* f1 */
938 m_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
939 n_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
940 sst_dac_write(DACREG_ICS_PLLRMA, 0x7); /* f7 */
941 m_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
942 n_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
943 sst_dac_write(DACREG_ICS_PLLRMA, 0xb); /* fB */
944 m_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
945 n_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
946 f_ddprintk("m_clk0_1: %#x, m_clk0_7: %#x, m_clk1_b: %#x\n",
947 m_clk0_1, m_clk0_7, m_clk1_b);
948 f_ddprintk("n_clk0_1: %#x, n_clk0_7: %#x, n_clk1_b: %#x\n",
949 n_clk0_1, n_clk0_7, n_clk1_b);
950 if (( m_clk0_1 == DACREG_ICS_PLL_CLK0_1_INI)
951 && (m_clk0_7 == DACREG_ICS_PLL_CLK0_7_INI)
952 && (m_clk1_b == DACREG_ICS_PLL_CLK1_B_INI)) {
953 return 1;
954 }
955 }
956 return 0;
957 }
958
959
960 /*
961 * gfx, video, pci fifo should be reset, dram refresh disabled
962 * see detect_dac
963 */
964
965 static int sst_set_pll_att_ti(struct fb_info *info,
966 const struct pll_timing *t, const int clock)
967 {
968 struct sstfb_par *par = info->par;
969 u8 cr0, cc;
970
971 /* enable indexed mode */
972 sst_dac_write(DACREG_WMA, 0); /* backdoor */
973 sst_dac_read(DACREG_RMR); /* 1 time: RMR */
974 sst_dac_read(DACREG_RMR); /* 2 RMR */
975 sst_dac_read(DACREG_RMR); /* 3 // */
976 sst_dac_read(DACREG_RMR); /* 4 // */
977 cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */
978
979 sst_dac_write(DACREG_WMA, 0);
980 sst_dac_read(DACREG_RMR);
981 sst_dac_read(DACREG_RMR);
982 sst_dac_read(DACREG_RMR);
983 sst_dac_read(DACREG_RMR);
984 sst_dac_write(DACREG_RMR, (cr0 & 0xf0)
985 | DACREG_CR0_EN_INDEXED
986 | DACREG_CR0_8BIT
987 | DACREG_CR0_PWDOWN );
988 /* so, now we are in indexed mode . dunno if its common, but
989 i find this way of doing things a little bit weird :p */
990
991 udelay(300);
992 cc = dac_i_read(DACREG_CC_I);
993 switch (clock) {
994 case VID_CLOCK:
995 dac_i_write(DACREG_AC0_I, t->m);
996 dac_i_write(DACREG_AC1_I, t->p << 6 | t->n);
997 dac_i_write(DACREG_CC_I,
998 (cc & 0x0f) | DACREG_CC_CLKA | DACREG_CC_CLKA_C);
999 break;
1000 case GFX_CLOCK:
1001 dac_i_write(DACREG_BD0_I, t->m);
1002 dac_i_write(DACREG_BD1_I, t->p << 6 | t->n);
1003 dac_i_write(DACREG_CC_I,
1004 (cc & 0xf0) | DACREG_CC_CLKB | DACREG_CC_CLKB_D);
1005 break;
1006 default:
1007 dprintk("%s: wrong clock code '%d'\n",
1008 __func__, clock);
1009 return 0;
1010 }
1011 udelay(300);
1012
1013 /* power up the dac & return to "normal" non-indexed mode */
1014 dac_i_write(DACREG_CR0_I,
1015 cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED);
1016 return 1;
1017 }
1018
1019 static int sst_set_pll_ics(struct fb_info *info,
1020 const struct pll_timing *t, const int clock)
1021 {
1022 struct sstfb_par *par = info->par;
1023 u8 pll_ctrl;
1024
1025 sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL);
1026 pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA);
1027 switch(clock) {
1028 case VID_CLOCK:
1029 sst_dac_write(DACREG_ICS_PLLWMA, 0x0); /* CLK0, f0 */
1030 sst_dac_write(DACREG_ICS_PLLDATA, t->m);
1031 sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
1032 /* selects freq f0 for clock 0 */
1033 sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
1034 sst_dac_write(DACREG_ICS_PLLDATA,
1035 (pll_ctrl & 0xd8)
1036 | DACREG_ICS_CLK0
1037 | DACREG_ICS_CLK0_0);
1038 break;
1039 case GFX_CLOCK :
1040 sst_dac_write(DACREG_ICS_PLLWMA, 0xa); /* CLK1, fA */
1041 sst_dac_write(DACREG_ICS_PLLDATA, t->m);
1042 sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
1043 /* selects freq fA for clock 1 */
1044 sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
1045 sst_dac_write(DACREG_ICS_PLLDATA,
1046 (pll_ctrl & 0xef) | DACREG_ICS_CLK1_A);
1047 break;
1048 default:
1049 dprintk("%s: wrong clock code '%d'\n",
1050 __func__, clock);
1051 return 0;
1052 }
1053 udelay(300);
1054 return 1;
1055 }
1056
1057 static void sst_set_vidmod_att_ti(struct fb_info *info, const int bpp)
1058 {
1059 struct sstfb_par *par = info->par;
1060 u8 cr0;
1061
1062 sst_dac_write(DACREG_WMA, 0); /* backdoor */
1063 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
1064 sst_dac_read(DACREG_RMR);
1065 sst_dac_read(DACREG_RMR);
1066 sst_dac_read(DACREG_RMR);
1067 /* the fifth time, CR0 is read */
1068 cr0 = sst_dac_read(DACREG_RMR);
1069
1070 sst_dac_write(DACREG_WMA, 0); /* backdoor */
1071 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
1072 sst_dac_read(DACREG_RMR);
1073 sst_dac_read(DACREG_RMR);
1074 sst_dac_read(DACREG_RMR);
1075 /* cr0 */
1076 switch(bpp) {
1077 case 16:
1078 sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP);
1079 break;
1080 default:
1081 dprintk("%s: bad depth '%u'\n", __func__, bpp);
1082 break;
1083 }
1084 }
1085
1086 static void sst_set_vidmod_ics(struct fb_info *info, const int bpp)
1087 {
1088 struct sstfb_par *par = info->par;
1089
1090 switch(bpp) {
1091 case 16:
1092 sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP);
1093 break;
1094 default:
1095 dprintk("%s: bad depth '%u'\n", __func__, bpp);
1096 break;
1097 }
1098 }
1099
1100 /*
1101 * detect dac type
1102 * prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset,
1103 * dram refresh disabled, FbiInit remaped.
1104 * TODO: mmh.. maybe i should put the "prerequisite" in the func ...
1105 */
1106
1107
1108 static struct dac_switch dacs[] = {
1109 { .name = "TI TVP3409",
1110 .detect = sst_detect_ti,
1111 .set_pll = sst_set_pll_att_ti,
1112 .set_vidmod = sst_set_vidmod_att_ti },
1113
1114 { .name = "AT&T ATT20C409",
1115 .detect = sst_detect_att,
1116 .set_pll = sst_set_pll_att_ti,
1117 .set_vidmod = sst_set_vidmod_att_ti },
1118 { .name = "ICS ICS5342",
1119 .detect = sst_detect_ics,
1120 .set_pll = sst_set_pll_ics,
1121 .set_vidmod = sst_set_vidmod_ics },
1122 };
1123
1124 static int sst_detect_dactype(struct fb_info *info, struct sstfb_par *par)
1125 {
1126 int i, ret = 0;
1127
1128 for (i = 0; i < ARRAY_SIZE(dacs); i++) {
1129 ret = dacs[i].detect(info);
1130 if (ret)
1131 break;
1132 }
1133 if (!ret)
1134 return 0;
1135 f_dprintk("%s found %s\n", __func__, dacs[i].name);
1136 par->dac_sw = dacs[i];
1137 return 1;
1138 }
1139
1140 /*
1141 * Internal Routines
1142 */
1143 static int sst_init(struct fb_info *info, struct sstfb_par *par)
1144 {
1145 u32 fbiinit0, fbiinit1, fbiinit4;
1146 struct pci_dev *dev = par->dev;
1147 struct pll_timing gfx_timings;
1148 struct sst_spec *spec;
1149 int Fout;
1150 int gfx_clock;
1151
1152 spec = &voodoo_spec[par->type];
1153 f_ddprintk(" fbiinit0 fbiinit1 fbiinit2 fbiinit3 fbiinit4 "
1154 " fbiinit6\n");
1155 f_ddprintk("%0#10x %0#10x %0#10x %0#10x %0#10x %0#10x\n",
1156 sst_read(FBIINIT0), sst_read(FBIINIT1), sst_read(FBIINIT2),
1157 sst_read(FBIINIT3), sst_read(FBIINIT4), sst_read(FBIINIT6));
1158 /* disable video clock */
1159 pci_write_config_dword(dev, PCI_VCLK_DISABLE, 0);
1160
1161 /* enable writing to init registers, disable pci fifo */
1162 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
1163 /* reset video */
1164 sst_set_bits(FBIINIT1, VIDEO_RESET);
1165 sst_wait_idle();
1166 /* reset gfx + pci fifo */
1167 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
1168 sst_wait_idle();
1169
1170 /* unreset fifo */
1171 /*sst_unset_bits(FBIINIT0, FIFO_RESET);
1172 sst_wait_idle();*/
1173 /* unreset FBI */
1174 /*sst_unset_bits(FBIINIT0, FBI_RESET);
1175 sst_wait_idle();*/
1176
1177 /* disable dram refresh */
1178 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
1179 sst_wait_idle();
1180 /* remap fbinit2/3 to dac */
1181 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1182 PCI_EN_INIT_WR | PCI_REMAP_DAC );
1183 /* detect dac type */
1184 if (!sst_detect_dactype(info, par)) {
1185 printk(KERN_ERR "sstfb: unknown dac type.\n");
1186 //FIXME watch it: we are not in a safe state, bad bad bad.
1187 return 0;
1188 }
1189
1190 /* set graphic clock */
1191 gfx_clock = spec->default_gfx_clock;
1192 if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) {
1193 printk(KERN_INFO "sstfb: Using supplied graphic freq : %dMHz\n", gfxclk);
1194 gfx_clock = gfxclk *1000;
1195 } else if (gfxclk) {
1196 printk(KERN_WARNING "sstfb: %dMhz is way out of spec! Using default\n", gfxclk);
1197 }
1198
1199 sst_calc_pll(gfx_clock, &Fout, &gfx_timings);
1200 par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
1201
1202 /* disable fbiinit remap */
1203 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1204 PCI_EN_INIT_WR| PCI_EN_FIFO_WR );
1205 /* defaults init registers */
1206 /* FbiInit0: unreset gfx, unreset fifo */
1207 fbiinit0 = FBIINIT0_DEFAULT;
1208 fbiinit1 = FBIINIT1_DEFAULT;
1209 fbiinit4 = FBIINIT4_DEFAULT;
1210 par->vgapass = vgapass;
1211 if (par->vgapass)
1212 fbiinit0 &= ~DIS_VGA_PASSTHROUGH;
1213 else
1214 fbiinit0 |= DIS_VGA_PASSTHROUGH;
1215 if (slowpci) {
1216 fbiinit1 |= SLOW_PCI_WRITES;
1217 fbiinit4 |= SLOW_PCI_READS;
1218 } else {
1219 fbiinit1 &= ~SLOW_PCI_WRITES;
1220 fbiinit4 &= ~SLOW_PCI_READS;
1221 }
1222 sst_write(FBIINIT0, fbiinit0);
1223 sst_wait_idle();
1224 sst_write(FBIINIT1, fbiinit1);
1225 sst_wait_idle();
1226 sst_write(FBIINIT2, FBIINIT2_DEFAULT);
1227 sst_wait_idle();
1228 sst_write(FBIINIT3, FBIINIT3_DEFAULT);
1229 sst_wait_idle();
1230 sst_write(FBIINIT4, fbiinit4);
1231 sst_wait_idle();
1232 if (IS_VOODOO2(par)) {
1233 sst_write(FBIINIT6, FBIINIT6_DEFAULT);
1234 sst_wait_idle();
1235 }
1236
1237 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
1238 pci_write_config_dword(dev, PCI_VCLK_ENABLE, 0);
1239 return 1;
1240 }
1241
1242 static void sst_shutdown(struct fb_info *info)
1243 {
1244 struct sstfb_par *par = info->par;
1245 struct pci_dev *dev = par->dev;
1246 struct pll_timing gfx_timings;
1247 int Fout;
1248
1249 /* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */
1250 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
1251 sst_set_bits(FBIINIT1, VIDEO_RESET | EN_BLANKING);
1252 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
1253 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
1254 sst_wait_idle();
1255 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1256 PCI_EN_INIT_WR | PCI_REMAP_DAC);
1257 /* set 20Mhz gfx clock */
1258 sst_calc_pll(20000, &Fout, &gfx_timings);
1259 par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
1260 /* TODO maybe shutdown the dac, vrefresh and so on... */
1261 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1262 PCI_EN_INIT_WR);
1263 sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | DIS_VGA_PASSTHROUGH);
1264 pci_write_config_dword(dev, PCI_VCLK_DISABLE,0);
1265 /* maybe keep fbiinit* and PCI_INIT_enable in the fb_info struct
1266 * from start ? */
1267 pci_write_config_dword(dev, PCI_INIT_ENABLE, 0);
1268
1269 }
1270
1271 /*
1272 * Interface to the world
1273 */
1274 static int sstfb_setup(char *options)
1275 {
1276 char *this_opt;
1277
1278 if (!options || !*options)
1279 return 0;
1280
1281 while ((this_opt = strsep(&options, ",")) != NULL) {
1282 if (!*this_opt) continue;
1283
1284 f_ddprintk("option %s\n", this_opt);
1285
1286 if (!strcmp(this_opt, "vganopass"))
1287 vgapass = 0;
1288 else if (!strcmp(this_opt, "vgapass"))
1289 vgapass = 1;
1290 else if (!strcmp(this_opt, "clipping"))
1291 clipping = 1;
1292 else if (!strcmp(this_opt, "noclipping"))
1293 clipping = 0;
1294 else if (!strcmp(this_opt, "fastpci"))
1295 slowpci = 0;
1296 else if (!strcmp(this_opt, "slowpci"))
1297 slowpci = 1;
1298 else if (!strncmp(this_opt, "mem:",4))
1299 mem = simple_strtoul (this_opt+4, NULL, 0);
1300 else if (!strncmp(this_opt, "gfxclk:",7))
1301 gfxclk = simple_strtoul (this_opt+7, NULL, 0);
1302 else
1303 mode_option = this_opt;
1304 }
1305 return 0;
1306 }
1307
1308
1309 static struct fb_ops sstfb_ops = {
1310 .owner = THIS_MODULE,
1311 .fb_check_var = sstfb_check_var,
1312 .fb_set_par = sstfb_set_par,
1313 .fb_setcolreg = sstfb_setcolreg,
1314 .fb_fillrect = cfb_fillrect, /* sstfb_fillrect */
1315 .fb_copyarea = cfb_copyarea, /* sstfb_copyarea */
1316 .fb_imageblit = cfb_imageblit,
1317 .fb_ioctl = sstfb_ioctl,
1318 };
1319
1320 static int sstfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1321 {
1322 struct fb_info *info;
1323 struct fb_fix_screeninfo *fix;
1324 struct sstfb_par *par;
1325 struct sst_spec *spec;
1326 int err;
1327
1328 /* Enable device in PCI config. */
1329 if ((err=pci_enable_device(pdev))) {
1330 printk(KERN_ERR "cannot enable device\n");
1331 return err;
1332 }
1333
1334 /* Allocate the fb and par structures. */
1335 info = framebuffer_alloc(sizeof(struct sstfb_par), &pdev->dev);
1336 if (!info)
1337 return -ENOMEM;
1338
1339 pci_set_drvdata(pdev, info);
1340
1341 par = info->par;
1342 fix = &info->fix;
1343
1344 par->type = id->driver_data;
1345 spec = &voodoo_spec[par->type];
1346 f_ddprintk("found device : %s\n", spec->name);
1347
1348 par->dev = pdev;
1349 par->revision = pdev->revision;
1350
1351 fix->mmio_start = pci_resource_start(pdev,0);
1352 fix->mmio_len = 0x400000;
1353 fix->smem_start = fix->mmio_start + 0x400000;
1354
1355 if (!request_mem_region(fix->mmio_start, fix->mmio_len, "sstfb MMIO")) {
1356 printk(KERN_ERR "sstfb: cannot reserve mmio memory\n");
1357 goto fail_mmio_mem;
1358 }
1359
1360 if (!request_mem_region(fix->smem_start, 0x400000,"sstfb FB")) {
1361 printk(KERN_ERR "sstfb: cannot reserve fb memory\n");
1362 goto fail_fb_mem;
1363 }
1364
1365 par->mmio_vbase = ioremap_nocache(fix->mmio_start,
1366 fix->mmio_len);
1367 if (!par->mmio_vbase) {
1368 printk(KERN_ERR "sstfb: cannot remap register area %#lx\n",
1369 fix->mmio_start);
1370 goto fail_mmio_remap;
1371 }
1372 info->screen_base = ioremap_nocache(fix->smem_start, 0x400000);
1373 if (!info->screen_base) {
1374 printk(KERN_ERR "sstfb: cannot remap framebuffer %#lx\n",
1375 fix->smem_start);
1376 goto fail_fb_remap;
1377 }
1378
1379 if (!sst_init(info, par)) {
1380 printk(KERN_ERR "sstfb: Init failed\n");
1381 goto fail;
1382 }
1383 sst_get_memsize(info, &fix->smem_len);
1384 strlcpy(fix->id, spec->name, sizeof(fix->id));
1385
1386 printk(KERN_INFO "%s (revision %d) with %s dac\n",
1387 fix->id, par->revision, par->dac_sw.name);
1388 printk(KERN_INFO "framebuffer at %#lx, mapped to 0x%p, size %dMB\n",
1389 fix->smem_start, info->screen_base,
1390 fix->smem_len >> 20);
1391
1392 f_ddprintk("regbase_virt: %#lx\n", par->mmio_vbase);
1393 f_ddprintk("membase_phys: %#lx\n", fix->smem_start);
1394 f_ddprintk("fbbase_virt: %p\n", info->screen_base);
1395
1396 info->flags = FBINFO_DEFAULT;
1397 info->fbops = &sstfb_ops;
1398 info->pseudo_palette = par->palette;
1399
1400 fix->type = FB_TYPE_PACKED_PIXELS;
1401 fix->visual = FB_VISUAL_TRUECOLOR;
1402 fix->accel = FB_ACCEL_NONE; /* FIXME */
1403 /*
1404 * According to the specs, the linelength must be of 1024 *pixels*
1405 * and the 24bpp mode is in fact a 32 bpp mode (and both are in
1406 * fact dithered to 16bit).
1407 */
1408 fix->line_length = 2048; /* default value, for 24 or 32bit: 4096 */
1409
1410 fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 16);
1411
1412 if (sstfb_check_var(&info->var, info)) {
1413 printk(KERN_ERR "sstfb: invalid video mode.\n");
1414 goto fail;
1415 }
1416
1417 if (sstfb_set_par(info)) {
1418 printk(KERN_ERR "sstfb: can't set default video mode.\n");
1419 goto fail;
1420 }
1421
1422 if (fb_alloc_cmap(&info->cmap, 256, 0)) {
1423 printk(KERN_ERR "sstfb: can't alloc cmap memory.\n");
1424 goto fail;
1425 }
1426
1427 /* register fb */
1428 info->device = &pdev->dev;
1429 if (register_framebuffer(info) < 0) {
1430 printk(KERN_ERR "sstfb: can't register framebuffer.\n");
1431 goto fail_register;
1432 }
1433
1434 sstfb_clear_screen(info);
1435
1436 if (device_create_file(info->dev, &device_attrs[0]))
1437 printk(KERN_WARNING "sstfb: can't create sysfs entry.\n");
1438
1439
1440 fb_info(info, "%s frame buffer device at 0x%p\n",
1441 fix->id, info->screen_base);
1442
1443 return 0;
1444
1445 fail_register:
1446 fb_dealloc_cmap(&info->cmap);
1447 fail:
1448 iounmap(info->screen_base);
1449 fail_fb_remap:
1450 iounmap(par->mmio_vbase);
1451 fail_mmio_remap:
1452 release_mem_region(fix->smem_start, 0x400000);
1453 fail_fb_mem:
1454 release_mem_region(fix->mmio_start, info->fix.mmio_len);
1455 fail_mmio_mem:
1456 framebuffer_release(info);
1457 return -ENXIO; /* no voodoo detected */
1458 }
1459
1460 static void sstfb_remove(struct pci_dev *pdev)
1461 {
1462 struct sstfb_par *par;
1463 struct fb_info *info;
1464
1465 info = pci_get_drvdata(pdev);
1466 par = info->par;
1467
1468 device_remove_file(info->dev, &device_attrs[0]);
1469 sst_shutdown(info);
1470 iounmap(info->screen_base);
1471 iounmap(par->mmio_vbase);
1472 release_mem_region(info->fix.smem_start, 0x400000);
1473 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1474 fb_dealloc_cmap(&info->cmap);
1475 unregister_framebuffer(info);
1476 framebuffer_release(info);
1477 }
1478
1479
1480 static const struct pci_device_id sstfb_id_tbl[] = {
1481 { PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO ),
1482 .driver_data = ID_VOODOO1, },
1483 { PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2),
1484 .driver_data = ID_VOODOO2, },
1485 { 0 },
1486 };
1487
1488 static struct pci_driver sstfb_driver = {
1489 .name = "sstfb",
1490 .id_table = sstfb_id_tbl,
1491 .probe = sstfb_probe,
1492 .remove = sstfb_remove,
1493 };
1494
1495
1496 static int sstfb_init(void)
1497 {
1498 char *option = NULL;
1499
1500 if (fb_get_options("sstfb", &option))
1501 return -ENODEV;
1502 sstfb_setup(option);
1503
1504 return pci_register_driver(&sstfb_driver);
1505 }
1506
1507 static void sstfb_exit(void)
1508 {
1509 pci_unregister_driver(&sstfb_driver);
1510 }
1511
1512
1513 module_init(sstfb_init);
1514 module_exit(sstfb_exit);
1515
1516 MODULE_AUTHOR("(c) 2000,2002 Ghozlane Toumi <gtoumi@laposte.net>");
1517 MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards");
1518 MODULE_LICENSE("GPL");
1519
1520 module_param(mem, int, 0);
1521 MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)");
1522 module_param(vgapass, bool, 0);
1523 MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)");
1524 module_param(clipping, bool, 0);
1525 MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)");
1526 module_param(gfxclk, int, 0);
1527 MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)");
1528 module_param(slowpci, bool, 0);
1529 MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)");
1530 module_param(mode_option, charp, 0);
1531 MODULE_PARM_DESC(mode_option, "Initial video mode (default=" DEFAULT_VIDEO_MODE ")");
1532
Linux with added FPC-III support