Linux 4.16.11
[linux/fpc-iii.git] / sound / firewire / dice / dice-stream.c
blob928a255bfc351406058b1c2bd8a43d785f63ef97
1 /*
2 * dice_stream.c - a part of driver for DICE based devices
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 * Copyright (c) 2014 Takashi Sakamoto <o-takashi@sakamocchi.jp>
7 * Licensed under the terms of the GNU General Public License, version 2.
8 */
10 #include "dice.h"
12 #define CALLBACK_TIMEOUT 200
13 #define NOTIFICATION_TIMEOUT_MS (2 * MSEC_PER_SEC)
15 struct reg_params {
16 unsigned int count;
17 unsigned int size;
20 const unsigned int snd_dice_rates[SND_DICE_RATES_COUNT] = {
21 /* mode 0 */
22 [0] = 32000,
23 [1] = 44100,
24 [2] = 48000,
25 /* mode 1 */
26 [3] = 88200,
27 [4] = 96000,
28 /* mode 2 */
29 [5] = 176400,
30 [6] = 192000,
34 * This operation has an effect to synchronize GLOBAL_STATUS/GLOBAL_SAMPLE_RATE
35 * to GLOBAL_STATUS. Especially, just after powering on, these are different.
37 static int ensure_phase_lock(struct snd_dice *dice)
39 __be32 reg, nominal;
40 int err;
42 err = snd_dice_transaction_read_global(dice, GLOBAL_CLOCK_SELECT,
43 &reg, sizeof(reg));
44 if (err < 0)
45 return err;
47 if (completion_done(&dice->clock_accepted))
48 reinit_completion(&dice->clock_accepted);
50 err = snd_dice_transaction_write_global(dice, GLOBAL_CLOCK_SELECT,
51 &reg, sizeof(reg));
52 if (err < 0)
53 return err;
55 if (wait_for_completion_timeout(&dice->clock_accepted,
56 msecs_to_jiffies(NOTIFICATION_TIMEOUT_MS)) == 0) {
58 * Old versions of Dice firmware transfer no notification when
59 * the same clock status as current one is set. In this case,
60 * just check current clock status.
62 err = snd_dice_transaction_read_global(dice, GLOBAL_STATUS,
63 &nominal, sizeof(nominal));
64 if (err < 0)
65 return err;
66 if (!(be32_to_cpu(nominal) & STATUS_SOURCE_LOCKED))
67 return -ETIMEDOUT;
70 return 0;
73 static int get_register_params(struct snd_dice *dice,
74 struct reg_params *tx_params,
75 struct reg_params *rx_params)
77 __be32 reg[2];
78 int err;
80 err = snd_dice_transaction_read_tx(dice, TX_NUMBER, reg, sizeof(reg));
81 if (err < 0)
82 return err;
83 tx_params->count =
84 min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS);
85 tx_params->size = be32_to_cpu(reg[1]) * 4;
87 err = snd_dice_transaction_read_rx(dice, RX_NUMBER, reg, sizeof(reg));
88 if (err < 0)
89 return err;
90 rx_params->count =
91 min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS);
92 rx_params->size = be32_to_cpu(reg[1]) * 4;
94 return 0;
97 static void release_resources(struct snd_dice *dice)
99 unsigned int i;
101 for (i = 0; i < MAX_STREAMS; i++) {
102 if (amdtp_stream_running(&dice->tx_stream[i])) {
103 amdtp_stream_pcm_abort(&dice->tx_stream[i]);
104 amdtp_stream_stop(&dice->tx_stream[i]);
106 if (amdtp_stream_running(&dice->rx_stream[i])) {
107 amdtp_stream_pcm_abort(&dice->rx_stream[i]);
108 amdtp_stream_stop(&dice->rx_stream[i]);
111 fw_iso_resources_free(&dice->tx_resources[i]);
112 fw_iso_resources_free(&dice->rx_resources[i]);
116 static void stop_streams(struct snd_dice *dice, enum amdtp_stream_direction dir,
117 struct reg_params *params)
119 __be32 reg;
120 unsigned int i;
122 for (i = 0; i < params->count; i++) {
123 reg = cpu_to_be32((u32)-1);
124 if (dir == AMDTP_IN_STREAM) {
125 snd_dice_transaction_write_tx(dice,
126 params->size * i + TX_ISOCHRONOUS,
127 &reg, sizeof(reg));
128 } else {
129 snd_dice_transaction_write_rx(dice,
130 params->size * i + RX_ISOCHRONOUS,
131 &reg, sizeof(reg));
136 static int keep_resources(struct snd_dice *dice,
137 enum amdtp_stream_direction dir, unsigned int index,
138 unsigned int rate, unsigned int pcm_chs,
139 unsigned int midi_ports)
141 struct amdtp_stream *stream;
142 struct fw_iso_resources *resources;
143 bool double_pcm_frames;
144 unsigned int i;
145 int err;
147 if (dir == AMDTP_IN_STREAM) {
148 stream = &dice->tx_stream[index];
149 resources = &dice->tx_resources[index];
150 } else {
151 stream = &dice->rx_stream[index];
152 resources = &dice->rx_resources[index];
156 * At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in
157 * one data block of AMDTP packet. Thus sampling transfer frequency is
158 * a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are
159 * transferred on AMDTP packets at 96 kHz. Two successive samples of a
160 * channel are stored consecutively in the packet. This quirk is called
161 * as 'Dual Wire'.
162 * For this quirk, blocking mode is required and PCM buffer size should
163 * be aligned to SYT_INTERVAL.
165 double_pcm_frames = rate > 96000;
166 if (double_pcm_frames) {
167 rate /= 2;
168 pcm_chs *= 2;
171 err = amdtp_am824_set_parameters(stream, rate, pcm_chs, midi_ports,
172 double_pcm_frames);
173 if (err < 0)
174 return err;
176 if (double_pcm_frames) {
177 pcm_chs /= 2;
179 for (i = 0; i < pcm_chs; i++) {
180 amdtp_am824_set_pcm_position(stream, i, i * 2);
181 amdtp_am824_set_pcm_position(stream, i + pcm_chs,
182 i * 2 + 1);
186 return fw_iso_resources_allocate(resources,
187 amdtp_stream_get_max_payload(stream),
188 fw_parent_device(dice->unit)->max_speed);
191 static int start_streams(struct snd_dice *dice, enum amdtp_stream_direction dir,
192 unsigned int rate, struct reg_params *params)
194 __be32 reg[2];
195 unsigned int i, pcm_chs, midi_ports;
196 struct amdtp_stream *streams;
197 struct fw_iso_resources *resources;
198 struct fw_device *fw_dev = fw_parent_device(dice->unit);
199 int err = 0;
201 if (dir == AMDTP_IN_STREAM) {
202 streams = dice->tx_stream;
203 resources = dice->tx_resources;
204 } else {
205 streams = dice->rx_stream;
206 resources = dice->rx_resources;
209 for (i = 0; i < params->count; i++) {
210 if (dir == AMDTP_IN_STREAM) {
211 err = snd_dice_transaction_read_tx(dice,
212 params->size * i + TX_NUMBER_AUDIO,
213 reg, sizeof(reg));
214 } else {
215 err = snd_dice_transaction_read_rx(dice,
216 params->size * i + RX_NUMBER_AUDIO,
217 reg, sizeof(reg));
219 if (err < 0)
220 return err;
221 pcm_chs = be32_to_cpu(reg[0]);
222 midi_ports = be32_to_cpu(reg[1]);
224 err = keep_resources(dice, dir, i, rate, pcm_chs, midi_ports);
225 if (err < 0)
226 return err;
228 reg[0] = cpu_to_be32(resources[i].channel);
229 if (dir == AMDTP_IN_STREAM) {
230 err = snd_dice_transaction_write_tx(dice,
231 params->size * i + TX_ISOCHRONOUS,
232 reg, sizeof(reg[0]));
233 } else {
234 err = snd_dice_transaction_write_rx(dice,
235 params->size * i + RX_ISOCHRONOUS,
236 reg, sizeof(reg[0]));
238 if (err < 0)
239 return err;
241 if (dir == AMDTP_IN_STREAM) {
242 reg[0] = cpu_to_be32(fw_dev->max_speed);
243 err = snd_dice_transaction_write_tx(dice,
244 params->size * i + TX_SPEED,
245 reg, sizeof(reg[0]));
246 if (err < 0)
247 return err;
250 err = amdtp_stream_start(&streams[i], resources[i].channel,
251 fw_dev->max_speed);
252 if (err < 0)
253 return err;
256 return err;
260 * MEMO: After this function, there're two states of streams:
261 * - None streams are running.
262 * - All streams are running.
264 int snd_dice_stream_start_duplex(struct snd_dice *dice, unsigned int rate)
266 unsigned int curr_rate;
267 unsigned int i;
268 struct reg_params tx_params, rx_params;
269 bool need_to_start;
270 int err;
272 if (dice->substreams_counter == 0)
273 return -EIO;
275 err = get_register_params(dice, &tx_params, &rx_params);
276 if (err < 0)
277 return err;
279 err = snd_dice_transaction_get_rate(dice, &curr_rate);
280 if (err < 0) {
281 dev_err(&dice->unit->device,
282 "fail to get sampling rate\n");
283 return err;
285 if (rate == 0)
286 rate = curr_rate;
287 if (rate != curr_rate)
288 return -EINVAL;
290 /* Judge to need to restart streams. */
291 for (i = 0; i < MAX_STREAMS; i++) {
292 if (i < tx_params.count) {
293 if (amdtp_streaming_error(&dice->tx_stream[i]) ||
294 !amdtp_stream_running(&dice->tx_stream[i]))
295 break;
297 if (i < rx_params.count) {
298 if (amdtp_streaming_error(&dice->rx_stream[i]) ||
299 !amdtp_stream_running(&dice->rx_stream[i]))
300 break;
303 need_to_start = (i < MAX_STREAMS);
305 if (need_to_start) {
306 /* Stop transmission. */
307 snd_dice_transaction_clear_enable(dice);
308 stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
309 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
310 release_resources(dice);
312 err = ensure_phase_lock(dice);
313 if (err < 0) {
314 dev_err(&dice->unit->device,
315 "fail to ensure phase lock\n");
316 return err;
319 /* Start both streams. */
320 err = start_streams(dice, AMDTP_IN_STREAM, rate, &tx_params);
321 if (err < 0)
322 goto error;
323 err = start_streams(dice, AMDTP_OUT_STREAM, rate, &rx_params);
324 if (err < 0)
325 goto error;
327 err = snd_dice_transaction_set_enable(dice);
328 if (err < 0) {
329 dev_err(&dice->unit->device,
330 "fail to enable interface\n");
331 goto error;
334 for (i = 0; i < MAX_STREAMS; i++) {
335 if ((i < tx_params.count &&
336 !amdtp_stream_wait_callback(&dice->tx_stream[i],
337 CALLBACK_TIMEOUT)) ||
338 (i < rx_params.count &&
339 !amdtp_stream_wait_callback(&dice->rx_stream[i],
340 CALLBACK_TIMEOUT))) {
341 err = -ETIMEDOUT;
342 goto error;
347 return err;
348 error:
349 snd_dice_transaction_clear_enable(dice);
350 stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
351 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
352 release_resources(dice);
353 return err;
357 * MEMO: After this function, there're two states of streams:
358 * - None streams are running.
359 * - All streams are running.
361 void snd_dice_stream_stop_duplex(struct snd_dice *dice)
363 struct reg_params tx_params, rx_params;
365 if (dice->substreams_counter > 0)
366 return;
368 snd_dice_transaction_clear_enable(dice);
370 if (get_register_params(dice, &tx_params, &rx_params) == 0) {
371 stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
372 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
375 release_resources(dice);
378 static int init_stream(struct snd_dice *dice, enum amdtp_stream_direction dir,
379 unsigned int index)
381 struct amdtp_stream *stream;
382 struct fw_iso_resources *resources;
383 int err;
385 if (dir == AMDTP_IN_STREAM) {
386 stream = &dice->tx_stream[index];
387 resources = &dice->tx_resources[index];
388 } else {
389 stream = &dice->rx_stream[index];
390 resources = &dice->rx_resources[index];
393 err = fw_iso_resources_init(resources, dice->unit);
394 if (err < 0)
395 goto end;
396 resources->channels_mask = 0x00000000ffffffffuLL;
398 err = amdtp_am824_init(stream, dice->unit, dir, CIP_BLOCKING);
399 if (err < 0) {
400 amdtp_stream_destroy(stream);
401 fw_iso_resources_destroy(resources);
403 end:
404 return err;
408 * This function should be called before starting streams or after stopping
409 * streams.
411 static void destroy_stream(struct snd_dice *dice,
412 enum amdtp_stream_direction dir,
413 unsigned int index)
415 struct amdtp_stream *stream;
416 struct fw_iso_resources *resources;
418 if (dir == AMDTP_IN_STREAM) {
419 stream = &dice->tx_stream[index];
420 resources = &dice->tx_resources[index];
421 } else {
422 stream = &dice->rx_stream[index];
423 resources = &dice->rx_resources[index];
426 amdtp_stream_destroy(stream);
427 fw_iso_resources_destroy(resources);
430 int snd_dice_stream_init_duplex(struct snd_dice *dice)
432 int i, err;
434 for (i = 0; i < MAX_STREAMS; i++) {
435 err = init_stream(dice, AMDTP_IN_STREAM, i);
436 if (err < 0) {
437 for (; i >= 0; i--)
438 destroy_stream(dice, AMDTP_IN_STREAM, i);
439 goto end;
443 for (i = 0; i < MAX_STREAMS; i++) {
444 err = init_stream(dice, AMDTP_OUT_STREAM, i);
445 if (err < 0) {
446 for (; i >= 0; i--)
447 destroy_stream(dice, AMDTP_OUT_STREAM, i);
448 for (i = 0; i < MAX_STREAMS; i++)
449 destroy_stream(dice, AMDTP_IN_STREAM, i);
450 break;
453 end:
454 return err;
457 void snd_dice_stream_destroy_duplex(struct snd_dice *dice)
459 unsigned int i;
461 for (i = 0; i < MAX_STREAMS; i++) {
462 destroy_stream(dice, AMDTP_IN_STREAM, i);
463 destroy_stream(dice, AMDTP_OUT_STREAM, i);
467 void snd_dice_stream_update_duplex(struct snd_dice *dice)
469 struct reg_params tx_params, rx_params;
472 * On a bus reset, the DICE firmware disables streaming and then goes
473 * off contemplating its own navel for hundreds of milliseconds before
474 * it can react to any of our attempts to reenable streaming. This
475 * means that we lose synchronization anyway, so we force our streams
476 * to stop so that the application can restart them in an orderly
477 * manner.
479 dice->global_enabled = false;
481 if (get_register_params(dice, &tx_params, &rx_params) == 0) {
482 stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
483 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
487 static void dice_lock_changed(struct snd_dice *dice)
489 dice->dev_lock_changed = true;
490 wake_up(&dice->hwdep_wait);
493 int snd_dice_stream_lock_try(struct snd_dice *dice)
495 int err;
497 spin_lock_irq(&dice->lock);
499 if (dice->dev_lock_count < 0) {
500 err = -EBUSY;
501 goto out;
504 if (dice->dev_lock_count++ == 0)
505 dice_lock_changed(dice);
506 err = 0;
507 out:
508 spin_unlock_irq(&dice->lock);
509 return err;
512 void snd_dice_stream_lock_release(struct snd_dice *dice)
514 spin_lock_irq(&dice->lock);
516 if (WARN_ON(dice->dev_lock_count <= 0))
517 goto out;
519 if (--dice->dev_lock_count == 0)
520 dice_lock_changed(dice);
521 out:
522 spin_unlock_irq(&dice->lock);