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Linux 4.16.11
[linux/fpc-iii.git] / sound / soc / fsl / fsl_esai.c
blob81268760b7a9d5435abc43ad17917fcd20908b05
1 /*
2 * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
3 *
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11 #include <linux/clk.h>
12 #include <linux/dmaengine.h>
13 #include <linux/module.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
18
19 #include "fsl_esai.h"
20 #include "imx-pcm.h"
21
22 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
23 SNDRV_PCM_FMTBIT_S16_LE | \
24 SNDRV_PCM_FMTBIT_S20_3LE | \
25 SNDRV_PCM_FMTBIT_S24_LE)
26
27 /**
28 * fsl_esai: ESAI private data
29 *
30 * @dma_params_rx: DMA parameters for receive channel
31 * @dma_params_tx: DMA parameters for transmit channel
32 * @pdev: platform device pointer
33 * @regmap: regmap handler
34 * @coreclk: clock source to access register
35 * @extalclk: esai clock source to derive HCK, SCK and FS
36 * @fsysclk: system clock source to derive HCK, SCK and FS
37 * @spbaclk: SPBA clock (optional, depending on SoC design)
38 * @fifo_depth: depth of tx/rx FIFO
39 * @slot_width: width of each DAI slot
40 * @slots: number of slots
41 * @hck_rate: clock rate of desired HCKx clock
42 * @sck_rate: clock rate of desired SCKx clock
43 * @hck_dir: the direction of HCKx pads
44 * @sck_div: if using PSR/PM dividers for SCKx clock
45 * @slave_mode: if fully using DAI slave mode
46 * @synchronous: if using tx/rx synchronous mode
47 * @name: driver name
48 */
49 struct fsl_esai {
50 struct snd_dmaengine_dai_dma_data dma_params_rx;
51 struct snd_dmaengine_dai_dma_data dma_params_tx;
52 struct platform_device *pdev;
53 struct regmap *regmap;
54 struct clk *coreclk;
55 struct clk *extalclk;
56 struct clk *fsysclk;
57 struct clk *spbaclk;
58 u32 fifo_depth;
59 u32 slot_width;
60 u32 slots;
61 u32 hck_rate[2];
62 u32 sck_rate[2];
63 bool hck_dir[2];
64 bool sck_div[2];
65 bool slave_mode;
66 bool synchronous;
67 char name[32];
68 };
69
70 static irqreturn_t esai_isr(int irq, void *devid)
71 {
72 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
73 struct platform_device *pdev = esai_priv->pdev;
74 u32 esr;
75
76 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
77
78 if (esr & ESAI_ESR_TINIT_MASK)
79 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n");
80
81 if (esr & ESAI_ESR_RFF_MASK)
82 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
83
84 if (esr & ESAI_ESR_TFE_MASK)
85 dev_warn(&pdev->dev, "isr: Transmission underrun\n");
86
87 if (esr & ESAI_ESR_TLS_MASK)
88 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
89
90 if (esr & ESAI_ESR_TDE_MASK)
91 dev_dbg(&pdev->dev, "isr: Transmission data exception\n");
92
93 if (esr & ESAI_ESR_TED_MASK)
94 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
95
96 if (esr & ESAI_ESR_TD_MASK)
97 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
98
99 if (esr & ESAI_ESR_RLS_MASK)
100 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
101
102 if (esr & ESAI_ESR_RDE_MASK)
103 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
104
105 if (esr & ESAI_ESR_RED_MASK)
106 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
107
108 if (esr & ESAI_ESR_RD_MASK)
109 dev_dbg(&pdev->dev, "isr: Receiving data\n");
110
111 return IRQ_HANDLED;
112 }
113
114 /**
115 * This function is used to calculate the divisors of psr, pm, fp and it is
116 * supposed to be called in set_dai_sysclk() and set_bclk().
117 *
118 * @ratio: desired overall ratio for the paticipating dividers
119 * @usefp: for HCK setting, there is no need to set fp divider
120 * @fp: bypass other dividers by setting fp directly if fp != 0
121 * @tx: current setting is for playback or capture
122 */
123 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
124 bool usefp, u32 fp)
125 {
126 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
127 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
128
129 maxfp = usefp ? 16 : 1;
130
131 if (usefp && fp)
132 goto out_fp;
133
134 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
135 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
136 2 * 8 * 256 * maxfp);
137 return -EINVAL;
138 } else if (ratio % 2) {
139 dev_err(dai->dev, "the raio must be even if using upper divider\n");
140 return -EINVAL;
141 }
142
143 ratio /= 2;
144
145 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
146
147 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
148 if (ratio <= 256) {
149 pm = ratio;
150 fp = 1;
151 goto out;
152 }
153
154 /* Set the max fluctuation -- 0.1% of the max devisor */
155 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
156
157 /* Find the best value for PM */
158 for (i = 1; i <= 256; i++) {
159 for (j = 1; j <= maxfp; j++) {
160 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
161 prod = (psr ? 1 : 8) * i * j;
162
163 if (prod == ratio)
164 sub = 0;
165 else if (prod / ratio == 1)
166 sub = prod - ratio;
167 else if (ratio / prod == 1)
168 sub = ratio - prod;
169 else
170 continue;
171
172 /* Calculate the fraction */
173 sub = sub * 1000 / ratio;
174 if (sub < savesub) {
175 savesub = sub;
176 pm = i;
177 fp = j;
178 }
179
180 /* We are lucky */
181 if (savesub == 0)
182 goto out;
183 }
184 }
185
186 if (pm == 999) {
187 dev_err(dai->dev, "failed to calculate proper divisors\n");
188 return -EINVAL;
189 }
190
191 out:
192 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
193 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
194 psr | ESAI_xCCR_xPM(pm));
195
196 out_fp:
197 /* Bypass fp if not being required */
198 if (maxfp <= 1)
199 return 0;
200
201 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
202 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
203
204 return 0;
205 }
206
207 /**
208 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
209 *
210 * @Parameters:
211 * clk_id: The clock source of HCKT/HCKR
212 * (Input from outside; output from inside, FSYS or EXTAL)
213 * freq: The required clock rate of HCKT/HCKR
214 * dir: The clock direction of HCKT/HCKR
215 *
216 * Note: If the direction is input, we do not care about clk_id.
217 */
218 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
219 unsigned int freq, int dir)
220 {
221 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
222 struct clk *clksrc = esai_priv->extalclk;
223 bool tx = clk_id <= ESAI_HCKT_EXTAL;
224 bool in = dir == SND_SOC_CLOCK_IN;
225 u32 ratio, ecr = 0;
226 unsigned long clk_rate;
227 int ret;
228
229 /* Bypass divider settings if the requirement doesn't change */
230 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
231 return 0;
232
233 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
234 esai_priv->sck_div[tx] = true;
235
236 /* Set the direction of HCKT/HCKR pins */
237 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
238 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
239
240 if (in)
241 goto out;
242
243 switch (clk_id) {
244 case ESAI_HCKT_FSYS:
245 case ESAI_HCKR_FSYS:
246 clksrc = esai_priv->fsysclk;
247 break;
248 case ESAI_HCKT_EXTAL:
249 ecr |= ESAI_ECR_ETI;
250 case ESAI_HCKR_EXTAL:
251 ecr |= ESAI_ECR_ERI;
252 break;
253 default:
254 return -EINVAL;
255 }
256
257 if (IS_ERR(clksrc)) {
258 dev_err(dai->dev, "no assigned %s clock\n",
259 clk_id % 2 ? "extal" : "fsys");
260 return PTR_ERR(clksrc);
261 }
262 clk_rate = clk_get_rate(clksrc);
263
264 ratio = clk_rate / freq;
265 if (ratio * freq > clk_rate)
266 ret = ratio * freq - clk_rate;
267 else if (ratio * freq < clk_rate)
268 ret = clk_rate - ratio * freq;
269 else
270 ret = 0;
271
272 /* Block if clock source can not be divided into the required rate */
273 if (ret != 0 && clk_rate / ret < 1000) {
274 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
275 tx ? 'T' : 'R');
276 return -EINVAL;
277 }
278
279 /* Only EXTAL source can be output directly without using PSR and PM */
280 if (ratio == 1 && clksrc == esai_priv->extalclk) {
281 /* Bypass all the dividers if not being needed */
282 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
283 goto out;
284 } else if (ratio < 2) {
285 /* The ratio should be no less than 2 if using other sources */
286 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
287 tx ? 'T' : 'R');
288 return -EINVAL;
289 }
290
291 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
292 if (ret)
293 return ret;
294
295 esai_priv->sck_div[tx] = false;
296
297 out:
298 esai_priv->hck_dir[tx] = dir;
299 esai_priv->hck_rate[tx] = freq;
300
301 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
302 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
303 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
304
305 return 0;
306 }
307
308 /**
309 * This function configures the related dividers according to the bclk rate
310 */
311 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
312 {
313 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
314 u32 hck_rate = esai_priv->hck_rate[tx];
315 u32 sub, ratio = hck_rate / freq;
316 int ret;
317
318 /* Don't apply for fully slave mode or unchanged bclk */
319 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
320 return 0;
321
322 if (ratio * freq > hck_rate)
323 sub = ratio * freq - hck_rate;
324 else if (ratio * freq < hck_rate)
325 sub = hck_rate - ratio * freq;
326 else
327 sub = 0;
328
329 /* Block if clock source can not be divided into the required rate */
330 if (sub != 0 && hck_rate / sub < 1000) {
331 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
332 tx ? 'T' : 'R');
333 return -EINVAL;
334 }
335
336 /* The ratio should be contented by FP alone if bypassing PM and PSR */
337 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
338 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
339 return -EINVAL;
340 }
341
342 ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
343 esai_priv->sck_div[tx] ? 0 : ratio);
344 if (ret)
345 return ret;
346
347 /* Save current bclk rate */
348 esai_priv->sck_rate[tx] = freq;
349
350 return 0;
351 }
352
353 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
354 u32 rx_mask, int slots, int slot_width)
355 {
356 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
357
358 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
359 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
360
361 regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMA,
362 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(tx_mask));
363 regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMB,
364 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(tx_mask));
365
366 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
367 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
368
369 regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMA,
370 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(rx_mask));
371 regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMB,
372 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(rx_mask));
373
374 esai_priv->slot_width = slot_width;
375 esai_priv->slots = slots;
376
377 return 0;
378 }
379
380 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
381 {
382 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
383 u32 xcr = 0, xccr = 0, mask;
384
385 /* DAI mode */
386 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
387 case SND_SOC_DAIFMT_I2S:
388 /* Data on rising edge of bclk, frame low, 1clk before data */
389 xcr |= ESAI_xCR_xFSR;
390 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
391 break;
392 case SND_SOC_DAIFMT_LEFT_J:
393 /* Data on rising edge of bclk, frame high */
394 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
395 break;
396 case SND_SOC_DAIFMT_RIGHT_J:
397 /* Data on rising edge of bclk, frame high, right aligned */
398 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCR_xWA;
399 break;
400 case SND_SOC_DAIFMT_DSP_A:
401 /* Data on rising edge of bclk, frame high, 1clk before data */
402 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
403 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
404 break;
405 case SND_SOC_DAIFMT_DSP_B:
406 /* Data on rising edge of bclk, frame high */
407 xcr |= ESAI_xCR_xFSL;
408 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
409 break;
410 default:
411 return -EINVAL;
412 }
413
414 /* DAI clock inversion */
415 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
416 case SND_SOC_DAIFMT_NB_NF:
417 /* Nothing to do for both normal cases */
418 break;
419 case SND_SOC_DAIFMT_IB_NF:
420 /* Invert bit clock */
421 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
422 break;
423 case SND_SOC_DAIFMT_NB_IF:
424 /* Invert frame clock */
425 xccr ^= ESAI_xCCR_xFSP;
426 break;
427 case SND_SOC_DAIFMT_IB_IF:
428 /* Invert both clocks */
429 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
430 break;
431 default:
432 return -EINVAL;
433 }
434
435 esai_priv->slave_mode = false;
436
437 /* DAI clock master masks */
438 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
439 case SND_SOC_DAIFMT_CBM_CFM:
440 esai_priv->slave_mode = true;
441 break;
442 case SND_SOC_DAIFMT_CBS_CFM:
443 xccr |= ESAI_xCCR_xCKD;
444 break;
445 case SND_SOC_DAIFMT_CBM_CFS:
446 xccr |= ESAI_xCCR_xFSD;
447 break;
448 case SND_SOC_DAIFMT_CBS_CFS:
449 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
450 break;
451 default:
452 return -EINVAL;
453 }
454
455 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR;
456 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
457 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
458
459 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
460 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD | ESAI_xCR_xWA;
461 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
462 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
463
464 return 0;
465 }
466
467 static int fsl_esai_startup(struct snd_pcm_substream *substream,
468 struct snd_soc_dai *dai)
469 {
470 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
471 int ret;
472
473 /*
474 * Some platforms might use the same bit to gate all three or two of
475 * clocks, so keep all clocks open/close at the same time for safety
476 */
477 ret = clk_prepare_enable(esai_priv->coreclk);
478 if (ret)
479 return ret;
480 if (!IS_ERR(esai_priv->spbaclk)) {
481 ret = clk_prepare_enable(esai_priv->spbaclk);
482 if (ret)
483 goto err_spbaclk;
484 }
485 if (!IS_ERR(esai_priv->extalclk)) {
486 ret = clk_prepare_enable(esai_priv->extalclk);
487 if (ret)
488 goto err_extalck;
489 }
490 if (!IS_ERR(esai_priv->fsysclk)) {
491 ret = clk_prepare_enable(esai_priv->fsysclk);
492 if (ret)
493 goto err_fsysclk;
494 }
495
496 if (!dai->active) {
497 /* Set synchronous mode */
498 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
499 ESAI_SAICR_SYNC, esai_priv->synchronous ?
500 ESAI_SAICR_SYNC : 0);
501
502 /* Set a default slot number -- 2 */
503 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
504 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
505 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
506 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
507 }
508
509 return 0;
510
511 err_fsysclk:
512 if (!IS_ERR(esai_priv->extalclk))
513 clk_disable_unprepare(esai_priv->extalclk);
514 err_extalck:
515 if (!IS_ERR(esai_priv->spbaclk))
516 clk_disable_unprepare(esai_priv->spbaclk);
517 err_spbaclk:
518 clk_disable_unprepare(esai_priv->coreclk);
519
520 return ret;
521 }
522
523 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
524 struct snd_pcm_hw_params *params,
525 struct snd_soc_dai *dai)
526 {
527 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
528 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
529 u32 width = params_width(params);
530 u32 channels = params_channels(params);
531 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
532 u32 slot_width = width;
533 u32 bclk, mask, val;
534 int ret;
535
536 /* Override slot_width if being specifically set */
537 if (esai_priv->slot_width)
538 slot_width = esai_priv->slot_width;
539
540 bclk = params_rate(params) * slot_width * esai_priv->slots;
541
542 ret = fsl_esai_set_bclk(dai, tx, bclk);
543 if (ret)
544 return ret;
545
546 /* Use Normal mode to support monaural audio */
547 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
548 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
549 ESAI_xCR_xMOD_NETWORK : 0);
550
551 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
552 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
553
554 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
555 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
556 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
557 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
558
559 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
560
561 mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
562 val = ESAI_xCR_xSWS(slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
563
564 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
565
566 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
567 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
568 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
569 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
570 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
571 return 0;
572 }
573
574 static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
575 struct snd_soc_dai *dai)
576 {
577 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
578
579 if (!IS_ERR(esai_priv->fsysclk))
580 clk_disable_unprepare(esai_priv->fsysclk);
581 if (!IS_ERR(esai_priv->extalclk))
582 clk_disable_unprepare(esai_priv->extalclk);
583 if (!IS_ERR(esai_priv->spbaclk))
584 clk_disable_unprepare(esai_priv->spbaclk);
585 clk_disable_unprepare(esai_priv->coreclk);
586 }
587
588 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
589 struct snd_soc_dai *dai)
590 {
591 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
592 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
593 u8 i, channels = substream->runtime->channels;
594 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
595
596 switch (cmd) {
597 case SNDRV_PCM_TRIGGER_START:
598 case SNDRV_PCM_TRIGGER_RESUME:
599 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
600 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
601 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
602
603 /* Write initial words reqiured by ESAI as normal procedure */
604 for (i = 0; tx && i < channels; i++)
605 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
606
607 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
608 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
609 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
610 break;
611 case SNDRV_PCM_TRIGGER_SUSPEND:
612 case SNDRV_PCM_TRIGGER_STOP:
613 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
614 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
615 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
616
617 /* Disable and reset FIFO */
618 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
619 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
620 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
621 ESAI_xFCR_xFR, 0);
622 break;
623 default:
624 return -EINVAL;
625 }
626
627 return 0;
628 }
629
630 static const struct snd_soc_dai_ops fsl_esai_dai_ops = {
631 .startup = fsl_esai_startup,
632 .shutdown = fsl_esai_shutdown,
633 .trigger = fsl_esai_trigger,
634 .hw_params = fsl_esai_hw_params,
635 .set_sysclk = fsl_esai_set_dai_sysclk,
636 .set_fmt = fsl_esai_set_dai_fmt,
637 .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
638 };
639
640 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
641 {
642 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
643
644 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
645 &esai_priv->dma_params_rx);
646
647 return 0;
648 }
649
650 static struct snd_soc_dai_driver fsl_esai_dai = {
651 .probe = fsl_esai_dai_probe,
652 .playback = {
653 .stream_name = "CPU-Playback",
654 .channels_min = 1,
655 .channels_max = 12,
656 .rates = SNDRV_PCM_RATE_8000_192000,
657 .formats = FSL_ESAI_FORMATS,
658 },
659 .capture = {
660 .stream_name = "CPU-Capture",
661 .channels_min = 1,
662 .channels_max = 8,
663 .rates = SNDRV_PCM_RATE_8000_192000,
664 .formats = FSL_ESAI_FORMATS,
665 },
666 .ops = &fsl_esai_dai_ops,
667 };
668
669 static const struct snd_soc_component_driver fsl_esai_component = {
670 .name = "fsl-esai",
671 };
672
673 static const struct reg_default fsl_esai_reg_defaults[] = {
674 {REG_ESAI_ETDR, 0x00000000},
675 {REG_ESAI_ECR, 0x00000000},
676 {REG_ESAI_TFCR, 0x00000000},
677 {REG_ESAI_RFCR, 0x00000000},
678 {REG_ESAI_TX0, 0x00000000},
679 {REG_ESAI_TX1, 0x00000000},
680 {REG_ESAI_TX2, 0x00000000},
681 {REG_ESAI_TX3, 0x00000000},
682 {REG_ESAI_TX4, 0x00000000},
683 {REG_ESAI_TX5, 0x00000000},
684 {REG_ESAI_TSR, 0x00000000},
685 {REG_ESAI_SAICR, 0x00000000},
686 {REG_ESAI_TCR, 0x00000000},
687 {REG_ESAI_TCCR, 0x00000000},
688 {REG_ESAI_RCR, 0x00000000},
689 {REG_ESAI_RCCR, 0x00000000},
690 {REG_ESAI_TSMA, 0x0000ffff},
691 {REG_ESAI_TSMB, 0x0000ffff},
692 {REG_ESAI_RSMA, 0x0000ffff},
693 {REG_ESAI_RSMB, 0x0000ffff},
694 {REG_ESAI_PRRC, 0x00000000},
695 {REG_ESAI_PCRC, 0x00000000},
696 };
697
698 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
699 {
700 switch (reg) {
701 case REG_ESAI_ERDR:
702 case REG_ESAI_ECR:
703 case REG_ESAI_ESR:
704 case REG_ESAI_TFCR:
705 case REG_ESAI_TFSR:
706 case REG_ESAI_RFCR:
707 case REG_ESAI_RFSR:
708 case REG_ESAI_RX0:
709 case REG_ESAI_RX1:
710 case REG_ESAI_RX2:
711 case REG_ESAI_RX3:
712 case REG_ESAI_SAISR:
713 case REG_ESAI_SAICR:
714 case REG_ESAI_TCR:
715 case REG_ESAI_TCCR:
716 case REG_ESAI_RCR:
717 case REG_ESAI_RCCR:
718 case REG_ESAI_TSMA:
719 case REG_ESAI_TSMB:
720 case REG_ESAI_RSMA:
721 case REG_ESAI_RSMB:
722 case REG_ESAI_PRRC:
723 case REG_ESAI_PCRC:
724 return true;
725 default:
726 return false;
727 }
728 }
729
730 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
731 {
732 switch (reg) {
733 case REG_ESAI_ERDR:
734 case REG_ESAI_ESR:
735 case REG_ESAI_TFSR:
736 case REG_ESAI_RFSR:
737 case REG_ESAI_RX0:
738 case REG_ESAI_RX1:
739 case REG_ESAI_RX2:
740 case REG_ESAI_RX3:
741 case REG_ESAI_SAISR:
742 return true;
743 default:
744 return false;
745 }
746 }
747
748 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
749 {
750 switch (reg) {
751 case REG_ESAI_ETDR:
752 case REG_ESAI_ECR:
753 case REG_ESAI_TFCR:
754 case REG_ESAI_RFCR:
755 case REG_ESAI_TX0:
756 case REG_ESAI_TX1:
757 case REG_ESAI_TX2:
758 case REG_ESAI_TX3:
759 case REG_ESAI_TX4:
760 case REG_ESAI_TX5:
761 case REG_ESAI_TSR:
762 case REG_ESAI_SAICR:
763 case REG_ESAI_TCR:
764 case REG_ESAI_TCCR:
765 case REG_ESAI_RCR:
766 case REG_ESAI_RCCR:
767 case REG_ESAI_TSMA:
768 case REG_ESAI_TSMB:
769 case REG_ESAI_RSMA:
770 case REG_ESAI_RSMB:
771 case REG_ESAI_PRRC:
772 case REG_ESAI_PCRC:
773 return true;
774 default:
775 return false;
776 }
777 }
778
779 static const struct regmap_config fsl_esai_regmap_config = {
780 .reg_bits = 32,
781 .reg_stride = 4,
782 .val_bits = 32,
783
784 .max_register = REG_ESAI_PCRC,
785 .reg_defaults = fsl_esai_reg_defaults,
786 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults),
787 .readable_reg = fsl_esai_readable_reg,
788 .volatile_reg = fsl_esai_volatile_reg,
789 .writeable_reg = fsl_esai_writeable_reg,
790 .cache_type = REGCACHE_FLAT,
791 };
792
793 static int fsl_esai_probe(struct platform_device *pdev)
794 {
795 struct device_node *np = pdev->dev.of_node;
796 struct fsl_esai *esai_priv;
797 struct resource *res;
798 const uint32_t *iprop;
799 void __iomem *regs;
800 int irq, ret;
801
802 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
803 if (!esai_priv)
804 return -ENOMEM;
805
806 esai_priv->pdev = pdev;
807 strncpy(esai_priv->name, np->name, sizeof(esai_priv->name) - 1);
808
809 /* Get the addresses and IRQ */
810 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
811 regs = devm_ioremap_resource(&pdev->dev, res);
812 if (IS_ERR(regs))
813 return PTR_ERR(regs);
814
815 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
816 "core", regs, &fsl_esai_regmap_config);
817 if (IS_ERR(esai_priv->regmap)) {
818 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
819 PTR_ERR(esai_priv->regmap));
820 return PTR_ERR(esai_priv->regmap);
821 }
822
823 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
824 if (IS_ERR(esai_priv->coreclk)) {
825 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
826 PTR_ERR(esai_priv->coreclk));
827 return PTR_ERR(esai_priv->coreclk);
828 }
829
830 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
831 if (IS_ERR(esai_priv->extalclk))
832 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
833 PTR_ERR(esai_priv->extalclk));
834
835 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
836 if (IS_ERR(esai_priv->fsysclk))
837 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
838 PTR_ERR(esai_priv->fsysclk));
839
840 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
841 if (IS_ERR(esai_priv->spbaclk))
842 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
843 PTR_ERR(esai_priv->spbaclk));
844
845 irq = platform_get_irq(pdev, 0);
846 if (irq < 0) {
847 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
848 return irq;
849 }
850
851 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
852 esai_priv->name, esai_priv);
853 if (ret) {
854 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
855 return ret;
856 }
857
858 /* Set a default slot number */
859 esai_priv->slots = 2;
860
861 /* Set a default master/slave state */
862 esai_priv->slave_mode = true;
863
864 /* Determine the FIFO depth */
865 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
866 if (iprop)
867 esai_priv->fifo_depth = be32_to_cpup(iprop);
868 else
869 esai_priv->fifo_depth = 64;
870
871 esai_priv->dma_params_tx.maxburst = 16;
872 esai_priv->dma_params_rx.maxburst = 16;
873 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
874 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
875
876 esai_priv->synchronous =
877 of_property_read_bool(np, "fsl,esai-synchronous");
878
879 /* Implement full symmetry for synchronous mode */
880 if (esai_priv->synchronous) {
881 fsl_esai_dai.symmetric_rates = 1;
882 fsl_esai_dai.symmetric_channels = 1;
883 fsl_esai_dai.symmetric_samplebits = 1;
884 }
885
886 dev_set_drvdata(&pdev->dev, esai_priv);
887
888 /* Reset ESAI unit */
889 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
890 if (ret) {
891 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
892 return ret;
893 }
894
895 /*
896 * We need to enable ESAI so as to access some of its registers.
897 * Otherwise, we would fail to dump regmap from user space.
898 */
899 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
900 if (ret) {
901 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
902 return ret;
903 }
904
905 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
906 &fsl_esai_dai, 1);
907 if (ret) {
908 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
909 return ret;
910 }
911
912 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
913 if (ret)
914 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
915
916 return ret;
917 }
918
919 static const struct of_device_id fsl_esai_dt_ids[] = {
920 { .compatible = "fsl,imx35-esai", },
921 { .compatible = "fsl,vf610-esai", },
922 {}
923 };
924 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
925
926 #ifdef CONFIG_PM_SLEEP
927 static int fsl_esai_suspend(struct device *dev)
928 {
929 struct fsl_esai *esai = dev_get_drvdata(dev);
930
931 regcache_cache_only(esai->regmap, true);
932 regcache_mark_dirty(esai->regmap);
933
934 return 0;
935 }
936
937 static int fsl_esai_resume(struct device *dev)
938 {
939 struct fsl_esai *esai = dev_get_drvdata(dev);
940 int ret;
941
942 regcache_cache_only(esai->regmap, false);
943
944 /* FIFO reset for safety */
945 regmap_update_bits(esai->regmap, REG_ESAI_TFCR,
946 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
947 regmap_update_bits(esai->regmap, REG_ESAI_RFCR,
948 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
949
950 ret = regcache_sync(esai->regmap);
951 if (ret)
952 return ret;
953
954 /* FIFO reset done */
955 regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
956 regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
957
958 return 0;
959 }
960 #endif /* CONFIG_PM_SLEEP */
961
962 static const struct dev_pm_ops fsl_esai_pm_ops = {
963 SET_SYSTEM_SLEEP_PM_OPS(fsl_esai_suspend, fsl_esai_resume)
964 };
965
966 static struct platform_driver fsl_esai_driver = {
967 .probe = fsl_esai_probe,
968 .driver = {
969 .name = "fsl-esai-dai",
970 .pm = &fsl_esai_pm_ops,
971 .of_match_table = fsl_esai_dt_ids,
972 },
973 };
974
975 module_platform_driver(fsl_esai_driver);
976
977 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
978 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
979 MODULE_LICENSE("GPL v2");
980 MODULE_ALIAS("platform:fsl-esai-dai");
Linux with added FPC-III support