sound/soc/fsl/fsl_ssi.h

   1 /*
   2  * fsl_ssi.h - ALSA SSI interface for the Freescale MPC8610 and i.MX SoC
   3  *
   4  * Author: Timur Tabi <timur@freescale.com>
   5  *
   6  * Copyright 2007-2008 Freescale Semiconductor, Inc.  This file is licensed
   7  * under the terms of the GNU General Public License version 2.  This
   8  * program is licensed "as is" without any warranty of any kind, whether
   9  * express or implied.
  10  */
  11
  12 #ifndef _MPC8610_I2S_H
  13 #define _MPC8610_I2S_H
  14
  15 #define RX 0
  16 #define TX 1
  17
  18 /* -- SSI Register Map -- */
  19
  20 /* SSI Transmit Data Register 0 */
  21 #define REG_SSI_STX0                    0x00
  22 /* SSI Transmit Data Register 1 */
  23 #define REG_SSI_STX1                    0x04
  24 /* SSI Receive Data Register 0 */
  25 #define REG_SSI_SRX0                    0x08
  26 /* SSI Receive Data Register 1 */
  27 #define REG_SSI_SRX1                    0x0c
  28 /* SSI Control Register */
  29 #define REG_SSI_SCR                     0x10
  30 /* SSI Interrupt Status Register */
  31 #define REG_SSI_SISR                    0x14
  32 /* SSI Interrupt Enable Register */
  33 #define REG_SSI_SIER                    0x18
  34 /* SSI Transmit Configuration Register */
  35 #define REG_SSI_STCR                    0x1c
  36 /* SSI Receive Configuration Register */
  37 #define REG_SSI_SRCR                    0x20
  38 #define REG_SSI_SxCR(tx)                ((tx) ? REG_SSI_STCR : REG_SSI_SRCR)
  39 /* SSI Transmit Clock Control Register */
  40 #define REG_SSI_STCCR                   0x24
  41 /* SSI Receive Clock Control Register */
  42 #define REG_SSI_SRCCR                   0x28
  43 #define REG_SSI_SxCCR(tx)               ((tx) ? REG_SSI_STCCR : REG_SSI_SRCCR)
  44 /* SSI FIFO Control/Status Register */
  45 #define REG_SSI_SFCSR                   0x2c
  46 /*
  47  * SSI Test Register (Intended for debugging purposes only)
  48  *
  49  * Note: STR is not documented in recent IMX datasheet, but
  50  * is described in IMX51 reference manual at section 56.3.3.14
  51  */
  52 #define REG_SSI_STR                     0x30
  53 /*
  54  * SSI Option Register (Intended for internal use only)
  55  *
  56  * Note: SOR is not documented in recent IMX datasheet, but
  57  * is described in IMX51 reference manual at section 56.3.3.15
  58  */
  59 #define REG_SSI_SOR                     0x34
  60 /* SSI AC97 Control Register */
  61 #define REG_SSI_SACNT                   0x38
  62 /* SSI AC97 Command Address Register */
  63 #define REG_SSI_SACADD                  0x3c
  64 /* SSI AC97 Command Data Register */
  65 #define REG_SSI_SACDAT                  0x40
  66 /* SSI AC97 Tag Register */
  67 #define REG_SSI_SATAG                   0x44
  68 /* SSI Transmit Time Slot Mask Register */
  69 #define REG_SSI_STMSK                   0x48
  70 /* SSI  Receive Time Slot Mask Register */
  71 #define REG_SSI_SRMSK                   0x4c
  72 #define REG_SSI_SxMSK(tx)               ((tx) ? REG_SSI_STMSK : REG_SSI_SRMSK)
  73 /*
  74  * SSI AC97 Channel Status Register
  75  *
  76  * The status could be changed by:
  77  * 1) Writing a '1' bit at some position in SACCEN sets relevant bit in SACCST
  78  * 2) Writing a '1' bit at some position in SACCDIS unsets the relevant bit
  79  * 3) Receivng a '1' in SLOTREQ bit from external CODEC via AC Link
  80  */
  81 #define REG_SSI_SACCST                  0x50
  82 /* SSI AC97 Channel Enable Register -- Set bits in SACCST */
  83 #define REG_SSI_SACCEN                  0x54
  84 /* SSI AC97 Channel Disable Register -- Clear bits in SACCST */
  85 #define REG_SSI_SACCDIS                 0x58
  86
  87 /* -- SSI Register Field Maps -- */
  88
  89 /* SSI Control Register -- REG_SSI_SCR 0x10 */
  90 #define SSI_SCR_SYNC_TX_FS              0x00001000
  91 #define SSI_SCR_RFR_CLK_DIS             0x00000800
  92 #define SSI_SCR_TFR_CLK_DIS             0x00000400
  93 #define SSI_SCR_TCH_EN                  0x00000100
  94 #define SSI_SCR_SYS_CLK_EN              0x00000080
  95 #define SSI_SCR_I2S_MODE_MASK           0x00000060
  96 #define SSI_SCR_I2S_MODE_NORMAL         0x00000000
  97 #define SSI_SCR_I2S_MODE_MASTER         0x00000020
  98 #define SSI_SCR_I2S_MODE_SLAVE          0x00000040
  99 #define SSI_SCR_SYN                     0x00000010
 100 #define SSI_SCR_NET                     0x00000008
 101 #define SSI_SCR_I2S_NET_MASK            (SSI_SCR_NET | SSI_SCR_I2S_MODE_MASK)
 102 #define SSI_SCR_RE                      0x00000004
 103 #define SSI_SCR_TE                      0x00000002
 104 #define SSI_SCR_SSIEN                   0x00000001
 105
 106 /* SSI Interrupt Status Register -- REG_SSI_SISR 0x14 */
 107 #define SSI_SISR_RFRC                   0x01000000
 108 #define SSI_SISR_TFRC                   0x00800000
 109 #define SSI_SISR_CMDAU                  0x00040000
 110 #define SSI_SISR_CMDDU                  0x00020000
 111 #define SSI_SISR_RXT                    0x00010000
 112 #define SSI_SISR_RDR1                   0x00008000
 113 #define SSI_SISR_RDR0                   0x00004000
 114 #define SSI_SISR_TDE1                   0x00002000
 115 #define SSI_SISR_TDE0                   0x00001000
 116 #define SSI_SISR_ROE1                   0x00000800
 117 #define SSI_SISR_ROE0                   0x00000400
 118 #define SSI_SISR_TUE1                   0x00000200
 119 #define SSI_SISR_TUE0                   0x00000100
 120 #define SSI_SISR_TFS                    0x00000080
 121 #define SSI_SISR_RFS                    0x00000040
 122 #define SSI_SISR_TLS                    0x00000020
 123 #define SSI_SISR_RLS                    0x00000010
 124 #define SSI_SISR_RFF1                   0x00000008
 125 #define SSI_SISR_RFF0                   0x00000004
 126 #define SSI_SISR_TFE1                   0x00000002
 127 #define SSI_SISR_TFE0                   0x00000001
 128
 129 /* SSI Interrupt Enable Register -- REG_SSI_SIER 0x18 */
 130 #define SSI_SIER_RFRC_EN                0x01000000
 131 #define SSI_SIER_TFRC_EN                0x00800000
 132 #define SSI_SIER_RDMAE                  0x00400000
 133 #define SSI_SIER_RIE                    0x00200000
 134 #define SSI_SIER_TDMAE                  0x00100000
 135 #define SSI_SIER_TIE                    0x00080000
 136 #define SSI_SIER_CMDAU_EN               0x00040000
 137 #define SSI_SIER_CMDDU_EN               0x00020000
 138 #define SSI_SIER_RXT_EN                 0x00010000
 139 #define SSI_SIER_RDR1_EN                0x00008000
 140 #define SSI_SIER_RDR0_EN                0x00004000
 141 #define SSI_SIER_TDE1_EN                0x00002000
 142 #define SSI_SIER_TDE0_EN                0x00001000
 143 #define SSI_SIER_ROE1_EN                0x00000800
 144 #define SSI_SIER_ROE0_EN                0x00000400
 145 #define SSI_SIER_TUE1_EN                0x00000200
 146 #define SSI_SIER_TUE0_EN                0x00000100
 147 #define SSI_SIER_TFS_EN                 0x00000080
 148 #define SSI_SIER_RFS_EN                 0x00000040
 149 #define SSI_SIER_TLS_EN                 0x00000020
 150 #define SSI_SIER_RLS_EN                 0x00000010
 151 #define SSI_SIER_RFF1_EN                0x00000008
 152 #define SSI_SIER_RFF0_EN                0x00000004
 153 #define SSI_SIER_TFE1_EN                0x00000002
 154 #define SSI_SIER_TFE0_EN                0x00000001
 155
 156 /* SSI Transmit Configuration Register -- REG_SSI_STCR 0x1C */
 157 #define SSI_STCR_TXBIT0                 0x00000200
 158 #define SSI_STCR_TFEN1                  0x00000100
 159 #define SSI_STCR_TFEN0                  0x00000080
 160 #define SSI_STCR_TFDIR                  0x00000040
 161 #define SSI_STCR_TXDIR                  0x00000020
 162 #define SSI_STCR_TSHFD                  0x00000010
 163 #define SSI_STCR_TSCKP                  0x00000008
 164 #define SSI_STCR_TFSI                   0x00000004
 165 #define SSI_STCR_TFSL                   0x00000002
 166 #define SSI_STCR_TEFS                   0x00000001
 167
 168 /* SSI Receive Configuration Register -- REG_SSI_SRCR 0x20 */
 169 #define SSI_SRCR_RXEXT                  0x00000400
 170 #define SSI_SRCR_RXBIT0                 0x00000200
 171 #define SSI_SRCR_RFEN1                  0x00000100
 172 #define SSI_SRCR_RFEN0                  0x00000080
 173 #define SSI_SRCR_RFDIR                  0x00000040
 174 #define SSI_SRCR_RXDIR                  0x00000020
 175 #define SSI_SRCR_RSHFD                  0x00000010
 176 #define SSI_SRCR_RSCKP                  0x00000008
 177 #define SSI_SRCR_RFSI                   0x00000004
 178 #define SSI_SRCR_RFSL                   0x00000002
 179 #define SSI_SRCR_REFS                   0x00000001
 180
 181 /*
 182  * SSI Transmit Clock Control Register -- REG_SSI_STCCR 0x24
 183  * SSI Receive Clock Control Register -- REG_SSI_SRCCR 0x28
 184  */
 185 #define SSI_SxCCR_DIV2_SHIFT            18
 186 #define SSI_SxCCR_DIV2                  0x00040000
 187 #define SSI_SxCCR_PSR_SHIFT             17
 188 #define SSI_SxCCR_PSR                   0x00020000
 189 #define SSI_SxCCR_WL_SHIFT              13
 190 #define SSI_SxCCR_WL_MASK               0x0001E000
 191 #define SSI_SxCCR_WL(x) \
 192         (((((x) / 2) - 1) << SSI_SxCCR_WL_SHIFT) & SSI_SxCCR_WL_MASK)
 193 #define SSI_SxCCR_DC_SHIFT              8
 194 #define SSI_SxCCR_DC_MASK               0x00001F00
 195 #define SSI_SxCCR_DC(x) \
 196         ((((x) - 1) << SSI_SxCCR_DC_SHIFT) & SSI_SxCCR_DC_MASK)
 197 #define SSI_SxCCR_PM_SHIFT              0
 198 #define SSI_SxCCR_PM_MASK               0x000000FF
 199 #define SSI_SxCCR_PM(x) \
 200         ((((x) - 1) << SSI_SxCCR_PM_SHIFT) & SSI_SxCCR_PM_MASK)
 201
 202 /*
 203  * SSI FIFO Control/Status Register -- REG_SSI_SFCSR 0x2c
 204  *
 205  * Tx or Rx FIFO Counter -- SSI_SFCSR_xFCNTy Read-Only
 206  * Tx or Rx FIFO Watermarks -- SSI_SFCSR_xFWMy Read/Write
 207  */
 208 #define SSI_SFCSR_RFCNT1_SHIFT          28
 209 #define SSI_SFCSR_RFCNT1_MASK           0xF0000000
 210 #define SSI_SFCSR_RFCNT1(x) \
 211         (((x) & SSI_SFCSR_RFCNT1_MASK) >> SSI_SFCSR_RFCNT1_SHIFT)
 212 #define SSI_SFCSR_TFCNT1_SHIFT          24
 213 #define SSI_SFCSR_TFCNT1_MASK           0x0F000000
 214 #define SSI_SFCSR_TFCNT1(x) \
 215         (((x) & SSI_SFCSR_TFCNT1_MASK) >> SSI_SFCSR_TFCNT1_SHIFT)
 216 #define SSI_SFCSR_RFWM1_SHIFT           20
 217 #define SSI_SFCSR_RFWM1_MASK            0x00F00000
 218 #define SSI_SFCSR_RFWM1(x)      \
 219         (((x) << SSI_SFCSR_RFWM1_SHIFT) & SSI_SFCSR_RFWM1_MASK)
 220 #define SSI_SFCSR_TFWM1_SHIFT           16
 221 #define SSI_SFCSR_TFWM1_MASK            0x000F0000
 222 #define SSI_SFCSR_TFWM1(x)      \
 223         (((x) << SSI_SFCSR_TFWM1_SHIFT) & SSI_SFCSR_TFWM1_MASK)
 224 #define SSI_SFCSR_RFCNT0_SHIFT          12
 225 #define SSI_SFCSR_RFCNT0_MASK           0x0000F000
 226 #define SSI_SFCSR_RFCNT0(x) \
 227         (((x) & SSI_SFCSR_RFCNT0_MASK) >> SSI_SFCSR_RFCNT0_SHIFT)
 228 #define SSI_SFCSR_TFCNT0_SHIFT          8
 229 #define SSI_SFCSR_TFCNT0_MASK           0x00000F00
 230 #define SSI_SFCSR_TFCNT0(x) \
 231         (((x) & SSI_SFCSR_TFCNT0_MASK) >> SSI_SFCSR_TFCNT0_SHIFT)
 232 #define SSI_SFCSR_RFWM0_SHIFT           4
 233 #define SSI_SFCSR_RFWM0_MASK            0x000000F0
 234 #define SSI_SFCSR_RFWM0(x)      \
 235         (((x) << SSI_SFCSR_RFWM0_SHIFT) & SSI_SFCSR_RFWM0_MASK)
 236 #define SSI_SFCSR_TFWM0_SHIFT           0
 237 #define SSI_SFCSR_TFWM0_MASK            0x0000000F
 238 #define SSI_SFCSR_TFWM0(x)      \
 239         (((x) << SSI_SFCSR_TFWM0_SHIFT) & SSI_SFCSR_TFWM0_MASK)
 240
 241 /* SSI Test Register -- REG_SSI_STR 0x30 */
 242 #define SSI_STR_TEST                    0x00008000
 243 #define SSI_STR_RCK2TCK                 0x00004000
 244 #define SSI_STR_RFS2TFS                 0x00002000
 245 #define SSI_STR_RXSTATE(x)              (((x) >> 8) & 0x1F)
 246 #define SSI_STR_TXD2RXD                 0x00000080
 247 #define SSI_STR_TCK2RCK                 0x00000040
 248 #define SSI_STR_TFS2RFS                 0x00000020
 249 #define SSI_STR_TXSTATE(x)              ((x) & 0x1F)
 250
 251 /* SSI Option Register -- REG_SSI_SOR 0x34 */
 252 #define SSI_SOR_CLKOFF                  0x00000040
 253 #define SSI_SOR_RX_CLR                  0x00000020
 254 #define SSI_SOR_TX_CLR                  0x00000010
 255 #define SSI_SOR_xX_CLR(tx)              ((tx) ? SSI_SOR_TX_CLR : SSI_SOR_RX_CLR)
 256 #define SSI_SOR_INIT                    0x00000008
 257 #define SSI_SOR_WAIT_SHIFT              1
 258 #define SSI_SOR_WAIT_MASK               0x00000006
 259 #define SSI_SOR_WAIT(x)                 (((x) & 3) << SSI_SOR_WAIT_SHIFT)
 260 #define SSI_SOR_SYNRST                  0x00000001
 261
 262 /* SSI AC97 Control Register -- REG_SSI_SACNT 0x38 */
 263 #define SSI_SACNT_FRDIV(x)              (((x) & 0x3f) << 5)
 264 #define SSI_SACNT_WR                    0x00000010
 265 #define SSI_SACNT_RD                    0x00000008
 266 #define SSI_SACNT_RDWR_MASK             0x00000018
 267 #define SSI_SACNT_TIF                   0x00000004
 268 #define SSI_SACNT_FV                    0x00000002
 269 #define SSI_SACNT_AC97EN                0x00000001
 270
 271
 272 struct device;
 273
 274 #if IS_ENABLED(CONFIG_DEBUG_FS)
 275
 276 struct fsl_ssi_dbg {
 277         struct dentry *dbg_dir;
 278         struct dentry *dbg_stats;
 279
 280         struct {
 281                 unsigned int rfrc;
 282                 unsigned int tfrc;
 283                 unsigned int cmdau;
 284                 unsigned int cmddu;
 285                 unsigned int rxt;
 286                 unsigned int rdr1;
 287                 unsigned int rdr0;
 288                 unsigned int tde1;
 289                 unsigned int tde0;
 290                 unsigned int roe1;
 291                 unsigned int roe0;
 292                 unsigned int tue1;
 293                 unsigned int tue0;
 294                 unsigned int tfs;
 295                 unsigned int rfs;
 296                 unsigned int tls;
 297                 unsigned int rls;
 298                 unsigned int rff1;
 299                 unsigned int rff0;
 300                 unsigned int tfe1;
 301                 unsigned int tfe0;
 302         } stats;
 303 };
 304
 305 void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *ssi_dbg, u32 sisr);
 306
 307 int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev);
 308
 309 void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg);
 310
 311 #else
 312
 313 struct fsl_ssi_dbg {
 314 };
 315
 316 static inline void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *stats, u32 sisr)
 317 {
 318 }
 319
 320 static inline int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg,
 321                                          struct device *dev)
 322 {
 323         return 0;
 324 }
 325
 326 static inline void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg)
 327 {
 328 }
 329 #endif  /* ! IS_ENABLED(CONFIG_DEBUG_FS) */
 330
 331 #endif