2 * Mediatek ALSA SoC AFE platform driver for 2701
4 * Copyright (c) 2016 MediaTek Inc.
5 * Author: Garlic Tseng <garlic.tseng@mediatek.com>
6 * Ir Lian <ir.lian@mediatek.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 and
10 * only version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/delay.h>
19 #include <linux/module.h>
20 #include <linux/mfd/syscon.h>
22 #include <linux/of_address.h>
23 #include <linux/pm_runtime.h>
25 #include "mt2701-afe-common.h"
26 #include "mt2701-afe-clock-ctrl.h"
27 #include "../common/mtk-afe-platform-driver.h"
28 #include "../common/mtk-afe-fe-dai.h"
30 static const struct snd_pcm_hardware mt2701_afe_hardware
= {
31 .info
= SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
32 | SNDRV_PCM_INFO_RESUME
| SNDRV_PCM_INFO_MMAP_VALID
,
33 .formats
= SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
34 | SNDRV_PCM_FMTBIT_S32_LE
,
35 .period_bytes_min
= 1024,
36 .period_bytes_max
= 1024 * 256,
39 .buffer_bytes_max
= 1024 * 1024 * 16,
43 struct mt2701_afe_rate
{
45 unsigned int regvalue
;
48 static const struct mt2701_afe_rate mt2701_afe_i2s_rates
[] = {
49 { .rate
= 8000, .regvalue
= 0 },
50 { .rate
= 12000, .regvalue
= 1 },
51 { .rate
= 16000, .regvalue
= 2 },
52 { .rate
= 24000, .regvalue
= 3 },
53 { .rate
= 32000, .regvalue
= 4 },
54 { .rate
= 48000, .regvalue
= 5 },
55 { .rate
= 96000, .regvalue
= 6 },
56 { .rate
= 192000, .regvalue
= 7 },
57 { .rate
= 384000, .regvalue
= 8 },
58 { .rate
= 7350, .regvalue
= 16 },
59 { .rate
= 11025, .regvalue
= 17 },
60 { .rate
= 14700, .regvalue
= 18 },
61 { .rate
= 22050, .regvalue
= 19 },
62 { .rate
= 29400, .regvalue
= 20 },
63 { .rate
= 44100, .regvalue
= 21 },
64 { .rate
= 88200, .regvalue
= 22 },
65 { .rate
= 176400, .regvalue
= 23 },
66 { .rate
= 352800, .regvalue
= 24 },
69 static int mt2701_dai_num_to_i2s(struct mtk_base_afe
*afe
, int num
)
71 int val
= num
- MT2701_IO_I2S
;
73 if (val
< 0 || val
>= MT2701_I2S_NUM
) {
74 dev_err(afe
->dev
, "%s, num not available, num %d, val %d\n",
81 static int mt2701_afe_i2s_fs(unsigned int sample_rate
)
85 for (i
= 0; i
< ARRAY_SIZE(mt2701_afe_i2s_rates
); i
++)
86 if (mt2701_afe_i2s_rates
[i
].rate
== sample_rate
)
87 return mt2701_afe_i2s_rates
[i
].regvalue
;
92 static int mt2701_afe_i2s_startup(struct snd_pcm_substream
*substream
,
93 struct snd_soc_dai
*dai
)
95 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
96 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
97 int i2s_num
= mt2701_dai_num_to_i2s(afe
, dai
->id
);
102 return mt2701_afe_enable_mclk(afe
, i2s_num
);
105 static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream
*substream
,
106 struct snd_soc_dai
*dai
,
110 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
111 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
112 struct mt2701_afe_private
*afe_priv
= afe
->platform_priv
;
113 struct mt2701_i2s_path
*i2s_path
= &afe_priv
->i2s_path
[i2s_num
];
114 const struct mt2701_i2s_data
*i2s_data
;
115 int stream_dir
= substream
->stream
;
118 if (stream_dir
== SNDRV_PCM_STREAM_PLAYBACK
)
119 stream_dir
= SNDRV_PCM_STREAM_CAPTURE
;
121 stream_dir
= SNDRV_PCM_STREAM_PLAYBACK
;
123 i2s_data
= i2s_path
->i2s_data
[stream_dir
];
125 i2s_path
->on
[stream_dir
]--;
126 if (i2s_path
->on
[stream_dir
] < 0) {
127 dev_warn(afe
->dev
, "i2s_path->on: %d, dir: %d\n",
128 i2s_path
->on
[stream_dir
], stream_dir
);
129 i2s_path
->on
[stream_dir
] = 0;
131 if (i2s_path
->on
[stream_dir
])
135 regmap_update_bits(afe
->regmap
, i2s_data
->i2s_ctrl_reg
,
136 ASYS_I2S_CON_I2S_EN
, 0);
138 mt2701_afe_disable_i2s(afe
, i2s_num
, stream_dir
);
143 static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream
*substream
,
144 struct snd_soc_dai
*dai
)
146 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
147 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
148 struct mt2701_afe_private
*afe_priv
= afe
->platform_priv
;
149 int i2s_num
= mt2701_dai_num_to_i2s(afe
, dai
->id
);
150 struct mt2701_i2s_path
*i2s_path
;
155 i2s_path
= &afe_priv
->i2s_path
[i2s_num
];
157 if (i2s_path
->occupied
[substream
->stream
])
158 i2s_path
->occupied
[substream
->stream
] = 0;
162 mt2701_afe_i2s_path_shutdown(substream
, dai
, i2s_num
, 0);
164 /* need to disable i2s-out path when disable i2s-in */
165 if (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
)
166 mt2701_afe_i2s_path_shutdown(substream
, dai
, i2s_num
, 1);
170 mt2701_afe_disable_mclk(afe
, i2s_num
);
173 static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream
*substream
,
174 struct snd_soc_dai
*dai
,
178 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
179 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
180 struct mt2701_afe_private
*afe_priv
= afe
->platform_priv
;
181 struct mt2701_i2s_path
*i2s_path
= &afe_priv
->i2s_path
[i2s_num
];
182 const struct mt2701_i2s_data
*i2s_data
;
183 struct snd_pcm_runtime
* const runtime
= substream
->runtime
;
184 int reg
, fs
, w_len
= 1; /* now we support bck 64bits only */
185 int stream_dir
= substream
->stream
;
186 unsigned int mask
= 0, val
= 0;
189 if (stream_dir
== SNDRV_PCM_STREAM_PLAYBACK
)
190 stream_dir
= SNDRV_PCM_STREAM_CAPTURE
;
192 stream_dir
= SNDRV_PCM_STREAM_PLAYBACK
;
194 i2s_data
= i2s_path
->i2s_data
[stream_dir
];
196 /* no need to enable if already done */
197 i2s_path
->on
[stream_dir
]++;
199 if (i2s_path
->on
[stream_dir
] != 1)
202 fs
= mt2701_afe_i2s_fs(runtime
->rate
);
204 mask
= ASYS_I2S_CON_FS
|
205 ASYS_I2S_CON_I2S_COUPLE_MODE
| /* 0 */
206 ASYS_I2S_CON_I2S_MODE
|
207 ASYS_I2S_CON_WIDE_MODE
;
209 val
= ASYS_I2S_CON_FS_SET(fs
) |
210 ASYS_I2S_CON_I2S_MODE
|
211 ASYS_I2S_CON_WIDE_MODE_SET(w_len
);
213 if (stream_dir
== SNDRV_PCM_STREAM_CAPTURE
) {
214 mask
|= ASYS_I2S_IN_PHASE_FIX
;
215 val
|= ASYS_I2S_IN_PHASE_FIX
;
218 regmap_update_bits(afe
->regmap
, i2s_data
->i2s_ctrl_reg
, mask
, val
);
220 if (stream_dir
== SNDRV_PCM_STREAM_PLAYBACK
)
221 reg
= ASMO_TIMING_CON1
;
223 reg
= ASMI_TIMING_CON1
;
225 regmap_update_bits(afe
->regmap
, reg
,
226 i2s_data
->i2s_asrc_fs_mask
227 << i2s_data
->i2s_asrc_fs_shift
,
228 fs
<< i2s_data
->i2s_asrc_fs_shift
);
231 mt2701_afe_enable_i2s(afe
, i2s_num
, stream_dir
);
233 /* reset i2s hw status before enable */
234 regmap_update_bits(afe
->regmap
, i2s_data
->i2s_ctrl_reg
,
235 ASYS_I2S_CON_RESET
, ASYS_I2S_CON_RESET
);
237 regmap_update_bits(afe
->regmap
, i2s_data
->i2s_ctrl_reg
,
238 ASYS_I2S_CON_RESET
, 0);
240 regmap_update_bits(afe
->regmap
, i2s_data
->i2s_ctrl_reg
,
241 ASYS_I2S_CON_I2S_EN
, ASYS_I2S_CON_I2S_EN
);
245 static int mt2701_afe_i2s_prepare(struct snd_pcm_substream
*substream
,
246 struct snd_soc_dai
*dai
)
249 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
250 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
251 struct mt2701_afe_private
*afe_priv
= afe
->platform_priv
;
252 int i2s_num
= mt2701_dai_num_to_i2s(afe
, dai
->id
);
253 struct mt2701_i2s_path
*i2s_path
;
259 i2s_path
= &afe_priv
->i2s_path
[i2s_num
];
260 mclk_rate
= i2s_path
->mclk_rate
;
262 if (i2s_path
->occupied
[substream
->stream
])
264 i2s_path
->occupied
[substream
->stream
] = 1;
266 if (MT2701_PLL_DOMAIN_0_RATE
% mclk_rate
== 0) {
268 } else if (MT2701_PLL_DOMAIN_1_RATE
% mclk_rate
== 0) {
271 dev_err(dai
->dev
, "%s() bad mclk rate %d\n",
272 __func__
, mclk_rate
);
275 mt2701_mclk_configuration(afe
, i2s_num
, clk_domain
, mclk_rate
);
277 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
278 mt2701_i2s_path_prepare_enable(substream
, dai
, i2s_num
, 0);
280 /* need to enable i2s-out path when enable i2s-in */
281 /* prepare for another direction "out" */
282 mt2701_i2s_path_prepare_enable(substream
, dai
, i2s_num
, 1);
283 /* prepare for "in" */
284 mt2701_i2s_path_prepare_enable(substream
, dai
, i2s_num
, 0);
290 static int mt2701_afe_i2s_set_sysclk(struct snd_soc_dai
*dai
, int clk_id
,
291 unsigned int freq
, int dir
)
293 struct mtk_base_afe
*afe
= dev_get_drvdata(dai
->dev
);
294 struct mt2701_afe_private
*afe_priv
= afe
->platform_priv
;
295 int i2s_num
= mt2701_dai_num_to_i2s(afe
, dai
->id
);
301 if (dir
== SND_SOC_CLOCK_IN
) {
303 "%s() warning: mt2701 doesn't support mclk input\n",
307 afe_priv
->i2s_path
[i2s_num
].mclk_rate
= freq
;
311 static int mt2701_btmrg_startup(struct snd_pcm_substream
*substream
,
312 struct snd_soc_dai
*dai
)
314 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
315 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
316 struct mt2701_afe_private
*afe_priv
= afe
->platform_priv
;
319 ret
= mt2701_enable_btmrg_clk(afe
);
323 afe_priv
->mrg_enable
[substream
->stream
] = 1;
327 static int mt2701_btmrg_hw_params(struct snd_pcm_substream
*substream
,
328 struct snd_pcm_hw_params
*params
,
329 struct snd_soc_dai
*dai
)
331 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
332 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
336 stream_fs
= params_rate(params
);
338 if ((stream_fs
!= 8000) && (stream_fs
!= 16000)) {
339 dev_err(afe
->dev
, "%s() btmgr not supprt this stream_fs %d\n",
340 __func__
, stream_fs
);
344 regmap_update_bits(afe
->regmap
, AFE_MRGIF_CON
,
345 AFE_MRGIF_CON_I2S_MODE_MASK
,
346 AFE_MRGIF_CON_I2S_MODE_32K
);
348 val
= AFE_DAIBT_CON0_BT_FUNC_EN
| AFE_DAIBT_CON0_BT_FUNC_RDY
349 | AFE_DAIBT_CON0_MRG_USE
;
352 if (stream_fs
== 16000)
353 val
|= AFE_DAIBT_CON0_BT_WIDE_MODE_EN
;
355 msk
|= AFE_DAIBT_CON0_BT_WIDE_MODE_EN
;
357 regmap_update_bits(afe
->regmap
, AFE_DAIBT_CON0
, msk
, val
);
359 regmap_update_bits(afe
->regmap
, AFE_DAIBT_CON0
,
360 AFE_DAIBT_CON0_DAIBT_EN
,
361 AFE_DAIBT_CON0_DAIBT_EN
);
362 regmap_update_bits(afe
->regmap
, AFE_MRGIF_CON
,
363 AFE_MRGIF_CON_MRG_I2S_EN
,
364 AFE_MRGIF_CON_MRG_I2S_EN
);
365 regmap_update_bits(afe
->regmap
, AFE_MRGIF_CON
,
366 AFE_MRGIF_CON_MRG_EN
,
367 AFE_MRGIF_CON_MRG_EN
);
371 static void mt2701_btmrg_shutdown(struct snd_pcm_substream
*substream
,
372 struct snd_soc_dai
*dai
)
374 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
375 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
376 struct mt2701_afe_private
*afe_priv
= afe
->platform_priv
;
378 /* if the other direction stream is not occupied */
379 if (!afe_priv
->mrg_enable
[!substream
->stream
]) {
380 regmap_update_bits(afe
->regmap
, AFE_DAIBT_CON0
,
381 AFE_DAIBT_CON0_DAIBT_EN
, 0);
382 regmap_update_bits(afe
->regmap
, AFE_MRGIF_CON
,
383 AFE_MRGIF_CON_MRG_EN
, 0);
384 regmap_update_bits(afe
->regmap
, AFE_MRGIF_CON
,
385 AFE_MRGIF_CON_MRG_I2S_EN
, 0);
386 mt2701_disable_btmrg_clk(afe
);
388 afe_priv
->mrg_enable
[substream
->stream
] = 0;
391 static int mt2701_simple_fe_startup(struct snd_pcm_substream
*substream
,
392 struct snd_soc_dai
*dai
)
394 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
395 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
396 int stream_dir
= substream
->stream
;
397 int memif_num
= rtd
->cpu_dai
->id
;
398 struct mtk_base_afe_memif
*memif_tmp
;
400 /* can't run single DL & DLM at the same time */
401 if (stream_dir
== SNDRV_PCM_STREAM_PLAYBACK
) {
402 memif_tmp
= &afe
->memif
[MT2701_MEMIF_DLM
];
403 if (memif_tmp
->substream
) {
404 dev_warn(afe
->dev
, "%s memif is not available, stream_dir %d, memif_num %d\n",
405 __func__
, stream_dir
, memif_num
);
409 return mtk_afe_fe_startup(substream
, dai
);
412 static int mt2701_simple_fe_hw_params(struct snd_pcm_substream
*substream
,
413 struct snd_pcm_hw_params
*params
,
414 struct snd_soc_dai
*dai
)
416 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
417 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
418 int stream_dir
= substream
->stream
;
420 /* single DL use PAIR_INTERLEAVE */
421 if (stream_dir
== SNDRV_PCM_STREAM_PLAYBACK
) {
422 regmap_update_bits(afe
->regmap
,
424 AFE_MEMIF_PBUF_SIZE_DLM_MASK
,
425 AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE
);
427 return mtk_afe_fe_hw_params(substream
, params
, dai
);
430 static int mt2701_dlm_fe_startup(struct snd_pcm_substream
*substream
,
431 struct snd_soc_dai
*dai
)
433 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
434 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
435 struct mtk_base_afe_memif
*memif_tmp
;
436 const struct mtk_base_memif_data
*memif_data
;
439 for (i
= MT2701_MEMIF_DL1
; i
< MT2701_MEMIF_DL_SINGLE_NUM
; ++i
) {
440 memif_tmp
= &afe
->memif
[i
];
441 if (memif_tmp
->substream
)
445 /* enable agent for all signal DL (due to hw design) */
446 for (i
= MT2701_MEMIF_DL1
; i
< MT2701_MEMIF_DL_SINGLE_NUM
; ++i
) {
447 memif_data
= afe
->memif
[i
].data
;
448 regmap_update_bits(afe
->regmap
,
449 memif_data
->agent_disable_reg
,
450 1 << memif_data
->agent_disable_shift
,
451 0 << memif_data
->agent_disable_shift
);
454 return mtk_afe_fe_startup(substream
, dai
);
457 static void mt2701_dlm_fe_shutdown(struct snd_pcm_substream
*substream
,
458 struct snd_soc_dai
*dai
)
460 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
461 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
462 const struct mtk_base_memif_data
*memif_data
;
465 for (i
= MT2701_MEMIF_DL1
; i
< MT2701_MEMIF_DL_SINGLE_NUM
; ++i
) {
466 memif_data
= afe
->memif
[i
].data
;
467 regmap_update_bits(afe
->regmap
,
468 memif_data
->agent_disable_reg
,
469 1 << memif_data
->agent_disable_shift
,
470 1 << memif_data
->agent_disable_shift
);
472 return mtk_afe_fe_shutdown(substream
, dai
);
475 static int mt2701_dlm_fe_hw_params(struct snd_pcm_substream
*substream
,
476 struct snd_pcm_hw_params
*params
,
477 struct snd_soc_dai
*dai
)
479 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
480 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
481 int channels
= params_channels(params
);
483 regmap_update_bits(afe
->regmap
,
485 AFE_MEMIF_PBUF_SIZE_DLM_MASK
,
486 AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE
);
487 regmap_update_bits(afe
->regmap
,
489 AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK
,
490 AFE_MEMIF_PBUF_SIZE_DLM_32BYTES
);
491 regmap_update_bits(afe
->regmap
,
493 AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK
,
494 AFE_MEMIF_PBUF_SIZE_DLM_CH(channels
));
496 return mtk_afe_fe_hw_params(substream
, params
, dai
);
499 static int mt2701_dlm_fe_trigger(struct snd_pcm_substream
*substream
,
500 int cmd
, struct snd_soc_dai
*dai
)
502 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
503 struct mtk_base_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
504 struct mtk_base_afe_memif
*memif_tmp
= &afe
->memif
[MT2701_MEMIF_DL1
];
507 case SNDRV_PCM_TRIGGER_START
:
508 case SNDRV_PCM_TRIGGER_RESUME
:
509 regmap_update_bits(afe
->regmap
, memif_tmp
->data
->enable_reg
,
510 1 << memif_tmp
->data
->enable_shift
,
511 1 << memif_tmp
->data
->enable_shift
);
512 mtk_afe_fe_trigger(substream
, cmd
, dai
);
514 case SNDRV_PCM_TRIGGER_STOP
:
515 case SNDRV_PCM_TRIGGER_SUSPEND
:
516 mtk_afe_fe_trigger(substream
, cmd
, dai
);
517 regmap_update_bits(afe
->regmap
, memif_tmp
->data
->enable_reg
,
518 1 << memif_tmp
->data
->enable_shift
, 0);
526 static int mt2701_memif_fs(struct snd_pcm_substream
*substream
,
529 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
532 if (rtd
->cpu_dai
->id
!= MT2701_MEMIF_ULBT
)
533 fs
= mt2701_afe_i2s_fs(rate
);
535 fs
= (rate
== 16000 ? 1 : 0);
539 static int mt2701_irq_fs(struct snd_pcm_substream
*substream
, unsigned int rate
)
541 return mt2701_afe_i2s_fs(rate
);
545 static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops
= {
546 .startup
= mt2701_simple_fe_startup
,
547 .shutdown
= mtk_afe_fe_shutdown
,
548 .hw_params
= mt2701_simple_fe_hw_params
,
549 .hw_free
= mtk_afe_fe_hw_free
,
550 .prepare
= mtk_afe_fe_prepare
,
551 .trigger
= mtk_afe_fe_trigger
,
554 static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops
= {
555 .startup
= mt2701_dlm_fe_startup
,
556 .shutdown
= mt2701_dlm_fe_shutdown
,
557 .hw_params
= mt2701_dlm_fe_hw_params
,
558 .hw_free
= mtk_afe_fe_hw_free
,
559 .prepare
= mtk_afe_fe_prepare
,
560 .trigger
= mt2701_dlm_fe_trigger
,
564 static const struct snd_soc_dai_ops mt2701_afe_i2s_ops
= {
565 .startup
= mt2701_afe_i2s_startup
,
566 .shutdown
= mt2701_afe_i2s_shutdown
,
567 .prepare
= mt2701_afe_i2s_prepare
,
568 .set_sysclk
= mt2701_afe_i2s_set_sysclk
,
572 static const struct snd_soc_dai_ops mt2701_btmrg_ops
= {
573 .startup
= mt2701_btmrg_startup
,
574 .shutdown
= mt2701_btmrg_shutdown
,
575 .hw_params
= mt2701_btmrg_hw_params
,
578 static struct snd_soc_dai_driver mt2701_afe_pcm_dais
[] = {
579 /* FE DAIs: memory intefaces to CPU */
582 .id
= MT2701_MEMIF_DL1
,
583 .suspend
= mtk_afe_dai_suspend
,
584 .resume
= mtk_afe_dai_resume
,
586 .stream_name
= "DL1",
589 .rates
= SNDRV_PCM_RATE_8000_192000
,
590 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
591 | SNDRV_PCM_FMTBIT_S24_LE
592 | SNDRV_PCM_FMTBIT_S32_LE
)
594 .ops
= &mt2701_single_memif_dai_ops
,
598 .id
= MT2701_MEMIF_DLM
,
599 .suspend
= mtk_afe_dai_suspend
,
600 .resume
= mtk_afe_dai_resume
,
602 .stream_name
= "DLM",
605 .rates
= SNDRV_PCM_RATE_8000_192000
,
606 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
607 | SNDRV_PCM_FMTBIT_S24_LE
608 | SNDRV_PCM_FMTBIT_S32_LE
)
611 .ops
= &mt2701_dlm_memif_dai_ops
,
615 .id
= MT2701_MEMIF_UL1
,
616 .suspend
= mtk_afe_dai_suspend
,
617 .resume
= mtk_afe_dai_resume
,
619 .stream_name
= "UL1",
622 .rates
= SNDRV_PCM_RATE_8000_48000
,
623 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
624 | SNDRV_PCM_FMTBIT_S24_LE
625 | SNDRV_PCM_FMTBIT_S32_LE
)
627 .ops
= &mt2701_single_memif_dai_ops
,
631 .id
= MT2701_MEMIF_UL2
,
632 .suspend
= mtk_afe_dai_suspend
,
633 .resume
= mtk_afe_dai_resume
,
635 .stream_name
= "UL2",
638 .rates
= SNDRV_PCM_RATE_8000_192000
,
639 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
640 | SNDRV_PCM_FMTBIT_S24_LE
641 | SNDRV_PCM_FMTBIT_S32_LE
)
644 .ops
= &mt2701_single_memif_dai_ops
,
648 .id
= MT2701_MEMIF_DLBT
,
649 .suspend
= mtk_afe_dai_suspend
,
650 .resume
= mtk_afe_dai_resume
,
652 .stream_name
= "DLBT",
655 .rates
= (SNDRV_PCM_RATE_8000
656 | SNDRV_PCM_RATE_16000
),
657 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
659 .ops
= &mt2701_single_memif_dai_ops
,
663 .id
= MT2701_MEMIF_ULBT
,
664 .suspend
= mtk_afe_dai_suspend
,
665 .resume
= mtk_afe_dai_resume
,
667 .stream_name
= "ULBT",
670 .rates
= (SNDRV_PCM_RATE_8000
671 | SNDRV_PCM_RATE_16000
),
672 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
674 .ops
= &mt2701_single_memif_dai_ops
,
681 .stream_name
= "I2S0 Playback",
684 .rates
= SNDRV_PCM_RATE_8000_192000
,
685 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
686 | SNDRV_PCM_FMTBIT_S24_LE
687 | SNDRV_PCM_FMTBIT_S32_LE
)
691 .stream_name
= "I2S0 Capture",
694 .rates
= SNDRV_PCM_RATE_8000_192000
,
695 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
696 | SNDRV_PCM_FMTBIT_S24_LE
697 | SNDRV_PCM_FMTBIT_S32_LE
)
700 .ops
= &mt2701_afe_i2s_ops
,
701 .symmetric_rates
= 1,
705 .id
= MT2701_IO_2ND_I2S
,
707 .stream_name
= "I2S1 Playback",
710 .rates
= SNDRV_PCM_RATE_8000_192000
,
711 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
712 | SNDRV_PCM_FMTBIT_S24_LE
713 | SNDRV_PCM_FMTBIT_S32_LE
)
716 .stream_name
= "I2S1 Capture",
719 .rates
= SNDRV_PCM_RATE_8000_192000
,
720 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
721 | SNDRV_PCM_FMTBIT_S24_LE
722 | SNDRV_PCM_FMTBIT_S32_LE
)
724 .ops
= &mt2701_afe_i2s_ops
,
725 .symmetric_rates
= 1,
729 .id
= MT2701_IO_3RD_I2S
,
731 .stream_name
= "I2S2 Playback",
734 .rates
= SNDRV_PCM_RATE_8000_192000
,
735 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
736 | SNDRV_PCM_FMTBIT_S24_LE
737 | SNDRV_PCM_FMTBIT_S32_LE
)
740 .stream_name
= "I2S2 Capture",
743 .rates
= SNDRV_PCM_RATE_8000_192000
,
744 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
745 | SNDRV_PCM_FMTBIT_S24_LE
746 | SNDRV_PCM_FMTBIT_S32_LE
)
748 .ops
= &mt2701_afe_i2s_ops
,
749 .symmetric_rates
= 1,
753 .id
= MT2701_IO_4TH_I2S
,
755 .stream_name
= "I2S3 Playback",
758 .rates
= SNDRV_PCM_RATE_8000_192000
,
759 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
760 | SNDRV_PCM_FMTBIT_S24_LE
761 | SNDRV_PCM_FMTBIT_S32_LE
)
764 .stream_name
= "I2S3 Capture",
767 .rates
= SNDRV_PCM_RATE_8000_192000
,
768 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
769 | SNDRV_PCM_FMTBIT_S24_LE
770 | SNDRV_PCM_FMTBIT_S32_LE
)
772 .ops
= &mt2701_afe_i2s_ops
,
773 .symmetric_rates
= 1,
779 .stream_name
= "BT Playback",
782 .rates
= (SNDRV_PCM_RATE_8000
783 | SNDRV_PCM_RATE_16000
),
784 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
787 .stream_name
= "BT Capture",
790 .rates
= (SNDRV_PCM_RATE_8000
791 | SNDRV_PCM_RATE_16000
),
792 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
794 .ops
= &mt2701_btmrg_ops
,
795 .symmetric_rates
= 1,
799 static const struct snd_kcontrol_new mt2701_afe_o00_mix
[] = {
800 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN0
, 0, 1, 0),
803 static const struct snd_kcontrol_new mt2701_afe_o01_mix
[] = {
804 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN1
, 1, 1, 0),
807 static const struct snd_kcontrol_new mt2701_afe_o02_mix
[] = {
808 SOC_DAPM_SINGLE_AUTODISABLE("I02 Switch", AFE_CONN2
, 2, 1, 0),
811 static const struct snd_kcontrol_new mt2701_afe_o03_mix
[] = {
812 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3
, 3, 1, 0),
815 static const struct snd_kcontrol_new mt2701_afe_o14_mix
[] = {
816 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN14
, 26, 1, 0),
819 static const struct snd_kcontrol_new mt2701_afe_o15_mix
[] = {
820 SOC_DAPM_SINGLE_AUTODISABLE("I12 Switch", AFE_CONN15
, 12, 1, 0),
823 static const struct snd_kcontrol_new mt2701_afe_o16_mix
[] = {
824 SOC_DAPM_SINGLE_AUTODISABLE("I13 Switch", AFE_CONN16
, 13, 1, 0),
827 static const struct snd_kcontrol_new mt2701_afe_o17_mix
[] = {
828 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN17
, 14, 1, 0),
831 static const struct snd_kcontrol_new mt2701_afe_o18_mix
[] = {
832 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN18
, 15, 1, 0),
835 static const struct snd_kcontrol_new mt2701_afe_o19_mix
[] = {
836 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN19
, 16, 1, 0),
839 static const struct snd_kcontrol_new mt2701_afe_o20_mix
[] = {
840 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN20
, 17, 1, 0),
843 static const struct snd_kcontrol_new mt2701_afe_o21_mix
[] = {
844 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN21
, 18, 1, 0),
847 static const struct snd_kcontrol_new mt2701_afe_o22_mix
[] = {
848 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN22
, 19, 1, 0),
851 static const struct snd_kcontrol_new mt2701_afe_o23_mix
[] = {
852 SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN23
, 20, 1, 0),
855 static const struct snd_kcontrol_new mt2701_afe_o24_mix
[] = {
856 SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN24
, 21, 1, 0),
859 static const struct snd_kcontrol_new mt2701_afe_o31_mix
[] = {
860 SOC_DAPM_SINGLE_AUTODISABLE("I35 Switch", AFE_CONN41
, 9, 1, 0),
863 static const struct snd_kcontrol_new mt2701_afe_i02_mix
[] = {
864 SOC_DAPM_SINGLE("I2S0 Switch", SND_SOC_NOPM
, 0, 1, 0),
867 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s0
[] = {
868 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S0 Out Switch",
869 ASYS_I2SO1_CON
, 26, 1, 0),
872 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s1
[] = {
873 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S1 Out Switch",
874 ASYS_I2SO2_CON
, 26, 1, 0),
877 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s2
[] = {
878 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S2 Out Switch",
879 PWR2_TOP_CON
, 17, 1, 0),
882 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s3
[] = {
883 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S3 Out Switch",
884 PWR2_TOP_CON
, 18, 1, 0),
887 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s4
[] = {
888 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S4 Out Switch",
889 PWR2_TOP_CON
, 19, 1, 0),
892 static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets
[] = {
893 /* inter-connections */
894 SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM
, 0, 0, NULL
, 0),
895 SND_SOC_DAPM_MIXER("I01", SND_SOC_NOPM
, 0, 0, NULL
, 0),
896 SND_SOC_DAPM_MIXER("I02", SND_SOC_NOPM
, 0, 0, mt2701_afe_i02_mix
,
897 ARRAY_SIZE(mt2701_afe_i02_mix
)),
898 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM
, 0, 0, NULL
, 0),
899 SND_SOC_DAPM_MIXER("I12", SND_SOC_NOPM
, 0, 0, NULL
, 0),
900 SND_SOC_DAPM_MIXER("I13", SND_SOC_NOPM
, 0, 0, NULL
, 0),
901 SND_SOC_DAPM_MIXER("I14", SND_SOC_NOPM
, 0, 0, NULL
, 0),
902 SND_SOC_DAPM_MIXER("I15", SND_SOC_NOPM
, 0, 0, NULL
, 0),
903 SND_SOC_DAPM_MIXER("I16", SND_SOC_NOPM
, 0, 0, NULL
, 0),
904 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM
, 0, 0, NULL
, 0),
905 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM
, 0, 0, NULL
, 0),
906 SND_SOC_DAPM_MIXER("I19", SND_SOC_NOPM
, 0, 0, NULL
, 0),
907 SND_SOC_DAPM_MIXER("I26", SND_SOC_NOPM
, 0, 0, NULL
, 0),
908 SND_SOC_DAPM_MIXER("I35", SND_SOC_NOPM
, 0, 0, NULL
, 0),
910 SND_SOC_DAPM_MIXER("O00", SND_SOC_NOPM
, 0, 0, mt2701_afe_o00_mix
,
911 ARRAY_SIZE(mt2701_afe_o00_mix
)),
912 SND_SOC_DAPM_MIXER("O01", SND_SOC_NOPM
, 0, 0, mt2701_afe_o01_mix
,
913 ARRAY_SIZE(mt2701_afe_o01_mix
)),
914 SND_SOC_DAPM_MIXER("O02", SND_SOC_NOPM
, 0, 0, mt2701_afe_o02_mix
,
915 ARRAY_SIZE(mt2701_afe_o02_mix
)),
916 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM
, 0, 0, mt2701_afe_o03_mix
,
917 ARRAY_SIZE(mt2701_afe_o03_mix
)),
918 SND_SOC_DAPM_MIXER("O14", SND_SOC_NOPM
, 0, 0, mt2701_afe_o14_mix
,
919 ARRAY_SIZE(mt2701_afe_o14_mix
)),
920 SND_SOC_DAPM_MIXER("O15", SND_SOC_NOPM
, 0, 0, mt2701_afe_o15_mix
,
921 ARRAY_SIZE(mt2701_afe_o15_mix
)),
922 SND_SOC_DAPM_MIXER("O16", SND_SOC_NOPM
, 0, 0, mt2701_afe_o16_mix
,
923 ARRAY_SIZE(mt2701_afe_o16_mix
)),
924 SND_SOC_DAPM_MIXER("O17", SND_SOC_NOPM
, 0, 0, mt2701_afe_o17_mix
,
925 ARRAY_SIZE(mt2701_afe_o17_mix
)),
926 SND_SOC_DAPM_MIXER("O18", SND_SOC_NOPM
, 0, 0, mt2701_afe_o18_mix
,
927 ARRAY_SIZE(mt2701_afe_o18_mix
)),
928 SND_SOC_DAPM_MIXER("O19", SND_SOC_NOPM
, 0, 0, mt2701_afe_o19_mix
,
929 ARRAY_SIZE(mt2701_afe_o19_mix
)),
930 SND_SOC_DAPM_MIXER("O20", SND_SOC_NOPM
, 0, 0, mt2701_afe_o20_mix
,
931 ARRAY_SIZE(mt2701_afe_o20_mix
)),
932 SND_SOC_DAPM_MIXER("O21", SND_SOC_NOPM
, 0, 0, mt2701_afe_o21_mix
,
933 ARRAY_SIZE(mt2701_afe_o21_mix
)),
934 SND_SOC_DAPM_MIXER("O22", SND_SOC_NOPM
, 0, 0, mt2701_afe_o22_mix
,
935 ARRAY_SIZE(mt2701_afe_o22_mix
)),
936 SND_SOC_DAPM_MIXER("O31", SND_SOC_NOPM
, 0, 0, mt2701_afe_o31_mix
,
937 ARRAY_SIZE(mt2701_afe_o31_mix
)),
939 SND_SOC_DAPM_MIXER("I12I13", SND_SOC_NOPM
, 0, 0,
940 mt2701_afe_multi_ch_out_i2s0
,
941 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s0
)),
942 SND_SOC_DAPM_MIXER("I14I15", SND_SOC_NOPM
, 0, 0,
943 mt2701_afe_multi_ch_out_i2s1
,
944 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s1
)),
945 SND_SOC_DAPM_MIXER("I16I17", SND_SOC_NOPM
, 0, 0,
946 mt2701_afe_multi_ch_out_i2s2
,
947 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s2
)),
948 SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM
, 0, 0,
949 mt2701_afe_multi_ch_out_i2s3
,
950 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3
)),
953 static const struct snd_soc_dapm_route mt2701_afe_pcm_routes
[] = {
954 {"I12", NULL
, "DL1"},
955 {"I13", NULL
, "DL1"},
956 {"I35", NULL
, "DLBT"},
958 {"I2S0 Playback", NULL
, "O15"},
959 {"I2S0 Playback", NULL
, "O16"},
960 {"I2S1 Playback", NULL
, "O17"},
961 {"I2S1 Playback", NULL
, "O18"},
962 {"I2S2 Playback", NULL
, "O19"},
963 {"I2S2 Playback", NULL
, "O20"},
964 {"I2S3 Playback", NULL
, "O21"},
965 {"I2S3 Playback", NULL
, "O22"},
966 {"BT Playback", NULL
, "O31"},
968 {"UL1", NULL
, "O00"},
969 {"UL1", NULL
, "O01"},
970 {"UL2", NULL
, "O02"},
971 {"UL2", NULL
, "O03"},
972 {"ULBT", NULL
, "O14"},
974 {"I00", NULL
, "I2S0 Capture"},
975 {"I01", NULL
, "I2S0 Capture"},
976 {"I02", NULL
, "I2S1 Capture"},
977 {"I03", NULL
, "I2S1 Capture"},
978 /* I02,03 link to UL2, also need to open I2S0 */
979 {"I02", "I2S0 Switch", "I2S0 Capture"},
981 {"I26", NULL
, "BT Capture"},
983 {"I12I13", "Multich I2S0 Out Switch", "DLM"},
984 {"I14I15", "Multich I2S1 Out Switch", "DLM"},
985 {"I16I17", "Multich I2S2 Out Switch", "DLM"},
986 {"I18I19", "Multich I2S3 Out Switch", "DLM"},
988 { "I12", NULL
, "I12I13" },
989 { "I13", NULL
, "I12I13" },
990 { "I14", NULL
, "I14I15" },
991 { "I15", NULL
, "I14I15" },
992 { "I16", NULL
, "I16I17" },
993 { "I17", NULL
, "I16I17" },
994 { "I18", NULL
, "I18I19" },
995 { "I19", NULL
, "I18I19" },
997 { "O00", "I00 Switch", "I00" },
998 { "O01", "I01 Switch", "I01" },
999 { "O02", "I02 Switch", "I02" },
1000 { "O03", "I03 Switch", "I03" },
1001 { "O14", "I26 Switch", "I26" },
1002 { "O15", "I12 Switch", "I12" },
1003 { "O16", "I13 Switch", "I13" },
1004 { "O17", "I14 Switch", "I14" },
1005 { "O18", "I15 Switch", "I15" },
1006 { "O19", "I16 Switch", "I16" },
1007 { "O20", "I17 Switch", "I17" },
1008 { "O21", "I18 Switch", "I18" },
1009 { "O22", "I19 Switch", "I19" },
1010 { "O31", "I35 Switch", "I35" },
1013 static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component
= {
1014 .name
= "mt2701-afe-pcm-dai",
1015 .dapm_widgets
= mt2701_afe_pcm_widgets
,
1016 .num_dapm_widgets
= ARRAY_SIZE(mt2701_afe_pcm_widgets
),
1017 .dapm_routes
= mt2701_afe_pcm_routes
,
1018 .num_dapm_routes
= ARRAY_SIZE(mt2701_afe_pcm_routes
),
1021 static const struct mtk_base_memif_data memif_data
[MT2701_MEMIF_NUM
] = {
1024 .id
= MT2701_MEMIF_DL1
,
1025 .reg_ofs_base
= AFE_DL1_BASE
,
1026 .reg_ofs_cur
= AFE_DL1_CUR
,
1027 .fs_reg
= AFE_DAC_CON1
,
1030 .mono_reg
= AFE_DAC_CON3
,
1032 .enable_reg
= AFE_DAC_CON0
,
1034 .hd_reg
= AFE_MEMIF_HD_CON0
,
1036 .agent_disable_reg
= AUDIO_TOP_CON5
,
1037 .agent_disable_shift
= 6,
1043 .id
= MT2701_MEMIF_DL2
,
1044 .reg_ofs_base
= AFE_DL2_BASE
,
1045 .reg_ofs_cur
= AFE_DL2_CUR
,
1046 .fs_reg
= AFE_DAC_CON1
,
1049 .mono_reg
= AFE_DAC_CON3
,
1051 .enable_reg
= AFE_DAC_CON0
,
1053 .hd_reg
= AFE_MEMIF_HD_CON0
,
1055 .agent_disable_reg
= AUDIO_TOP_CON5
,
1056 .agent_disable_shift
= 7,
1062 .id
= MT2701_MEMIF_DL3
,
1063 .reg_ofs_base
= AFE_DL3_BASE
,
1064 .reg_ofs_cur
= AFE_DL3_CUR
,
1065 .fs_reg
= AFE_DAC_CON1
,
1068 .mono_reg
= AFE_DAC_CON3
,
1070 .enable_reg
= AFE_DAC_CON0
,
1072 .hd_reg
= AFE_MEMIF_HD_CON0
,
1074 .agent_disable_reg
= AUDIO_TOP_CON5
,
1075 .agent_disable_shift
= 8,
1081 .id
= MT2701_MEMIF_DL4
,
1082 .reg_ofs_base
= AFE_DL4_BASE
,
1083 .reg_ofs_cur
= AFE_DL4_CUR
,
1084 .fs_reg
= AFE_DAC_CON1
,
1087 .mono_reg
= AFE_DAC_CON3
,
1089 .enable_reg
= AFE_DAC_CON0
,
1091 .hd_reg
= AFE_MEMIF_HD_CON0
,
1093 .agent_disable_reg
= AUDIO_TOP_CON5
,
1094 .agent_disable_shift
= 9,
1100 .id
= MT2701_MEMIF_DL5
,
1101 .reg_ofs_base
= AFE_DL5_BASE
,
1102 .reg_ofs_cur
= AFE_DL5_CUR
,
1103 .fs_reg
= AFE_DAC_CON1
,
1106 .mono_reg
= AFE_DAC_CON3
,
1108 .enable_reg
= AFE_DAC_CON0
,
1110 .hd_reg
= AFE_MEMIF_HD_CON0
,
1112 .agent_disable_reg
= AUDIO_TOP_CON5
,
1113 .agent_disable_shift
= 10,
1119 .id
= MT2701_MEMIF_DLM
,
1120 .reg_ofs_base
= AFE_DLMCH_BASE
,
1121 .reg_ofs_cur
= AFE_DLMCH_CUR
,
1122 .fs_reg
= AFE_DAC_CON1
,
1127 .enable_reg
= AFE_DAC_CON0
,
1129 .hd_reg
= AFE_MEMIF_PBUF_SIZE
,
1131 .agent_disable_reg
= AUDIO_TOP_CON5
,
1132 .agent_disable_shift
= 12,
1138 .id
= MT2701_MEMIF_UL1
,
1139 .reg_ofs_base
= AFE_VUL_BASE
,
1140 .reg_ofs_cur
= AFE_VUL_CUR
,
1141 .fs_reg
= AFE_DAC_CON2
,
1144 .mono_reg
= AFE_DAC_CON4
,
1146 .enable_reg
= AFE_DAC_CON0
,
1148 .hd_reg
= AFE_MEMIF_HD_CON1
,
1150 .agent_disable_reg
= AUDIO_TOP_CON5
,
1151 .agent_disable_shift
= 0,
1157 .id
= MT2701_MEMIF_UL2
,
1158 .reg_ofs_base
= AFE_UL2_BASE
,
1159 .reg_ofs_cur
= AFE_UL2_CUR
,
1160 .fs_reg
= AFE_DAC_CON2
,
1163 .mono_reg
= AFE_DAC_CON4
,
1165 .enable_reg
= AFE_DAC_CON0
,
1167 .hd_reg
= AFE_MEMIF_HD_CON1
,
1169 .agent_disable_reg
= AUDIO_TOP_CON5
,
1170 .agent_disable_shift
= 1,
1176 .id
= MT2701_MEMIF_UL3
,
1177 .reg_ofs_base
= AFE_UL3_BASE
,
1178 .reg_ofs_cur
= AFE_UL3_CUR
,
1179 .fs_reg
= AFE_DAC_CON2
,
1182 .mono_reg
= AFE_DAC_CON4
,
1184 .enable_reg
= AFE_DAC_CON0
,
1186 .hd_reg
= AFE_MEMIF_HD_CON0
,
1188 .agent_disable_reg
= AUDIO_TOP_CON5
,
1189 .agent_disable_shift
= 2,
1195 .id
= MT2701_MEMIF_UL4
,
1196 .reg_ofs_base
= AFE_UL4_BASE
,
1197 .reg_ofs_cur
= AFE_UL4_CUR
,
1198 .fs_reg
= AFE_DAC_CON2
,
1201 .mono_reg
= AFE_DAC_CON4
,
1203 .enable_reg
= AFE_DAC_CON0
,
1205 .hd_reg
= AFE_MEMIF_HD_CON0
,
1207 .agent_disable_reg
= AUDIO_TOP_CON5
,
1208 .agent_disable_shift
= 3,
1214 .id
= MT2701_MEMIF_UL5
,
1215 .reg_ofs_base
= AFE_UL5_BASE
,
1216 .reg_ofs_cur
= AFE_UL5_CUR
,
1217 .fs_reg
= AFE_DAC_CON2
,
1219 .mono_reg
= AFE_DAC_CON4
,
1222 .enable_reg
= AFE_DAC_CON0
,
1224 .hd_reg
= AFE_MEMIF_HD_CON0
,
1226 .agent_disable_reg
= AUDIO_TOP_CON5
,
1227 .agent_disable_shift
= 4,
1233 .id
= MT2701_MEMIF_DLBT
,
1234 .reg_ofs_base
= AFE_ARB1_BASE
,
1235 .reg_ofs_cur
= AFE_ARB1_CUR
,
1236 .fs_reg
= AFE_DAC_CON3
,
1239 .mono_reg
= AFE_DAC_CON3
,
1241 .enable_reg
= AFE_DAC_CON0
,
1243 .hd_reg
= AFE_MEMIF_HD_CON0
,
1245 .agent_disable_reg
= AUDIO_TOP_CON5
,
1246 .agent_disable_shift
= 13,
1252 .id
= MT2701_MEMIF_ULBT
,
1253 .reg_ofs_base
= AFE_DAI_BASE
,
1254 .reg_ofs_cur
= AFE_DAI_CUR
,
1255 .fs_reg
= AFE_DAC_CON2
,
1260 .enable_reg
= AFE_DAC_CON0
,
1262 .hd_reg
= AFE_MEMIF_HD_CON1
,
1264 .agent_disable_reg
= AUDIO_TOP_CON5
,
1265 .agent_disable_shift
= 16,
1271 static const struct mtk_base_irq_data irq_data
[MT2701_IRQ_ASYS_END
] = {
1273 .id
= MT2701_IRQ_ASYS_IRQ1
,
1274 .irq_cnt_reg
= ASYS_IRQ1_CON
,
1276 .irq_cnt_maskbit
= 0xffffff,
1277 .irq_fs_reg
= ASYS_IRQ1_CON
,
1279 .irq_fs_maskbit
= 0x1f,
1280 .irq_en_reg
= ASYS_IRQ1_CON
,
1282 .irq_clr_reg
= ASYS_IRQ_CLR
,
1286 .id
= MT2701_IRQ_ASYS_IRQ2
,
1287 .irq_cnt_reg
= ASYS_IRQ2_CON
,
1289 .irq_cnt_maskbit
= 0xffffff,
1290 .irq_fs_reg
= ASYS_IRQ2_CON
,
1292 .irq_fs_maskbit
= 0x1f,
1293 .irq_en_reg
= ASYS_IRQ2_CON
,
1295 .irq_clr_reg
= ASYS_IRQ_CLR
,
1299 .id
= MT2701_IRQ_ASYS_IRQ3
,
1300 .irq_cnt_reg
= ASYS_IRQ3_CON
,
1302 .irq_cnt_maskbit
= 0xffffff,
1303 .irq_fs_reg
= ASYS_IRQ3_CON
,
1305 .irq_fs_maskbit
= 0x1f,
1306 .irq_en_reg
= ASYS_IRQ3_CON
,
1308 .irq_clr_reg
= ASYS_IRQ_CLR
,
1313 static const struct mt2701_i2s_data mt2701_i2s_data
[MT2701_I2S_NUM
][2] = {
1316 .i2s_ctrl_reg
= ASYS_I2SO1_CON
,
1317 .i2s_asrc_fs_shift
= 0,
1318 .i2s_asrc_fs_mask
= 0x1f,
1322 .i2s_ctrl_reg
= ASYS_I2SIN1_CON
,
1323 .i2s_asrc_fs_shift
= 0,
1324 .i2s_asrc_fs_mask
= 0x1f,
1330 .i2s_ctrl_reg
= ASYS_I2SO2_CON
,
1331 .i2s_asrc_fs_shift
= 5,
1332 .i2s_asrc_fs_mask
= 0x1f,
1336 .i2s_ctrl_reg
= ASYS_I2SIN2_CON
,
1337 .i2s_asrc_fs_shift
= 5,
1338 .i2s_asrc_fs_mask
= 0x1f,
1344 .i2s_ctrl_reg
= ASYS_I2SO3_CON
,
1345 .i2s_asrc_fs_shift
= 10,
1346 .i2s_asrc_fs_mask
= 0x1f,
1350 .i2s_ctrl_reg
= ASYS_I2SIN3_CON
,
1351 .i2s_asrc_fs_shift
= 10,
1352 .i2s_asrc_fs_mask
= 0x1f,
1358 .i2s_ctrl_reg
= ASYS_I2SO4_CON
,
1359 .i2s_asrc_fs_shift
= 15,
1360 .i2s_asrc_fs_mask
= 0x1f,
1364 .i2s_ctrl_reg
= ASYS_I2SIN4_CON
,
1365 .i2s_asrc_fs_shift
= 15,
1366 .i2s_asrc_fs_mask
= 0x1f,
1372 static irqreturn_t
mt2701_asys_isr(int irq_id
, void *dev
)
1375 struct mtk_base_afe
*afe
= dev
;
1376 struct mtk_base_afe_memif
*memif
;
1377 struct mtk_base_afe_irq
*irq
;
1380 regmap_read(afe
->regmap
, ASYS_IRQ_STATUS
, &status
);
1381 regmap_write(afe
->regmap
, ASYS_IRQ_CLR
, status
);
1383 for (id
= 0; id
< MT2701_MEMIF_NUM
; ++id
) {
1384 memif
= &afe
->memif
[id
];
1385 if (memif
->irq_usage
< 0)
1387 irq
= &afe
->irqs
[memif
->irq_usage
];
1388 if (status
& 1 << (irq
->irq_data
->irq_clr_shift
))
1389 snd_pcm_period_elapsed(memif
->substream
);
1394 static int mt2701_afe_runtime_suspend(struct device
*dev
)
1396 struct mtk_base_afe
*afe
= dev_get_drvdata(dev
);
1398 return mt2701_afe_disable_clock(afe
);
1401 static int mt2701_afe_runtime_resume(struct device
*dev
)
1403 struct mtk_base_afe
*afe
= dev_get_drvdata(dev
);
1405 return mt2701_afe_enable_clock(afe
);
1408 static int mt2701_afe_add_component(struct mtk_base_afe
*afe
)
1410 struct snd_soc_component
*component
;
1412 component
= kzalloc(sizeof(*component
), GFP_KERNEL
);
1416 component
->regmap
= afe
->regmap
;
1418 return snd_soc_add_component(afe
->dev
, component
,
1419 &mt2701_afe_pcm_dai_component
,
1420 mt2701_afe_pcm_dais
,
1421 ARRAY_SIZE(mt2701_afe_pcm_dais
));
1424 static int mt2701_afe_pcm_dev_probe(struct platform_device
*pdev
)
1426 struct mtk_base_afe
*afe
;
1427 struct mt2701_afe_private
*afe_priv
;
1431 afe
= devm_kzalloc(&pdev
->dev
, sizeof(*afe
), GFP_KERNEL
);
1435 afe
->platform_priv
= devm_kzalloc(&pdev
->dev
, sizeof(*afe_priv
),
1437 if (!afe
->platform_priv
)
1440 afe_priv
= afe
->platform_priv
;
1441 afe
->dev
= &pdev
->dev
;
1444 irq_id
= platform_get_irq_byname(pdev
, "asys");
1446 dev_err(dev
, "unable to get ASYS IRQ\n");
1450 ret
= devm_request_irq(dev
, irq_id
, mt2701_asys_isr
,
1451 IRQF_TRIGGER_NONE
, "asys-isr", (void *)afe
);
1453 dev_err(dev
, "could not request_irq for asys-isr\n");
1457 afe
->regmap
= syscon_node_to_regmap(dev
->parent
->of_node
);
1458 if (IS_ERR(afe
->regmap
)) {
1459 dev_err(dev
, "could not get regmap from parent\n");
1460 return PTR_ERR(afe
->regmap
);
1463 mutex_init(&afe
->irq_alloc_lock
);
1465 /* memif initialize */
1466 afe
->memif_size
= MT2701_MEMIF_NUM
;
1467 afe
->memif
= devm_kcalloc(dev
, afe
->memif_size
, sizeof(*afe
->memif
),
1472 for (i
= 0; i
< afe
->memif_size
; i
++) {
1473 afe
->memif
[i
].data
= &memif_data
[i
];
1474 afe
->memif
[i
].irq_usage
= -1;
1477 /* irq initialize */
1478 afe
->irqs_size
= MT2701_IRQ_ASYS_END
;
1479 afe
->irqs
= devm_kcalloc(dev
, afe
->irqs_size
, sizeof(*afe
->irqs
),
1484 for (i
= 0; i
< afe
->irqs_size
; i
++)
1485 afe
->irqs
[i
].irq_data
= &irq_data
[i
];
1487 /* I2S initialize */
1488 for (i
= 0; i
< MT2701_I2S_NUM
; i
++) {
1489 afe_priv
->i2s_path
[i
].i2s_data
[I2S_OUT
]
1490 = &mt2701_i2s_data
[i
][I2S_OUT
];
1491 afe_priv
->i2s_path
[i
].i2s_data
[I2S_IN
]
1492 = &mt2701_i2s_data
[i
][I2S_IN
];
1495 afe
->mtk_afe_hardware
= &mt2701_afe_hardware
;
1496 afe
->memif_fs
= mt2701_memif_fs
;
1497 afe
->irq_fs
= mt2701_irq_fs
;
1498 afe
->reg_back_up_list
= mt2701_afe_backup_list
;
1499 afe
->reg_back_up_list_num
= ARRAY_SIZE(mt2701_afe_backup_list
);
1500 afe
->runtime_resume
= mt2701_afe_runtime_resume
;
1501 afe
->runtime_suspend
= mt2701_afe_runtime_suspend
;
1503 /* initial audio related clock */
1504 ret
= mt2701_init_clock(afe
);
1506 dev_err(dev
, "init clock error\n");
1510 platform_set_drvdata(pdev
, afe
);
1512 pm_runtime_enable(dev
);
1513 if (!pm_runtime_enabled(dev
)) {
1514 ret
= mt2701_afe_runtime_resume(dev
);
1516 goto err_pm_disable
;
1518 pm_runtime_get_sync(dev
);
1520 ret
= snd_soc_register_platform(dev
, &mtk_afe_pcm_platform
);
1522 dev_warn(dev
, "err_platform\n");
1526 ret
= mt2701_afe_add_component(afe
);
1528 dev_warn(dev
, "err_dai_component\n");
1529 goto err_dai_component
;
1535 snd_soc_unregister_platform(dev
);
1537 pm_runtime_put_sync(dev
);
1539 pm_runtime_disable(dev
);
1544 static int mt2701_afe_pcm_dev_remove(struct platform_device
*pdev
)
1546 pm_runtime_put_sync(&pdev
->dev
);
1547 pm_runtime_disable(&pdev
->dev
);
1548 if (!pm_runtime_status_suspended(&pdev
->dev
))
1549 mt2701_afe_runtime_suspend(&pdev
->dev
);
1551 snd_soc_unregister_component(&pdev
->dev
);
1552 snd_soc_unregister_platform(&pdev
->dev
);
1557 static const struct of_device_id mt2701_afe_pcm_dt_match
[] = {
1558 { .compatible
= "mediatek,mt2701-audio", },
1561 MODULE_DEVICE_TABLE(of
, mt2701_afe_pcm_dt_match
);
1563 static const struct dev_pm_ops mt2701_afe_pm_ops
= {
1564 SET_RUNTIME_PM_OPS(mt2701_afe_runtime_suspend
,
1565 mt2701_afe_runtime_resume
, NULL
)
1568 static struct platform_driver mt2701_afe_pcm_driver
= {
1570 .name
= "mt2701-audio",
1571 .of_match_table
= mt2701_afe_pcm_dt_match
,
1573 .pm
= &mt2701_afe_pm_ops
,
1576 .probe
= mt2701_afe_pcm_dev_probe
,
1577 .remove
= mt2701_afe_pcm_dev_remove
,
1580 module_platform_driver(mt2701_afe_pcm_driver
);
1582 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
1583 MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
1584 MODULE_LICENSE("GPL v2");