1 /* sound/soc/rockchip/rockchip_i2s.c
3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6 * Author: Jianqun <jay.xu@rock-chips.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/delay.h>
16 #include <linux/of_gpio.h>
17 #include <linux/of_device.h>
18 #include <linux/clk.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21 #include <sound/pcm_params.h>
22 #include <sound/dmaengine_pcm.h>
24 #include "rockchip_i2s.h"
26 #define DRV_NAME "rockchip-i2s"
39 struct snd_dmaengine_dai_dma_data capture_dma_data
;
40 struct snd_dmaengine_dai_dma_data playback_dma_data
;
42 struct regmap
*regmap
;
46 * Used to indicate the tx/rx status.
47 * I2S controller hopes to start the tx and rx together,
48 * also to stop them when they are both try to stop.
53 const struct rk_i2s_pins
*pins
;
56 static int i2s_runtime_suspend(struct device
*dev
)
58 struct rk_i2s_dev
*i2s
= dev_get_drvdata(dev
);
60 regcache_cache_only(i2s
->regmap
, true);
61 clk_disable_unprepare(i2s
->mclk
);
66 static int i2s_runtime_resume(struct device
*dev
)
68 struct rk_i2s_dev
*i2s
= dev_get_drvdata(dev
);
71 ret
= clk_prepare_enable(i2s
->mclk
);
73 dev_err(i2s
->dev
, "clock enable failed %d\n", ret
);
77 regcache_cache_only(i2s
->regmap
, false);
78 regcache_mark_dirty(i2s
->regmap
);
80 ret
= regcache_sync(i2s
->regmap
);
82 clk_disable_unprepare(i2s
->mclk
);
87 static inline struct rk_i2s_dev
*to_info(struct snd_soc_dai
*dai
)
89 return snd_soc_dai_get_drvdata(dai
);
92 static void rockchip_snd_txctrl(struct rk_i2s_dev
*i2s
, int on
)
98 regmap_update_bits(i2s
->regmap
, I2S_DMACR
,
99 I2S_DMACR_TDE_ENABLE
, I2S_DMACR_TDE_ENABLE
);
101 regmap_update_bits(i2s
->regmap
, I2S_XFER
,
102 I2S_XFER_TXS_START
| I2S_XFER_RXS_START
,
103 I2S_XFER_TXS_START
| I2S_XFER_RXS_START
);
105 i2s
->tx_start
= true;
107 i2s
->tx_start
= false;
109 regmap_update_bits(i2s
->regmap
, I2S_DMACR
,
110 I2S_DMACR_TDE_ENABLE
, I2S_DMACR_TDE_DISABLE
);
112 if (!i2s
->rx_start
) {
113 regmap_update_bits(i2s
->regmap
, I2S_XFER
,
120 regmap_update_bits(i2s
->regmap
, I2S_CLR
,
121 I2S_CLR_TXC
| I2S_CLR_RXC
,
122 I2S_CLR_TXC
| I2S_CLR_RXC
);
124 regmap_read(i2s
->regmap
, I2S_CLR
, &val
);
126 /* Should wait for clear operation to finish */
128 regmap_read(i2s
->regmap
, I2S_CLR
, &val
);
131 dev_warn(i2s
->dev
, "fail to clear\n");
139 static void rockchip_snd_rxctrl(struct rk_i2s_dev
*i2s
, int on
)
141 unsigned int val
= 0;
145 regmap_update_bits(i2s
->regmap
, I2S_DMACR
,
146 I2S_DMACR_RDE_ENABLE
, I2S_DMACR_RDE_ENABLE
);
148 regmap_update_bits(i2s
->regmap
, I2S_XFER
,
149 I2S_XFER_TXS_START
| I2S_XFER_RXS_START
,
150 I2S_XFER_TXS_START
| I2S_XFER_RXS_START
);
152 i2s
->rx_start
= true;
154 i2s
->rx_start
= false;
156 regmap_update_bits(i2s
->regmap
, I2S_DMACR
,
157 I2S_DMACR_RDE_ENABLE
, I2S_DMACR_RDE_DISABLE
);
159 if (!i2s
->tx_start
) {
160 regmap_update_bits(i2s
->regmap
, I2S_XFER
,
167 regmap_update_bits(i2s
->regmap
, I2S_CLR
,
168 I2S_CLR_TXC
| I2S_CLR_RXC
,
169 I2S_CLR_TXC
| I2S_CLR_RXC
);
171 regmap_read(i2s
->regmap
, I2S_CLR
, &val
);
173 /* Should wait for clear operation to finish */
175 regmap_read(i2s
->regmap
, I2S_CLR
, &val
);
178 dev_warn(i2s
->dev
, "fail to clear\n");
186 static int rockchip_i2s_set_fmt(struct snd_soc_dai
*cpu_dai
,
189 struct rk_i2s_dev
*i2s
= to_info(cpu_dai
);
190 unsigned int mask
= 0, val
= 0;
192 mask
= I2S_CKR_MSS_MASK
;
193 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
194 case SND_SOC_DAIFMT_CBS_CFS
:
195 /* Set source clock in Master mode */
196 val
= I2S_CKR_MSS_MASTER
;
197 i2s
->is_master_mode
= true;
199 case SND_SOC_DAIFMT_CBM_CFM
:
200 val
= I2S_CKR_MSS_SLAVE
;
201 i2s
->is_master_mode
= false;
207 regmap_update_bits(i2s
->regmap
, I2S_CKR
, mask
, val
);
209 mask
= I2S_CKR_CKP_MASK
;
210 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
211 case SND_SOC_DAIFMT_NB_NF
:
212 val
= I2S_CKR_CKP_NEG
;
214 case SND_SOC_DAIFMT_IB_NF
:
215 val
= I2S_CKR_CKP_POS
;
221 regmap_update_bits(i2s
->regmap
, I2S_CKR
, mask
, val
);
223 mask
= I2S_TXCR_IBM_MASK
| I2S_TXCR_TFS_MASK
| I2S_TXCR_PBM_MASK
;
224 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
225 case SND_SOC_DAIFMT_RIGHT_J
:
226 val
= I2S_TXCR_IBM_RSJM
;
228 case SND_SOC_DAIFMT_LEFT_J
:
229 val
= I2S_TXCR_IBM_LSJM
;
231 case SND_SOC_DAIFMT_I2S
:
232 val
= I2S_TXCR_IBM_NORMAL
;
234 case SND_SOC_DAIFMT_DSP_A
: /* PCM no delay mode */
235 val
= I2S_TXCR_TFS_PCM
;
237 case SND_SOC_DAIFMT_DSP_B
: /* PCM delay 1 mode */
238 val
= I2S_TXCR_TFS_PCM
| I2S_TXCR_PBM_MODE(1);
244 regmap_update_bits(i2s
->regmap
, I2S_TXCR
, mask
, val
);
246 mask
= I2S_RXCR_IBM_MASK
| I2S_RXCR_TFS_MASK
| I2S_RXCR_PBM_MASK
;
247 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
248 case SND_SOC_DAIFMT_RIGHT_J
:
249 val
= I2S_RXCR_IBM_RSJM
;
251 case SND_SOC_DAIFMT_LEFT_J
:
252 val
= I2S_RXCR_IBM_LSJM
;
254 case SND_SOC_DAIFMT_I2S
:
255 val
= I2S_RXCR_IBM_NORMAL
;
257 case SND_SOC_DAIFMT_DSP_A
: /* PCM no delay mode */
258 val
= I2S_RXCR_TFS_PCM
;
260 case SND_SOC_DAIFMT_DSP_B
: /* PCM delay 1 mode */
261 val
= I2S_RXCR_TFS_PCM
| I2S_RXCR_PBM_MODE(1);
267 regmap_update_bits(i2s
->regmap
, I2S_RXCR
, mask
, val
);
272 static int rockchip_i2s_hw_params(struct snd_pcm_substream
*substream
,
273 struct snd_pcm_hw_params
*params
,
274 struct snd_soc_dai
*dai
)
276 struct rk_i2s_dev
*i2s
= to_info(dai
);
277 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
278 unsigned int val
= 0;
279 unsigned int mclk_rate
, bclk_rate
, div_bclk
, div_lrck
;
281 if (i2s
->is_master_mode
) {
282 mclk_rate
= clk_get_rate(i2s
->mclk
);
283 bclk_rate
= 2 * 32 * params_rate(params
);
284 if (bclk_rate
&& mclk_rate
% bclk_rate
)
287 div_bclk
= mclk_rate
/ bclk_rate
;
288 div_lrck
= bclk_rate
/ params_rate(params
);
289 regmap_update_bits(i2s
->regmap
, I2S_CKR
,
291 I2S_CKR_MDIV(div_bclk
));
293 regmap_update_bits(i2s
->regmap
, I2S_CKR
,
296 I2S_CKR_TSD(div_lrck
) |
297 I2S_CKR_RSD(div_lrck
));
300 switch (params_format(params
)) {
301 case SNDRV_PCM_FORMAT_S8
:
302 val
|= I2S_TXCR_VDW(8);
304 case SNDRV_PCM_FORMAT_S16_LE
:
305 val
|= I2S_TXCR_VDW(16);
307 case SNDRV_PCM_FORMAT_S20_3LE
:
308 val
|= I2S_TXCR_VDW(20);
310 case SNDRV_PCM_FORMAT_S24_LE
:
311 val
|= I2S_TXCR_VDW(24);
313 case SNDRV_PCM_FORMAT_S32_LE
:
314 val
|= I2S_TXCR_VDW(32);
320 switch (params_channels(params
)) {
335 dev_err(i2s
->dev
, "invalid channel: %d\n",
336 params_channels(params
));
340 if (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
)
341 regmap_update_bits(i2s
->regmap
, I2S_RXCR
,
342 I2S_RXCR_VDW_MASK
| I2S_RXCR_CSR_MASK
,
345 regmap_update_bits(i2s
->regmap
, I2S_TXCR
,
346 I2S_TXCR_VDW_MASK
| I2S_TXCR_CSR_MASK
,
349 if (!IS_ERR(i2s
->grf
) && i2s
->pins
) {
350 regmap_read(i2s
->regmap
, I2S_TXCR
, &val
);
351 val
&= I2S_TXCR_CSR_MASK
;
355 val
= I2S_IO_4CH_OUT_6CH_IN
;
358 val
= I2S_IO_6CH_OUT_4CH_IN
;
361 val
= I2S_IO_8CH_OUT_2CH_IN
;
364 val
= I2S_IO_2CH_OUT_8CH_IN
;
368 val
<<= i2s
->pins
->shift
;
369 val
|= (I2S_IO_DIRECTION_MASK
<< i2s
->pins
->shift
) << 16;
370 regmap_write(i2s
->grf
, i2s
->pins
->reg_offset
, val
);
373 regmap_update_bits(i2s
->regmap
, I2S_DMACR
, I2S_DMACR_TDL_MASK
,
375 regmap_update_bits(i2s
->regmap
, I2S_DMACR
, I2S_DMACR_RDL_MASK
,
378 val
= I2S_CKR_TRCM_TXRX
;
379 if (dai
->driver
->symmetric_rates
&& rtd
->dai_link
->symmetric_rates
)
380 val
= I2S_CKR_TRCM_TXONLY
;
382 regmap_update_bits(i2s
->regmap
, I2S_CKR
,
388 static int rockchip_i2s_trigger(struct snd_pcm_substream
*substream
,
389 int cmd
, struct snd_soc_dai
*dai
)
391 struct rk_i2s_dev
*i2s
= to_info(dai
);
395 case SNDRV_PCM_TRIGGER_START
:
396 case SNDRV_PCM_TRIGGER_RESUME
:
397 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
398 if (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
)
399 rockchip_snd_rxctrl(i2s
, 1);
401 rockchip_snd_txctrl(i2s
, 1);
403 case SNDRV_PCM_TRIGGER_SUSPEND
:
404 case SNDRV_PCM_TRIGGER_STOP
:
405 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
406 if (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
)
407 rockchip_snd_rxctrl(i2s
, 0);
409 rockchip_snd_txctrl(i2s
, 0);
419 static int rockchip_i2s_set_sysclk(struct snd_soc_dai
*cpu_dai
, int clk_id
,
420 unsigned int freq
, int dir
)
422 struct rk_i2s_dev
*i2s
= to_info(cpu_dai
);
425 ret
= clk_set_rate(i2s
->mclk
, freq
);
427 dev_err(i2s
->dev
, "Fail to set mclk %d\n", ret
);
432 static int rockchip_i2s_dai_probe(struct snd_soc_dai
*dai
)
434 struct rk_i2s_dev
*i2s
= snd_soc_dai_get_drvdata(dai
);
436 dai
->capture_dma_data
= &i2s
->capture_dma_data
;
437 dai
->playback_dma_data
= &i2s
->playback_dma_data
;
442 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops
= {
443 .hw_params
= rockchip_i2s_hw_params
,
444 .set_sysclk
= rockchip_i2s_set_sysclk
,
445 .set_fmt
= rockchip_i2s_set_fmt
,
446 .trigger
= rockchip_i2s_trigger
,
449 static struct snd_soc_dai_driver rockchip_i2s_dai
= {
450 .probe
= rockchip_i2s_dai_probe
,
452 .stream_name
= "Playback",
455 .rates
= SNDRV_PCM_RATE_8000_192000
,
456 .formats
= (SNDRV_PCM_FMTBIT_S8
|
457 SNDRV_PCM_FMTBIT_S16_LE
|
458 SNDRV_PCM_FMTBIT_S20_3LE
|
459 SNDRV_PCM_FMTBIT_S24_LE
|
460 SNDRV_PCM_FMTBIT_S32_LE
),
463 .stream_name
= "Capture",
466 .rates
= SNDRV_PCM_RATE_8000_192000
,
467 .formats
= (SNDRV_PCM_FMTBIT_S8
|
468 SNDRV_PCM_FMTBIT_S16_LE
|
469 SNDRV_PCM_FMTBIT_S20_3LE
|
470 SNDRV_PCM_FMTBIT_S24_LE
|
471 SNDRV_PCM_FMTBIT_S32_LE
),
473 .ops
= &rockchip_i2s_dai_ops
,
474 .symmetric_rates
= 1,
477 static const struct snd_soc_component_driver rockchip_i2s_component
= {
481 static bool rockchip_i2s_wr_reg(struct device
*dev
, unsigned int reg
)
498 static bool rockchip_i2s_rd_reg(struct device
*dev
, unsigned int reg
)
518 static bool rockchip_i2s_volatile_reg(struct device
*dev
, unsigned int reg
)
532 static bool rockchip_i2s_precious_reg(struct device
*dev
, unsigned int reg
)
542 static const struct reg_default rockchip_i2s_reg_defaults
[] = {
550 static const struct regmap_config rockchip_i2s_regmap_config
= {
554 .max_register
= I2S_RXDR
,
555 .reg_defaults
= rockchip_i2s_reg_defaults
,
556 .num_reg_defaults
= ARRAY_SIZE(rockchip_i2s_reg_defaults
),
557 .writeable_reg
= rockchip_i2s_wr_reg
,
558 .readable_reg
= rockchip_i2s_rd_reg
,
559 .volatile_reg
= rockchip_i2s_volatile_reg
,
560 .precious_reg
= rockchip_i2s_precious_reg
,
561 .cache_type
= REGCACHE_FLAT
,
564 static const struct rk_i2s_pins rk3399_i2s_pins
= {
565 .reg_offset
= 0xe220,
569 static const struct of_device_id rockchip_i2s_match
[] = {
570 { .compatible
= "rockchip,rk3066-i2s", },
571 { .compatible
= "rockchip,rk3188-i2s", },
572 { .compatible
= "rockchip,rk3288-i2s", },
573 { .compatible
= "rockchip,rk3399-i2s", .data
= &rk3399_i2s_pins
},
577 static int rockchip_i2s_probe(struct platform_device
*pdev
)
579 struct device_node
*node
= pdev
->dev
.of_node
;
580 const struct of_device_id
*of_id
;
581 struct rk_i2s_dev
*i2s
;
582 struct snd_soc_dai_driver
*soc_dai
;
583 struct resource
*res
;
588 i2s
= devm_kzalloc(&pdev
->dev
, sizeof(*i2s
), GFP_KERNEL
);
592 i2s
->dev
= &pdev
->dev
;
594 i2s
->grf
= syscon_regmap_lookup_by_phandle(node
, "rockchip,grf");
595 if (!IS_ERR(i2s
->grf
)) {
596 of_id
= of_match_device(rockchip_i2s_match
, &pdev
->dev
);
597 if (!of_id
|| !of_id
->data
)
600 i2s
->pins
= of_id
->data
;
603 /* try to prepare related clocks */
604 i2s
->hclk
= devm_clk_get(&pdev
->dev
, "i2s_hclk");
605 if (IS_ERR(i2s
->hclk
)) {
606 dev_err(&pdev
->dev
, "Can't retrieve i2s bus clock\n");
607 return PTR_ERR(i2s
->hclk
);
609 ret
= clk_prepare_enable(i2s
->hclk
);
611 dev_err(i2s
->dev
, "hclock enable failed %d\n", ret
);
615 i2s
->mclk
= devm_clk_get(&pdev
->dev
, "i2s_clk");
616 if (IS_ERR(i2s
->mclk
)) {
617 dev_err(&pdev
->dev
, "Can't retrieve i2s master clock\n");
618 return PTR_ERR(i2s
->mclk
);
621 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
622 regs
= devm_ioremap_resource(&pdev
->dev
, res
);
624 return PTR_ERR(regs
);
626 i2s
->regmap
= devm_regmap_init_mmio(&pdev
->dev
, regs
,
627 &rockchip_i2s_regmap_config
);
628 if (IS_ERR(i2s
->regmap
)) {
630 "Failed to initialise managed register map\n");
631 return PTR_ERR(i2s
->regmap
);
634 i2s
->playback_dma_data
.addr
= res
->start
+ I2S_TXDR
;
635 i2s
->playback_dma_data
.addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
636 i2s
->playback_dma_data
.maxburst
= 4;
638 i2s
->capture_dma_data
.addr
= res
->start
+ I2S_RXDR
;
639 i2s
->capture_dma_data
.addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
640 i2s
->capture_dma_data
.maxburst
= 4;
642 dev_set_drvdata(&pdev
->dev
, i2s
);
644 pm_runtime_enable(&pdev
->dev
);
645 if (!pm_runtime_enabled(&pdev
->dev
)) {
646 ret
= i2s_runtime_resume(&pdev
->dev
);
651 soc_dai
= devm_kmemdup(&pdev
->dev
, &rockchip_i2s_dai
,
652 sizeof(*soc_dai
), GFP_KERNEL
);
658 if (!of_property_read_u32(node
, "rockchip,playback-channels", &val
)) {
659 if (val
>= 2 && val
<= 8)
660 soc_dai
->playback
.channels_max
= val
;
663 if (!of_property_read_u32(node
, "rockchip,capture-channels", &val
)) {
664 if (val
>= 1 && val
<= 8)
665 soc_dai
->capture
.channels_max
= val
;
668 ret
= devm_snd_soc_register_component(&pdev
->dev
,
669 &rockchip_i2s_component
,
673 dev_err(&pdev
->dev
, "Could not register DAI\n");
677 ret
= devm_snd_dmaengine_pcm_register(&pdev
->dev
, NULL
, 0);
679 dev_err(&pdev
->dev
, "Could not register PCM\n");
686 if (!pm_runtime_status_suspended(&pdev
->dev
))
687 i2s_runtime_suspend(&pdev
->dev
);
689 pm_runtime_disable(&pdev
->dev
);
694 static int rockchip_i2s_remove(struct platform_device
*pdev
)
696 struct rk_i2s_dev
*i2s
= dev_get_drvdata(&pdev
->dev
);
698 pm_runtime_disable(&pdev
->dev
);
699 if (!pm_runtime_status_suspended(&pdev
->dev
))
700 i2s_runtime_suspend(&pdev
->dev
);
702 clk_disable_unprepare(i2s
->hclk
);
707 static const struct dev_pm_ops rockchip_i2s_pm_ops
= {
708 SET_RUNTIME_PM_OPS(i2s_runtime_suspend
, i2s_runtime_resume
,
712 static struct platform_driver rockchip_i2s_driver
= {
713 .probe
= rockchip_i2s_probe
,
714 .remove
= rockchip_i2s_remove
,
717 .of_match_table
= of_match_ptr(rockchip_i2s_match
),
718 .pm
= &rockchip_i2s_pm_ops
,
721 module_platform_driver(rockchip_i2s_driver
);
723 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
724 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
725 MODULE_LICENSE("GPL v2");
726 MODULE_ALIAS("platform:" DRV_NAME
);
727 MODULE_DEVICE_TABLE(of
, rockchip_i2s_match
);