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mtd: nand_base: use __func__ instead of typing names
[linux/fpc-iii.git] / drivers / s390 / net / qeth_core_main.c
blobd53621c4acbbaca813ddd49e630cbf16582cd58e
1 /*
2 * drivers/s390/net/qeth_core_main.c
3 *
4 * Copyright IBM Corp. 2007, 2009
5 * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
6 * Frank Pavlic <fpavlic@de.ibm.com>,
7 * Thomas Spatzier <tspat@de.ibm.com>,
8 * Frank Blaschka <frank.blaschka@de.ibm.com>
9 */
10
11 #define KMSG_COMPONENT "qeth"
12 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/string.h>
17 #include <linux/errno.h>
18 #include <linux/kernel.h>
19 #include <linux/ip.h>
20 #include <linux/tcp.h>
21 #include <linux/mii.h>
22 #include <linux/kthread.h>
23
24 #include <asm/ebcdic.h>
25 #include <asm/io.h>
26
27 #include "qeth_core.h"
28
29 struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
30 /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
31 /* N P A M L V H */
32 [QETH_DBF_SETUP] = {"qeth_setup",
33 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
34 [QETH_DBF_QERR] = {"qeth_qerr",
35 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
36 [QETH_DBF_TRACE] = {"qeth_trace",
37 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
38 [QETH_DBF_MSG] = {"qeth_msg",
39 8, 1, 128, 3, &debug_sprintf_view, NULL},
40 [QETH_DBF_SENSE] = {"qeth_sense",
41 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
42 [QETH_DBF_MISC] = {"qeth_misc",
43 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
44 [QETH_DBF_CTRL] = {"qeth_control",
45 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
46 };
47 EXPORT_SYMBOL_GPL(qeth_dbf);
48
49 struct qeth_card_list_struct qeth_core_card_list;
50 EXPORT_SYMBOL_GPL(qeth_core_card_list);
51 struct kmem_cache *qeth_core_header_cache;
52 EXPORT_SYMBOL_GPL(qeth_core_header_cache);
53
54 static struct device *qeth_core_root_dev;
55 static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
56 static struct lock_class_key qdio_out_skb_queue_key;
57
58 static void qeth_send_control_data_cb(struct qeth_channel *,
59 struct qeth_cmd_buffer *);
60 static int qeth_issue_next_read(struct qeth_card *);
61 static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
62 static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
63 static void qeth_free_buffer_pool(struct qeth_card *);
64 static int qeth_qdio_establish(struct qeth_card *);
65
66
67 static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
68 struct qdio_buffer *buffer, int is_tso,
69 int *next_element_to_fill)
70 {
71 struct skb_frag_struct *frag;
72 int fragno;
73 unsigned long addr;
74 int element, cnt, dlen;
75
76 fragno = skb_shinfo(skb)->nr_frags;
77 element = *next_element_to_fill;
78 dlen = 0;
79
80 if (is_tso)
81 buffer->element[element].flags =
82 SBAL_FLAGS_MIDDLE_FRAG;
83 else
84 buffer->element[element].flags =
85 SBAL_FLAGS_FIRST_FRAG;
86 dlen = skb->len - skb->data_len;
87 if (dlen) {
88 buffer->element[element].addr = skb->data;
89 buffer->element[element].length = dlen;
90 element++;
91 }
92 for (cnt = 0; cnt < fragno; cnt++) {
93 frag = &skb_shinfo(skb)->frags[cnt];
94 addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
95 frag->page_offset;
96 buffer->element[element].addr = (char *)addr;
97 buffer->element[element].length = frag->size;
98 if (cnt < (fragno - 1))
99 buffer->element[element].flags =
100 SBAL_FLAGS_MIDDLE_FRAG;
101 else
102 buffer->element[element].flags =
103 SBAL_FLAGS_LAST_FRAG;
104 element++;
105 }
106 *next_element_to_fill = element;
107 }
108
109 static inline const char *qeth_get_cardname(struct qeth_card *card)
110 {
111 if (card->info.guestlan) {
112 switch (card->info.type) {
113 case QETH_CARD_TYPE_OSAE:
114 return " Guest LAN QDIO";
115 case QETH_CARD_TYPE_IQD:
116 return " Guest LAN Hiper";
117 default:
118 return " unknown";
119 }
120 } else {
121 switch (card->info.type) {
122 case QETH_CARD_TYPE_OSAE:
123 return " OSD Express";
124 case QETH_CARD_TYPE_IQD:
125 return " HiperSockets";
126 case QETH_CARD_TYPE_OSN:
127 return " OSN QDIO";
128 default:
129 return " unknown";
130 }
131 }
132 return " n/a";
133 }
134
135 /* max length to be returned: 14 */
136 const char *qeth_get_cardname_short(struct qeth_card *card)
137 {
138 if (card->info.guestlan) {
139 switch (card->info.type) {
140 case QETH_CARD_TYPE_OSAE:
141 return "GuestLAN QDIO";
142 case QETH_CARD_TYPE_IQD:
143 return "GuestLAN Hiper";
144 default:
145 return "unknown";
146 }
147 } else {
148 switch (card->info.type) {
149 case QETH_CARD_TYPE_OSAE:
150 switch (card->info.link_type) {
151 case QETH_LINK_TYPE_FAST_ETH:
152 return "OSD_100";
153 case QETH_LINK_TYPE_HSTR:
154 return "HSTR";
155 case QETH_LINK_TYPE_GBIT_ETH:
156 return "OSD_1000";
157 case QETH_LINK_TYPE_10GBIT_ETH:
158 return "OSD_10GIG";
159 case QETH_LINK_TYPE_LANE_ETH100:
160 return "OSD_FE_LANE";
161 case QETH_LINK_TYPE_LANE_TR:
162 return "OSD_TR_LANE";
163 case QETH_LINK_TYPE_LANE_ETH1000:
164 return "OSD_GbE_LANE";
165 case QETH_LINK_TYPE_LANE:
166 return "OSD_ATM_LANE";
167 default:
168 return "OSD_Express";
169 }
170 case QETH_CARD_TYPE_IQD:
171 return "HiperSockets";
172 case QETH_CARD_TYPE_OSN:
173 return "OSN";
174 default:
175 return "unknown";
176 }
177 }
178 return "n/a";
179 }
180
181 void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
182 int clear_start_mask)
183 {
184 unsigned long flags;
185
186 spin_lock_irqsave(&card->thread_mask_lock, flags);
187 card->thread_allowed_mask = threads;
188 if (clear_start_mask)
189 card->thread_start_mask &= threads;
190 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
191 wake_up(&card->wait_q);
192 }
193 EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
194
195 int qeth_threads_running(struct qeth_card *card, unsigned long threads)
196 {
197 unsigned long flags;
198 int rc = 0;
199
200 spin_lock_irqsave(&card->thread_mask_lock, flags);
201 rc = (card->thread_running_mask & threads);
202 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
203 return rc;
204 }
205 EXPORT_SYMBOL_GPL(qeth_threads_running);
206
207 int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
208 {
209 return wait_event_interruptible(card->wait_q,
210 qeth_threads_running(card, threads) == 0);
211 }
212 EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
213
214 void qeth_clear_working_pool_list(struct qeth_card *card)
215 {
216 struct qeth_buffer_pool_entry *pool_entry, *tmp;
217
218 QETH_DBF_TEXT(TRACE, 5, "clwrklst");
219 list_for_each_entry_safe(pool_entry, tmp,
220 &card->qdio.in_buf_pool.entry_list, list){
221 list_del(&pool_entry->list);
222 }
223 }
224 EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
225
226 static int qeth_alloc_buffer_pool(struct qeth_card *card)
227 {
228 struct qeth_buffer_pool_entry *pool_entry;
229 void *ptr;
230 int i, j;
231
232 QETH_DBF_TEXT(TRACE, 5, "alocpool");
233 for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
234 pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
235 if (!pool_entry) {
236 qeth_free_buffer_pool(card);
237 return -ENOMEM;
238 }
239 for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
240 ptr = (void *) __get_free_page(GFP_KERNEL);
241 if (!ptr) {
242 while (j > 0)
243 free_page((unsigned long)
244 pool_entry->elements[--j]);
245 kfree(pool_entry);
246 qeth_free_buffer_pool(card);
247 return -ENOMEM;
248 }
249 pool_entry->elements[j] = ptr;
250 }
251 list_add(&pool_entry->init_list,
252 &card->qdio.init_pool.entry_list);
253 }
254 return 0;
255 }
256
257 int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
258 {
259 QETH_DBF_TEXT(TRACE, 2, "realcbp");
260
261 if ((card->state != CARD_STATE_DOWN) &&
262 (card->state != CARD_STATE_RECOVER))
263 return -EPERM;
264
265 /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
266 qeth_clear_working_pool_list(card);
267 qeth_free_buffer_pool(card);
268 card->qdio.in_buf_pool.buf_count = bufcnt;
269 card->qdio.init_pool.buf_count = bufcnt;
270 return qeth_alloc_buffer_pool(card);
271 }
272
273 int qeth_set_large_send(struct qeth_card *card,
274 enum qeth_large_send_types type)
275 {
276 int rc = 0;
277
278 if (card->dev == NULL) {
279 card->options.large_send = type;
280 return 0;
281 }
282 if (card->state == CARD_STATE_UP)
283 netif_tx_disable(card->dev);
284 card->options.large_send = type;
285 switch (card->options.large_send) {
286 case QETH_LARGE_SEND_TSO:
287 if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
288 card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
289 NETIF_F_HW_CSUM;
290 } else {
291 card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
292 NETIF_F_HW_CSUM);
293 card->options.large_send = QETH_LARGE_SEND_NO;
294 rc = -EOPNOTSUPP;
295 }
296 break;
297 default: /* includes QETH_LARGE_SEND_NO */
298 card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
299 NETIF_F_HW_CSUM);
300 break;
301 }
302 if (card->state == CARD_STATE_UP)
303 netif_wake_queue(card->dev);
304 return rc;
305 }
306 EXPORT_SYMBOL_GPL(qeth_set_large_send);
307
308 static int qeth_issue_next_read(struct qeth_card *card)
309 {
310 int rc;
311 struct qeth_cmd_buffer *iob;
312
313 QETH_DBF_TEXT(TRACE, 5, "issnxrd");
314 if (card->read.state != CH_STATE_UP)
315 return -EIO;
316 iob = qeth_get_buffer(&card->read);
317 if (!iob) {
318 dev_warn(&card->gdev->dev, "The qeth device driver "
319 "failed to recover an error on the device\n");
320 QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
321 "available\n", dev_name(&card->gdev->dev));
322 return -ENOMEM;
323 }
324 qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
325 QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
326 rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
327 (addr_t) iob, 0, 0);
328 if (rc) {
329 QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
330 "rc=%i\n", dev_name(&card->gdev->dev), rc);
331 atomic_set(&card->read.irq_pending, 0);
332 qeth_schedule_recovery(card);
333 wake_up(&card->wait_q);
334 }
335 return rc;
336 }
337
338 static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
339 {
340 struct qeth_reply *reply;
341
342 reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
343 if (reply) {
344 atomic_set(&reply->refcnt, 1);
345 atomic_set(&reply->received, 0);
346 reply->card = card;
347 };
348 return reply;
349 }
350
351 static void qeth_get_reply(struct qeth_reply *reply)
352 {
353 WARN_ON(atomic_read(&reply->refcnt) <= 0);
354 atomic_inc(&reply->refcnt);
355 }
356
357 static void qeth_put_reply(struct qeth_reply *reply)
358 {
359 WARN_ON(atomic_read(&reply->refcnt) <= 0);
360 if (atomic_dec_and_test(&reply->refcnt))
361 kfree(reply);
362 }
363
364 static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
365 struct qeth_card *card)
366 {
367 char *ipa_name;
368 int com = cmd->hdr.command;
369 ipa_name = qeth_get_ipa_cmd_name(com);
370 if (rc)
371 QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
372 ipa_name, com, QETH_CARD_IFNAME(card),
373 rc, qeth_get_ipa_msg(rc));
374 else
375 QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
376 ipa_name, com, QETH_CARD_IFNAME(card));
377 }
378
379 static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
380 struct qeth_cmd_buffer *iob)
381 {
382 struct qeth_ipa_cmd *cmd = NULL;
383
384 QETH_DBF_TEXT(TRACE, 5, "chkipad");
385 if (IS_IPA(iob->data)) {
386 cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
387 if (IS_IPA_REPLY(cmd)) {
388 if (cmd->hdr.command < IPA_CMD_SETCCID ||
389 cmd->hdr.command > IPA_CMD_MODCCID)
390 qeth_issue_ipa_msg(cmd,
391 cmd->hdr.return_code, card);
392 return cmd;
393 } else {
394 switch (cmd->hdr.command) {
395 case IPA_CMD_STOPLAN:
396 dev_warn(&card->gdev->dev,
397 "The link for interface %s on CHPID"
398 " 0x%X failed\n",
399 QETH_CARD_IFNAME(card),
400 card->info.chpid);
401 card->lan_online = 0;
402 if (card->dev && netif_carrier_ok(card->dev))
403 netif_carrier_off(card->dev);
404 return NULL;
405 case IPA_CMD_STARTLAN:
406 dev_info(&card->gdev->dev,
407 "The link for %s on CHPID 0x%X has"
408 " been restored\n",
409 QETH_CARD_IFNAME(card),
410 card->info.chpid);
411 netif_carrier_on(card->dev);
412 card->lan_online = 1;
413 qeth_schedule_recovery(card);
414 return NULL;
415 case IPA_CMD_MODCCID:
416 return cmd;
417 case IPA_CMD_REGISTER_LOCAL_ADDR:
418 QETH_DBF_TEXT(TRACE, 3, "irla");
419 break;
420 case IPA_CMD_UNREGISTER_LOCAL_ADDR:
421 QETH_DBF_TEXT(TRACE, 3, "urla");
422 break;
423 default:
424 QETH_DBF_MESSAGE(2, "Received data is IPA "
425 "but not a reply!\n");
426 break;
427 }
428 }
429 }
430 return cmd;
431 }
432
433 void qeth_clear_ipacmd_list(struct qeth_card *card)
434 {
435 struct qeth_reply *reply, *r;
436 unsigned long flags;
437
438 QETH_DBF_TEXT(TRACE, 4, "clipalst");
439
440 spin_lock_irqsave(&card->lock, flags);
441 list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
442 qeth_get_reply(reply);
443 reply->rc = -EIO;
444 atomic_inc(&reply->received);
445 list_del_init(&reply->list);
446 wake_up(&reply->wait_q);
447 qeth_put_reply(reply);
448 }
449 spin_unlock_irqrestore(&card->lock, flags);
450 }
451 EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
452
453 static int qeth_check_idx_response(unsigned char *buffer)
454 {
455 if (!buffer)
456 return 0;
457
458 QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
459 if ((buffer[2] & 0xc0) == 0xc0) {
460 QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
461 "with cause code 0x%02x%s\n",
462 buffer[4],
463 ((buffer[4] == 0x22) ?
464 " -- try another portname" : ""));
465 QETH_DBF_TEXT(TRACE, 2, "ckidxres");
466 QETH_DBF_TEXT(TRACE, 2, " idxterm");
467 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
468 return -EIO;
469 }
470 return 0;
471 }
472
473 static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
474 __u32 len)
475 {
476 struct qeth_card *card;
477
478 QETH_DBF_TEXT(TRACE, 4, "setupccw");
479 card = CARD_FROM_CDEV(channel->ccwdev);
480 if (channel == &card->read)
481 memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
482 else
483 memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
484 channel->ccw.count = len;
485 channel->ccw.cda = (__u32) __pa(iob);
486 }
487
488 static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
489 {
490 __u8 index;
491
492 QETH_DBF_TEXT(TRACE, 6, "getbuff");
493 index = channel->io_buf_no;
494 do {
495 if (channel->iob[index].state == BUF_STATE_FREE) {
496 channel->iob[index].state = BUF_STATE_LOCKED;
497 channel->io_buf_no = (channel->io_buf_no + 1) %
498 QETH_CMD_BUFFER_NO;
499 memset(channel->iob[index].data, 0, QETH_BUFSIZE);
500 return channel->iob + index;
501 }
502 index = (index + 1) % QETH_CMD_BUFFER_NO;
503 } while (index != channel->io_buf_no);
504
505 return NULL;
506 }
507
508 void qeth_release_buffer(struct qeth_channel *channel,
509 struct qeth_cmd_buffer *iob)
510 {
511 unsigned long flags;
512
513 QETH_DBF_TEXT(TRACE, 6, "relbuff");
514 spin_lock_irqsave(&channel->iob_lock, flags);
515 memset(iob->data, 0, QETH_BUFSIZE);
516 iob->state = BUF_STATE_FREE;
517 iob->callback = qeth_send_control_data_cb;
518 iob->rc = 0;
519 spin_unlock_irqrestore(&channel->iob_lock, flags);
520 }
521 EXPORT_SYMBOL_GPL(qeth_release_buffer);
522
523 static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
524 {
525 struct qeth_cmd_buffer *buffer = NULL;
526 unsigned long flags;
527
528 spin_lock_irqsave(&channel->iob_lock, flags);
529 buffer = __qeth_get_buffer(channel);
530 spin_unlock_irqrestore(&channel->iob_lock, flags);
531 return buffer;
532 }
533
534 struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
535 {
536 struct qeth_cmd_buffer *buffer;
537 wait_event(channel->wait_q,
538 ((buffer = qeth_get_buffer(channel)) != NULL));
539 return buffer;
540 }
541 EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
542
543 void qeth_clear_cmd_buffers(struct qeth_channel *channel)
544 {
545 int cnt;
546
547 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
548 qeth_release_buffer(channel, &channel->iob[cnt]);
549 channel->buf_no = 0;
550 channel->io_buf_no = 0;
551 }
552 EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
553
554 static void qeth_send_control_data_cb(struct qeth_channel *channel,
555 struct qeth_cmd_buffer *iob)
556 {
557 struct qeth_card *card;
558 struct qeth_reply *reply, *r;
559 struct qeth_ipa_cmd *cmd;
560 unsigned long flags;
561 int keep_reply;
562
563 QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
564
565 card = CARD_FROM_CDEV(channel->ccwdev);
566 if (qeth_check_idx_response(iob->data)) {
567 qeth_clear_ipacmd_list(card);
568 if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6)
569 dev_err(&card->gdev->dev,
570 "The qeth device is not configured "
571 "for the OSI layer required by z/VM\n");
572 qeth_schedule_recovery(card);
573 goto out;
574 }
575
576 cmd = qeth_check_ipa_data(card, iob);
577 if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
578 goto out;
579 /*in case of OSN : check if cmd is set */
580 if (card->info.type == QETH_CARD_TYPE_OSN &&
581 cmd &&
582 cmd->hdr.command != IPA_CMD_STARTLAN &&
583 card->osn_info.assist_cb != NULL) {
584 card->osn_info.assist_cb(card->dev, cmd);
585 goto out;
586 }
587
588 spin_lock_irqsave(&card->lock, flags);
589 list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
590 if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
591 ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
592 qeth_get_reply(reply);
593 list_del_init(&reply->list);
594 spin_unlock_irqrestore(&card->lock, flags);
595 keep_reply = 0;
596 if (reply->callback != NULL) {
597 if (cmd) {
598 reply->offset = (__u16)((char *)cmd -
599 (char *)iob->data);
600 keep_reply = reply->callback(card,
601 reply,
602 (unsigned long)cmd);
603 } else
604 keep_reply = reply->callback(card,
605 reply,
606 (unsigned long)iob);
607 }
608 if (cmd)
609 reply->rc = (u16) cmd->hdr.return_code;
610 else if (iob->rc)
611 reply->rc = iob->rc;
612 if (keep_reply) {
613 spin_lock_irqsave(&card->lock, flags);
614 list_add_tail(&reply->list,
615 &card->cmd_waiter_list);
616 spin_unlock_irqrestore(&card->lock, flags);
617 } else {
618 atomic_inc(&reply->received);
619 wake_up(&reply->wait_q);
620 }
621 qeth_put_reply(reply);
622 goto out;
623 }
624 }
625 spin_unlock_irqrestore(&card->lock, flags);
626 out:
627 memcpy(&card->seqno.pdu_hdr_ack,
628 QETH_PDU_HEADER_SEQ_NO(iob->data),
629 QETH_SEQ_NO_LENGTH);
630 qeth_release_buffer(channel, iob);
631 }
632
633 static int qeth_setup_channel(struct qeth_channel *channel)
634 {
635 int cnt;
636
637 QETH_DBF_TEXT(SETUP, 2, "setupch");
638 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
639 channel->iob[cnt].data = (char *)
640 kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
641 if (channel->iob[cnt].data == NULL)
642 break;
643 channel->iob[cnt].state = BUF_STATE_FREE;
644 channel->iob[cnt].channel = channel;
645 channel->iob[cnt].callback = qeth_send_control_data_cb;
646 channel->iob[cnt].rc = 0;
647 }
648 if (cnt < QETH_CMD_BUFFER_NO) {
649 while (cnt-- > 0)
650 kfree(channel->iob[cnt].data);
651 return -ENOMEM;
652 }
653 channel->buf_no = 0;
654 channel->io_buf_no = 0;
655 atomic_set(&channel->irq_pending, 0);
656 spin_lock_init(&channel->iob_lock);
657
658 init_waitqueue_head(&channel->wait_q);
659 return 0;
660 }
661
662 static int qeth_set_thread_start_bit(struct qeth_card *card,
663 unsigned long thread)
664 {
665 unsigned long flags;
666
667 spin_lock_irqsave(&card->thread_mask_lock, flags);
668 if (!(card->thread_allowed_mask & thread) ||
669 (card->thread_start_mask & thread)) {
670 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
671 return -EPERM;
672 }
673 card->thread_start_mask |= thread;
674 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
675 return 0;
676 }
677
678 void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
679 {
680 unsigned long flags;
681
682 spin_lock_irqsave(&card->thread_mask_lock, flags);
683 card->thread_start_mask &= ~thread;
684 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
685 wake_up(&card->wait_q);
686 }
687 EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
688
689 void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
690 {
691 unsigned long flags;
692
693 spin_lock_irqsave(&card->thread_mask_lock, flags);
694 card->thread_running_mask &= ~thread;
695 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
696 wake_up(&card->wait_q);
697 }
698 EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
699
700 static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
701 {
702 unsigned long flags;
703 int rc = 0;
704
705 spin_lock_irqsave(&card->thread_mask_lock, flags);
706 if (card->thread_start_mask & thread) {
707 if ((card->thread_allowed_mask & thread) &&
708 !(card->thread_running_mask & thread)) {
709 rc = 1;
710 card->thread_start_mask &= ~thread;
711 card->thread_running_mask |= thread;
712 } else
713 rc = -EPERM;
714 }
715 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
716 return rc;
717 }
718
719 int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
720 {
721 int rc = 0;
722
723 wait_event(card->wait_q,
724 (rc = __qeth_do_run_thread(card, thread)) >= 0);
725 return rc;
726 }
727 EXPORT_SYMBOL_GPL(qeth_do_run_thread);
728
729 void qeth_schedule_recovery(struct qeth_card *card)
730 {
731 QETH_DBF_TEXT(TRACE, 2, "startrec");
732 if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
733 schedule_work(&card->kernel_thread_starter);
734 }
735 EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
736
737 static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
738 {
739 int dstat, cstat;
740 char *sense;
741
742 sense = (char *) irb->ecw;
743 cstat = irb->scsw.cmd.cstat;
744 dstat = irb->scsw.cmd.dstat;
745
746 if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
747 SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
748 SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
749 QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
750 dev_warn(&cdev->dev, "The qeth device driver "
751 "failed to recover an error on the device\n");
752 QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ",
753 dev_name(&cdev->dev), dstat, cstat);
754 print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
755 16, 1, irb, 64, 1);
756 return 1;
757 }
758
759 if (dstat & DEV_STAT_UNIT_CHECK) {
760 if (sense[SENSE_RESETTING_EVENT_BYTE] &
761 SENSE_RESETTING_EVENT_FLAG) {
762 QETH_DBF_TEXT(TRACE, 2, "REVIND");
763 return 1;
764 }
765 if (sense[SENSE_COMMAND_REJECT_BYTE] &
766 SENSE_COMMAND_REJECT_FLAG) {
767 QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
768 return 1;
769 }
770 if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
771 QETH_DBF_TEXT(TRACE, 2, "AFFE");
772 return 1;
773 }
774 if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
775 QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
776 return 0;
777 }
778 QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
779 return 1;
780 }
781 return 0;
782 }
783
784 static long __qeth_check_irb_error(struct ccw_device *cdev,
785 unsigned long intparm, struct irb *irb)
786 {
787 if (!IS_ERR(irb))
788 return 0;
789
790 switch (PTR_ERR(irb)) {
791 case -EIO:
792 QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
793 dev_name(&cdev->dev));
794 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
795 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
796 break;
797 case -ETIMEDOUT:
798 dev_warn(&cdev->dev, "A hardware operation timed out"
799 " on the device\n");
800 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
801 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
802 if (intparm == QETH_RCD_PARM) {
803 struct qeth_card *card = CARD_FROM_CDEV(cdev);
804
805 if (card && (card->data.ccwdev == cdev)) {
806 card->data.state = CH_STATE_DOWN;
807 wake_up(&card->wait_q);
808 }
809 }
810 break;
811 default:
812 QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
813 dev_name(&cdev->dev), PTR_ERR(irb));
814 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
815 QETH_DBF_TEXT(TRACE, 2, " rc???");
816 }
817 return PTR_ERR(irb);
818 }
819
820 static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
821 struct irb *irb)
822 {
823 int rc;
824 int cstat, dstat;
825 struct qeth_cmd_buffer *buffer;
826 struct qeth_channel *channel;
827 struct qeth_card *card;
828 struct qeth_cmd_buffer *iob;
829 __u8 index;
830
831 QETH_DBF_TEXT(TRACE, 5, "irq");
832
833 if (__qeth_check_irb_error(cdev, intparm, irb))
834 return;
835 cstat = irb->scsw.cmd.cstat;
836 dstat = irb->scsw.cmd.dstat;
837
838 card = CARD_FROM_CDEV(cdev);
839 if (!card)
840 return;
841
842 if (card->read.ccwdev == cdev) {
843 channel = &card->read;
844 QETH_DBF_TEXT(TRACE, 5, "read");
845 } else if (card->write.ccwdev == cdev) {
846 channel = &card->write;
847 QETH_DBF_TEXT(TRACE, 5, "write");
848 } else {
849 channel = &card->data;
850 QETH_DBF_TEXT(TRACE, 5, "data");
851 }
852 atomic_set(&channel->irq_pending, 0);
853
854 if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
855 channel->state = CH_STATE_STOPPED;
856
857 if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
858 channel->state = CH_STATE_HALTED;
859
860 /*let's wake up immediately on data channel*/
861 if ((channel == &card->data) && (intparm != 0) &&
862 (intparm != QETH_RCD_PARM))
863 goto out;
864
865 if (intparm == QETH_CLEAR_CHANNEL_PARM) {
866 QETH_DBF_TEXT(TRACE, 6, "clrchpar");
867 /* we don't have to handle this further */
868 intparm = 0;
869 }
870 if (intparm == QETH_HALT_CHANNEL_PARM) {
871 QETH_DBF_TEXT(TRACE, 6, "hltchpar");
872 /* we don't have to handle this further */
873 intparm = 0;
874 }
875 if ((dstat & DEV_STAT_UNIT_EXCEP) ||
876 (dstat & DEV_STAT_UNIT_CHECK) ||
877 (cstat)) {
878 if (irb->esw.esw0.erw.cons) {
879 dev_warn(&channel->ccwdev->dev,
880 "The qeth device driver failed to recover "
881 "an error on the device\n");
882 QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
883 "0x%X dstat 0x%X\n",
884 dev_name(&channel->ccwdev->dev), cstat, dstat);
885 print_hex_dump(KERN_WARNING, "qeth: irb ",
886 DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
887 print_hex_dump(KERN_WARNING, "qeth: sense data ",
888 DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
889 }
890 if (intparm == QETH_RCD_PARM) {
891 channel->state = CH_STATE_DOWN;
892 goto out;
893 }
894 rc = qeth_get_problem(cdev, irb);
895 if (rc) {
896 qeth_clear_ipacmd_list(card);
897 qeth_schedule_recovery(card);
898 goto out;
899 }
900 }
901
902 if (intparm == QETH_RCD_PARM) {
903 channel->state = CH_STATE_RCD_DONE;
904 goto out;
905 }
906 if (intparm) {
907 buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
908 buffer->state = BUF_STATE_PROCESSED;
909 }
910 if (channel == &card->data)
911 return;
912 if (channel == &card->read &&
913 channel->state == CH_STATE_UP)
914 qeth_issue_next_read(card);
915
916 iob = channel->iob;
917 index = channel->buf_no;
918 while (iob[index].state == BUF_STATE_PROCESSED) {
919 if (iob[index].callback != NULL)
920 iob[index].callback(channel, iob + index);
921
922 index = (index + 1) % QETH_CMD_BUFFER_NO;
923 }
924 channel->buf_no = index;
925 out:
926 wake_up(&card->wait_q);
927 return;
928 }
929
930 static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
931 struct qeth_qdio_out_buffer *buf)
932 {
933 int i;
934 struct sk_buff *skb;
935
936 /* is PCI flag set on buffer? */
937 if (buf->buffer->element[0].flags & 0x40)
938 atomic_dec(&queue->set_pci_flags_count);
939
940 skb = skb_dequeue(&buf->skb_list);
941 while (skb) {
942 atomic_dec(&skb->users);
943 dev_kfree_skb_any(skb);
944 skb = skb_dequeue(&buf->skb_list);
945 }
946 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
947 if (buf->buffer->element[i].addr && buf->is_header[i])
948 kmem_cache_free(qeth_core_header_cache,
949 buf->buffer->element[i].addr);
950 buf->is_header[i] = 0;
951 buf->buffer->element[i].length = 0;
952 buf->buffer->element[i].addr = NULL;
953 buf->buffer->element[i].flags = 0;
954 }
955 buf->buffer->element[15].flags = 0;
956 buf->next_element_to_fill = 0;
957 atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
958 }
959
960 void qeth_clear_qdio_buffers(struct qeth_card *card)
961 {
962 int i, j;
963
964 QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
965 /* clear outbound buffers to free skbs */
966 for (i = 0; i < card->qdio.no_out_queues; ++i)
967 if (card->qdio.out_qs[i]) {
968 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
969 qeth_clear_output_buffer(card->qdio.out_qs[i],
970 &card->qdio.out_qs[i]->bufs[j]);
971 }
972 }
973 EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
974
975 static void qeth_free_buffer_pool(struct qeth_card *card)
976 {
977 struct qeth_buffer_pool_entry *pool_entry, *tmp;
978 int i = 0;
979 QETH_DBF_TEXT(TRACE, 5, "freepool");
980 list_for_each_entry_safe(pool_entry, tmp,
981 &card->qdio.init_pool.entry_list, init_list){
982 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
983 free_page((unsigned long)pool_entry->elements[i]);
984 list_del(&pool_entry->init_list);
985 kfree(pool_entry);
986 }
987 }
988
989 static void qeth_free_qdio_buffers(struct qeth_card *card)
990 {
991 int i, j;
992
993 QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
994 if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
995 QETH_QDIO_UNINITIALIZED)
996 return;
997 kfree(card->qdio.in_q);
998 card->qdio.in_q = NULL;
999 /* inbound buffer pool */
1000 qeth_free_buffer_pool(card);
1001 /* free outbound qdio_qs */
1002 if (card->qdio.out_qs) {
1003 for (i = 0; i < card->qdio.no_out_queues; ++i) {
1004 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
1005 qeth_clear_output_buffer(card->qdio.out_qs[i],
1006 &card->qdio.out_qs[i]->bufs[j]);
1007 kfree(card->qdio.out_qs[i]);
1008 }
1009 kfree(card->qdio.out_qs);
1010 card->qdio.out_qs = NULL;
1011 }
1012 }
1013
1014 static void qeth_clean_channel(struct qeth_channel *channel)
1015 {
1016 int cnt;
1017
1018 QETH_DBF_TEXT(SETUP, 2, "freech");
1019 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
1020 kfree(channel->iob[cnt].data);
1021 }
1022
1023 static int qeth_is_1920_device(struct qeth_card *card)
1024 {
1025 int single_queue = 0;
1026 struct ccw_device *ccwdev;
1027 struct channelPath_dsc {
1028 u8 flags;
1029 u8 lsn;
1030 u8 desc;
1031 u8 chpid;
1032 u8 swla;
1033 u8 zeroes;
1034 u8 chla;
1035 u8 chpp;
1036 } *chp_dsc;
1037
1038 QETH_DBF_TEXT(SETUP, 2, "chk_1920");
1039
1040 ccwdev = card->data.ccwdev;
1041 chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
1042 if (chp_dsc != NULL) {
1043 /* CHPP field bit 6 == 1 -> single queue */
1044 single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
1045 kfree(chp_dsc);
1046 }
1047 QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
1048 return single_queue;
1049 }
1050
1051 static void qeth_init_qdio_info(struct qeth_card *card)
1052 {
1053 QETH_DBF_TEXT(SETUP, 4, "intqdinf");
1054 atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
1055 /* inbound */
1056 card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
1057 card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
1058 card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
1059 INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
1060 INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
1061 }
1062
1063 static void qeth_set_intial_options(struct qeth_card *card)
1064 {
1065 card->options.route4.type = NO_ROUTER;
1066 card->options.route6.type = NO_ROUTER;
1067 card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
1068 card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
1069 card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
1070 card->options.fake_broadcast = 0;
1071 card->options.add_hhlen = DEFAULT_ADD_HHLEN;
1072 card->options.performance_stats = 0;
1073 card->options.rx_sg_cb = QETH_RX_SG_CB;
1074 }
1075
1076 static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
1077 {
1078 unsigned long flags;
1079 int rc = 0;
1080
1081 spin_lock_irqsave(&card->thread_mask_lock, flags);
1082 QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
1083 (u8) card->thread_start_mask,
1084 (u8) card->thread_allowed_mask,
1085 (u8) card->thread_running_mask);
1086 rc = (card->thread_start_mask & thread);
1087 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
1088 return rc;
1089 }
1090
1091 static void qeth_start_kernel_thread(struct work_struct *work)
1092 {
1093 struct qeth_card *card = container_of(work, struct qeth_card,
1094 kernel_thread_starter);
1095 QETH_DBF_TEXT(TRACE , 2, "strthrd");
1096
1097 if (card->read.state != CH_STATE_UP &&
1098 card->write.state != CH_STATE_UP)
1099 return;
1100 if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
1101 kthread_run(card->discipline.recover, (void *) card,
1102 "qeth_recover");
1103 }
1104
1105 static int qeth_setup_card(struct qeth_card *card)
1106 {
1107
1108 QETH_DBF_TEXT(SETUP, 2, "setupcrd");
1109 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
1110
1111 card->read.state = CH_STATE_DOWN;
1112 card->write.state = CH_STATE_DOWN;
1113 card->data.state = CH_STATE_DOWN;
1114 card->state = CARD_STATE_DOWN;
1115 card->lan_online = 0;
1116 card->use_hard_stop = 0;
1117 card->dev = NULL;
1118 spin_lock_init(&card->vlanlock);
1119 spin_lock_init(&card->mclock);
1120 card->vlangrp = NULL;
1121 spin_lock_init(&card->lock);
1122 spin_lock_init(&card->ip_lock);
1123 spin_lock_init(&card->thread_mask_lock);
1124 card->thread_start_mask = 0;
1125 card->thread_allowed_mask = 0;
1126 card->thread_running_mask = 0;
1127 INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
1128 INIT_LIST_HEAD(&card->ip_list);
1129 card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
1130 if (!card->ip_tbd_list) {
1131 QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
1132 return -ENOMEM;
1133 }
1134 INIT_LIST_HEAD(card->ip_tbd_list);
1135 INIT_LIST_HEAD(&card->cmd_waiter_list);
1136 init_waitqueue_head(&card->wait_q);
1137 /* intial options */
1138 qeth_set_intial_options(card);
1139 /* IP address takeover */
1140 INIT_LIST_HEAD(&card->ipato.entries);
1141 card->ipato.enabled = 0;
1142 card->ipato.invert4 = 0;
1143 card->ipato.invert6 = 0;
1144 if (card->info.type == QETH_CARD_TYPE_IQD)
1145 card->options.checksum_type = NO_CHECKSUMMING;
1146 /* init QDIO stuff */
1147 qeth_init_qdio_info(card);
1148 return 0;
1149 }
1150
1151 static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
1152 {
1153 struct qeth_card *card = container_of(slr, struct qeth_card,
1154 qeth_service_level);
1155 seq_printf(m, "qeth: %s firmware level %s\n", CARD_BUS_ID(card),
1156 card->info.mcl_level);
1157 }
1158
1159 static struct qeth_card *qeth_alloc_card(void)
1160 {
1161 struct qeth_card *card;
1162
1163 QETH_DBF_TEXT(SETUP, 2, "alloccrd");
1164 card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
1165 if (!card)
1166 return NULL;
1167 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
1168 if (qeth_setup_channel(&card->read)) {
1169 kfree(card);
1170 return NULL;
1171 }
1172 if (qeth_setup_channel(&card->write)) {
1173 qeth_clean_channel(&card->read);
1174 kfree(card);
1175 return NULL;
1176 }
1177 card->options.layer2 = -1;
1178 card->qeth_service_level.seq_print = qeth_core_sl_print;
1179 register_service_level(&card->qeth_service_level);
1180 return card;
1181 }
1182
1183 static int qeth_determine_card_type(struct qeth_card *card)
1184 {
1185 int i = 0;
1186
1187 QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
1188
1189 card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
1190 card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
1191 while (known_devices[i][4]) {
1192 if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
1193 (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
1194 card->info.type = known_devices[i][4];
1195 card->qdio.no_out_queues = known_devices[i][8];
1196 card->info.is_multicast_different = known_devices[i][9];
1197 if (qeth_is_1920_device(card)) {
1198 dev_info(&card->gdev->dev,
1199 "Priority Queueing not supported\n");
1200 card->qdio.no_out_queues = 1;
1201 card->qdio.default_out_queue = 0;
1202 }
1203 return 0;
1204 }
1205 i++;
1206 }
1207 card->info.type = QETH_CARD_TYPE_UNKNOWN;
1208 dev_err(&card->gdev->dev, "The adapter hardware is of an "
1209 "unknown type\n");
1210 return -ENOENT;
1211 }
1212
1213 static int qeth_clear_channel(struct qeth_channel *channel)
1214 {
1215 unsigned long flags;
1216 struct qeth_card *card;
1217 int rc;
1218
1219 QETH_DBF_TEXT(TRACE, 3, "clearch");
1220 card = CARD_FROM_CDEV(channel->ccwdev);
1221 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1222 rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
1223 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1224
1225 if (rc)
1226 return rc;
1227 rc = wait_event_interruptible_timeout(card->wait_q,
1228 channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
1229 if (rc == -ERESTARTSYS)
1230 return rc;
1231 if (channel->state != CH_STATE_STOPPED)
1232 return -ETIME;
1233 channel->state = CH_STATE_DOWN;
1234 return 0;
1235 }
1236
1237 static int qeth_halt_channel(struct qeth_channel *channel)
1238 {
1239 unsigned long flags;
1240 struct qeth_card *card;
1241 int rc;
1242
1243 QETH_DBF_TEXT(TRACE, 3, "haltch");
1244 card = CARD_FROM_CDEV(channel->ccwdev);
1245 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1246 rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
1247 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1248
1249 if (rc)
1250 return rc;
1251 rc = wait_event_interruptible_timeout(card->wait_q,
1252 channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
1253 if (rc == -ERESTARTSYS)
1254 return rc;
1255 if (channel->state != CH_STATE_HALTED)
1256 return -ETIME;
1257 return 0;
1258 }
1259
1260 static int qeth_halt_channels(struct qeth_card *card)
1261 {
1262 int rc1 = 0, rc2 = 0, rc3 = 0;
1263
1264 QETH_DBF_TEXT(TRACE, 3, "haltchs");
1265 rc1 = qeth_halt_channel(&card->read);
1266 rc2 = qeth_halt_channel(&card->write);
1267 rc3 = qeth_halt_channel(&card->data);
1268 if (rc1)
1269 return rc1;
1270 if (rc2)
1271 return rc2;
1272 return rc3;
1273 }
1274
1275 static int qeth_clear_channels(struct qeth_card *card)
1276 {
1277 int rc1 = 0, rc2 = 0, rc3 = 0;
1278
1279 QETH_DBF_TEXT(TRACE, 3, "clearchs");
1280 rc1 = qeth_clear_channel(&card->read);
1281 rc2 = qeth_clear_channel(&card->write);
1282 rc3 = qeth_clear_channel(&card->data);
1283 if (rc1)
1284 return rc1;
1285 if (rc2)
1286 return rc2;
1287 return rc3;
1288 }
1289
1290 static int qeth_clear_halt_card(struct qeth_card *card, int halt)
1291 {
1292 int rc = 0;
1293
1294 QETH_DBF_TEXT(TRACE, 3, "clhacrd");
1295 QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
1296
1297 if (halt)
1298 rc = qeth_halt_channels(card);
1299 if (rc)
1300 return rc;
1301 return qeth_clear_channels(card);
1302 }
1303
1304 int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
1305 {
1306 int rc = 0;
1307
1308 QETH_DBF_TEXT(TRACE, 3, "qdioclr");
1309 switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
1310 QETH_QDIO_CLEANING)) {
1311 case QETH_QDIO_ESTABLISHED:
1312 if (card->info.type == QETH_CARD_TYPE_IQD)
1313 rc = qdio_cleanup(CARD_DDEV(card),
1314 QDIO_FLAG_CLEANUP_USING_HALT);
1315 else
1316 rc = qdio_cleanup(CARD_DDEV(card),
1317 QDIO_FLAG_CLEANUP_USING_CLEAR);
1318 if (rc)
1319 QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
1320 atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
1321 break;
1322 case QETH_QDIO_CLEANING:
1323 return rc;
1324 default:
1325 break;
1326 }
1327 rc = qeth_clear_halt_card(card, use_halt);
1328 if (rc)
1329 QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
1330 card->state = CARD_STATE_DOWN;
1331 return rc;
1332 }
1333 EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
1334
1335 static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
1336 int *length)
1337 {
1338 struct ciw *ciw;
1339 char *rcd_buf;
1340 int ret;
1341 struct qeth_channel *channel = &card->data;
1342 unsigned long flags;
1343
1344 /*
1345 * scan for RCD command in extended SenseID data
1346 */
1347 ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
1348 if (!ciw || ciw->cmd == 0)
1349 return -EOPNOTSUPP;
1350 rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
1351 if (!rcd_buf)
1352 return -ENOMEM;
1353
1354 channel->ccw.cmd_code = ciw->cmd;
1355 channel->ccw.cda = (__u32) __pa(rcd_buf);
1356 channel->ccw.count = ciw->count;
1357 channel->ccw.flags = CCW_FLAG_SLI;
1358 channel->state = CH_STATE_RCD;
1359 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1360 ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
1361 QETH_RCD_PARM, LPM_ANYPATH, 0,
1362 QETH_RCD_TIMEOUT);
1363 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1364 if (!ret)
1365 wait_event(card->wait_q,
1366 (channel->state == CH_STATE_RCD_DONE ||
1367 channel->state == CH_STATE_DOWN));
1368 if (channel->state == CH_STATE_DOWN)
1369 ret = -EIO;
1370 else
1371 channel->state = CH_STATE_DOWN;
1372 if (ret) {
1373 kfree(rcd_buf);
1374 *buffer = NULL;
1375 *length = 0;
1376 } else {
1377 *length = ciw->count;
1378 *buffer = rcd_buf;
1379 }
1380 return ret;
1381 }
1382
1383 static int qeth_get_unitaddr(struct qeth_card *card)
1384 {
1385 int length;
1386 char *prcd;
1387 int rc;
1388
1389 QETH_DBF_TEXT(SETUP, 2, "getunit");
1390 rc = qeth_read_conf_data(card, (void **) &prcd, &length);
1391 if (rc) {
1392 QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
1393 dev_name(&card->gdev->dev), rc);
1394 return rc;
1395 }
1396 card->info.chpid = prcd[30];
1397 card->info.unit_addr2 = prcd[31];
1398 card->info.cula = prcd[63];
1399 card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
1400 (prcd[0x11] == _ascebc['M']));
1401 kfree(prcd);
1402 return 0;
1403 }
1404
1405 static void qeth_init_tokens(struct qeth_card *card)
1406 {
1407 card->token.issuer_rm_w = 0x00010103UL;
1408 card->token.cm_filter_w = 0x00010108UL;
1409 card->token.cm_connection_w = 0x0001010aUL;
1410 card->token.ulp_filter_w = 0x0001010bUL;
1411 card->token.ulp_connection_w = 0x0001010dUL;
1412 }
1413
1414 static void qeth_init_func_level(struct qeth_card *card)
1415 {
1416 if (card->ipato.enabled) {
1417 if (card->info.type == QETH_CARD_TYPE_IQD)
1418 card->info.func_level =
1419 QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
1420 else
1421 card->info.func_level =
1422 QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
1423 } else {
1424 if (card->info.type == QETH_CARD_TYPE_IQD)
1425 /*FIXME:why do we have same values for dis and ena for
1426 osae??? */
1427 card->info.func_level =
1428 QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
1429 else
1430 card->info.func_level =
1431 QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
1432 }
1433 }
1434
1435 static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
1436 void (*idx_reply_cb)(struct qeth_channel *,
1437 struct qeth_cmd_buffer *))
1438 {
1439 struct qeth_cmd_buffer *iob;
1440 unsigned long flags;
1441 int rc;
1442 struct qeth_card *card;
1443
1444 QETH_DBF_TEXT(SETUP, 2, "idxanswr");
1445 card = CARD_FROM_CDEV(channel->ccwdev);
1446 iob = qeth_get_buffer(channel);
1447 iob->callback = idx_reply_cb;
1448 memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
1449 channel->ccw.count = QETH_BUFSIZE;
1450 channel->ccw.cda = (__u32) __pa(iob->data);
1451
1452 wait_event(card->wait_q,
1453 atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
1454 QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
1455 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1456 rc = ccw_device_start(channel->ccwdev,
1457 &channel->ccw, (addr_t) iob, 0, 0);
1458 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1459
1460 if (rc) {
1461 QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
1462 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
1463 atomic_set(&channel->irq_pending, 0);
1464 wake_up(&card->wait_q);
1465 return rc;
1466 }
1467 rc = wait_event_interruptible_timeout(card->wait_q,
1468 channel->state == CH_STATE_UP, QETH_TIMEOUT);
1469 if (rc == -ERESTARTSYS)
1470 return rc;
1471 if (channel->state != CH_STATE_UP) {
1472 rc = -ETIME;
1473 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
1474 qeth_clear_cmd_buffers(channel);
1475 } else
1476 rc = 0;
1477 return rc;
1478 }
1479
1480 static int qeth_idx_activate_channel(struct qeth_channel *channel,
1481 void (*idx_reply_cb)(struct qeth_channel *,
1482 struct qeth_cmd_buffer *))
1483 {
1484 struct qeth_card *card;
1485 struct qeth_cmd_buffer *iob;
1486 unsigned long flags;
1487 __u16 temp;
1488 __u8 tmp;
1489 int rc;
1490 struct ccw_dev_id temp_devid;
1491
1492 card = CARD_FROM_CDEV(channel->ccwdev);
1493
1494 QETH_DBF_TEXT(SETUP, 2, "idxactch");
1495
1496 iob = qeth_get_buffer(channel);
1497 iob->callback = idx_reply_cb;
1498 memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
1499 channel->ccw.count = IDX_ACTIVATE_SIZE;
1500 channel->ccw.cda = (__u32) __pa(iob->data);
1501 if (channel == &card->write) {
1502 memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
1503 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1504 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1505 card->seqno.trans_hdr++;
1506 } else {
1507 memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
1508 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1509 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1510 }
1511 tmp = ((__u8)card->info.portno) | 0x80;
1512 memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
1513 memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
1514 &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
1515 memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
1516 &card->info.func_level, sizeof(__u16));
1517 ccw_device_get_id(CARD_DDEV(card), &temp_devid);
1518 memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
1519 temp = (card->info.cula << 8) + card->info.unit_addr2;
1520 memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
1521
1522 wait_event(card->wait_q,
1523 atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
1524 QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
1525 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1526 rc = ccw_device_start(channel->ccwdev,
1527 &channel->ccw, (addr_t) iob, 0, 0);
1528 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1529
1530 if (rc) {
1531 QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
1532 rc);
1533 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
1534 atomic_set(&channel->irq_pending, 0);
1535 wake_up(&card->wait_q);
1536 return rc;
1537 }
1538 rc = wait_event_interruptible_timeout(card->wait_q,
1539 channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
1540 if (rc == -ERESTARTSYS)
1541 return rc;
1542 if (channel->state != CH_STATE_ACTIVATING) {
1543 dev_warn(&channel->ccwdev->dev, "The qeth device driver"
1544 " failed to recover an error on the device\n");
1545 QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
1546 dev_name(&channel->ccwdev->dev));
1547 QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
1548 qeth_clear_cmd_buffers(channel);
1549 return -ETIME;
1550 }
1551 return qeth_idx_activate_get_answer(channel, idx_reply_cb);
1552 }
1553
1554 static int qeth_peer_func_level(int level)
1555 {
1556 if ((level & 0xff) == 8)
1557 return (level & 0xff) + 0x400;
1558 if (((level >> 8) & 3) == 1)
1559 return (level & 0xff) + 0x200;
1560 return level;
1561 }
1562
1563 static void qeth_idx_write_cb(struct qeth_channel *channel,
1564 struct qeth_cmd_buffer *iob)
1565 {
1566 struct qeth_card *card;
1567 __u16 temp;
1568
1569 QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
1570
1571 if (channel->state == CH_STATE_DOWN) {
1572 channel->state = CH_STATE_ACTIVATING;
1573 goto out;
1574 }
1575 card = CARD_FROM_CDEV(channel->ccwdev);
1576
1577 if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
1578 if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
1579 dev_err(&card->write.ccwdev->dev,
1580 "The adapter is used exclusively by another "
1581 "host\n");
1582 else
1583 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
1584 " negative reply\n",
1585 dev_name(&card->write.ccwdev->dev));
1586 goto out;
1587 }
1588 memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
1589 if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
1590 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
1591 "function level mismatch (sent: 0x%x, received: "
1592 "0x%x)\n", dev_name(&card->write.ccwdev->dev),
1593 card->info.func_level, temp);
1594 goto out;
1595 }
1596 channel->state = CH_STATE_UP;
1597 out:
1598 qeth_release_buffer(channel, iob);
1599 }
1600
1601 static void qeth_idx_read_cb(struct qeth_channel *channel,
1602 struct qeth_cmd_buffer *iob)
1603 {
1604 struct qeth_card *card;
1605 __u16 temp;
1606
1607 QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
1608 if (channel->state == CH_STATE_DOWN) {
1609 channel->state = CH_STATE_ACTIVATING;
1610 goto out;
1611 }
1612
1613 card = CARD_FROM_CDEV(channel->ccwdev);
1614 if (qeth_check_idx_response(iob->data))
1615 goto out;
1616
1617 if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
1618 if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
1619 dev_err(&card->write.ccwdev->dev,
1620 "The adapter is used exclusively by another "
1621 "host\n");
1622 else
1623 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
1624 " negative reply\n",
1625 dev_name(&card->read.ccwdev->dev));
1626 goto out;
1627 }
1628
1629 /**
1630 * temporary fix for microcode bug
1631 * to revert it,replace OR by AND
1632 */
1633 if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
1634 (card->info.type == QETH_CARD_TYPE_OSAE))
1635 card->info.portname_required = 1;
1636
1637 memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
1638 if (temp != qeth_peer_func_level(card->info.func_level)) {
1639 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
1640 "level mismatch (sent: 0x%x, received: 0x%x)\n",
1641 dev_name(&card->read.ccwdev->dev),
1642 card->info.func_level, temp);
1643 goto out;
1644 }
1645 memcpy(&card->token.issuer_rm_r,
1646 QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
1647 QETH_MPC_TOKEN_LENGTH);
1648 memcpy(&card->info.mcl_level[0],
1649 QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
1650 channel->state = CH_STATE_UP;
1651 out:
1652 qeth_release_buffer(channel, iob);
1653 }
1654
1655 void qeth_prepare_control_data(struct qeth_card *card, int len,
1656 struct qeth_cmd_buffer *iob)
1657 {
1658 qeth_setup_ccw(&card->write, iob->data, len);
1659 iob->callback = qeth_release_buffer;
1660
1661 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1662 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1663 card->seqno.trans_hdr++;
1664 memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
1665 &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
1666 card->seqno.pdu_hdr++;
1667 memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
1668 &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
1669 QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
1670 }
1671 EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
1672
1673 int qeth_send_control_data(struct qeth_card *card, int len,
1674 struct qeth_cmd_buffer *iob,
1675 int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
1676 unsigned long),
1677 void *reply_param)
1678 {
1679 int rc;
1680 unsigned long flags;
1681 struct qeth_reply *reply = NULL;
1682 unsigned long timeout, event_timeout;
1683 struct qeth_ipa_cmd *cmd;
1684
1685 QETH_DBF_TEXT(TRACE, 2, "sendctl");
1686
1687 reply = qeth_alloc_reply(card);
1688 if (!reply) {
1689 return -ENOMEM;
1690 }
1691 reply->callback = reply_cb;
1692 reply->param = reply_param;
1693 if (card->state == CARD_STATE_DOWN)
1694 reply->seqno = QETH_IDX_COMMAND_SEQNO;
1695 else
1696 reply->seqno = card->seqno.ipa++;
1697 init_waitqueue_head(&reply->wait_q);
1698 spin_lock_irqsave(&card->lock, flags);
1699 list_add_tail(&reply->list, &card->cmd_waiter_list);
1700 spin_unlock_irqrestore(&card->lock, flags);
1701 QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
1702
1703 while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
1704 qeth_prepare_control_data(card, len, iob);
1705
1706 if (IS_IPA(iob->data))
1707 event_timeout = QETH_IPA_TIMEOUT;
1708 else
1709 event_timeout = QETH_TIMEOUT;
1710 timeout = jiffies + event_timeout;
1711
1712 QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
1713 spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
1714 rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
1715 (addr_t) iob, 0, 0);
1716 spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
1717 if (rc) {
1718 QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
1719 "ccw_device_start rc = %i\n",
1720 dev_name(&card->write.ccwdev->dev), rc);
1721 QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
1722 spin_lock_irqsave(&card->lock, flags);
1723 list_del_init(&reply->list);
1724 qeth_put_reply(reply);
1725 spin_unlock_irqrestore(&card->lock, flags);
1726 qeth_release_buffer(iob->channel, iob);
1727 atomic_set(&card->write.irq_pending, 0);
1728 wake_up(&card->wait_q);
1729 return rc;
1730 }
1731
1732 /* we have only one long running ipassist, since we can ensure
1733 process context of this command we can sleep */
1734 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
1735 if ((cmd->hdr.command == IPA_CMD_SETIP) &&
1736 (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
1737 if (!wait_event_timeout(reply->wait_q,
1738 atomic_read(&reply->received), event_timeout))
1739 goto time_err;
1740 } else {
1741 while (!atomic_read(&reply->received)) {
1742 if (time_after(jiffies, timeout))
1743 goto time_err;
1744 cpu_relax();
1745 };
1746 }
1747
1748 rc = reply->rc;
1749 qeth_put_reply(reply);
1750 return rc;
1751
1752 time_err:
1753 spin_lock_irqsave(&reply->card->lock, flags);
1754 list_del_init(&reply->list);
1755 spin_unlock_irqrestore(&reply->card->lock, flags);
1756 reply->rc = -ETIME;
1757 atomic_inc(&reply->received);
1758 wake_up(&reply->wait_q);
1759 rc = reply->rc;
1760 qeth_put_reply(reply);
1761 return rc;
1762 }
1763 EXPORT_SYMBOL_GPL(qeth_send_control_data);
1764
1765 static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
1766 unsigned long data)
1767 {
1768 struct qeth_cmd_buffer *iob;
1769
1770 QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
1771
1772 iob = (struct qeth_cmd_buffer *) data;
1773 memcpy(&card->token.cm_filter_r,
1774 QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
1775 QETH_MPC_TOKEN_LENGTH);
1776 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1777 return 0;
1778 }
1779
1780 static int qeth_cm_enable(struct qeth_card *card)
1781 {
1782 int rc;
1783 struct qeth_cmd_buffer *iob;
1784
1785 QETH_DBF_TEXT(SETUP, 2, "cmenable");
1786
1787 iob = qeth_wait_for_buffer(&card->write);
1788 memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
1789 memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
1790 &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
1791 memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
1792 &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
1793
1794 rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
1795 qeth_cm_enable_cb, NULL);
1796 return rc;
1797 }
1798
1799 static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
1800 unsigned long data)
1801 {
1802
1803 struct qeth_cmd_buffer *iob;
1804
1805 QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
1806
1807 iob = (struct qeth_cmd_buffer *) data;
1808 memcpy(&card->token.cm_connection_r,
1809 QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
1810 QETH_MPC_TOKEN_LENGTH);
1811 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1812 return 0;
1813 }
1814
1815 static int qeth_cm_setup(struct qeth_card *card)
1816 {
1817 int rc;
1818 struct qeth_cmd_buffer *iob;
1819
1820 QETH_DBF_TEXT(SETUP, 2, "cmsetup");
1821
1822 iob = qeth_wait_for_buffer(&card->write);
1823 memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
1824 memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
1825 &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
1826 memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
1827 &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
1828 memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
1829 &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
1830 rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
1831 qeth_cm_setup_cb, NULL);
1832 return rc;
1833
1834 }
1835
1836 static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
1837 {
1838 switch (card->info.type) {
1839 case QETH_CARD_TYPE_UNKNOWN:
1840 return 1500;
1841 case QETH_CARD_TYPE_IQD:
1842 return card->info.max_mtu;
1843 case QETH_CARD_TYPE_OSAE:
1844 switch (card->info.link_type) {
1845 case QETH_LINK_TYPE_HSTR:
1846 case QETH_LINK_TYPE_LANE_TR:
1847 return 2000;
1848 default:
1849 return 1492;
1850 }
1851 default:
1852 return 1500;
1853 }
1854 }
1855
1856 static inline int qeth_get_max_mtu_for_card(int cardtype)
1857 {
1858 switch (cardtype) {
1859
1860 case QETH_CARD_TYPE_UNKNOWN:
1861 case QETH_CARD_TYPE_OSAE:
1862 case QETH_CARD_TYPE_OSN:
1863 return 61440;
1864 case QETH_CARD_TYPE_IQD:
1865 return 57344;
1866 default:
1867 return 1500;
1868 }
1869 }
1870
1871 static inline int qeth_get_mtu_out_of_mpc(int cardtype)
1872 {
1873 switch (cardtype) {
1874 case QETH_CARD_TYPE_IQD:
1875 return 1;
1876 default:
1877 return 0;
1878 }
1879 }
1880
1881 static inline int qeth_get_mtu_outof_framesize(int framesize)
1882 {
1883 switch (framesize) {
1884 case 0x4000:
1885 return 8192;
1886 case 0x6000:
1887 return 16384;
1888 case 0xa000:
1889 return 32768;
1890 case 0xffff:
1891 return 57344;
1892 default:
1893 return 0;
1894 }
1895 }
1896
1897 static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
1898 {
1899 switch (card->info.type) {
1900 case QETH_CARD_TYPE_OSAE:
1901 return ((mtu >= 576) && (mtu <= 61440));
1902 case QETH_CARD_TYPE_IQD:
1903 return ((mtu >= 576) &&
1904 (mtu <= card->info.max_mtu + 4096 - 32));
1905 case QETH_CARD_TYPE_OSN:
1906 case QETH_CARD_TYPE_UNKNOWN:
1907 default:
1908 return 1;
1909 }
1910 }
1911
1912 static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
1913 unsigned long data)
1914 {
1915
1916 __u16 mtu, framesize;
1917 __u16 len;
1918 __u8 link_type;
1919 struct qeth_cmd_buffer *iob;
1920
1921 QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
1922
1923 iob = (struct qeth_cmd_buffer *) data;
1924 memcpy(&card->token.ulp_filter_r,
1925 QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
1926 QETH_MPC_TOKEN_LENGTH);
1927 if (qeth_get_mtu_out_of_mpc(card->info.type)) {
1928 memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
1929 mtu = qeth_get_mtu_outof_framesize(framesize);
1930 if (!mtu) {
1931 iob->rc = -EINVAL;
1932 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1933 return 0;
1934 }
1935 card->info.max_mtu = mtu;
1936 card->info.initial_mtu = mtu;
1937 card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
1938 } else {
1939 card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
1940 card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
1941 card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
1942 }
1943
1944 memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
1945 if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
1946 memcpy(&link_type,
1947 QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
1948 card->info.link_type = link_type;
1949 } else
1950 card->info.link_type = 0;
1951 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1952 return 0;
1953 }
1954
1955 static int qeth_ulp_enable(struct qeth_card *card)
1956 {
1957 int rc;
1958 char prot_type;
1959 struct qeth_cmd_buffer *iob;
1960
1961 /*FIXME: trace view callbacks*/
1962 QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
1963
1964 iob = qeth_wait_for_buffer(&card->write);
1965 memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
1966
1967 *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
1968 (__u8) card->info.portno;
1969 if (card->options.layer2)
1970 if (card->info.type == QETH_CARD_TYPE_OSN)
1971 prot_type = QETH_PROT_OSN2;
1972 else
1973 prot_type = QETH_PROT_LAYER2;
1974 else
1975 prot_type = QETH_PROT_TCPIP;
1976
1977 memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
1978 memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
1979 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
1980 memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
1981 &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
1982 memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
1983 card->info.portname, 9);
1984 rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
1985 qeth_ulp_enable_cb, NULL);
1986 return rc;
1987
1988 }
1989
1990 static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
1991 unsigned long data)
1992 {
1993 struct qeth_cmd_buffer *iob;
1994
1995 QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
1996
1997 iob = (struct qeth_cmd_buffer *) data;
1998 memcpy(&card->token.ulp_connection_r,
1999 QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
2000 QETH_MPC_TOKEN_LENGTH);
2001 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
2002 return 0;
2003 }
2004
2005 static int qeth_ulp_setup(struct qeth_card *card)
2006 {
2007 int rc;
2008 __u16 temp;
2009 struct qeth_cmd_buffer *iob;
2010 struct ccw_dev_id dev_id;
2011
2012 QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
2013
2014 iob = qeth_wait_for_buffer(&card->write);
2015 memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
2016
2017 memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
2018 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
2019 memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
2020 &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
2021 memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
2022 &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
2023
2024 ccw_device_get_id(CARD_DDEV(card), &dev_id);
2025 memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
2026 temp = (card->info.cula << 8) + card->info.unit_addr2;
2027 memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
2028 rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
2029 qeth_ulp_setup_cb, NULL);
2030 return rc;
2031 }
2032
2033 static int qeth_alloc_qdio_buffers(struct qeth_card *card)
2034 {
2035 int i, j;
2036
2037 QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
2038
2039 if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
2040 QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
2041 return 0;
2042
2043 card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
2044 GFP_KERNEL);
2045 if (!card->qdio.in_q)
2046 goto out_nomem;
2047 QETH_DBF_TEXT(SETUP, 2, "inq");
2048 QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
2049 memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
2050 /* give inbound qeth_qdio_buffers their qdio_buffers */
2051 for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
2052 card->qdio.in_q->bufs[i].buffer =
2053 &card->qdio.in_q->qdio_bufs[i];
2054 /* inbound buffer pool */
2055 if (qeth_alloc_buffer_pool(card))
2056 goto out_freeinq;
2057 /* outbound */
2058 card->qdio.out_qs =
2059 kmalloc(card->qdio.no_out_queues *
2060 sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
2061 if (!card->qdio.out_qs)
2062 goto out_freepool;
2063 for (i = 0; i < card->qdio.no_out_queues; ++i) {
2064 card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
2065 GFP_KERNEL);
2066 if (!card->qdio.out_qs[i])
2067 goto out_freeoutq;
2068 QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
2069 QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
2070 memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
2071 card->qdio.out_qs[i]->queue_no = i;
2072 /* give outbound qeth_qdio_buffers their qdio_buffers */
2073 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
2074 card->qdio.out_qs[i]->bufs[j].buffer =
2075 &card->qdio.out_qs[i]->qdio_bufs[j];
2076 skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
2077 skb_list);
2078 lockdep_set_class(
2079 &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
2080 &qdio_out_skb_queue_key);
2081 INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
2082 }
2083 }
2084 return 0;
2085
2086 out_freeoutq:
2087 while (i > 0)
2088 kfree(card->qdio.out_qs[--i]);
2089 kfree(card->qdio.out_qs);
2090 card->qdio.out_qs = NULL;
2091 out_freepool:
2092 qeth_free_buffer_pool(card);
2093 out_freeinq:
2094 kfree(card->qdio.in_q);
2095 card->qdio.in_q = NULL;
2096 out_nomem:
2097 atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
2098 return -ENOMEM;
2099 }
2100
2101 static void qeth_create_qib_param_field(struct qeth_card *card,
2102 char *param_field)
2103 {
2104
2105 param_field[0] = _ascebc['P'];
2106 param_field[1] = _ascebc['C'];
2107 param_field[2] = _ascebc['I'];
2108 param_field[3] = _ascebc['T'];
2109 *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
2110 *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
2111 *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
2112 }
2113
2114 static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
2115 char *param_field)
2116 {
2117 param_field[16] = _ascebc['B'];
2118 param_field[17] = _ascebc['L'];
2119 param_field[18] = _ascebc['K'];
2120 param_field[19] = _ascebc['T'];
2121 *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
2122 *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
2123 *((unsigned int *) (&param_field[28])) =
2124 card->info.blkt.inter_packet_jumbo;
2125 }
2126
2127 static int qeth_qdio_activate(struct qeth_card *card)
2128 {
2129 QETH_DBF_TEXT(SETUP, 3, "qdioact");
2130 return qdio_activate(CARD_DDEV(card));
2131 }
2132
2133 static int qeth_dm_act(struct qeth_card *card)
2134 {
2135 int rc;
2136 struct qeth_cmd_buffer *iob;
2137
2138 QETH_DBF_TEXT(SETUP, 2, "dmact");
2139
2140 iob = qeth_wait_for_buffer(&card->write);
2141 memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
2142
2143 memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
2144 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
2145 memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
2146 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
2147 rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
2148 return rc;
2149 }
2150
2151 static int qeth_mpc_initialize(struct qeth_card *card)
2152 {
2153 int rc;
2154
2155 QETH_DBF_TEXT(SETUP, 2, "mpcinit");
2156
2157 rc = qeth_issue_next_read(card);
2158 if (rc) {
2159 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
2160 return rc;
2161 }
2162 rc = qeth_cm_enable(card);
2163 if (rc) {
2164 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
2165 goto out_qdio;
2166 }
2167 rc = qeth_cm_setup(card);
2168 if (rc) {
2169 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
2170 goto out_qdio;
2171 }
2172 rc = qeth_ulp_enable(card);
2173 if (rc) {
2174 QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
2175 goto out_qdio;
2176 }
2177 rc = qeth_ulp_setup(card);
2178 if (rc) {
2179 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
2180 goto out_qdio;
2181 }
2182 rc = qeth_alloc_qdio_buffers(card);
2183 if (rc) {
2184 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
2185 goto out_qdio;
2186 }
2187 rc = qeth_qdio_establish(card);
2188 if (rc) {
2189 QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
2190 qeth_free_qdio_buffers(card);
2191 goto out_qdio;
2192 }
2193 rc = qeth_qdio_activate(card);
2194 if (rc) {
2195 QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
2196 goto out_qdio;
2197 }
2198 rc = qeth_dm_act(card);
2199 if (rc) {
2200 QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
2201 goto out_qdio;
2202 }
2203
2204 return 0;
2205 out_qdio:
2206 qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
2207 return rc;
2208 }
2209
2210 static void qeth_print_status_with_portname(struct qeth_card *card)
2211 {
2212 char dbf_text[15];
2213 int i;
2214
2215 sprintf(dbf_text, "%s", card->info.portname + 1);
2216 for (i = 0; i < 8; i++)
2217 dbf_text[i] =
2218 (char) _ebcasc[(__u8) dbf_text[i]];
2219 dbf_text[8] = 0;
2220 dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
2221 "with link type %s (portname: %s)\n",
2222 qeth_get_cardname(card),
2223 (card->info.mcl_level[0]) ? " (level: " : "",
2224 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2225 (card->info.mcl_level[0]) ? ")" : "",
2226 qeth_get_cardname_short(card),
2227 dbf_text);
2228
2229 }
2230
2231 static void qeth_print_status_no_portname(struct qeth_card *card)
2232 {
2233 if (card->info.portname[0])
2234 dev_info(&card->gdev->dev, "Device is a%s "
2235 "card%s%s%s\nwith link type %s "
2236 "(no portname needed by interface).\n",
2237 qeth_get_cardname(card),
2238 (card->info.mcl_level[0]) ? " (level: " : "",
2239 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2240 (card->info.mcl_level[0]) ? ")" : "",
2241 qeth_get_cardname_short(card));
2242 else
2243 dev_info(&card->gdev->dev, "Device is a%s "
2244 "card%s%s%s\nwith link type %s.\n",
2245 qeth_get_cardname(card),
2246 (card->info.mcl_level[0]) ? " (level: " : "",
2247 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2248 (card->info.mcl_level[0]) ? ")" : "",
2249 qeth_get_cardname_short(card));
2250 }
2251
2252 void qeth_print_status_message(struct qeth_card *card)
2253 {
2254 switch (card->info.type) {
2255 case QETH_CARD_TYPE_OSAE:
2256 /* VM will use a non-zero first character
2257 * to indicate a HiperSockets like reporting
2258 * of the level OSA sets the first character to zero
2259 * */
2260 if (!card->info.mcl_level[0]) {
2261 sprintf(card->info.mcl_level, "%02x%02x",
2262 card->info.mcl_level[2],
2263 card->info.mcl_level[3]);
2264
2265 card->info.mcl_level[QETH_MCL_LENGTH] = 0;
2266 break;
2267 }
2268 /* fallthrough */
2269 case QETH_CARD_TYPE_IQD:
2270 if ((card->info.guestlan) ||
2271 (card->info.mcl_level[0] & 0x80)) {
2272 card->info.mcl_level[0] = (char) _ebcasc[(__u8)
2273 card->info.mcl_level[0]];
2274 card->info.mcl_level[1] = (char) _ebcasc[(__u8)
2275 card->info.mcl_level[1]];
2276 card->info.mcl_level[2] = (char) _ebcasc[(__u8)
2277 card->info.mcl_level[2]];
2278 card->info.mcl_level[3] = (char) _ebcasc[(__u8)
2279 card->info.mcl_level[3]];
2280 card->info.mcl_level[QETH_MCL_LENGTH] = 0;
2281 }
2282 break;
2283 default:
2284 memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
2285 }
2286 if (card->info.portname_required)
2287 qeth_print_status_with_portname(card);
2288 else
2289 qeth_print_status_no_portname(card);
2290 }
2291 EXPORT_SYMBOL_GPL(qeth_print_status_message);
2292
2293 static void qeth_initialize_working_pool_list(struct qeth_card *card)
2294 {
2295 struct qeth_buffer_pool_entry *entry;
2296
2297 QETH_DBF_TEXT(TRACE, 5, "inwrklst");
2298
2299 list_for_each_entry(entry,
2300 &card->qdio.init_pool.entry_list, init_list) {
2301 qeth_put_buffer_pool_entry(card, entry);
2302 }
2303 }
2304
2305 static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
2306 struct qeth_card *card)
2307 {
2308 struct list_head *plh;
2309 struct qeth_buffer_pool_entry *entry;
2310 int i, free;
2311 struct page *page;
2312
2313 if (list_empty(&card->qdio.in_buf_pool.entry_list))
2314 return NULL;
2315
2316 list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
2317 entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
2318 free = 1;
2319 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2320 if (page_count(virt_to_page(entry->elements[i])) > 1) {
2321 free = 0;
2322 break;
2323 }
2324 }
2325 if (free) {
2326 list_del_init(&entry->list);
2327 return entry;
2328 }
2329 }
2330
2331 /* no free buffer in pool so take first one and swap pages */
2332 entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
2333 struct qeth_buffer_pool_entry, list);
2334 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2335 if (page_count(virt_to_page(entry->elements[i])) > 1) {
2336 page = alloc_page(GFP_ATOMIC);
2337 if (!page) {
2338 return NULL;
2339 } else {
2340 free_page((unsigned long)entry->elements[i]);
2341 entry->elements[i] = page_address(page);
2342 if (card->options.performance_stats)
2343 card->perf_stats.sg_alloc_page_rx++;
2344 }
2345 }
2346 }
2347 list_del_init(&entry->list);
2348 return entry;
2349 }
2350
2351 static int qeth_init_input_buffer(struct qeth_card *card,
2352 struct qeth_qdio_buffer *buf)
2353 {
2354 struct qeth_buffer_pool_entry *pool_entry;
2355 int i;
2356
2357 pool_entry = qeth_find_free_buffer_pool_entry(card);
2358 if (!pool_entry)
2359 return 1;
2360
2361 /*
2362 * since the buffer is accessed only from the input_tasklet
2363 * there shouldn't be a need to synchronize; also, since we use
2364 * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
2365 * buffers
2366 */
2367
2368 buf->pool_entry = pool_entry;
2369 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2370 buf->buffer->element[i].length = PAGE_SIZE;
2371 buf->buffer->element[i].addr = pool_entry->elements[i];
2372 if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
2373 buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
2374 else
2375 buf->buffer->element[i].flags = 0;
2376 }
2377 return 0;
2378 }
2379
2380 int qeth_init_qdio_queues(struct qeth_card *card)
2381 {
2382 int i, j;
2383 int rc;
2384
2385 QETH_DBF_TEXT(SETUP, 2, "initqdqs");
2386
2387 /* inbound queue */
2388 memset(card->qdio.in_q->qdio_bufs, 0,
2389 QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
2390 qeth_initialize_working_pool_list(card);
2391 /*give only as many buffers to hardware as we have buffer pool entries*/
2392 for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
2393 qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
2394 card->qdio.in_q->next_buf_to_init =
2395 card->qdio.in_buf_pool.buf_count - 1;
2396 rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
2397 card->qdio.in_buf_pool.buf_count - 1);
2398 if (rc) {
2399 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
2400 return rc;
2401 }
2402 /* outbound queue */
2403 for (i = 0; i < card->qdio.no_out_queues; ++i) {
2404 memset(card->qdio.out_qs[i]->qdio_bufs, 0,
2405 QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
2406 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
2407 qeth_clear_output_buffer(card->qdio.out_qs[i],
2408 &card->qdio.out_qs[i]->bufs[j]);
2409 }
2410 card->qdio.out_qs[i]->card = card;
2411 card->qdio.out_qs[i]->next_buf_to_fill = 0;
2412 card->qdio.out_qs[i]->do_pack = 0;
2413 atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
2414 atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
2415 atomic_set(&card->qdio.out_qs[i]->state,
2416 QETH_OUT_Q_UNLOCKED);
2417 }
2418 return 0;
2419 }
2420 EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
2421
2422 static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
2423 {
2424 switch (link_type) {
2425 case QETH_LINK_TYPE_HSTR:
2426 return 2;
2427 default:
2428 return 1;
2429 }
2430 }
2431
2432 static void qeth_fill_ipacmd_header(struct qeth_card *card,
2433 struct qeth_ipa_cmd *cmd, __u8 command,
2434 enum qeth_prot_versions prot)
2435 {
2436 memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
2437 cmd->hdr.command = command;
2438 cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
2439 cmd->hdr.seqno = card->seqno.ipa;
2440 cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
2441 cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
2442 if (card->options.layer2)
2443 cmd->hdr.prim_version_no = 2;
2444 else
2445 cmd->hdr.prim_version_no = 1;
2446 cmd->hdr.param_count = 1;
2447 cmd->hdr.prot_version = prot;
2448 cmd->hdr.ipa_supported = 0;
2449 cmd->hdr.ipa_enabled = 0;
2450 }
2451
2452 struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
2453 enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
2454 {
2455 struct qeth_cmd_buffer *iob;
2456 struct qeth_ipa_cmd *cmd;
2457
2458 iob = qeth_wait_for_buffer(&card->write);
2459 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
2460 qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
2461
2462 return iob;
2463 }
2464 EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
2465
2466 void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
2467 char prot_type)
2468 {
2469 memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
2470 memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
2471 memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
2472 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
2473 }
2474 EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
2475
2476 int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
2477 int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
2478 unsigned long),
2479 void *reply_param)
2480 {
2481 int rc;
2482 char prot_type;
2483
2484 QETH_DBF_TEXT(TRACE, 4, "sendipa");
2485
2486 if (card->options.layer2)
2487 if (card->info.type == QETH_CARD_TYPE_OSN)
2488 prot_type = QETH_PROT_OSN2;
2489 else
2490 prot_type = QETH_PROT_LAYER2;
2491 else
2492 prot_type = QETH_PROT_TCPIP;
2493 qeth_prepare_ipa_cmd(card, iob, prot_type);
2494 rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
2495 iob, reply_cb, reply_param);
2496 return rc;
2497 }
2498 EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
2499
2500 static int qeth_send_startstoplan(struct qeth_card *card,
2501 enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
2502 {
2503 int rc;
2504 struct qeth_cmd_buffer *iob;
2505
2506 iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
2507 rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
2508
2509 return rc;
2510 }
2511
2512 int qeth_send_startlan(struct qeth_card *card)
2513 {
2514 int rc;
2515
2516 QETH_DBF_TEXT(SETUP, 2, "strtlan");
2517
2518 rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
2519 return rc;
2520 }
2521 EXPORT_SYMBOL_GPL(qeth_send_startlan);
2522
2523 int qeth_send_stoplan(struct qeth_card *card)
2524 {
2525 int rc = 0;
2526
2527 /*
2528 * TODO: according to the IPA format document page 14,
2529 * TCP/IP (we!) never issue a STOPLAN
2530 * is this right ?!?
2531 */
2532 QETH_DBF_TEXT(SETUP, 2, "stoplan");
2533
2534 rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
2535 return rc;
2536 }
2537 EXPORT_SYMBOL_GPL(qeth_send_stoplan);
2538
2539 int qeth_default_setadapterparms_cb(struct qeth_card *card,
2540 struct qeth_reply *reply, unsigned long data)
2541 {
2542 struct qeth_ipa_cmd *cmd;
2543
2544 QETH_DBF_TEXT(TRACE, 4, "defadpcb");
2545
2546 cmd = (struct qeth_ipa_cmd *) data;
2547 if (cmd->hdr.return_code == 0)
2548 cmd->hdr.return_code =
2549 cmd->data.setadapterparms.hdr.return_code;
2550 return 0;
2551 }
2552 EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
2553
2554 static int qeth_query_setadapterparms_cb(struct qeth_card *card,
2555 struct qeth_reply *reply, unsigned long data)
2556 {
2557 struct qeth_ipa_cmd *cmd;
2558
2559 QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
2560
2561 cmd = (struct qeth_ipa_cmd *) data;
2562 if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
2563 card->info.link_type =
2564 cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
2565 card->options.adp.supported_funcs =
2566 cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
2567 return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
2568 }
2569
2570 struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
2571 __u32 command, __u32 cmdlen)
2572 {
2573 struct qeth_cmd_buffer *iob;
2574 struct qeth_ipa_cmd *cmd;
2575
2576 iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
2577 QETH_PROT_IPV4);
2578 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
2579 cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
2580 cmd->data.setadapterparms.hdr.command_code = command;
2581 cmd->data.setadapterparms.hdr.used_total = 1;
2582 cmd->data.setadapterparms.hdr.seq_no = 1;
2583
2584 return iob;
2585 }
2586 EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
2587
2588 int qeth_query_setadapterparms(struct qeth_card *card)
2589 {
2590 int rc;
2591 struct qeth_cmd_buffer *iob;
2592
2593 QETH_DBF_TEXT(TRACE, 3, "queryadp");
2594 iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
2595 sizeof(struct qeth_ipacmd_setadpparms));
2596 rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
2597 return rc;
2598 }
2599 EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
2600
2601 int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
2602 const char *dbftext)
2603 {
2604 if (qdio_error) {
2605 QETH_DBF_TEXT(TRACE, 2, dbftext);
2606 QETH_DBF_TEXT(QERR, 2, dbftext);
2607 QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
2608 buf->element[15].flags & 0xff);
2609 QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
2610 buf->element[14].flags & 0xff);
2611 QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
2612 return 1;
2613 }
2614 return 0;
2615 }
2616 EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
2617
2618 void qeth_queue_input_buffer(struct qeth_card *card, int index)
2619 {
2620 struct qeth_qdio_q *queue = card->qdio.in_q;
2621 int count;
2622 int i;
2623 int rc;
2624 int newcount = 0;
2625
2626 count = (index < queue->next_buf_to_init)?
2627 card->qdio.in_buf_pool.buf_count -
2628 (queue->next_buf_to_init - index) :
2629 card->qdio.in_buf_pool.buf_count -
2630 (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
2631 /* only requeue at a certain threshold to avoid SIGAs */
2632 if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
2633 for (i = queue->next_buf_to_init;
2634 i < queue->next_buf_to_init + count; ++i) {
2635 if (qeth_init_input_buffer(card,
2636 &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
2637 break;
2638 } else {
2639 newcount++;
2640 }
2641 }
2642
2643 if (newcount < count) {
2644 /* we are in memory shortage so we switch back to
2645 traditional skb allocation and drop packages */
2646 atomic_set(&card->force_alloc_skb, 3);
2647 count = newcount;
2648 } else {
2649 atomic_add_unless(&card->force_alloc_skb, -1, 0);
2650 }
2651
2652 /*
2653 * according to old code it should be avoided to requeue all
2654 * 128 buffers in order to benefit from PCI avoidance.
2655 * this function keeps at least one buffer (the buffer at
2656 * 'index') un-requeued -> this buffer is the first buffer that
2657 * will be requeued the next time
2658 */
2659 if (card->options.performance_stats) {
2660 card->perf_stats.inbound_do_qdio_cnt++;
2661 card->perf_stats.inbound_do_qdio_start_time =
2662 qeth_get_micros();
2663 }
2664 rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
2665 queue->next_buf_to_init, count);
2666 if (card->options.performance_stats)
2667 card->perf_stats.inbound_do_qdio_time +=
2668 qeth_get_micros() -
2669 card->perf_stats.inbound_do_qdio_start_time;
2670 if (rc) {
2671 dev_warn(&card->gdev->dev,
2672 "QDIO reported an error, rc=%i\n", rc);
2673 QETH_DBF_TEXT(TRACE, 2, "qinberr");
2674 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
2675 }
2676 queue->next_buf_to_init = (queue->next_buf_to_init + count) %
2677 QDIO_MAX_BUFFERS_PER_Q;
2678 }
2679 }
2680 EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
2681
2682 static int qeth_handle_send_error(struct qeth_card *card,
2683 struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
2684 {
2685 int sbalf15 = buffer->buffer->element[15].flags & 0xff;
2686
2687 QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
2688 qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr");
2689
2690 if (!qdio_err)
2691 return QETH_SEND_ERROR_NONE;
2692
2693 if ((sbalf15 >= 15) && (sbalf15 <= 31))
2694 return QETH_SEND_ERROR_RETRY;
2695
2696 QETH_DBF_TEXT(TRACE, 1, "lnkfail");
2697 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
2698 QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
2699 (u16)qdio_err, (u8)sbalf15);
2700 return QETH_SEND_ERROR_LINK_FAILURE;
2701 }
2702
2703 /*
2704 * Switched to packing state if the number of used buffers on a queue
2705 * reaches a certain limit.
2706 */
2707 static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
2708 {
2709 if (!queue->do_pack) {
2710 if (atomic_read(&queue->used_buffers)
2711 >= QETH_HIGH_WATERMARK_PACK){
2712 /* switch non-PACKING -> PACKING */
2713 QETH_DBF_TEXT(TRACE, 6, "np->pack");
2714 if (queue->card->options.performance_stats)
2715 queue->card->perf_stats.sc_dp_p++;
2716 queue->do_pack = 1;
2717 }
2718 }
2719 }
2720
2721 /*
2722 * Switches from packing to non-packing mode. If there is a packing
2723 * buffer on the queue this buffer will be prepared to be flushed.
2724 * In that case 1 is returned to inform the caller. If no buffer
2725 * has to be flushed, zero is returned.
2726 */
2727 static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
2728 {
2729 struct qeth_qdio_out_buffer *buffer;
2730 int flush_count = 0;
2731
2732 if (queue->do_pack) {
2733 if (atomic_read(&queue->used_buffers)
2734 <= QETH_LOW_WATERMARK_PACK) {
2735 /* switch PACKING -> non-PACKING */
2736 QETH_DBF_TEXT(TRACE, 6, "pack->np");
2737 if (queue->card->options.performance_stats)
2738 queue->card->perf_stats.sc_p_dp++;
2739 queue->do_pack = 0;
2740 /* flush packing buffers */
2741 buffer = &queue->bufs[queue->next_buf_to_fill];
2742 if ((atomic_read(&buffer->state) ==
2743 QETH_QDIO_BUF_EMPTY) &&
2744 (buffer->next_element_to_fill > 0)) {
2745 atomic_set(&buffer->state,
2746 QETH_QDIO_BUF_PRIMED);
2747 flush_count++;
2748 queue->next_buf_to_fill =
2749 (queue->next_buf_to_fill + 1) %
2750 QDIO_MAX_BUFFERS_PER_Q;
2751 }
2752 }
2753 }
2754 return flush_count;
2755 }
2756
2757 /*
2758 * Called to flush a packing buffer if no more pci flags are on the queue.
2759 * Checks if there is a packing buffer and prepares it to be flushed.
2760 * In that case returns 1, otherwise zero.
2761 */
2762 static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
2763 {
2764 struct qeth_qdio_out_buffer *buffer;
2765
2766 buffer = &queue->bufs[queue->next_buf_to_fill];
2767 if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
2768 (buffer->next_element_to_fill > 0)) {
2769 /* it's a packing buffer */
2770 atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
2771 queue->next_buf_to_fill =
2772 (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
2773 return 1;
2774 }
2775 return 0;
2776 }
2777
2778 static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
2779 int count)
2780 {
2781 struct qeth_qdio_out_buffer *buf;
2782 int rc;
2783 int i;
2784 unsigned int qdio_flags;
2785
2786 for (i = index; i < index + count; ++i) {
2787 buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
2788 buf->buffer->element[buf->next_element_to_fill - 1].flags |=
2789 SBAL_FLAGS_LAST_ENTRY;
2790
2791 if (queue->card->info.type == QETH_CARD_TYPE_IQD)
2792 continue;
2793
2794 if (!queue->do_pack) {
2795 if ((atomic_read(&queue->used_buffers) >=
2796 (QETH_HIGH_WATERMARK_PACK -
2797 QETH_WATERMARK_PACK_FUZZ)) &&
2798 !atomic_read(&queue->set_pci_flags_count)) {
2799 /* it's likely that we'll go to packing
2800 * mode soon */
2801 atomic_inc(&queue->set_pci_flags_count);
2802 buf->buffer->element[0].flags |= 0x40;
2803 }
2804 } else {
2805 if (!atomic_read(&queue->set_pci_flags_count)) {
2806 /*
2807 * there's no outstanding PCI any more, so we
2808 * have to request a PCI to be sure the the PCI
2809 * will wake at some time in the future then we
2810 * can flush packed buffers that might still be
2811 * hanging around, which can happen if no
2812 * further send was requested by the stack
2813 */
2814 atomic_inc(&queue->set_pci_flags_count);
2815 buf->buffer->element[0].flags |= 0x40;
2816 }
2817 }
2818 }
2819
2820 queue->card->dev->trans_start = jiffies;
2821 if (queue->card->options.performance_stats) {
2822 queue->card->perf_stats.outbound_do_qdio_cnt++;
2823 queue->card->perf_stats.outbound_do_qdio_start_time =
2824 qeth_get_micros();
2825 }
2826 qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
2827 if (atomic_read(&queue->set_pci_flags_count))
2828 qdio_flags |= QDIO_FLAG_PCI_OUT;
2829 rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
2830 queue->queue_no, index, count);
2831 if (queue->card->options.performance_stats)
2832 queue->card->perf_stats.outbound_do_qdio_time +=
2833 qeth_get_micros() -
2834 queue->card->perf_stats.outbound_do_qdio_start_time;
2835 if (rc) {
2836 queue->card->stats.tx_errors += count;
2837 /* ignore temporary SIGA errors without busy condition */
2838 if (rc == QDIO_ERROR_SIGA_TARGET)
2839 return;
2840 QETH_DBF_TEXT(TRACE, 2, "flushbuf");
2841 QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
2842 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
2843
2844 /* this must not happen under normal circumstances. if it
2845 * happens something is really wrong -> recover */
2846 qeth_schedule_recovery(queue->card);
2847 return;
2848 }
2849 atomic_add(count, &queue->used_buffers);
2850 if (queue->card->options.performance_stats)
2851 queue->card->perf_stats.bufs_sent += count;
2852 }
2853
2854 static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
2855 {
2856 int index;
2857 int flush_cnt = 0;
2858 int q_was_packing = 0;
2859
2860 /*
2861 * check if weed have to switch to non-packing mode or if
2862 * we have to get a pci flag out on the queue
2863 */
2864 if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
2865 !atomic_read(&queue->set_pci_flags_count)) {
2866 if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
2867 QETH_OUT_Q_UNLOCKED) {
2868 /*
2869 * If we get in here, there was no action in
2870 * do_send_packet. So, we check if there is a
2871 * packing buffer to be flushed here.
2872 */
2873 netif_stop_queue(queue->card->dev);
2874 index = queue->next_buf_to_fill;
2875 q_was_packing = queue->do_pack;
2876 /* queue->do_pack may change */
2877 barrier();
2878 flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
2879 if (!flush_cnt &&
2880 !atomic_read(&queue->set_pci_flags_count))
2881 flush_cnt +=
2882 qeth_flush_buffers_on_no_pci(queue);
2883 if (queue->card->options.performance_stats &&
2884 q_was_packing)
2885 queue->card->perf_stats.bufs_sent_pack +=
2886 flush_cnt;
2887 if (flush_cnt)
2888 qeth_flush_buffers(queue, index, flush_cnt);
2889 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
2890 }
2891 }
2892 }
2893
2894 void qeth_qdio_output_handler(struct ccw_device *ccwdev,
2895 unsigned int qdio_error, int __queue, int first_element,
2896 int count, unsigned long card_ptr)
2897 {
2898 struct qeth_card *card = (struct qeth_card *) card_ptr;
2899 struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
2900 struct qeth_qdio_out_buffer *buffer;
2901 int i;
2902
2903 QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
2904 if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
2905 QETH_DBF_TEXT(TRACE, 2, "achkcond");
2906 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
2907 netif_stop_queue(card->dev);
2908 qeth_schedule_recovery(card);
2909 return;
2910 }
2911 if (card->options.performance_stats) {
2912 card->perf_stats.outbound_handler_cnt++;
2913 card->perf_stats.outbound_handler_start_time =
2914 qeth_get_micros();
2915 }
2916 for (i = first_element; i < (first_element + count); ++i) {
2917 buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
2918 qeth_handle_send_error(card, buffer, qdio_error);
2919 qeth_clear_output_buffer(queue, buffer);
2920 }
2921 atomic_sub(count, &queue->used_buffers);
2922 /* check if we need to do something on this outbound queue */
2923 if (card->info.type != QETH_CARD_TYPE_IQD)
2924 qeth_check_outbound_queue(queue);
2925
2926 netif_wake_queue(queue->card->dev);
2927 if (card->options.performance_stats)
2928 card->perf_stats.outbound_handler_time += qeth_get_micros() -
2929 card->perf_stats.outbound_handler_start_time;
2930 }
2931 EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
2932
2933 int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
2934 {
2935 int cast_type = RTN_UNSPEC;
2936
2937 if (card->info.type == QETH_CARD_TYPE_OSN)
2938 return cast_type;
2939
2940 if (skb_dst(skb) && skb_dst(skb)->neighbour) {
2941 cast_type = skb_dst(skb)->neighbour->type;
2942 if ((cast_type == RTN_BROADCAST) ||
2943 (cast_type == RTN_MULTICAST) ||
2944 (cast_type == RTN_ANYCAST))
2945 return cast_type;
2946 else
2947 return RTN_UNSPEC;
2948 }
2949 /* try something else */
2950 if (skb->protocol == ETH_P_IPV6)
2951 return (skb_network_header(skb)[24] == 0xff) ?
2952 RTN_MULTICAST : 0;
2953 else if (skb->protocol == ETH_P_IP)
2954 return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
2955 RTN_MULTICAST : 0;
2956 /* ... */
2957 if (!memcmp(skb->data, skb->dev->broadcast, 6))
2958 return RTN_BROADCAST;
2959 else {
2960 u16 hdr_mac;
2961
2962 hdr_mac = *((u16 *)skb->data);
2963 /* tr multicast? */
2964 switch (card->info.link_type) {
2965 case QETH_LINK_TYPE_HSTR:
2966 case QETH_LINK_TYPE_LANE_TR:
2967 if ((hdr_mac == QETH_TR_MAC_NC) ||
2968 (hdr_mac == QETH_TR_MAC_C))
2969 return RTN_MULTICAST;
2970 break;
2971 /* eth or so multicast? */
2972 default:
2973 if ((hdr_mac == QETH_ETH_MAC_V4) ||
2974 (hdr_mac == QETH_ETH_MAC_V6))
2975 return RTN_MULTICAST;
2976 }
2977 }
2978 return cast_type;
2979 }
2980 EXPORT_SYMBOL_GPL(qeth_get_cast_type);
2981
2982 int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
2983 int ipv, int cast_type)
2984 {
2985 if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
2986 return card->qdio.default_out_queue;
2987 switch (card->qdio.no_out_queues) {
2988 case 4:
2989 if (cast_type && card->info.is_multicast_different)
2990 return card->info.is_multicast_different &
2991 (card->qdio.no_out_queues - 1);
2992 if (card->qdio.do_prio_queueing && (ipv == 4)) {
2993 const u8 tos = ip_hdr(skb)->tos;
2994
2995 if (card->qdio.do_prio_queueing ==
2996 QETH_PRIO_Q_ING_TOS) {
2997 if (tos & IP_TOS_NOTIMPORTANT)
2998 return 3;
2999 if (tos & IP_TOS_HIGHRELIABILITY)
3000 return 2;
3001 if (tos & IP_TOS_HIGHTHROUGHPUT)
3002 return 1;
3003 if (tos & IP_TOS_LOWDELAY)
3004 return 0;
3005 }
3006 if (card->qdio.do_prio_queueing ==
3007 QETH_PRIO_Q_ING_PREC)
3008 return 3 - (tos >> 6);
3009 } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
3010 /* TODO: IPv6!!! */
3011 }
3012 return card->qdio.default_out_queue;
3013 case 1: /* fallthrough for single-out-queue 1920-device */
3014 default:
3015 return card->qdio.default_out_queue;
3016 }
3017 }
3018 EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
3019
3020 int qeth_get_elements_no(struct qeth_card *card, void *hdr,
3021 struct sk_buff *skb, int elems)
3022 {
3023 int elements_needed = 0;
3024
3025 if (skb_shinfo(skb)->nr_frags > 0)
3026 elements_needed = (skb_shinfo(skb)->nr_frags + 1);
3027 if (elements_needed == 0)
3028 elements_needed = 1 + (((((unsigned long) skb->data) %
3029 PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
3030 if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
3031 QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
3032 "(Number=%d / Length=%d). Discarded.\n",
3033 (elements_needed+elems), skb->len);
3034 return 0;
3035 }
3036 return elements_needed;
3037 }
3038 EXPORT_SYMBOL_GPL(qeth_get_elements_no);
3039
3040 static inline void __qeth_fill_buffer(struct sk_buff *skb,
3041 struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
3042 int offset)
3043 {
3044 int length = skb->len;
3045 int length_here;
3046 int element;
3047 char *data;
3048 int first_lap ;
3049
3050 element = *next_element_to_fill;
3051 data = skb->data;
3052 first_lap = (is_tso == 0 ? 1 : 0);
3053
3054 if (offset >= 0) {
3055 data = skb->data + offset;
3056 length -= offset;
3057 first_lap = 0;
3058 }
3059
3060 while (length > 0) {
3061 /* length_here is the remaining amount of data in this page */
3062 length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
3063 if (length < length_here)
3064 length_here = length;
3065
3066 buffer->element[element].addr = data;
3067 buffer->element[element].length = length_here;
3068 length -= length_here;
3069 if (!length) {
3070 if (first_lap)
3071 buffer->element[element].flags = 0;
3072 else
3073 buffer->element[element].flags =
3074 SBAL_FLAGS_LAST_FRAG;
3075 } else {
3076 if (first_lap)
3077 buffer->element[element].flags =
3078 SBAL_FLAGS_FIRST_FRAG;
3079 else
3080 buffer->element[element].flags =
3081 SBAL_FLAGS_MIDDLE_FRAG;
3082 }
3083 data += length_here;
3084 element++;
3085 first_lap = 0;
3086 }
3087 *next_element_to_fill = element;
3088 }
3089
3090 static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
3091 struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
3092 struct qeth_hdr *hdr, int offset, int hd_len)
3093 {
3094 struct qdio_buffer *buffer;
3095 int flush_cnt = 0, hdr_len, large_send = 0;
3096
3097 buffer = buf->buffer;
3098 atomic_inc(&skb->users);
3099 skb_queue_tail(&buf->skb_list, skb);
3100
3101 /*check first on TSO ....*/
3102 if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
3103 int element = buf->next_element_to_fill;
3104
3105 hdr_len = sizeof(struct qeth_hdr_tso) +
3106 ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
3107 /*fill first buffer entry only with header information */
3108 buffer->element[element].addr = skb->data;
3109 buffer->element[element].length = hdr_len;
3110 buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
3111 buf->next_element_to_fill++;
3112 skb->data += hdr_len;
3113 skb->len -= hdr_len;
3114 large_send = 1;
3115 }
3116
3117 if (offset >= 0) {
3118 int element = buf->next_element_to_fill;
3119 buffer->element[element].addr = hdr;
3120 buffer->element[element].length = sizeof(struct qeth_hdr) +
3121 hd_len;
3122 buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
3123 buf->is_header[element] = 1;
3124 buf->next_element_to_fill++;
3125 }
3126
3127 if (skb_shinfo(skb)->nr_frags == 0)
3128 __qeth_fill_buffer(skb, buffer, large_send,
3129 (int *)&buf->next_element_to_fill, offset);
3130 else
3131 __qeth_fill_buffer_frag(skb, buffer, large_send,
3132 (int *)&buf->next_element_to_fill);
3133
3134 if (!queue->do_pack) {
3135 QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
3136 /* set state to PRIMED -> will be flushed */
3137 atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
3138 flush_cnt = 1;
3139 } else {
3140 QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
3141 if (queue->card->options.performance_stats)
3142 queue->card->perf_stats.skbs_sent_pack++;
3143 if (buf->next_element_to_fill >=
3144 QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
3145 /*
3146 * packed buffer if full -> set state PRIMED
3147 * -> will be flushed
3148 */
3149 atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
3150 flush_cnt = 1;
3151 }
3152 }
3153 return flush_cnt;
3154 }
3155
3156 int qeth_do_send_packet_fast(struct qeth_card *card,
3157 struct qeth_qdio_out_q *queue, struct sk_buff *skb,
3158 struct qeth_hdr *hdr, int elements_needed,
3159 int offset, int hd_len)
3160 {
3161 struct qeth_qdio_out_buffer *buffer;
3162 int index;
3163
3164 /* spin until we get the queue ... */
3165 while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
3166 QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
3167 /* ... now we've got the queue */
3168 index = queue->next_buf_to_fill;
3169 buffer = &queue->bufs[queue->next_buf_to_fill];
3170 /*
3171 * check if buffer is empty to make sure that we do not 'overtake'
3172 * ourselves and try to fill a buffer that is already primed
3173 */
3174 if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
3175 goto out;
3176 queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
3177 QDIO_MAX_BUFFERS_PER_Q;
3178 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3179 qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
3180 qeth_flush_buffers(queue, index, 1);
3181 return 0;
3182 out:
3183 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3184 return -EBUSY;
3185 }
3186 EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
3187
3188 int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
3189 struct sk_buff *skb, struct qeth_hdr *hdr,
3190 int elements_needed)
3191 {
3192 struct qeth_qdio_out_buffer *buffer;
3193 int start_index;
3194 int flush_count = 0;
3195 int do_pack = 0;
3196 int tmp;
3197 int rc = 0;
3198
3199 /* spin until we get the queue ... */
3200 while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
3201 QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
3202 start_index = queue->next_buf_to_fill;
3203 buffer = &queue->bufs[queue->next_buf_to_fill];
3204 /*
3205 * check if buffer is empty to make sure that we do not 'overtake'
3206 * ourselves and try to fill a buffer that is already primed
3207 */
3208 if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
3209 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3210 return -EBUSY;
3211 }
3212 /* check if we need to switch packing state of this queue */
3213 qeth_switch_to_packing_if_needed(queue);
3214 if (queue->do_pack) {
3215 do_pack = 1;
3216 /* does packet fit in current buffer? */
3217 if ((QETH_MAX_BUFFER_ELEMENTS(card) -
3218 buffer->next_element_to_fill) < elements_needed) {
3219 /* ... no -> set state PRIMED */
3220 atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
3221 flush_count++;
3222 queue->next_buf_to_fill =
3223 (queue->next_buf_to_fill + 1) %
3224 QDIO_MAX_BUFFERS_PER_Q;
3225 buffer = &queue->bufs[queue->next_buf_to_fill];
3226 /* we did a step forward, so check buffer state
3227 * again */
3228 if (atomic_read(&buffer->state) !=
3229 QETH_QDIO_BUF_EMPTY) {
3230 qeth_flush_buffers(queue, start_index,
3231 flush_count);
3232 atomic_set(&queue->state,
3233 QETH_OUT_Q_UNLOCKED);
3234 return -EBUSY;
3235 }
3236 }
3237 }
3238 tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
3239 queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
3240 QDIO_MAX_BUFFERS_PER_Q;
3241 flush_count += tmp;
3242 if (flush_count)
3243 qeth_flush_buffers(queue, start_index, flush_count);
3244 else if (!atomic_read(&queue->set_pci_flags_count))
3245 atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
3246 /*
3247 * queue->state will go from LOCKED -> UNLOCKED or from
3248 * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
3249 * (switch packing state or flush buffer to get another pci flag out).
3250 * In that case we will enter this loop
3251 */
3252 while (atomic_dec_return(&queue->state)) {
3253 flush_count = 0;
3254 start_index = queue->next_buf_to_fill;
3255 /* check if we can go back to non-packing state */
3256 flush_count += qeth_switch_to_nonpacking_if_needed(queue);
3257 /*
3258 * check if we need to flush a packing buffer to get a pci
3259 * flag out on the queue
3260 */
3261 if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
3262 flush_count += qeth_flush_buffers_on_no_pci(queue);
3263 if (flush_count)
3264 qeth_flush_buffers(queue, start_index, flush_count);
3265 }
3266 /* at this point the queue is UNLOCKED again */
3267 if (queue->card->options.performance_stats && do_pack)
3268 queue->card->perf_stats.bufs_sent_pack += flush_count;
3269
3270 return rc;
3271 }
3272 EXPORT_SYMBOL_GPL(qeth_do_send_packet);
3273
3274 static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
3275 struct qeth_reply *reply, unsigned long data)
3276 {
3277 struct qeth_ipa_cmd *cmd;
3278 struct qeth_ipacmd_setadpparms *setparms;
3279
3280 QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
3281
3282 cmd = (struct qeth_ipa_cmd *) data;
3283 setparms = &(cmd->data.setadapterparms);
3284
3285 qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
3286 if (cmd->hdr.return_code) {
3287 QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
3288 setparms->data.mode = SET_PROMISC_MODE_OFF;
3289 }
3290 card->info.promisc_mode = setparms->data.mode;
3291 return 0;
3292 }
3293
3294 void qeth_setadp_promisc_mode(struct qeth_card *card)
3295 {
3296 enum qeth_ipa_promisc_modes mode;
3297 struct net_device *dev = card->dev;
3298 struct qeth_cmd_buffer *iob;
3299 struct qeth_ipa_cmd *cmd;
3300
3301 QETH_DBF_TEXT(TRACE, 4, "setprom");
3302
3303 if (((dev->flags & IFF_PROMISC) &&
3304 (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
3305 (!(dev->flags & IFF_PROMISC) &&
3306 (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
3307 return;
3308 mode = SET_PROMISC_MODE_OFF;
3309 if (dev->flags & IFF_PROMISC)
3310 mode = SET_PROMISC_MODE_ON;
3311 QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
3312
3313 iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
3314 sizeof(struct qeth_ipacmd_setadpparms));
3315 cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
3316 cmd->data.setadapterparms.data.mode = mode;
3317 qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
3318 }
3319 EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
3320
3321 int qeth_change_mtu(struct net_device *dev, int new_mtu)
3322 {
3323 struct qeth_card *card;
3324 char dbf_text[15];
3325
3326 card = dev->ml_priv;
3327
3328 QETH_DBF_TEXT(TRACE, 4, "chgmtu");
3329 sprintf(dbf_text, "%8x", new_mtu);
3330 QETH_DBF_TEXT(TRACE, 4, dbf_text);
3331
3332 if (new_mtu < 64)
3333 return -EINVAL;
3334 if (new_mtu > 65535)
3335 return -EINVAL;
3336 if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
3337 (!qeth_mtu_is_valid(card, new_mtu)))
3338 return -EINVAL;
3339 dev->mtu = new_mtu;
3340 return 0;
3341 }
3342 EXPORT_SYMBOL_GPL(qeth_change_mtu);
3343
3344 struct net_device_stats *qeth_get_stats(struct net_device *dev)
3345 {
3346 struct qeth_card *card;
3347
3348 card = dev->ml_priv;
3349
3350 QETH_DBF_TEXT(TRACE, 5, "getstat");
3351
3352 return &card->stats;
3353 }
3354 EXPORT_SYMBOL_GPL(qeth_get_stats);
3355
3356 static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
3357 struct qeth_reply *reply, unsigned long data)
3358 {
3359 struct qeth_ipa_cmd *cmd;
3360
3361 QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
3362
3363 cmd = (struct qeth_ipa_cmd *) data;
3364 if (!card->options.layer2 ||
3365 !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
3366 memcpy(card->dev->dev_addr,
3367 &cmd->data.setadapterparms.data.change_addr.addr,
3368 OSA_ADDR_LEN);
3369 card->info.mac_bits |= QETH_LAYER2_MAC_READ;
3370 }
3371 qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
3372 return 0;
3373 }
3374
3375 int qeth_setadpparms_change_macaddr(struct qeth_card *card)
3376 {
3377 int rc;
3378 struct qeth_cmd_buffer *iob;
3379 struct qeth_ipa_cmd *cmd;
3380
3381 QETH_DBF_TEXT(TRACE, 4, "chgmac");
3382
3383 iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
3384 sizeof(struct qeth_ipacmd_setadpparms));
3385 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
3386 cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
3387 cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
3388 memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
3389 card->dev->dev_addr, OSA_ADDR_LEN);
3390 rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
3391 NULL);
3392 return rc;
3393 }
3394 EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
3395
3396 void qeth_tx_timeout(struct net_device *dev)
3397 {
3398 struct qeth_card *card;
3399
3400 card = dev->ml_priv;
3401 card->stats.tx_errors++;
3402 qeth_schedule_recovery(card);
3403 }
3404 EXPORT_SYMBOL_GPL(qeth_tx_timeout);
3405
3406 int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
3407 {
3408 struct qeth_card *card = dev->ml_priv;
3409 int rc = 0;
3410
3411 switch (regnum) {
3412 case MII_BMCR: /* Basic mode control register */
3413 rc = BMCR_FULLDPLX;
3414 if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
3415 (card->info.link_type != QETH_LINK_TYPE_OSN) &&
3416 (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
3417 rc |= BMCR_SPEED100;
3418 break;
3419 case MII_BMSR: /* Basic mode status register */
3420 rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
3421 BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
3422 BMSR_100BASE4;
3423 break;
3424 case MII_PHYSID1: /* PHYS ID 1 */
3425 rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
3426 dev->dev_addr[2];
3427 rc = (rc >> 5) & 0xFFFF;
3428 break;
3429 case MII_PHYSID2: /* PHYS ID 2 */
3430 rc = (dev->dev_addr[2] << 10) & 0xFFFF;
3431 break;
3432 case MII_ADVERTISE: /* Advertisement control reg */
3433 rc = ADVERTISE_ALL;
3434 break;
3435 case MII_LPA: /* Link partner ability reg */
3436 rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
3437 LPA_100BASE4 | LPA_LPACK;
3438 break;
3439 case MII_EXPANSION: /* Expansion register */
3440 break;
3441 case MII_DCOUNTER: /* disconnect counter */
3442 break;
3443 case MII_FCSCOUNTER: /* false carrier counter */
3444 break;
3445 case MII_NWAYTEST: /* N-way auto-neg test register */
3446 break;
3447 case MII_RERRCOUNTER: /* rx error counter */
3448 rc = card->stats.rx_errors;
3449 break;
3450 case MII_SREVISION: /* silicon revision */
3451 break;
3452 case MII_RESV1: /* reserved 1 */
3453 break;
3454 case MII_LBRERROR: /* loopback, rx, bypass error */
3455 break;
3456 case MII_PHYADDR: /* physical address */
3457 break;
3458 case MII_RESV2: /* reserved 2 */
3459 break;
3460 case MII_TPISTATUS: /* TPI status for 10mbps */
3461 break;
3462 case MII_NCONFIG: /* network interface config */
3463 break;
3464 default:
3465 break;
3466 }
3467 return rc;
3468 }
3469 EXPORT_SYMBOL_GPL(qeth_mdio_read);
3470
3471 static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
3472 struct qeth_cmd_buffer *iob, int len,
3473 int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
3474 unsigned long),
3475 void *reply_param)
3476 {
3477 u16 s1, s2;
3478
3479 QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
3480
3481 memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
3482 memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
3483 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
3484 /* adjust PDU length fields in IPA_PDU_HEADER */
3485 s1 = (u32) IPA_PDU_HEADER_SIZE + len;
3486 s2 = (u32) len;
3487 memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
3488 memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
3489 memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
3490 memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
3491 return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
3492 reply_cb, reply_param);
3493 }
3494
3495 static int qeth_snmp_command_cb(struct qeth_card *card,
3496 struct qeth_reply *reply, unsigned long sdata)
3497 {
3498 struct qeth_ipa_cmd *cmd;
3499 struct qeth_arp_query_info *qinfo;
3500 struct qeth_snmp_cmd *snmp;
3501 unsigned char *data;
3502 __u16 data_len;
3503
3504 QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
3505
3506 cmd = (struct qeth_ipa_cmd *) sdata;
3507 data = (unsigned char *)((char *)cmd - reply->offset);
3508 qinfo = (struct qeth_arp_query_info *) reply->param;
3509 snmp = &cmd->data.setadapterparms.data.snmp;
3510
3511 if (cmd->hdr.return_code) {
3512 QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
3513 return 0;
3514 }
3515 if (cmd->data.setadapterparms.hdr.return_code) {
3516 cmd->hdr.return_code =
3517 cmd->data.setadapterparms.hdr.return_code;
3518 QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
3519 return 0;
3520 }
3521 data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
3522 if (cmd->data.setadapterparms.hdr.seq_no == 1)
3523 data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
3524 else
3525 data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
3526
3527 /* check if there is enough room in userspace */
3528 if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
3529 QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
3530 cmd->hdr.return_code = -ENOMEM;
3531 return 0;
3532 }
3533 QETH_DBF_TEXT_(TRACE, 4, "snore%i",
3534 cmd->data.setadapterparms.hdr.used_total);
3535 QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
3536 cmd->data.setadapterparms.hdr.seq_no);
3537 /*copy entries to user buffer*/
3538 if (cmd->data.setadapterparms.hdr.seq_no == 1) {
3539 memcpy(qinfo->udata + qinfo->udata_offset,
3540 (char *)snmp,
3541 data_len + offsetof(struct qeth_snmp_cmd, data));
3542 qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
3543 } else {
3544 memcpy(qinfo->udata + qinfo->udata_offset,
3545 (char *)&snmp->request, data_len);
3546 }
3547 qinfo->udata_offset += data_len;
3548 /* check if all replies received ... */
3549 QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
3550 cmd->data.setadapterparms.hdr.used_total);
3551 QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
3552 cmd->data.setadapterparms.hdr.seq_no);
3553 if (cmd->data.setadapterparms.hdr.seq_no <
3554 cmd->data.setadapterparms.hdr.used_total)
3555 return 1;
3556 return 0;
3557 }
3558
3559 int qeth_snmp_command(struct qeth_card *card, char __user *udata)
3560 {
3561 struct qeth_cmd_buffer *iob;
3562 struct qeth_ipa_cmd *cmd;
3563 struct qeth_snmp_ureq *ureq;
3564 int req_len;
3565 struct qeth_arp_query_info qinfo = {0, };
3566 int rc = 0;
3567
3568 QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
3569
3570 if (card->info.guestlan)
3571 return -EOPNOTSUPP;
3572
3573 if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
3574 (!card->options.layer2)) {
3575 return -EOPNOTSUPP;
3576 }
3577 /* skip 4 bytes (data_len struct member) to get req_len */
3578 if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
3579 return -EFAULT;
3580 ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
3581 if (!ureq) {
3582 QETH_DBF_TEXT(TRACE, 2, "snmpnome");
3583 return -ENOMEM;
3584 }
3585 if (copy_from_user(ureq, udata,
3586 req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
3587 kfree(ureq);
3588 return -EFAULT;
3589 }
3590 qinfo.udata_len = ureq->hdr.data_len;
3591 qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
3592 if (!qinfo.udata) {
3593 kfree(ureq);
3594 return -ENOMEM;
3595 }
3596 qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
3597
3598 iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
3599 QETH_SNMP_SETADP_CMDLENGTH + req_len);
3600 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
3601 memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
3602 rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
3603 qeth_snmp_command_cb, (void *)&qinfo);
3604 if (rc)
3605 QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
3606 QETH_CARD_IFNAME(card), rc);
3607 else {
3608 if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
3609 rc = -EFAULT;
3610 }
3611
3612 kfree(ureq);
3613 kfree(qinfo.udata);
3614 return rc;
3615 }
3616 EXPORT_SYMBOL_GPL(qeth_snmp_command);
3617
3618 static inline int qeth_get_qdio_q_format(struct qeth_card *card)
3619 {
3620 switch (card->info.type) {
3621 case QETH_CARD_TYPE_IQD:
3622 return 2;
3623 default:
3624 return 0;
3625 }
3626 }
3627
3628 static int qeth_qdio_establish(struct qeth_card *card)
3629 {
3630 struct qdio_initialize init_data;
3631 char *qib_param_field;
3632 struct qdio_buffer **in_sbal_ptrs;
3633 struct qdio_buffer **out_sbal_ptrs;
3634 int i, j, k;
3635 int rc = 0;
3636
3637 QETH_DBF_TEXT(SETUP, 2, "qdioest");
3638
3639 qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
3640 GFP_KERNEL);
3641 if (!qib_param_field)
3642 return -ENOMEM;
3643
3644 qeth_create_qib_param_field(card, qib_param_field);
3645 qeth_create_qib_param_field_blkt(card, qib_param_field);
3646
3647 in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
3648 GFP_KERNEL);
3649 if (!in_sbal_ptrs) {
3650 kfree(qib_param_field);
3651 return -ENOMEM;
3652 }
3653 for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
3654 in_sbal_ptrs[i] = (struct qdio_buffer *)
3655 virt_to_phys(card->qdio.in_q->bufs[i].buffer);
3656
3657 out_sbal_ptrs =
3658 kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
3659 sizeof(void *), GFP_KERNEL);
3660 if (!out_sbal_ptrs) {
3661 kfree(in_sbal_ptrs);
3662 kfree(qib_param_field);
3663 return -ENOMEM;
3664 }
3665 for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
3666 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
3667 out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
3668 card->qdio.out_qs[i]->bufs[j].buffer);
3669 }
3670
3671 memset(&init_data, 0, sizeof(struct qdio_initialize));
3672 init_data.cdev = CARD_DDEV(card);
3673 init_data.q_format = qeth_get_qdio_q_format(card);
3674 init_data.qib_param_field_format = 0;
3675 init_data.qib_param_field = qib_param_field;
3676 init_data.no_input_qs = 1;
3677 init_data.no_output_qs = card->qdio.no_out_queues;
3678 init_data.input_handler = card->discipline.input_handler;
3679 init_data.output_handler = card->discipline.output_handler;
3680 init_data.int_parm = (unsigned long) card;
3681 init_data.flags = QDIO_INBOUND_0COPY_SBALS |
3682 QDIO_OUTBOUND_0COPY_SBALS |
3683 QDIO_USE_OUTBOUND_PCIS;
3684 init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
3685 init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
3686
3687 if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
3688 QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
3689 rc = qdio_initialize(&init_data);
3690 if (rc)
3691 atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
3692 }
3693 kfree(out_sbal_ptrs);
3694 kfree(in_sbal_ptrs);
3695 kfree(qib_param_field);
3696 return rc;
3697 }
3698
3699 static void qeth_core_free_card(struct qeth_card *card)
3700 {
3701
3702 QETH_DBF_TEXT(SETUP, 2, "freecrd");
3703 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
3704 qeth_clean_channel(&card->read);
3705 qeth_clean_channel(&card->write);
3706 if (card->dev)
3707 free_netdev(card->dev);
3708 kfree(card->ip_tbd_list);
3709 qeth_free_qdio_buffers(card);
3710 unregister_service_level(&card->qeth_service_level);
3711 kfree(card);
3712 }
3713
3714 static struct ccw_device_id qeth_ids[] = {
3715 {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
3716 {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
3717 {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
3718 {},
3719 };
3720 MODULE_DEVICE_TABLE(ccw, qeth_ids);
3721
3722 static struct ccw_driver qeth_ccw_driver = {
3723 .name = "qeth",
3724 .ids = qeth_ids,
3725 .probe = ccwgroup_probe_ccwdev,
3726 .remove = ccwgroup_remove_ccwdev,
3727 };
3728
3729 static int qeth_core_driver_group(const char *buf, struct device *root_dev,
3730 unsigned long driver_id)
3731 {
3732 return ccwgroup_create_from_string(root_dev, driver_id,
3733 &qeth_ccw_driver, 3, buf);
3734 }
3735
3736 int qeth_core_hardsetup_card(struct qeth_card *card)
3737 {
3738 struct qdio_ssqd_desc *ssqd;
3739 int retries = 3;
3740 int mpno = 0;
3741 int rc;
3742
3743 QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
3744 atomic_set(&card->force_alloc_skb, 0);
3745 retry:
3746 if (retries < 3) {
3747 QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
3748 dev_name(&card->gdev->dev));
3749 ccw_device_set_offline(CARD_DDEV(card));
3750 ccw_device_set_offline(CARD_WDEV(card));
3751 ccw_device_set_offline(CARD_RDEV(card));
3752 ccw_device_set_online(CARD_RDEV(card));
3753 ccw_device_set_online(CARD_WDEV(card));
3754 ccw_device_set_online(CARD_DDEV(card));
3755 }
3756 rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
3757 if (rc == -ERESTARTSYS) {
3758 QETH_DBF_TEXT(SETUP, 2, "break1");
3759 return rc;
3760 } else if (rc) {
3761 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
3762 if (--retries < 0)
3763 goto out;
3764 else
3765 goto retry;
3766 }
3767
3768 rc = qeth_get_unitaddr(card);
3769 if (rc) {
3770 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
3771 return rc;
3772 }
3773
3774 ssqd = kmalloc(sizeof(struct qdio_ssqd_desc), GFP_KERNEL);
3775 if (!ssqd) {
3776 rc = -ENOMEM;
3777 goto out;
3778 }
3779 rc = qdio_get_ssqd_desc(CARD_DDEV(card), ssqd);
3780 if (rc == 0)
3781 mpno = ssqd->pcnt;
3782 kfree(ssqd);
3783
3784 if (mpno)
3785 mpno = min(mpno - 1, QETH_MAX_PORTNO);
3786 if (card->info.portno > mpno) {
3787 QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
3788 "\n.", CARD_BUS_ID(card), card->info.portno);
3789 rc = -ENODEV;
3790 goto out;
3791 }
3792 qeth_init_tokens(card);
3793 qeth_init_func_level(card);
3794 rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
3795 if (rc == -ERESTARTSYS) {
3796 QETH_DBF_TEXT(SETUP, 2, "break2");
3797 return rc;
3798 } else if (rc) {
3799 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
3800 if (--retries < 0)
3801 goto out;
3802 else
3803 goto retry;
3804 }
3805 rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
3806 if (rc == -ERESTARTSYS) {
3807 QETH_DBF_TEXT(SETUP, 2, "break3");
3808 return rc;
3809 } else if (rc) {
3810 QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
3811 if (--retries < 0)
3812 goto out;
3813 else
3814 goto retry;
3815 }
3816 rc = qeth_mpc_initialize(card);
3817 if (rc) {
3818 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
3819 goto out;
3820 }
3821 return 0;
3822 out:
3823 dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
3824 "an error on the device\n");
3825 QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
3826 dev_name(&card->gdev->dev), rc);
3827 return rc;
3828 }
3829 EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
3830
3831 static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
3832 struct sk_buff **pskb, int offset, int *pfrag, int data_len)
3833 {
3834 struct page *page = virt_to_page(element->addr);
3835 if (*pskb == NULL) {
3836 /* the upper protocol layers assume that there is data in the
3837 * skb itself. Copy a small amount (64 bytes) to make them
3838 * happy. */
3839 *pskb = dev_alloc_skb(64 + ETH_HLEN);
3840 if (!(*pskb))
3841 return -ENOMEM;
3842 skb_reserve(*pskb, ETH_HLEN);
3843 if (data_len <= 64) {
3844 memcpy(skb_put(*pskb, data_len), element->addr + offset,
3845 data_len);
3846 } else {
3847 get_page(page);
3848 memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
3849 skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
3850 data_len - 64);
3851 (*pskb)->data_len += data_len - 64;
3852 (*pskb)->len += data_len - 64;
3853 (*pskb)->truesize += data_len - 64;
3854 (*pfrag)++;
3855 }
3856 } else {
3857 get_page(page);
3858 skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
3859 (*pskb)->data_len += data_len;
3860 (*pskb)->len += data_len;
3861 (*pskb)->truesize += data_len;
3862 (*pfrag)++;
3863 }
3864 return 0;
3865 }
3866
3867 struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
3868 struct qdio_buffer *buffer,
3869 struct qdio_buffer_element **__element, int *__offset,
3870 struct qeth_hdr **hdr)
3871 {
3872 struct qdio_buffer_element *element = *__element;
3873 int offset = *__offset;
3874 struct sk_buff *skb = NULL;
3875 int skb_len;
3876 void *data_ptr;
3877 int data_len;
3878 int headroom = 0;
3879 int use_rx_sg = 0;
3880 int frag = 0;
3881
3882 /* qeth_hdr must not cross element boundaries */
3883 if (element->length < offset + sizeof(struct qeth_hdr)) {
3884 if (qeth_is_last_sbale(element))
3885 return NULL;
3886 element++;
3887 offset = 0;
3888 if (element->length < sizeof(struct qeth_hdr))
3889 return NULL;
3890 }
3891 *hdr = element->addr + offset;
3892
3893 offset += sizeof(struct qeth_hdr);
3894 if (card->options.layer2) {
3895 if (card->info.type == QETH_CARD_TYPE_OSN) {
3896 skb_len = (*hdr)->hdr.osn.pdu_length;
3897 headroom = sizeof(struct qeth_hdr);
3898 } else {
3899 skb_len = (*hdr)->hdr.l2.pkt_length;
3900 }
3901 } else {
3902 skb_len = (*hdr)->hdr.l3.length;
3903 if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
3904 (card->info.link_type == QETH_LINK_TYPE_HSTR))
3905 headroom = TR_HLEN;
3906 else
3907 headroom = ETH_HLEN;
3908 }
3909
3910 if (!skb_len)
3911 return NULL;
3912
3913 if ((skb_len >= card->options.rx_sg_cb) &&
3914 (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
3915 (!atomic_read(&card->force_alloc_skb))) {
3916 use_rx_sg = 1;
3917 } else {
3918 skb = dev_alloc_skb(skb_len + headroom);
3919 if (!skb)
3920 goto no_mem;
3921 if (headroom)
3922 skb_reserve(skb, headroom);
3923 }
3924
3925 data_ptr = element->addr + offset;
3926 while (skb_len) {
3927 data_len = min(skb_len, (int)(element->length - offset));
3928 if (data_len) {
3929 if (use_rx_sg) {
3930 if (qeth_create_skb_frag(element, &skb, offset,
3931 &frag, data_len))
3932 goto no_mem;
3933 } else {
3934 memcpy(skb_put(skb, data_len), data_ptr,
3935 data_len);
3936 }
3937 }
3938 skb_len -= data_len;
3939 if (skb_len) {
3940 if (qeth_is_last_sbale(element)) {
3941 QETH_DBF_TEXT(TRACE, 4, "unexeob");
3942 QETH_DBF_TEXT_(TRACE, 4, "%s",
3943 CARD_BUS_ID(card));
3944 QETH_DBF_TEXT(QERR, 2, "unexeob");
3945 QETH_DBF_TEXT_(QERR, 2, "%s",
3946 CARD_BUS_ID(card));
3947 QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
3948 dev_kfree_skb_any(skb);
3949 card->stats.rx_errors++;
3950 return NULL;
3951 }
3952 element++;
3953 offset = 0;
3954 data_ptr = element->addr;
3955 } else {
3956 offset += data_len;
3957 }
3958 }
3959 *__element = element;
3960 *__offset = offset;
3961 if (use_rx_sg && card->options.performance_stats) {
3962 card->perf_stats.sg_skbs_rx++;
3963 card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
3964 }
3965 return skb;
3966 no_mem:
3967 if (net_ratelimit()) {
3968 QETH_DBF_TEXT(TRACE, 2, "noskbmem");
3969 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
3970 }
3971 card->stats.rx_dropped++;
3972 return NULL;
3973 }
3974 EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
3975
3976 static void qeth_unregister_dbf_views(void)
3977 {
3978 int x;
3979 for (x = 0; x < QETH_DBF_INFOS; x++) {
3980 debug_unregister(qeth_dbf[x].id);
3981 qeth_dbf[x].id = NULL;
3982 }
3983 }
3984
3985 void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
3986 {
3987 char dbf_txt_buf[32];
3988 va_list args;
3989
3990 if (level > (qeth_dbf[dbf_nix].id)->level)
3991 return;
3992 va_start(args, fmt);
3993 vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
3994 va_end(args);
3995 debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
3996 }
3997 EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
3998
3999 static int qeth_register_dbf_views(void)
4000 {
4001 int ret;
4002 int x;
4003
4004 for (x = 0; x < QETH_DBF_INFOS; x++) {
4005 /* register the areas */
4006 qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
4007 qeth_dbf[x].pages,
4008 qeth_dbf[x].areas,
4009 qeth_dbf[x].len);
4010 if (qeth_dbf[x].id == NULL) {
4011 qeth_unregister_dbf_views();
4012 return -ENOMEM;
4013 }
4014
4015 /* register a view */
4016 ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
4017 if (ret) {
4018 qeth_unregister_dbf_views();
4019 return ret;
4020 }
4021
4022 /* set a passing level */
4023 debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
4024 }
4025
4026 return 0;
4027 }
4028
4029 int qeth_core_load_discipline(struct qeth_card *card,
4030 enum qeth_discipline_id discipline)
4031 {
4032 int rc = 0;
4033 switch (discipline) {
4034 case QETH_DISCIPLINE_LAYER3:
4035 card->discipline.ccwgdriver = try_then_request_module(
4036 symbol_get(qeth_l3_ccwgroup_driver),
4037 "qeth_l3");
4038 break;
4039 case QETH_DISCIPLINE_LAYER2:
4040 card->discipline.ccwgdriver = try_then_request_module(
4041 symbol_get(qeth_l2_ccwgroup_driver),
4042 "qeth_l2");
4043 break;
4044 }
4045 if (!card->discipline.ccwgdriver) {
4046 dev_err(&card->gdev->dev, "There is no kernel module to "
4047 "support discipline %d\n", discipline);
4048 rc = -EINVAL;
4049 }
4050 return rc;
4051 }
4052
4053 void qeth_core_free_discipline(struct qeth_card *card)
4054 {
4055 if (card->options.layer2)
4056 symbol_put(qeth_l2_ccwgroup_driver);
4057 else
4058 symbol_put(qeth_l3_ccwgroup_driver);
4059 card->discipline.ccwgdriver = NULL;
4060 }
4061
4062 static int qeth_core_probe_device(struct ccwgroup_device *gdev)
4063 {
4064 struct qeth_card *card;
4065 struct device *dev;
4066 int rc;
4067 unsigned long flags;
4068
4069 QETH_DBF_TEXT(SETUP, 2, "probedev");
4070
4071 dev = &gdev->dev;
4072 if (!get_device(dev))
4073 return -ENODEV;
4074
4075 QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
4076
4077 card = qeth_alloc_card();
4078 if (!card) {
4079 QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
4080 rc = -ENOMEM;
4081 goto err_dev;
4082 }
4083 card->read.ccwdev = gdev->cdev[0];
4084 card->write.ccwdev = gdev->cdev[1];
4085 card->data.ccwdev = gdev->cdev[2];
4086 dev_set_drvdata(&gdev->dev, card);
4087 card->gdev = gdev;
4088 gdev->cdev[0]->handler = qeth_irq;
4089 gdev->cdev[1]->handler = qeth_irq;
4090 gdev->cdev[2]->handler = qeth_irq;
4091
4092 rc = qeth_determine_card_type(card);
4093 if (rc) {
4094 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
4095 goto err_card;
4096 }
4097 rc = qeth_setup_card(card);
4098 if (rc) {
4099 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
4100 goto err_card;
4101 }
4102
4103 if (card->info.type == QETH_CARD_TYPE_OSN) {
4104 rc = qeth_core_create_osn_attributes(dev);
4105 if (rc)
4106 goto err_card;
4107 rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
4108 if (rc) {
4109 qeth_core_remove_osn_attributes(dev);
4110 goto err_card;
4111 }
4112 rc = card->discipline.ccwgdriver->probe(card->gdev);
4113 if (rc) {
4114 qeth_core_free_discipline(card);
4115 qeth_core_remove_osn_attributes(dev);
4116 goto err_card;
4117 }
4118 } else {
4119 rc = qeth_core_create_device_attributes(dev);
4120 if (rc)
4121 goto err_card;
4122 }
4123
4124 write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
4125 list_add_tail(&card->list, &qeth_core_card_list.list);
4126 write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
4127 return 0;
4128
4129 err_card:
4130 qeth_core_free_card(card);
4131 err_dev:
4132 put_device(dev);
4133 return rc;
4134 }
4135
4136 static void qeth_core_remove_device(struct ccwgroup_device *gdev)
4137 {
4138 unsigned long flags;
4139 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4140
4141 QETH_DBF_TEXT(SETUP, 2, "removedv");
4142 if (card->discipline.ccwgdriver) {
4143 card->discipline.ccwgdriver->remove(gdev);
4144 qeth_core_free_discipline(card);
4145 }
4146
4147 if (card->info.type == QETH_CARD_TYPE_OSN) {
4148 qeth_core_remove_osn_attributes(&gdev->dev);
4149 } else {
4150 qeth_core_remove_device_attributes(&gdev->dev);
4151 }
4152 write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
4153 list_del(&card->list);
4154 write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
4155 qeth_core_free_card(card);
4156 dev_set_drvdata(&gdev->dev, NULL);
4157 put_device(&gdev->dev);
4158 return;
4159 }
4160
4161 static int qeth_core_set_online(struct ccwgroup_device *gdev)
4162 {
4163 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4164 int rc = 0;
4165 int def_discipline;
4166
4167 if (!card->discipline.ccwgdriver) {
4168 if (card->info.type == QETH_CARD_TYPE_IQD)
4169 def_discipline = QETH_DISCIPLINE_LAYER3;
4170 else
4171 def_discipline = QETH_DISCIPLINE_LAYER2;
4172 rc = qeth_core_load_discipline(card, def_discipline);
4173 if (rc)
4174 goto err;
4175 rc = card->discipline.ccwgdriver->probe(card->gdev);
4176 if (rc)
4177 goto err;
4178 }
4179 rc = card->discipline.ccwgdriver->set_online(gdev);
4180 err:
4181 return rc;
4182 }
4183
4184 static int qeth_core_set_offline(struct ccwgroup_device *gdev)
4185 {
4186 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4187 return card->discipline.ccwgdriver->set_offline(gdev);
4188 }
4189
4190 static void qeth_core_shutdown(struct ccwgroup_device *gdev)
4191 {
4192 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4193 if (card->discipline.ccwgdriver &&
4194 card->discipline.ccwgdriver->shutdown)
4195 card->discipline.ccwgdriver->shutdown(gdev);
4196 }
4197
4198 static int qeth_core_prepare(struct ccwgroup_device *gdev)
4199 {
4200 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4201 if (card->discipline.ccwgdriver &&
4202 card->discipline.ccwgdriver->prepare)
4203 return card->discipline.ccwgdriver->prepare(gdev);
4204 return 0;
4205 }
4206
4207 static void qeth_core_complete(struct ccwgroup_device *gdev)
4208 {
4209 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4210 if (card->discipline.ccwgdriver &&
4211 card->discipline.ccwgdriver->complete)
4212 card->discipline.ccwgdriver->complete(gdev);
4213 }
4214
4215 static int qeth_core_freeze(struct ccwgroup_device *gdev)
4216 {
4217 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4218 if (card->discipline.ccwgdriver &&
4219 card->discipline.ccwgdriver->freeze)
4220 return card->discipline.ccwgdriver->freeze(gdev);
4221 return 0;
4222 }
4223
4224 static int qeth_core_thaw(struct ccwgroup_device *gdev)
4225 {
4226 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4227 if (card->discipline.ccwgdriver &&
4228 card->discipline.ccwgdriver->thaw)
4229 return card->discipline.ccwgdriver->thaw(gdev);
4230 return 0;
4231 }
4232
4233 static int qeth_core_restore(struct ccwgroup_device *gdev)
4234 {
4235 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4236 if (card->discipline.ccwgdriver &&
4237 card->discipline.ccwgdriver->restore)
4238 return card->discipline.ccwgdriver->restore(gdev);
4239 return 0;
4240 }
4241
4242 static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
4243 .owner = THIS_MODULE,
4244 .name = "qeth",
4245 .driver_id = 0xD8C5E3C8,
4246 .probe = qeth_core_probe_device,
4247 .remove = qeth_core_remove_device,
4248 .set_online = qeth_core_set_online,
4249 .set_offline = qeth_core_set_offline,
4250 .shutdown = qeth_core_shutdown,
4251 .prepare = qeth_core_prepare,
4252 .complete = qeth_core_complete,
4253 .freeze = qeth_core_freeze,
4254 .thaw = qeth_core_thaw,
4255 .restore = qeth_core_restore,
4256 };
4257
4258 static ssize_t
4259 qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
4260 size_t count)
4261 {
4262 int err;
4263 err = qeth_core_driver_group(buf, qeth_core_root_dev,
4264 qeth_core_ccwgroup_driver.driver_id);
4265 if (err)
4266 return err;
4267 else
4268 return count;
4269 }
4270
4271 static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
4272
4273 static struct {
4274 const char str[ETH_GSTRING_LEN];
4275 } qeth_ethtool_stats_keys[] = {
4276 /* 0 */{"rx skbs"},
4277 {"rx buffers"},
4278 {"tx skbs"},
4279 {"tx buffers"},
4280 {"tx skbs no packing"},
4281 {"tx buffers no packing"},
4282 {"tx skbs packing"},
4283 {"tx buffers packing"},
4284 {"tx sg skbs"},
4285 {"tx sg frags"},
4286 /* 10 */{"rx sg skbs"},
4287 {"rx sg frags"},
4288 {"rx sg page allocs"},
4289 {"tx large kbytes"},
4290 {"tx large count"},
4291 {"tx pk state ch n->p"},
4292 {"tx pk state ch p->n"},
4293 {"tx pk watermark low"},
4294 {"tx pk watermark high"},
4295 {"queue 0 buffer usage"},
4296 /* 20 */{"queue 1 buffer usage"},
4297 {"queue 2 buffer usage"},
4298 {"queue 3 buffer usage"},
4299 {"rx handler time"},
4300 {"rx handler count"},
4301 {"rx do_QDIO time"},
4302 {"rx do_QDIO count"},
4303 {"tx handler time"},
4304 {"tx handler count"},
4305 {"tx time"},
4306 /* 30 */{"tx count"},
4307 {"tx do_QDIO time"},
4308 {"tx do_QDIO count"},
4309 {"tx csum"},
4310 };
4311
4312 int qeth_core_get_stats_count(struct net_device *dev)
4313 {
4314 return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
4315 }
4316 EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
4317
4318 void qeth_core_get_ethtool_stats(struct net_device *dev,
4319 struct ethtool_stats *stats, u64 *data)
4320 {
4321 struct qeth_card *card = dev->ml_priv;
4322 data[0] = card->stats.rx_packets -
4323 card->perf_stats.initial_rx_packets;
4324 data[1] = card->perf_stats.bufs_rec;
4325 data[2] = card->stats.tx_packets -
4326 card->perf_stats.initial_tx_packets;
4327 data[3] = card->perf_stats.bufs_sent;
4328 data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
4329 - card->perf_stats.skbs_sent_pack;
4330 data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
4331 data[6] = card->perf_stats.skbs_sent_pack;
4332 data[7] = card->perf_stats.bufs_sent_pack;
4333 data[8] = card->perf_stats.sg_skbs_sent;
4334 data[9] = card->perf_stats.sg_frags_sent;
4335 data[10] = card->perf_stats.sg_skbs_rx;
4336 data[11] = card->perf_stats.sg_frags_rx;
4337 data[12] = card->perf_stats.sg_alloc_page_rx;
4338 data[13] = (card->perf_stats.large_send_bytes >> 10);
4339 data[14] = card->perf_stats.large_send_cnt;
4340 data[15] = card->perf_stats.sc_dp_p;
4341 data[16] = card->perf_stats.sc_p_dp;
4342 data[17] = QETH_LOW_WATERMARK_PACK;
4343 data[18] = QETH_HIGH_WATERMARK_PACK;
4344 data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
4345 data[20] = (card->qdio.no_out_queues > 1) ?
4346 atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
4347 data[21] = (card->qdio.no_out_queues > 2) ?
4348 atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
4349 data[22] = (card->qdio.no_out_queues > 3) ?
4350 atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
4351 data[23] = card->perf_stats.inbound_time;
4352 data[24] = card->perf_stats.inbound_cnt;
4353 data[25] = card->perf_stats.inbound_do_qdio_time;
4354 data[26] = card->perf_stats.inbound_do_qdio_cnt;
4355 data[27] = card->perf_stats.outbound_handler_time;
4356 data[28] = card->perf_stats.outbound_handler_cnt;
4357 data[29] = card->perf_stats.outbound_time;
4358 data[30] = card->perf_stats.outbound_cnt;
4359 data[31] = card->perf_stats.outbound_do_qdio_time;
4360 data[32] = card->perf_stats.outbound_do_qdio_cnt;
4361 data[33] = card->perf_stats.tx_csum;
4362 }
4363 EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
4364
4365 void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4366 {
4367 switch (stringset) {
4368 case ETH_SS_STATS:
4369 memcpy(data, &qeth_ethtool_stats_keys,
4370 sizeof(qeth_ethtool_stats_keys));
4371 break;
4372 default:
4373 WARN_ON(1);
4374 break;
4375 }
4376 }
4377 EXPORT_SYMBOL_GPL(qeth_core_get_strings);
4378
4379 void qeth_core_get_drvinfo(struct net_device *dev,
4380 struct ethtool_drvinfo *info)
4381 {
4382 struct qeth_card *card = dev->ml_priv;
4383 if (card->options.layer2)
4384 strcpy(info->driver, "qeth_l2");
4385 else
4386 strcpy(info->driver, "qeth_l3");
4387
4388 strcpy(info->version, "1.0");
4389 strcpy(info->fw_version, card->info.mcl_level);
4390 sprintf(info->bus_info, "%s/%s/%s",
4391 CARD_RDEV_ID(card),
4392 CARD_WDEV_ID(card),
4393 CARD_DDEV_ID(card));
4394 }
4395 EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
4396
4397 int qeth_core_ethtool_get_settings(struct net_device *netdev,
4398 struct ethtool_cmd *ecmd)
4399 {
4400 struct qeth_card *card = netdev->ml_priv;
4401 enum qeth_link_types link_type;
4402
4403 if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
4404 link_type = QETH_LINK_TYPE_10GBIT_ETH;
4405 else
4406 link_type = card->info.link_type;
4407
4408 ecmd->transceiver = XCVR_INTERNAL;
4409 ecmd->supported = SUPPORTED_Autoneg;
4410 ecmd->advertising = ADVERTISED_Autoneg;
4411 ecmd->duplex = DUPLEX_FULL;
4412 ecmd->autoneg = AUTONEG_ENABLE;
4413
4414 switch (link_type) {
4415 case QETH_LINK_TYPE_FAST_ETH:
4416 case QETH_LINK_TYPE_LANE_ETH100:
4417 ecmd->supported |= SUPPORTED_10baseT_Half |
4418 SUPPORTED_10baseT_Full |
4419 SUPPORTED_100baseT_Half |
4420 SUPPORTED_100baseT_Full |
4421 SUPPORTED_TP;
4422 ecmd->advertising |= ADVERTISED_10baseT_Half |
4423 ADVERTISED_10baseT_Full |
4424 ADVERTISED_100baseT_Half |
4425 ADVERTISED_100baseT_Full |
4426 ADVERTISED_TP;
4427 ecmd->speed = SPEED_100;
4428 ecmd->port = PORT_TP;
4429 break;
4430
4431 case QETH_LINK_TYPE_GBIT_ETH:
4432 case QETH_LINK_TYPE_LANE_ETH1000:
4433 ecmd->supported |= SUPPORTED_10baseT_Half |
4434 SUPPORTED_10baseT_Full |
4435 SUPPORTED_100baseT_Half |
4436 SUPPORTED_100baseT_Full |
4437 SUPPORTED_1000baseT_Half |
4438 SUPPORTED_1000baseT_Full |
4439 SUPPORTED_FIBRE;
4440 ecmd->advertising |= ADVERTISED_10baseT_Half |
4441 ADVERTISED_10baseT_Full |
4442 ADVERTISED_100baseT_Half |
4443 ADVERTISED_100baseT_Full |
4444 ADVERTISED_1000baseT_Half |
4445 ADVERTISED_1000baseT_Full |
4446 ADVERTISED_FIBRE;
4447 ecmd->speed = SPEED_1000;
4448 ecmd->port = PORT_FIBRE;
4449 break;
4450
4451 case QETH_LINK_TYPE_10GBIT_ETH:
4452 ecmd->supported |= SUPPORTED_10baseT_Half |
4453 SUPPORTED_10baseT_Full |
4454 SUPPORTED_100baseT_Half |
4455 SUPPORTED_100baseT_Full |
4456 SUPPORTED_1000baseT_Half |
4457 SUPPORTED_1000baseT_Full |
4458 SUPPORTED_10000baseT_Full |
4459 SUPPORTED_FIBRE;
4460 ecmd->advertising |= ADVERTISED_10baseT_Half |
4461 ADVERTISED_10baseT_Full |
4462 ADVERTISED_100baseT_Half |
4463 ADVERTISED_100baseT_Full |
4464 ADVERTISED_1000baseT_Half |
4465 ADVERTISED_1000baseT_Full |
4466 ADVERTISED_10000baseT_Full |
4467 ADVERTISED_FIBRE;
4468 ecmd->speed = SPEED_10000;
4469 ecmd->port = PORT_FIBRE;
4470 break;
4471
4472 default:
4473 ecmd->supported |= SUPPORTED_10baseT_Half |
4474 SUPPORTED_10baseT_Full |
4475 SUPPORTED_TP;
4476 ecmd->advertising |= ADVERTISED_10baseT_Half |
4477 ADVERTISED_10baseT_Full |
4478 ADVERTISED_TP;
4479 ecmd->speed = SPEED_10;
4480 ecmd->port = PORT_TP;
4481 }
4482
4483 return 0;
4484 }
4485 EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
4486
4487 static int __init qeth_core_init(void)
4488 {
4489 int rc;
4490
4491 pr_info("loading core functions\n");
4492 INIT_LIST_HEAD(&qeth_core_card_list.list);
4493 rwlock_init(&qeth_core_card_list.rwlock);
4494
4495 rc = qeth_register_dbf_views();
4496 if (rc)
4497 goto out_err;
4498 rc = ccw_driver_register(&qeth_ccw_driver);
4499 if (rc)
4500 goto ccw_err;
4501 rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
4502 if (rc)
4503 goto ccwgroup_err;
4504 rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
4505 &driver_attr_group);
4506 if (rc)
4507 goto driver_err;
4508 qeth_core_root_dev = root_device_register("qeth");
4509 rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
4510 if (rc)
4511 goto register_err;
4512
4513 qeth_core_header_cache = kmem_cache_create("qeth_hdr",
4514 sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
4515 if (!qeth_core_header_cache) {
4516 rc = -ENOMEM;
4517 goto slab_err;
4518 }
4519
4520 return 0;
4521 slab_err:
4522 root_device_unregister(qeth_core_root_dev);
4523 register_err:
4524 driver_remove_file(&qeth_core_ccwgroup_driver.driver,
4525 &driver_attr_group);
4526 driver_err:
4527 ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
4528 ccwgroup_err:
4529 ccw_driver_unregister(&qeth_ccw_driver);
4530 ccw_err:
4531 QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
4532 qeth_unregister_dbf_views();
4533 out_err:
4534 pr_err("Initializing the qeth device driver failed\n");
4535 return rc;
4536 }
4537
4538 static void __exit qeth_core_exit(void)
4539 {
4540 root_device_unregister(qeth_core_root_dev);
4541 driver_remove_file(&qeth_core_ccwgroup_driver.driver,
4542 &driver_attr_group);
4543 ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
4544 ccw_driver_unregister(&qeth_ccw_driver);
4545 kmem_cache_destroy(qeth_core_header_cache);
4546 qeth_unregister_dbf_views();
4547 pr_info("core functions removed\n");
4548 }
4549
4550 module_init(qeth_core_init);
4551 module_exit(qeth_core_exit);
4552 MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
4553 MODULE_DESCRIPTION("qeth core functions");
4554 MODULE_LICENSE("GPL");
Linux with added FPC-III support