| blob | 42c090cf02927283ccb2dc597e30205a11050ecb |
1 config ARM64
2 def_bool y
3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
15 select ARCH_HAS_ELF_RANDOMIZE
16 select ARCH_HAS_FAST_MULTIPLIER
17 select ARCH_HAS_FORTIFY_SOURCE
18 select ARCH_HAS_GCOV_PROFILE_ALL
19 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
20 select ARCH_HAS_KCOV
21 select ARCH_HAS_MEMBARRIER_SYNC_CORE
22 select ARCH_HAS_PTE_SPECIAL
23 select ARCH_HAS_SET_MEMORY
24 select ARCH_HAS_SG_CHAIN
25 select ARCH_HAS_STRICT_KERNEL_RWX
26 select ARCH_HAS_STRICT_MODULE_RWX
27 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
28 select ARCH_HAVE_NMI_SAFE_CMPXCHG
29 select ARCH_INLINE_READ_LOCK if !PREEMPT
30 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
31 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
32 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
33 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
34 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
35 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
36 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
37 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
38 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
39 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
40 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
41 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
42 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
43 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
44 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
45 select ARCH_USE_CMPXCHG_LOCKREF
46 select ARCH_USE_QUEUED_RWLOCKS
47 select ARCH_SUPPORTS_MEMORY_FAILURE
48 select ARCH_SUPPORTS_ATOMIC_RMW
49 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
50 select ARCH_SUPPORTS_NUMA_BALANCING
51 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
52 select ARCH_WANT_FRAME_POINTERS
53 select ARCH_HAS_UBSAN_SANITIZE_ALL
54 select ARM_AMBA
55 select ARM_ARCH_TIMER
56 select ARM_GIC
57 select AUDIT_ARCH_COMPAT_GENERIC
58 select ARM_GIC_V2M if PCI
59 select ARM_GIC_V3
60 select ARM_GIC_V3_ITS if PCI
61 select ARM_PSCI_FW
62 select BUILDTIME_EXTABLE_SORT
63 select CLONE_BACKWARDS
64 select COMMON_CLK
65 select CPU_PM if (SUSPEND || CPU_IDLE)
66 select DCACHE_WORD_ACCESS
67 select DMA_DIRECT_OPS
68 select EDAC_SUPPORT
69 select FRAME_POINTER
70 select GENERIC_ALLOCATOR
71 select GENERIC_ARCH_TOPOLOGY
72 select GENERIC_CLOCKEVENTS
73 select GENERIC_CLOCKEVENTS_BROADCAST
74 select GENERIC_CPU_AUTOPROBE
75 select GENERIC_EARLY_IOREMAP
76 select GENERIC_IDLE_POLL_SETUP
77 select GENERIC_IRQ_PROBE
78 select GENERIC_IRQ_SHOW
79 select GENERIC_IRQ_SHOW_LEVEL
80 select GENERIC_PCI_IOMAP
81 select GENERIC_SCHED_CLOCK
82 select GENERIC_SMP_IDLE_THREAD
83 select GENERIC_STRNCPY_FROM_USER
84 select GENERIC_STRNLEN_USER
85 select GENERIC_TIME_VSYSCALL
86 select HANDLE_DOMAIN_IRQ
87 select HARDIRQS_SW_RESEND
88 select HAVE_ACPI_APEI if (ACPI && EFI)
89 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
90 select HAVE_ARCH_AUDITSYSCALL
91 select HAVE_ARCH_BITREVERSE
92 select HAVE_ARCH_HUGE_VMAP
93 select HAVE_ARCH_JUMP_LABEL
94 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
95 select HAVE_ARCH_KGDB
96 select HAVE_ARCH_MMAP_RND_BITS
97 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
98 select HAVE_ARCH_SECCOMP_FILTER
99 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
100 select HAVE_ARCH_TRACEHOOK
101 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
102 select HAVE_ARCH_VMAP_STACK
103 select HAVE_ARM_SMCCC
104 select HAVE_EBPF_JIT
105 select HAVE_C_RECORDMCOUNT
106 select HAVE_CMPXCHG_DOUBLE
107 select HAVE_CMPXCHG_LOCAL
108 select HAVE_CONTEXT_TRACKING
109 select HAVE_DEBUG_BUGVERBOSE
110 select HAVE_DEBUG_KMEMLEAK
111 select HAVE_DMA_CONTIGUOUS
112 select HAVE_DYNAMIC_FTRACE
113 select HAVE_EFFICIENT_UNALIGNED_ACCESS
114 select HAVE_FTRACE_MCOUNT_RECORD
115 select HAVE_FUNCTION_TRACER
116 select HAVE_FUNCTION_GRAPH_TRACER
117 select HAVE_GCC_PLUGINS
118 select HAVE_GENERIC_DMA_COHERENT
119 select HAVE_HW_BREAKPOINT if PERF_EVENTS
120 select HAVE_IRQ_TIME_ACCOUNTING
121 select HAVE_MEMBLOCK
122 select HAVE_MEMBLOCK_NODE_MAP if NUMA
123 select HAVE_NMI
124 select HAVE_PATA_PLATFORM
125 select HAVE_PERF_EVENTS
126 select HAVE_PERF_REGS
127 select HAVE_PERF_USER_STACK_DUMP
128 select HAVE_REGS_AND_STACK_ACCESS_API
129 select HAVE_RCU_TABLE_FREE
130 select HAVE_STACKPROTECTOR
131 select HAVE_SYSCALL_TRACEPOINTS
132 select HAVE_KPROBES
133 select HAVE_KRETPROBES
134 select IOMMU_DMA if IOMMU_SUPPORT
135 select IRQ_DOMAIN
136 select IRQ_FORCED_THREADING
137 select MODULES_USE_ELF_RELA
138 select MULTI_IRQ_HANDLER
139 select NEED_DMA_MAP_STATE
140 select NEED_SG_DMA_LENGTH
141 select NO_BOOTMEM
142 select OF
143 select OF_EARLY_FLATTREE
144 select OF_RESERVED_MEM
145 select PCI_ECAM if ACPI
146 select POWER_RESET
147 select POWER_SUPPLY
148 select REFCOUNT_FULL
149 select SPARSE_IRQ
150 select SWIOTLB
151 select SYSCTL_EXCEPTION_TRACE
152 select THREAD_INFO_IN_TASK
153 help
154 ARM 64-bit (AArch64) Linux support.
156 config 64BIT
157 def_bool y
159 config MMU
160 def_bool y
162 config ARM64_PAGE_SHIFT
163 int
164 default 16 if ARM64_64K_PAGES
165 default 14 if ARM64_16K_PAGES
166 default 12
168 config ARM64_CONT_SHIFT
169 int
170 default 5 if ARM64_64K_PAGES
171 default 7 if ARM64_16K_PAGES
172 default 4
174 config ARCH_MMAP_RND_BITS_MIN
175 default 14 if ARM64_64K_PAGES
176 default 16 if ARM64_16K_PAGES
177 default 18
179 # max bits determined by the following formula:
180 # VA_BITS - PAGE_SHIFT - 3
181 config ARCH_MMAP_RND_BITS_MAX
182 default 19 if ARM64_VA_BITS=36
183 default 24 if ARM64_VA_BITS=39
184 default 27 if ARM64_VA_BITS=42
185 default 30 if ARM64_VA_BITS=47
186 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
187 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
188 default 33 if ARM64_VA_BITS=48
189 default 14 if ARM64_64K_PAGES
190 default 16 if ARM64_16K_PAGES
191 default 18
193 config ARCH_MMAP_RND_COMPAT_BITS_MIN
194 default 7 if ARM64_64K_PAGES
195 default 9 if ARM64_16K_PAGES
196 default 11
198 config ARCH_MMAP_RND_COMPAT_BITS_MAX
199 default 16
201 config NO_IOPORT_MAP
202 def_bool y if !PCI
204 config STACKTRACE_SUPPORT
205 def_bool y
207 config ILLEGAL_POINTER_VALUE
208 hex
209 default 0xdead000000000000
211 config LOCKDEP_SUPPORT
212 def_bool y
214 config TRACE_IRQFLAGS_SUPPORT
215 def_bool y
217 config RWSEM_XCHGADD_ALGORITHM
218 def_bool y
220 config GENERIC_BUG
221 def_bool y
222 depends on BUG
224 config GENERIC_BUG_RELATIVE_POINTERS
225 def_bool y
226 depends on GENERIC_BUG
228 config GENERIC_HWEIGHT
229 def_bool y
231 config GENERIC_CSUM
232 def_bool y
234 config GENERIC_CALIBRATE_DELAY
235 def_bool y
237 config ZONE_DMA32
238 def_bool y
240 config HAVE_GENERIC_GUP
241 def_bool y
243 config SMP
244 def_bool y
246 config KERNEL_MODE_NEON
247 def_bool y
249 config FIX_EARLYCON_MEM
250 def_bool y
252 config PGTABLE_LEVELS
253 int
254 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
255 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
256 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
257 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
258 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
259 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
261 config ARCH_SUPPORTS_UPROBES
262 def_bool y
264 config ARCH_PROC_KCORE_TEXT
265 def_bool y
267 config MULTI_IRQ_HANDLER
268 def_bool y
270 source "init/Kconfig"
272 source "kernel/Kconfig.freezer"
274 source "arch/arm64/Kconfig.platforms"
276 menu "Bus support"
278 config PCI
279 bool "PCI support"
280 help
281 This feature enables support for PCI bus system. If you say Y
282 here, the kernel will include drivers and infrastructure code
283 to support PCI bus devices.
285 config PCI_DOMAINS
286 def_bool PCI
288 config PCI_DOMAINS_GENERIC
289 def_bool PCI
291 config PCI_SYSCALL
292 def_bool PCI
294 source "drivers/pci/Kconfig"
296 endmenu
298 menu "Kernel Features"
300 menu "ARM errata workarounds via the alternatives framework"
302 config ARM64_ERRATUM_826319
303 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
304 default y
305 help
306 This option adds an alternative code sequence to work around ARM
307 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
308 AXI master interface and an L2 cache.
310 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
311 and is unable to accept a certain write via this interface, it will
312 not progress on read data presented on the read data channel and the
313 system can deadlock.
315 The workaround promotes data cache clean instructions to
316 data cache clean-and-invalidate.
317 Please note that this does not necessarily enable the workaround,
318 as it depends on the alternative framework, which will only patch
319 the kernel if an affected CPU is detected.
321 If unsure, say Y.
323 config ARM64_ERRATUM_827319
324 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
325 default y
326 help
327 This option adds an alternative code sequence to work around ARM
328 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
329 master interface and an L2 cache.
331 Under certain conditions this erratum can cause a clean line eviction
332 to occur at the same time as another transaction to the same address
333 on the AMBA 5 CHI interface, which can cause data corruption if the
334 interconnect reorders the two transactions.
336 The workaround promotes data cache clean instructions to
337 data cache clean-and-invalidate.
338 Please note that this does not necessarily enable the workaround,
339 as it depends on the alternative framework, which will only patch
340 the kernel if an affected CPU is detected.
342 If unsure, say Y.
344 config ARM64_ERRATUM_824069
345 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
346 default y
347 help
348 This option adds an alternative code sequence to work around ARM
349 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
350 to a coherent interconnect.
352 If a Cortex-A53 processor is executing a store or prefetch for
353 write instruction at the same time as a processor in another
354 cluster is executing a cache maintenance operation to the same
355 address, then this erratum might cause a clean cache line to be
356 incorrectly marked as dirty.
358 The workaround promotes data cache clean instructions to
359 data cache clean-and-invalidate.
360 Please note that this option does not necessarily enable the
361 workaround, as it depends on the alternative framework, which will
362 only patch the kernel if an affected CPU is detected.
364 If unsure, say Y.
366 config ARM64_ERRATUM_819472
367 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
368 default y
369 help
370 This option adds an alternative code sequence to work around ARM
371 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
372 present when it is connected to a coherent interconnect.
374 If the processor is executing a load and store exclusive sequence at
375 the same time as a processor in another cluster is executing a cache
376 maintenance operation to the same address, then this erratum might
377 cause data corruption.
379 The workaround promotes data cache clean instructions to
380 data cache clean-and-invalidate.
381 Please note that this does not necessarily enable the workaround,
382 as it depends on the alternative framework, which will only patch
383 the kernel if an affected CPU is detected.
385 If unsure, say Y.
387 config ARM64_ERRATUM_832075
388 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
389 default y
390 help
391 This option adds an alternative code sequence to work around ARM
392 erratum 832075 on Cortex-A57 parts up to r1p2.
394 Affected Cortex-A57 parts might deadlock when exclusive load/store
395 instructions to Write-Back memory are mixed with Device loads.
397 The workaround is to promote device loads to use Load-Acquire
398 semantics.
399 Please note that this does not necessarily enable the workaround,
400 as it depends on the alternative framework, which will only patch
401 the kernel if an affected CPU is detected.
403 If unsure, say Y.
405 config ARM64_ERRATUM_834220
406 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
407 depends on KVM
408 default y
409 help
410 This option adds an alternative code sequence to work around ARM
411 erratum 834220 on Cortex-A57 parts up to r1p2.
413 Affected Cortex-A57 parts might report a Stage 2 translation
414 fault as the result of a Stage 1 fault for load crossing a
415 page boundary when there is a permission or device memory
416 alignment fault at Stage 1 and a translation fault at Stage 2.
418 The workaround is to verify that the Stage 1 translation
419 doesn't generate a fault before handling the Stage 2 fault.
420 Please note that this does not necessarily enable the workaround,
421 as it depends on the alternative framework, which will only patch
422 the kernel if an affected CPU is detected.
424 If unsure, say Y.
426 config ARM64_ERRATUM_845719
427 bool "Cortex-A53: 845719: a load might read incorrect data"
428 depends on COMPAT
429 default y
430 help
431 This option adds an alternative code sequence to work around ARM
432 erratum 845719 on Cortex-A53 parts up to r0p4.
434 When running a compat (AArch32) userspace on an affected Cortex-A53
435 part, a load at EL0 from a virtual address that matches the bottom 32
436 bits of the virtual address used by a recent load at (AArch64) EL1
437 might return incorrect data.
439 The workaround is to write the contextidr_el1 register on exception
440 return to a 32-bit task.
441 Please note that this does not necessarily enable the workaround,
442 as it depends on the alternative framework, which will only patch
443 the kernel if an affected CPU is detected.
445 If unsure, say Y.
447 config ARM64_ERRATUM_843419
448 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
449 default y
450 select ARM64_MODULE_PLTS if MODULES
451 help
452 This option links the kernel with '--fix-cortex-a53-843419' and
453 enables PLT support to replace certain ADRP instructions, which can
454 cause subsequent memory accesses to use an incorrect address on
455 Cortex-A53 parts up to r0p4.
457 If unsure, say Y.
459 config ARM64_ERRATUM_1024718
460 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
461 default y
462 help
463 This option adds work around for Arm Cortex-A55 Erratum 1024718.
465 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
466 update of the hardware dirty bit when the DBM/AP bits are updated
467 without a break-before-make. The work around is to disable the usage
468 of hardware DBM locally on the affected cores. CPUs not affected by
469 erratum will continue to use the feature.
471 If unsure, say Y.
473 config CAVIUM_ERRATUM_22375
474 bool "Cavium erratum 22375, 24313"
475 default y
476 help
477 Enable workaround for erratum 22375, 24313.
479 This implements two gicv3-its errata workarounds for ThunderX. Both
480 with small impact affecting only ITS table allocation.
482 erratum 22375: only alloc 8MB table size
483 erratum 24313: ignore memory access type
485 The fixes are in ITS initialization and basically ignore memory access
486 type and table size provided by the TYPER and BASER registers.
488 If unsure, say Y.
490 config CAVIUM_ERRATUM_23144
491 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
492 depends on NUMA
493 default y
494 help
495 ITS SYNC command hang for cross node io and collections/cpu mapping.
497 If unsure, say Y.
499 config CAVIUM_ERRATUM_23154
500 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
501 default y
502 help
503 The gicv3 of ThunderX requires a modified version for
504 reading the IAR status to ensure data synchronization
505 (access to icc_iar1_el1 is not sync'ed before and after).
507 If unsure, say Y.
509 config CAVIUM_ERRATUM_27456
510 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
511 default y
512 help
513 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
514 instructions may cause the icache to become corrupted if it
515 contains data for a non-current ASID. The fix is to
516 invalidate the icache when changing the mm context.
518 If unsure, say Y.
520 config CAVIUM_ERRATUM_30115
521 bool "Cavium erratum 30115: Guest may disable interrupts in host"
522 default y
523 help
524 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
525 1.2, and T83 Pass 1.0, KVM guest execution may disable
526 interrupts in host. Trapping both GICv3 group-0 and group-1
527 accesses sidesteps the issue.
529 If unsure, say Y.
531 config QCOM_FALKOR_ERRATUM_1003
532 bool "Falkor E1003: Incorrect translation due to ASID change"
533 default y
534 help
535 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
536 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
537 in TTBR1_EL1, this situation only occurs in the entry trampoline and
538 then only for entries in the walk cache, since the leaf translation
539 is unchanged. Work around the erratum by invalidating the walk cache
540 entries for the trampoline before entering the kernel proper.
542 config QCOM_FALKOR_ERRATUM_1009
543 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
544 default y
545 help
546 On Falkor v1, the CPU may prematurely complete a DSB following a
547 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
548 one more time to fix the issue.
550 If unsure, say Y.
552 config QCOM_QDF2400_ERRATUM_0065
553 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
554 default y
555 help
556 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
557 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
558 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
560 If unsure, say Y.
562 config SOCIONEXT_SYNQUACER_PREITS
563 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
564 default y
565 help
566 Socionext Synquacer SoCs implement a separate h/w block to generate
567 MSI doorbell writes with non-zero values for the device ID.
569 If unsure, say Y.
571 config HISILICON_ERRATUM_161600802
572 bool "Hip07 161600802: Erroneous redistributor VLPI base"
573 default y
574 help
575 The HiSilicon Hip07 SoC usees the wrong redistributor base
576 when issued ITS commands such as VMOVP and VMAPP, and requires
577 a 128kB offset to be applied to the target address in this commands.
579 If unsure, say Y.
581 config QCOM_FALKOR_ERRATUM_E1041
582 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
583 default y
584 help
585 Falkor CPU may speculatively fetch instructions from an improper
586 memory location when MMU translation is changed from SCTLR_ELn[M]=1
587 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
589 If unsure, say Y.
591 endmenu
594 choice
595 prompt "Page size"
596 default ARM64_4K_PAGES
597 help
598 Page size (translation granule) configuration.
600 config ARM64_4K_PAGES
601 bool "4KB"
602 help
603 This feature enables 4KB pages support.
605 config ARM64_16K_PAGES
606 bool "16KB"
607 help
608 The system will use 16KB pages support. AArch32 emulation
609 requires applications compiled with 16K (or a multiple of 16K)
610 aligned segments.
612 config ARM64_64K_PAGES
613 bool "64KB"
614 help
615 This feature enables 64KB pages support (4KB by default)
616 allowing only two levels of page tables and faster TLB
617 look-up. AArch32 emulation requires applications compiled
618 with 64K aligned segments.
620 endchoice
622 choice
623 prompt "Virtual address space size"
624 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
625 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
626 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
627 help
628 Allows choosing one of multiple possible virtual address
629 space sizes. The level of translation table is determined by
630 a combination of page size and virtual address space size.
632 config ARM64_VA_BITS_36
633 bool "36-bit" if EXPERT
634 depends on ARM64_16K_PAGES
636 config ARM64_VA_BITS_39
637 bool "39-bit"
638 depends on ARM64_4K_PAGES
640 config ARM64_VA_BITS_42
641 bool "42-bit"
642 depends on ARM64_64K_PAGES
644 config ARM64_VA_BITS_47
645 bool "47-bit"
646 depends on ARM64_16K_PAGES
648 config ARM64_VA_BITS_48
649 bool "48-bit"
651 endchoice
653 config ARM64_VA_BITS
654 int
655 default 36 if ARM64_VA_BITS_36
656 default 39 if ARM64_VA_BITS_39
657 default 42 if ARM64_VA_BITS_42
658 default 47 if ARM64_VA_BITS_47
659 default 48 if ARM64_VA_BITS_48
661 choice
662 prompt "Physical address space size"
663 default ARM64_PA_BITS_48
664 help
665 Choose the maximum physical address range that the kernel will
666 support.
668 config ARM64_PA_BITS_48
669 bool "48-bit"
671 config ARM64_PA_BITS_52
672 bool "52-bit (ARMv8.2)"
673 depends on ARM64_64K_PAGES
674 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
675 help
676 Enable support for a 52-bit physical address space, introduced as
677 part of the ARMv8.2-LPA extension.
679 With this enabled, the kernel will also continue to work on CPUs that
680 do not support ARMv8.2-LPA, but with some added memory overhead (and
681 minor performance overhead).
683 endchoice
685 config ARM64_PA_BITS
686 int
687 default 48 if ARM64_PA_BITS_48
688 default 52 if ARM64_PA_BITS_52
690 config CPU_BIG_ENDIAN
691 bool "Build big-endian kernel"
692 help
693 Say Y if you plan on running a kernel in big-endian mode.
695 config SCHED_MC
696 bool "Multi-core scheduler support"
697 help
698 Multi-core scheduler support improves the CPU scheduler's decision
699 making when dealing with multi-core CPU chips at a cost of slightly
700 increased overhead in some places. If unsure say N here.
702 config SCHED_SMT
703 bool "SMT scheduler support"
704 help
705 Improves the CPU scheduler's decision making when dealing with
706 MultiThreading at a cost of slightly increased overhead in some
707 places. If unsure say N here.
709 config NR_CPUS
710 int "Maximum number of CPUs (2-4096)"
711 range 2 4096
712 # These have to remain sorted largest to smallest
713 default "64"
715 config HOTPLUG_CPU
716 bool "Support for hot-pluggable CPUs"
717 select GENERIC_IRQ_MIGRATION
718 help
719 Say Y here to experiment with turning CPUs off and on. CPUs
720 can be controlled through /sys/devices/system/cpu.
722 # Common NUMA Features
723 config NUMA
724 bool "Numa Memory Allocation and Scheduler Support"
725 select ACPI_NUMA if ACPI
726 select OF_NUMA
727 help
728 Enable NUMA (Non Uniform Memory Access) support.
730 The kernel will try to allocate memory used by a CPU on the
731 local memory of the CPU and add some more
732 NUMA awareness to the kernel.
734 config NODES_SHIFT
735 int "Maximum NUMA Nodes (as a power of 2)"
736 range 1 10
737 default "2"
738 depends on NEED_MULTIPLE_NODES
739 help
740 Specify the maximum number of NUMA Nodes available on the target
741 system. Increases memory reserved to accommodate various tables.
743 config USE_PERCPU_NUMA_NODE_ID
744 def_bool y
745 depends on NUMA
747 config HAVE_SETUP_PER_CPU_AREA
748 def_bool y
749 depends on NUMA
751 config NEED_PER_CPU_EMBED_FIRST_CHUNK
752 def_bool y
753 depends on NUMA
755 config HOLES_IN_ZONE
756 def_bool y
757 depends on NUMA
759 source kernel/Kconfig.preempt
760 source kernel/Kconfig.hz
762 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
763 def_bool y
765 config ARCH_HAS_HOLES_MEMORYMODEL
766 def_bool y if SPARSEMEM
768 config ARCH_SPARSEMEM_ENABLE
769 def_bool y
770 select SPARSEMEM_VMEMMAP_ENABLE
772 config ARCH_SPARSEMEM_DEFAULT
773 def_bool ARCH_SPARSEMEM_ENABLE
775 config ARCH_SELECT_MEMORY_MODEL
776 def_bool ARCH_SPARSEMEM_ENABLE
778 config HAVE_ARCH_PFN_VALID
779 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
781 config HW_PERF_EVENTS
782 def_bool y
783 depends on ARM_PMU
785 config SYS_SUPPORTS_HUGETLBFS
786 def_bool y
788 config ARCH_WANT_HUGE_PMD_SHARE
789 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
791 config ARCH_HAS_CACHE_LINE_SIZE
792 def_bool y
794 source "mm/Kconfig"
796 config SECCOMP
797 bool "Enable seccomp to safely compute untrusted bytecode"
798 ---help---
799 This kernel feature is useful for number crunching applications
800 that may need to compute untrusted bytecode during their
801 execution. By using pipes or other transports made available to
802 the process as file descriptors supporting the read/write
803 syscalls, it's possible to isolate those applications in
804 their own address space using seccomp. Once seccomp is
805 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
806 and the task is only allowed to execute a few safe syscalls
807 defined by each seccomp mode.
809 config PARAVIRT
810 bool "Enable paravirtualization code"
811 help
812 This changes the kernel so it can modify itself when it is run
813 under a hypervisor, potentially improving performance significantly
814 over full virtualization.
816 config PARAVIRT_TIME_ACCOUNTING
817 bool "Paravirtual steal time accounting"
818 select PARAVIRT
819 default n
820 help
821 Select this option to enable fine granularity task steal time
822 accounting. Time spent executing other tasks in parallel with
823 the current vCPU is discounted from the vCPU power. To account for
824 that, there can be a small performance impact.
826 If in doubt, say N here.
828 config KEXEC
829 depends on PM_SLEEP_SMP
830 select KEXEC_CORE
831 bool "kexec system call"
832 ---help---
833 kexec is a system call that implements the ability to shutdown your
834 current kernel, and to start another kernel. It is like a reboot
835 but it is independent of the system firmware. And like a reboot
836 you can start any kernel with it, not just Linux.
838 config CRASH_DUMP
839 bool "Build kdump crash kernel"
840 help
841 Generate crash dump after being started by kexec. This should
842 be normally only set in special crash dump kernels which are
843 loaded in the main kernel with kexec-tools into a specially
844 reserved region and then later executed after a crash by
845 kdump/kexec.
847 For more details see Documentation/kdump/kdump.txt
849 config XEN_DOM0
850 def_bool y
851 depends on XEN
853 config XEN
854 bool "Xen guest support on ARM64"
855 depends on ARM64 && OF
856 select SWIOTLB_XEN
857 select PARAVIRT
858 help
859 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
861 config FORCE_MAX_ZONEORDER
862 int
863 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
864 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
865 default "11"
866 help
867 The kernel memory allocator divides physically contiguous memory
868 blocks into "zones", where each zone is a power of two number of
869 pages. This option selects the largest power of two that the kernel
870 keeps in the memory allocator. If you need to allocate very large
871 blocks of physically contiguous memory, then you may need to
872 increase this value.
874 This config option is actually maximum order plus one. For example,
875 a value of 11 means that the largest free memory block is 2^10 pages.
877 We make sure that we can allocate upto a HugePage size for each configuration.
878 Hence we have :
879 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
881 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
882 4M allocations matching the default size used by generic code.
884 config UNMAP_KERNEL_AT_EL0
885 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
886 default y
887 help
888 Speculation attacks against some high-performance processors can
889 be used to bypass MMU permission checks and leak kernel data to
890 userspace. This can be defended against by unmapping the kernel
891 when running in userspace, mapping it back in on exception entry
892 via a trampoline page in the vector table.
894 If unsure, say Y.
896 config HARDEN_BRANCH_PREDICTOR
897 bool "Harden the branch predictor against aliasing attacks" if EXPERT
898 default y
899 help
900 Speculation attacks against some high-performance processors rely on
901 being able to manipulate the branch predictor for a victim context by
902 executing aliasing branches in the attacker context. Such attacks
903 can be partially mitigated against by clearing internal branch
904 predictor state and limiting the prediction logic in some situations.
906 This config option will take CPU-specific actions to harden the
907 branch predictor against aliasing attacks and may rely on specific
908 instruction sequences or control bits being set by the system
909 firmware.
911 If unsure, say Y.
913 config HARDEN_EL2_VECTORS
914 bool "Harden EL2 vector mapping against system register leak" if EXPERT
915 default y
916 help
917 Speculation attacks against some high-performance processors can
918 be used to leak privileged information such as the vector base
919 register, resulting in a potential defeat of the EL2 layout
920 randomization.
922 This config option will map the vectors to a fixed location,
923 independent of the EL2 code mapping, so that revealing VBAR_EL2
924 to an attacker does not give away any extra information. This
925 only gets enabled on affected CPUs.
927 If unsure, say Y.
929 config ARM64_SSBD
930 bool "Speculative Store Bypass Disable" if EXPERT
931 default y
932 help
933 This enables mitigation of the bypassing of previous stores
934 by speculative loads.
936 If unsure, say Y.
938 menuconfig ARMV8_DEPRECATED
939 bool "Emulate deprecated/obsolete ARMv8 instructions"
940 depends on COMPAT
941 depends on SYSCTL
942 help
943 Legacy software support may require certain instructions
944 that have been deprecated or obsoleted in the architecture.
946 Enable this config to enable selective emulation of these
947 features.
949 If unsure, say Y
951 if ARMV8_DEPRECATED
953 config SWP_EMULATION
954 bool "Emulate SWP/SWPB instructions"
955 help
956 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
957 they are always undefined. Say Y here to enable software
958 emulation of these instructions for userspace using LDXR/STXR.
960 In some older versions of glibc [<=2.8] SWP is used during futex
961 trylock() operations with the assumption that the code will not
962 be preempted. This invalid assumption may be more likely to fail
963 with SWP emulation enabled, leading to deadlock of the user
964 application.
966 NOTE: when accessing uncached shared regions, LDXR/STXR rely
967 on an external transaction monitoring block called a global
968 monitor to maintain update atomicity. If your system does not
969 implement a global monitor, this option can cause programs that
970 perform SWP operations to uncached memory to deadlock.
972 If unsure, say Y
974 config CP15_BARRIER_EMULATION
975 bool "Emulate CP15 Barrier instructions"
976 help
977 The CP15 barrier instructions - CP15ISB, CP15DSB, and
978 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
979 strongly recommended to use the ISB, DSB, and DMB
980 instructions instead.
982 Say Y here to enable software emulation of these
983 instructions for AArch32 userspace code. When this option is
984 enabled, CP15 barrier usage is traced which can help
985 identify software that needs updating.
987 If unsure, say Y
989 config SETEND_EMULATION
990 bool "Emulate SETEND instruction"
991 help
992 The SETEND instruction alters the data-endianness of the
993 AArch32 EL0, and is deprecated in ARMv8.
995 Say Y here to enable software emulation of the instruction
996 for AArch32 userspace code.
998 Note: All the cpus on the system must have mixed endian support at EL0
999 for this feature to be enabled. If a new CPU - which doesn't support mixed
1000 endian - is hotplugged in after this feature has been enabled, there could
1001 be unexpected results in the applications.
1003 If unsure, say Y
1004 endif
1006 config ARM64_SW_TTBR0_PAN
1007 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1008 help
1009 Enabling this option prevents the kernel from accessing
1010 user-space memory directly by pointing TTBR0_EL1 to a reserved
1011 zeroed area and reserved ASID. The user access routines
1012 restore the valid TTBR0_EL1 temporarily.
1014 menu "ARMv8.1 architectural features"
1016 config ARM64_HW_AFDBM
1017 bool "Support for hardware updates of the Access and Dirty page flags"
1018 default y
1019 help
1020 The ARMv8.1 architecture extensions introduce support for
1021 hardware updates of the access and dirty information in page
1022 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1023 capable processors, accesses to pages with PTE_AF cleared will
1024 set this bit instead of raising an access flag fault.
1025 Similarly, writes to read-only pages with the DBM bit set will
1026 clear the read-only bit (AP[2]) instead of raising a
1027 permission fault.
1029 Kernels built with this configuration option enabled continue
1030 to work on pre-ARMv8.1 hardware and the performance impact is
1031 minimal. If unsure, say Y.
1033 config ARM64_PAN
1034 bool "Enable support for Privileged Access Never (PAN)"
1035 default y
1036 help
1037 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1038 prevents the kernel or hypervisor from accessing user-space (EL0)
1039 memory directly.
1041 Choosing this option will cause any unprotected (not using
1042 copy_to_user et al) memory access to fail with a permission fault.
1044 The feature is detected at runtime, and will remain as a 'nop'
1045 instruction if the cpu does not implement the feature.
1047 config ARM64_LSE_ATOMICS
1048 bool "Atomic instructions"
1049 default y
1050 help
1051 As part of the Large System Extensions, ARMv8.1 introduces new
1052 atomic instructions that are designed specifically to scale in
1053 very large systems.
1055 Say Y here to make use of these instructions for the in-kernel
1056 atomic routines. This incurs a small overhead on CPUs that do
1057 not support these instructions and requires the kernel to be
1058 built with binutils >= 2.25 in order for the new instructions
1059 to be used.
1061 config ARM64_VHE
1062 bool "Enable support for Virtualization Host Extensions (VHE)"
1063 default y
1064 help
1065 Virtualization Host Extensions (VHE) allow the kernel to run
1066 directly at EL2 (instead of EL1) on processors that support
1067 it. This leads to better performance for KVM, as they reduce
1068 the cost of the world switch.
1070 Selecting this option allows the VHE feature to be detected
1071 at runtime, and does not affect processors that do not
1072 implement this feature.
1074 endmenu
1076 menu "ARMv8.2 architectural features"
1078 config ARM64_UAO
1079 bool "Enable support for User Access Override (UAO)"
1080 default y
1081 help
1082 User Access Override (UAO; part of the ARMv8.2 Extensions)
1083 causes the 'unprivileged' variant of the load/store instructions to
1084 be overridden to be privileged.
1086 This option changes get_user() and friends to use the 'unprivileged'
1087 variant of the load/store instructions. This ensures that user-space
1088 really did have access to the supplied memory. When addr_limit is
1089 set to kernel memory the UAO bit will be set, allowing privileged
1090 access to kernel memory.
1092 Choosing this option will cause copy_to_user() et al to use user-space
1093 memory permissions.
1095 The feature is detected at runtime, the kernel will use the
1096 regular load/store instructions if the cpu does not implement the
1097 feature.
1099 config ARM64_PMEM
1100 bool "Enable support for persistent memory"
1101 select ARCH_HAS_PMEM_API
1102 select ARCH_HAS_UACCESS_FLUSHCACHE
1103 help
1104 Say Y to enable support for the persistent memory API based on the
1105 ARMv8.2 DCPoP feature.
1107 The feature is detected at runtime, and the kernel will use DC CVAC
1108 operations if DC CVAP is not supported (following the behaviour of
1109 DC CVAP itself if the system does not define a point of persistence).
1111 config ARM64_RAS_EXTN
1112 bool "Enable support for RAS CPU Extensions"
1113 default y
1114 help
1115 CPUs that support the Reliability, Availability and Serviceability
1116 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1117 errors, classify them and report them to software.
1119 On CPUs with these extensions system software can use additional
1120 barriers to determine if faults are pending and read the
1121 classification from a new set of registers.
1123 Selecting this feature will allow the kernel to use these barriers
1124 and access the new registers if the system supports the extension.
1125 Platform RAS features may additionally depend on firmware support.
1127 endmenu
1129 config ARM64_SVE
1130 bool "ARM Scalable Vector Extension support"
1131 default y
1132 depends on !KVM || ARM64_VHE
1133 help
1134 The Scalable Vector Extension (SVE) is an extension to the AArch64
1135 execution state which complements and extends the SIMD functionality
1136 of the base architecture to support much larger vectors and to enable
1137 additional vectorisation opportunities.
1139 To enable use of this extension on CPUs that implement it, say Y.
1141 Note that for architectural reasons, firmware _must_ implement SVE
1142 support when running on SVE capable hardware. The required support
1143 is present in:
1145 * version 1.5 and later of the ARM Trusted Firmware
1146 * the AArch64 boot wrapper since commit 5e1261e08abf
1147 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1149 For other firmware implementations, consult the firmware documentation
1150 or vendor.
1152 If you need the kernel to boot on SVE-capable hardware with broken
1153 firmware, you may need to say N here until you get your firmware
1154 fixed. Otherwise, you may experience firmware panics or lockups when
1155 booting the kernel. If unsure and you are not observing these
1156 symptoms, you should assume that it is safe to say Y.
1158 CPUs that support SVE are architecturally required to support the
1159 Virtualization Host Extensions (VHE), so the kernel makes no
1160 provision for supporting SVE alongside KVM without VHE enabled.
1161 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1162 KVM in the same kernel image.
1164 config ARM64_MODULE_PLTS
1165 bool
1166 select HAVE_MOD_ARCH_SPECIFIC
1168 config RELOCATABLE
1169 bool
1170 help
1171 This builds the kernel as a Position Independent Executable (PIE),
1172 which retains all relocation metadata required to relocate the
1173 kernel binary at runtime to a different virtual address than the
1174 address it was linked at.
1175 Since AArch64 uses the RELA relocation format, this requires a
1176 relocation pass at runtime even if the kernel is loaded at the
1177 same address it was linked at.
1179 config RANDOMIZE_BASE
1180 bool "Randomize the address of the kernel image"
1181 select ARM64_MODULE_PLTS if MODULES
1182 select RELOCATABLE
1183 help
1184 Randomizes the virtual address at which the kernel image is
1185 loaded, as a security feature that deters exploit attempts
1186 relying on knowledge of the location of kernel internals.
1188 It is the bootloader's job to provide entropy, by passing a
1189 random u64 value in /chosen/kaslr-seed at kernel entry.
1191 When booting via the UEFI stub, it will invoke the firmware's
1192 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1193 to the kernel proper. In addition, it will randomise the physical
1194 location of the kernel Image as well.
1196 If unsure, say N.
1198 config RANDOMIZE_MODULE_REGION_FULL
1199 bool "Randomize the module region over a 4 GB range"
1200 depends on RANDOMIZE_BASE
1201 default y
1202 help
1203 Randomizes the location of the module region inside a 4 GB window
1204 covering the core kernel. This way, it is less likely for modules
1205 to leak information about the location of core kernel data structures
1206 but it does imply that function calls between modules and the core
1207 kernel will need to be resolved via veneers in the module PLT.
1209 When this option is not set, the module region will be randomized over
1210 a limited range that contains the [_stext, _etext] interval of the
1211 core kernel, so branch relocations are always in range.
1213 endmenu
1215 menu "Boot options"
1217 config ARM64_ACPI_PARKING_PROTOCOL
1218 bool "Enable support for the ARM64 ACPI parking protocol"
1219 depends on ACPI
1220 help
1221 Enable support for the ARM64 ACPI parking protocol. If disabled
1222 the kernel will not allow booting through the ARM64 ACPI parking
1223 protocol even if the corresponding data is present in the ACPI
1224 MADT table.
1226 config CMDLINE
1227 string "Default kernel command string"
1228 default ""
1229 help
1230 Provide a set of default command-line options at build time by
1231 entering them here. As a minimum, you should specify the the
1232 root device (e.g. root=/dev/nfs).
1234 config CMDLINE_FORCE
1235 bool "Always use the default kernel command string"
1236 help
1237 Always use the default kernel command string, even if the boot
1238 loader passes other arguments to the kernel.
1239 This is useful if you cannot or don't want to change the
1240 command-line options your boot loader passes to the kernel.
1242 config EFI_STUB
1243 bool
1245 config EFI
1246 bool "UEFI runtime support"
1247 depends on OF && !CPU_BIG_ENDIAN
1248 depends on KERNEL_MODE_NEON
1249 select LIBFDT
1250 select UCS2_STRING
1251 select EFI_PARAMS_FROM_FDT
1252 select EFI_RUNTIME_WRAPPERS
1253 select EFI_STUB
1254 select EFI_ARMSTUB
1255 default y
1256 help
1257 This option provides support for runtime services provided
1258 by UEFI firmware (such as non-volatile variables, realtime
1259 clock, and platform reset). A UEFI stub is also provided to
1260 allow the kernel to be booted as an EFI application. This
1261 is only useful on systems that have UEFI firmware.
1263 config DMI
1264 bool "Enable support for SMBIOS (DMI) tables"
1265 depends on EFI
1266 default y
1267 help
1268 This enables SMBIOS/DMI feature for systems.
1270 This option is only useful on systems that have UEFI firmware.
1271 However, even with this option, the resultant kernel should
1272 continue to boot on existing non-UEFI platforms.
1274 endmenu
1276 menu "Userspace binary formats"
1278 source "fs/Kconfig.binfmt"
1280 config COMPAT
1281 bool "Kernel support for 32-bit EL0"
1282 depends on ARM64_4K_PAGES || EXPERT
1283 select COMPAT_BINFMT_ELF if BINFMT_ELF
1284 select HAVE_UID16
1285 select OLD_SIGSUSPEND3
1286 select COMPAT_OLD_SIGACTION
1287 help
1288 This option enables support for a 32-bit EL0 running under a 64-bit
1289 kernel at EL1. AArch32-specific components such as system calls,
1290 the user helper functions, VFP support and the ptrace interface are
1291 handled appropriately by the kernel.
1293 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1294 that you will only be able to execute AArch32 binaries that were compiled
1295 with page size aligned segments.
1297 If you want to execute 32-bit userspace applications, say Y.
1299 config SYSVIPC_COMPAT
1300 def_bool y
1301 depends on COMPAT && SYSVIPC
1303 endmenu
1305 menu "Power management options"
1307 source "kernel/power/Kconfig"
1309 config ARCH_HIBERNATION_POSSIBLE
1310 def_bool y
1311 depends on CPU_PM
1313 config ARCH_HIBERNATION_HEADER
1314 def_bool y
1315 depends on HIBERNATION
1317 config ARCH_SUSPEND_POSSIBLE
1318 def_bool y
1320 endmenu
1322 menu "CPU Power Management"
1324 source "drivers/cpuidle/Kconfig"
1326 source "drivers/cpufreq/Kconfig"
1328 endmenu
1330 source "net/Kconfig"
1332 source "drivers/Kconfig"
1334 source "drivers/firmware/Kconfig"
1336 source "drivers/acpi/Kconfig"
1338 source "fs/Kconfig"
1340 source "arch/arm64/kvm/Kconfig"
1342 source "arch/arm64/Kconfig.debug"
1344 source "security/Kconfig"
1346 source "crypto/Kconfig"
1347 if CRYPTO
1348 source "arch/arm64/crypto/Kconfig"
1349 endif
1351 source "lib/Kconfig"