2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/serial_8250.h>
16 struct uart_8250_port
{
17 struct uart_port port
;
18 struct timer_list timer
; /* "no irq" timer */
19 struct list_head list
; /* ports on this IRQ */
20 unsigned short capabilities
; /* port capabilities */
21 unsigned short bugs
; /* port bugs */
22 unsigned int tx_loadsz
; /* transmit fifo load size */
27 unsigned char mcr_mask
; /* mask of user bits */
28 unsigned char mcr_force
; /* mask of forced bits */
29 unsigned char cur_iotype
; /* Running I/O type */
32 * Some bits in registers are cleared on a read, so they must
33 * be saved whenever the register is read but the bits will not
34 * be immediately processed.
36 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
37 unsigned char lsr_saved_flags
;
38 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
39 unsigned char msr_saved_flags
;
42 struct old_serial_port
{
44 unsigned int baud_base
;
49 unsigned char io_type
;
50 unsigned char *iomem_base
;
51 unsigned short iomem_reg_shift
;
52 unsigned long irqflags
;
56 * This replaces serial_uart_config in include/linux/serial.h
58 struct serial8250_config
{
60 unsigned short fifo_size
;
61 unsigned short tx_loadsz
;
66 #define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
67 #define UART_CAP_EFR (1 << 9) /* UART has EFR */
68 #define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
69 #define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
70 #define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
71 #define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */
73 #define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
74 #define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
75 #define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
76 #define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
78 #define PROBE_RSA (1 << 0)
79 #define PROBE_ANY (~0)
81 #define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
83 #ifdef CONFIG_SERIAL_8250_SHARE_IRQ
84 #define SERIAL8250_SHARE_IRQS 1
86 #define SERIAL8250_SHARE_IRQS 0
89 #if defined(__alpha__) && !defined(CONFIG_PCI)
91 * Digital did something really horribly wrong with the OUT1 and OUT2
92 * lines on at least some ALPHA's. The failure mode is that if either
93 * is cleared, the machine locks up with endless interrupts.
95 #define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 | UART_MCR_OUT1)
96 #elif defined(CONFIG_SBC8560)
98 * WindRiver did something similarly broken on their SBC8560 board. The
99 * UART tristates its IRQ output while OUT2 is clear, but they pulled
100 * the interrupt line _up_ instead of down, so if we register the IRQ
101 * while the UART is in that state, we die in an IRQ storm. */
102 #define ALPHA_KLUDGE_MCR (UART_MCR_OUT2)
104 #define ALPHA_KLUDGE_MCR 0