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iwl3945: fix possible il->txq NULL pointer dereference in delayed works
[linux/fpc-iii.git] / drivers / tty / serial / omap-serial.c
blobd192dcbb82f5e464f9ab6beb8805a2dcd1c6733b
1 /*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
22
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #define SUPPORT_SYSRQ
25 #endif
26
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/io.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/of.h>
42
43 #include <plat/dma.h>
44 #include <plat/dmtimer.h>
45 #include <plat/omap-serial.h>
46
47 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
48
49 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
50
51 /* Forward declaration of functions */
52 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
53 static void serial_omap_rxdma_poll(unsigned long uart_no);
54 static int serial_omap_start_rxdma(struct uart_omap_port *up);
55 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
56
57 static struct workqueue_struct *serial_omap_uart_wq;
58
59 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
60 {
61 offset <<= up->port.regshift;
62 return readw(up->port.membase + offset);
63 }
64
65 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
66 {
67 offset <<= up->port.regshift;
68 writew(value, up->port.membase + offset);
69 }
70
71 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
72 {
73 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
74 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
75 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
76 serial_out(up, UART_FCR, 0);
77 }
78
79 /*
80 * serial_omap_get_divisor - calculate divisor value
81 * @port: uart port info
82 * @baud: baudrate for which divisor needs to be calculated.
83 *
84 * We have written our own function to get the divisor so as to support
85 * 13x mode. 3Mbps Baudrate as an different divisor.
86 * Reference OMAP TRM Chapter 17:
87 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
88 * referring to oversampling - divisor value
89 * baudrate 460,800 to 3,686,400 all have divisor 13
90 * except 3,000,000 which has divisor value 16
91 */
92 static unsigned int
93 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
94 {
95 unsigned int divisor;
96
97 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
98 divisor = 13;
99 else
100 divisor = 16;
101 return port->uartclk/(baud * divisor);
102 }
103
104 static void serial_omap_stop_rxdma(struct uart_omap_port *up)
105 {
106 if (up->uart_dma.rx_dma_used) {
107 del_timer(&up->uart_dma.rx_timer);
108 omap_stop_dma(up->uart_dma.rx_dma_channel);
109 omap_free_dma(up->uart_dma.rx_dma_channel);
110 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
111 up->uart_dma.rx_dma_used = false;
112 pm_runtime_mark_last_busy(&up->pdev->dev);
113 pm_runtime_put_autosuspend(&up->pdev->dev);
114 }
115 }
116
117 static void serial_omap_enable_ms(struct uart_port *port)
118 {
119 struct uart_omap_port *up = (struct uart_omap_port *)port;
120
121 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
122
123 pm_runtime_get_sync(&up->pdev->dev);
124 up->ier |= UART_IER_MSI;
125 serial_out(up, UART_IER, up->ier);
126 pm_runtime_put(&up->pdev->dev);
127 }
128
129 static void serial_omap_stop_tx(struct uart_port *port)
130 {
131 struct uart_omap_port *up = (struct uart_omap_port *)port;
132
133 if (up->use_dma &&
134 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
135 /*
136 * Check if dma is still active. If yes do nothing,
137 * return. Else stop dma
138 */
139 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
140 return;
141 omap_stop_dma(up->uart_dma.tx_dma_channel);
142 omap_free_dma(up->uart_dma.tx_dma_channel);
143 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
144 pm_runtime_mark_last_busy(&up->pdev->dev);
145 pm_runtime_put_autosuspend(&up->pdev->dev);
146 }
147
148 pm_runtime_get_sync(&up->pdev->dev);
149 if (up->ier & UART_IER_THRI) {
150 up->ier &= ~UART_IER_THRI;
151 serial_out(up, UART_IER, up->ier);
152 }
153
154 pm_runtime_mark_last_busy(&up->pdev->dev);
155 pm_runtime_put_autosuspend(&up->pdev->dev);
156 }
157
158 static void serial_omap_stop_rx(struct uart_port *port)
159 {
160 struct uart_omap_port *up = (struct uart_omap_port *)port;
161
162 pm_runtime_get_sync(&up->pdev->dev);
163 if (up->use_dma)
164 serial_omap_stop_rxdma(up);
165 up->ier &= ~UART_IER_RLSI;
166 up->port.read_status_mask &= ~UART_LSR_DR;
167 serial_out(up, UART_IER, up->ier);
168 pm_runtime_mark_last_busy(&up->pdev->dev);
169 pm_runtime_put_autosuspend(&up->pdev->dev);
170 }
171
172 static inline void receive_chars(struct uart_omap_port *up,
173 unsigned int *status)
174 {
175 struct tty_struct *tty = up->port.state->port.tty;
176 unsigned int flag, lsr = *status;
177 unsigned char ch = 0;
178 int max_count = 256;
179
180 do {
181 if (likely(lsr & UART_LSR_DR))
182 ch = serial_in(up, UART_RX);
183 flag = TTY_NORMAL;
184 up->port.icount.rx++;
185
186 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
187 /*
188 * For statistics only
189 */
190 if (lsr & UART_LSR_BI) {
191 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
192 up->port.icount.brk++;
193 /*
194 * We do the SysRQ and SAK checking
195 * here because otherwise the break
196 * may get masked by ignore_status_mask
197 * or read_status_mask.
198 */
199 if (uart_handle_break(&up->port))
200 goto ignore_char;
201 } else if (lsr & UART_LSR_PE) {
202 up->port.icount.parity++;
203 } else if (lsr & UART_LSR_FE) {
204 up->port.icount.frame++;
205 }
206
207 if (lsr & UART_LSR_OE)
208 up->port.icount.overrun++;
209
210 /*
211 * Mask off conditions which should be ignored.
212 */
213 lsr &= up->port.read_status_mask;
214
215 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
216 if (up->port.line == up->port.cons->index) {
217 /* Recover the break flag from console xmit */
218 lsr |= up->lsr_break_flag;
219 }
220 #endif
221 if (lsr & UART_LSR_BI)
222 flag = TTY_BREAK;
223 else if (lsr & UART_LSR_PE)
224 flag = TTY_PARITY;
225 else if (lsr & UART_LSR_FE)
226 flag = TTY_FRAME;
227 }
228
229 if (uart_handle_sysrq_char(&up->port, ch))
230 goto ignore_char;
231 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
232 ignore_char:
233 lsr = serial_in(up, UART_LSR);
234 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
235 spin_unlock(&up->port.lock);
236 tty_flip_buffer_push(tty);
237 spin_lock(&up->port.lock);
238 }
239
240 static void transmit_chars(struct uart_omap_port *up)
241 {
242 struct circ_buf *xmit = &up->port.state->xmit;
243 int count;
244
245 if (up->port.x_char) {
246 serial_out(up, UART_TX, up->port.x_char);
247 up->port.icount.tx++;
248 up->port.x_char = 0;
249 return;
250 }
251 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
252 serial_omap_stop_tx(&up->port);
253 return;
254 }
255 count = up->port.fifosize / 4;
256 do {
257 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
258 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
259 up->port.icount.tx++;
260 if (uart_circ_empty(xmit))
261 break;
262 } while (--count > 0);
263
264 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
265 uart_write_wakeup(&up->port);
266
267 if (uart_circ_empty(xmit))
268 serial_omap_stop_tx(&up->port);
269 }
270
271 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
272 {
273 if (!(up->ier & UART_IER_THRI)) {
274 up->ier |= UART_IER_THRI;
275 serial_out(up, UART_IER, up->ier);
276 }
277 }
278
279 static void serial_omap_start_tx(struct uart_port *port)
280 {
281 struct uart_omap_port *up = (struct uart_omap_port *)port;
282 struct circ_buf *xmit;
283 unsigned int start;
284 int ret = 0;
285
286 if (!up->use_dma) {
287 pm_runtime_get_sync(&up->pdev->dev);
288 serial_omap_enable_ier_thri(up);
289 pm_runtime_mark_last_busy(&up->pdev->dev);
290 pm_runtime_put_autosuspend(&up->pdev->dev);
291 return;
292 }
293
294 if (up->uart_dma.tx_dma_used)
295 return;
296
297 xmit = &up->port.state->xmit;
298
299 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
300 pm_runtime_get_sync(&up->pdev->dev);
301 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
302 "UART Tx DMA",
303 (void *)uart_tx_dma_callback, up,
304 &(up->uart_dma.tx_dma_channel));
305
306 if (ret < 0) {
307 serial_omap_enable_ier_thri(up);
308 return;
309 }
310 }
311 spin_lock(&(up->uart_dma.tx_lock));
312 up->uart_dma.tx_dma_used = true;
313 spin_unlock(&(up->uart_dma.tx_lock));
314
315 start = up->uart_dma.tx_buf_dma_phys +
316 (xmit->tail & (UART_XMIT_SIZE - 1));
317
318 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
319 /*
320 * It is a circular buffer. See if the buffer has wounded back.
321 * If yes it will have to be transferred in two separate dma
322 * transfers
323 */
324 if (start + up->uart_dma.tx_buf_size >=
325 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
326 up->uart_dma.tx_buf_size =
327 (up->uart_dma.tx_buf_dma_phys +
328 UART_XMIT_SIZE) - start;
329
330 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
331 OMAP_DMA_AMODE_CONSTANT,
332 up->uart_dma.uart_base, 0, 0);
333 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
334 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
335 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
336 OMAP_DMA_DATA_TYPE_S8,
337 up->uart_dma.tx_buf_size, 1,
338 OMAP_DMA_SYNC_ELEMENT,
339 up->uart_dma.uart_dma_tx, 0);
340 /* FIXME: Cache maintenance needed here? */
341 omap_start_dma(up->uart_dma.tx_dma_channel);
342 }
343
344 static unsigned int check_modem_status(struct uart_omap_port *up)
345 {
346 unsigned int status;
347
348 status = serial_in(up, UART_MSR);
349 status |= up->msr_saved_flags;
350 up->msr_saved_flags = 0;
351 if ((status & UART_MSR_ANY_DELTA) == 0)
352 return status;
353
354 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
355 up->port.state != NULL) {
356 if (status & UART_MSR_TERI)
357 up->port.icount.rng++;
358 if (status & UART_MSR_DDSR)
359 up->port.icount.dsr++;
360 if (status & UART_MSR_DDCD)
361 uart_handle_dcd_change
362 (&up->port, status & UART_MSR_DCD);
363 if (status & UART_MSR_DCTS)
364 uart_handle_cts_change
365 (&up->port, status & UART_MSR_CTS);
366 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
367 }
368
369 return status;
370 }
371
372 /**
373 * serial_omap_irq() - This handles the interrupt from one port
374 * @irq: uart port irq number
375 * @dev_id: uart port info
376 */
377 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
378 {
379 struct uart_omap_port *up = dev_id;
380 unsigned int iir, lsr;
381 unsigned long flags;
382
383 pm_runtime_get_sync(&up->pdev->dev);
384 iir = serial_in(up, UART_IIR);
385 if (iir & UART_IIR_NO_INT) {
386 pm_runtime_mark_last_busy(&up->pdev->dev);
387 pm_runtime_put_autosuspend(&up->pdev->dev);
388 return IRQ_NONE;
389 }
390
391 spin_lock_irqsave(&up->port.lock, flags);
392 lsr = serial_in(up, UART_LSR);
393 if (iir & UART_IIR_RLSI) {
394 if (!up->use_dma) {
395 if (lsr & UART_LSR_DR)
396 receive_chars(up, &lsr);
397 } else {
398 up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
399 serial_out(up, UART_IER, up->ier);
400 if ((serial_omap_start_rxdma(up) != 0) &&
401 (lsr & UART_LSR_DR))
402 receive_chars(up, &lsr);
403 }
404 }
405
406 check_modem_status(up);
407 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
408 transmit_chars(up);
409
410 spin_unlock_irqrestore(&up->port.lock, flags);
411 pm_runtime_mark_last_busy(&up->pdev->dev);
412 pm_runtime_put_autosuspend(&up->pdev->dev);
413
414 up->port_activity = jiffies;
415 return IRQ_HANDLED;
416 }
417
418 static unsigned int serial_omap_tx_empty(struct uart_port *port)
419 {
420 struct uart_omap_port *up = (struct uart_omap_port *)port;
421 unsigned long flags = 0;
422 unsigned int ret = 0;
423
424 pm_runtime_get_sync(&up->pdev->dev);
425 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
426 spin_lock_irqsave(&up->port.lock, flags);
427 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
428 spin_unlock_irqrestore(&up->port.lock, flags);
429 pm_runtime_put(&up->pdev->dev);
430 return ret;
431 }
432
433 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
434 {
435 struct uart_omap_port *up = (struct uart_omap_port *)port;
436 unsigned int status;
437 unsigned int ret = 0;
438
439 pm_runtime_get_sync(&up->pdev->dev);
440 status = check_modem_status(up);
441 pm_runtime_put(&up->pdev->dev);
442
443 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
444
445 if (status & UART_MSR_DCD)
446 ret |= TIOCM_CAR;
447 if (status & UART_MSR_RI)
448 ret |= TIOCM_RNG;
449 if (status & UART_MSR_DSR)
450 ret |= TIOCM_DSR;
451 if (status & UART_MSR_CTS)
452 ret |= TIOCM_CTS;
453 return ret;
454 }
455
456 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
457 {
458 struct uart_omap_port *up = (struct uart_omap_port *)port;
459 unsigned char mcr = 0;
460
461 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
462 if (mctrl & TIOCM_RTS)
463 mcr |= UART_MCR_RTS;
464 if (mctrl & TIOCM_DTR)
465 mcr |= UART_MCR_DTR;
466 if (mctrl & TIOCM_OUT1)
467 mcr |= UART_MCR_OUT1;
468 if (mctrl & TIOCM_OUT2)
469 mcr |= UART_MCR_OUT2;
470 if (mctrl & TIOCM_LOOP)
471 mcr |= UART_MCR_LOOP;
472
473 pm_runtime_get_sync(&up->pdev->dev);
474 up->mcr = serial_in(up, UART_MCR);
475 up->mcr |= mcr;
476 serial_out(up, UART_MCR, up->mcr);
477 pm_runtime_put(&up->pdev->dev);
478 }
479
480 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
481 {
482 struct uart_omap_port *up = (struct uart_omap_port *)port;
483 unsigned long flags = 0;
484
485 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
486 pm_runtime_get_sync(&up->pdev->dev);
487 spin_lock_irqsave(&up->port.lock, flags);
488 if (break_state == -1)
489 up->lcr |= UART_LCR_SBC;
490 else
491 up->lcr &= ~UART_LCR_SBC;
492 serial_out(up, UART_LCR, up->lcr);
493 spin_unlock_irqrestore(&up->port.lock, flags);
494 pm_runtime_put(&up->pdev->dev);
495 }
496
497 static int serial_omap_startup(struct uart_port *port)
498 {
499 struct uart_omap_port *up = (struct uart_omap_port *)port;
500 unsigned long flags = 0;
501 int retval;
502
503 /*
504 * Allocate the IRQ
505 */
506 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
507 up->name, up);
508 if (retval)
509 return retval;
510
511 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
512
513 pm_runtime_get_sync(&up->pdev->dev);
514 /*
515 * Clear the FIFO buffers and disable them.
516 * (they will be reenabled in set_termios())
517 */
518 serial_omap_clear_fifos(up);
519 /* For Hardware flow control */
520 serial_out(up, UART_MCR, UART_MCR_RTS);
521
522 /*
523 * Clear the interrupt registers.
524 */
525 (void) serial_in(up, UART_LSR);
526 if (serial_in(up, UART_LSR) & UART_LSR_DR)
527 (void) serial_in(up, UART_RX);
528 (void) serial_in(up, UART_IIR);
529 (void) serial_in(up, UART_MSR);
530
531 /*
532 * Now, initialize the UART
533 */
534 serial_out(up, UART_LCR, UART_LCR_WLEN8);
535 spin_lock_irqsave(&up->port.lock, flags);
536 /*
537 * Most PC uarts need OUT2 raised to enable interrupts.
538 */
539 up->port.mctrl |= TIOCM_OUT2;
540 serial_omap_set_mctrl(&up->port, up->port.mctrl);
541 spin_unlock_irqrestore(&up->port.lock, flags);
542
543 up->msr_saved_flags = 0;
544 if (up->use_dma) {
545 free_page((unsigned long)up->port.state->xmit.buf);
546 up->port.state->xmit.buf = dma_alloc_coherent(NULL,
547 UART_XMIT_SIZE,
548 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
549 0);
550 init_timer(&(up->uart_dma.rx_timer));
551 up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
552 up->uart_dma.rx_timer.data = up->port.line;
553 /* Currently the buffer size is 4KB. Can increase it */
554 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
555 up->uart_dma.rx_buf_size,
556 (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
557 }
558 /*
559 * Finally, enable interrupts. Note: Modem status interrupts
560 * are set via set_termios(), which will be occurring imminently
561 * anyway, so we don't enable them here.
562 */
563 up->ier = UART_IER_RLSI | UART_IER_RDI;
564 serial_out(up, UART_IER, up->ier);
565
566 /* Enable module level wake up */
567 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
568
569 pm_runtime_mark_last_busy(&up->pdev->dev);
570 pm_runtime_put_autosuspend(&up->pdev->dev);
571 up->port_activity = jiffies;
572 return 0;
573 }
574
575 static void serial_omap_shutdown(struct uart_port *port)
576 {
577 struct uart_omap_port *up = (struct uart_omap_port *)port;
578 unsigned long flags = 0;
579
580 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
581
582 pm_runtime_get_sync(&up->pdev->dev);
583 /*
584 * Disable interrupts from this port
585 */
586 up->ier = 0;
587 serial_out(up, UART_IER, 0);
588
589 spin_lock_irqsave(&up->port.lock, flags);
590 up->port.mctrl &= ~TIOCM_OUT2;
591 serial_omap_set_mctrl(&up->port, up->port.mctrl);
592 spin_unlock_irqrestore(&up->port.lock, flags);
593
594 /*
595 * Disable break condition and FIFOs
596 */
597 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
598 serial_omap_clear_fifos(up);
599
600 /*
601 * Read data port to reset things, and then free the irq
602 */
603 if (serial_in(up, UART_LSR) & UART_LSR_DR)
604 (void) serial_in(up, UART_RX);
605 if (up->use_dma) {
606 dma_free_coherent(up->port.dev,
607 UART_XMIT_SIZE, up->port.state->xmit.buf,
608 up->uart_dma.tx_buf_dma_phys);
609 up->port.state->xmit.buf = NULL;
610 serial_omap_stop_rx(port);
611 dma_free_coherent(up->port.dev,
612 up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
613 up->uart_dma.rx_buf_dma_phys);
614 up->uart_dma.rx_buf = NULL;
615 }
616
617 pm_runtime_put(&up->pdev->dev);
618 free_irq(up->port.irq, up);
619 }
620
621 static inline void
622 serial_omap_configure_xonxoff
623 (struct uart_omap_port *up, struct ktermios *termios)
624 {
625 up->lcr = serial_in(up, UART_LCR);
626 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
627 up->efr = serial_in(up, UART_EFR);
628 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
629
630 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
631 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
632
633 /* clear SW control mode bits */
634 up->efr &= OMAP_UART_SW_CLR;
635
636 /*
637 * IXON Flag:
638 * Enable XON/XOFF flow control on output.
639 * Transmit XON1, XOFF1
640 */
641 if (termios->c_iflag & IXON)
642 up->efr |= OMAP_UART_SW_TX;
643
644 /*
645 * IXOFF Flag:
646 * Enable XON/XOFF flow control on input.
647 * Receiver compares XON1, XOFF1.
648 */
649 if (termios->c_iflag & IXOFF)
650 up->efr |= OMAP_UART_SW_RX;
651
652 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
653 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
654
655 up->mcr = serial_in(up, UART_MCR);
656
657 /*
658 * IXANY Flag:
659 * Enable any character to restart output.
660 * Operation resumes after receiving any
661 * character after recognition of the XOFF character
662 */
663 if (termios->c_iflag & IXANY)
664 up->mcr |= UART_MCR_XONANY;
665
666 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
667 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
668 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
669 /* Enable special char function UARTi.EFR_REG[5] and
670 * load the new software flow control mode IXON or IXOFF
671 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
672 */
673 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
674 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
675
676 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
677 serial_out(up, UART_LCR, up->lcr);
678 }
679
680 static void serial_omap_uart_qos_work(struct work_struct *work)
681 {
682 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
683 qos_work);
684
685 pm_qos_update_request(&up->pm_qos_request, up->latency);
686 }
687
688 static void
689 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
690 struct ktermios *old)
691 {
692 struct uart_omap_port *up = (struct uart_omap_port *)port;
693 unsigned char cval = 0;
694 unsigned char efr = 0;
695 unsigned long flags = 0;
696 unsigned int baud, quot;
697
698 switch (termios->c_cflag & CSIZE) {
699 case CS5:
700 cval = UART_LCR_WLEN5;
701 break;
702 case CS6:
703 cval = UART_LCR_WLEN6;
704 break;
705 case CS7:
706 cval = UART_LCR_WLEN7;
707 break;
708 default:
709 case CS8:
710 cval = UART_LCR_WLEN8;
711 break;
712 }
713
714 if (termios->c_cflag & CSTOPB)
715 cval |= UART_LCR_STOP;
716 if (termios->c_cflag & PARENB)
717 cval |= UART_LCR_PARITY;
718 if (!(termios->c_cflag & PARODD))
719 cval |= UART_LCR_EPAR;
720
721 /*
722 * Ask the core to calculate the divisor for us.
723 */
724
725 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
726 quot = serial_omap_get_divisor(port, baud);
727
728 /* calculate wakeup latency constraint */
729 up->calc_latency = (1000000 * up->port.fifosize) /
730 (1000 * baud / 8);
731 up->latency = up->calc_latency;
732 schedule_work(&up->qos_work);
733
734 up->dll = quot & 0xff;
735 up->dlh = quot >> 8;
736 up->mdr1 = UART_OMAP_MDR1_DISABLE;
737
738 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
739 UART_FCR_ENABLE_FIFO;
740 if (up->use_dma)
741 up->fcr |= UART_FCR_DMA_SELECT;
742
743 /*
744 * Ok, we're now changing the port state. Do it with
745 * interrupts disabled.
746 */
747 pm_runtime_get_sync(&up->pdev->dev);
748 spin_lock_irqsave(&up->port.lock, flags);
749
750 /*
751 * Update the per-port timeout.
752 */
753 uart_update_timeout(port, termios->c_cflag, baud);
754
755 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
756 if (termios->c_iflag & INPCK)
757 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
758 if (termios->c_iflag & (BRKINT | PARMRK))
759 up->port.read_status_mask |= UART_LSR_BI;
760
761 /*
762 * Characters to ignore
763 */
764 up->port.ignore_status_mask = 0;
765 if (termios->c_iflag & IGNPAR)
766 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
767 if (termios->c_iflag & IGNBRK) {
768 up->port.ignore_status_mask |= UART_LSR_BI;
769 /*
770 * If we're ignoring parity and break indicators,
771 * ignore overruns too (for real raw support).
772 */
773 if (termios->c_iflag & IGNPAR)
774 up->port.ignore_status_mask |= UART_LSR_OE;
775 }
776
777 /*
778 * ignore all characters if CREAD is not set
779 */
780 if ((termios->c_cflag & CREAD) == 0)
781 up->port.ignore_status_mask |= UART_LSR_DR;
782
783 /*
784 * Modem status interrupts
785 */
786 up->ier &= ~UART_IER_MSI;
787 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
788 up->ier |= UART_IER_MSI;
789 serial_out(up, UART_IER, up->ier);
790 serial_out(up, UART_LCR, cval); /* reset DLAB */
791 up->lcr = cval;
792 up->scr = OMAP_UART_SCR_TX_EMPTY;
793
794 /* FIFOs and DMA Settings */
795
796 /* FCR can be changed only when the
797 * baud clock is not running
798 * DLL_REG and DLH_REG set to 0.
799 */
800 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
801 serial_out(up, UART_DLL, 0);
802 serial_out(up, UART_DLM, 0);
803 serial_out(up, UART_LCR, 0);
804
805 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
806
807 up->efr = serial_in(up, UART_EFR);
808 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
809
810 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
811 up->mcr = serial_in(up, UART_MCR);
812 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
813 /* FIFO ENABLE, DMA MODE */
814 serial_out(up, UART_FCR, up->fcr);
815 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
816
817 if (up->use_dma) {
818 serial_out(up, UART_TI752_TLR, 0);
819 up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8);
820 }
821
822 serial_out(up, UART_OMAP_SCR, up->scr);
823
824 serial_out(up, UART_EFR, up->efr);
825 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
826 serial_out(up, UART_MCR, up->mcr);
827
828 /* Protocol, Baud Rate, and Interrupt Settings */
829
830 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
831 serial_omap_mdr1_errataset(up, up->mdr1);
832 else
833 serial_out(up, UART_OMAP_MDR1, up->mdr1);
834
835 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
836
837 up->efr = serial_in(up, UART_EFR);
838 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
839
840 serial_out(up, UART_LCR, 0);
841 serial_out(up, UART_IER, 0);
842 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
843
844 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
845 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
846
847 serial_out(up, UART_LCR, 0);
848 serial_out(up, UART_IER, up->ier);
849 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
850
851 serial_out(up, UART_EFR, up->efr);
852 serial_out(up, UART_LCR, cval);
853
854 if (baud > 230400 && baud != 3000000)
855 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
856 else
857 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
858
859 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
860 serial_omap_mdr1_errataset(up, up->mdr1);
861 else
862 serial_out(up, UART_OMAP_MDR1, up->mdr1);
863
864 /* Hardware Flow Control Configuration */
865
866 if (termios->c_cflag & CRTSCTS) {
867 efr |= (UART_EFR_CTS | UART_EFR_RTS);
868 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
869
870 up->mcr = serial_in(up, UART_MCR);
871 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
872
873 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
874 up->efr = serial_in(up, UART_EFR);
875 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
876
877 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
878 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
879 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
880 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
881 serial_out(up, UART_LCR, cval);
882 }
883
884 serial_omap_set_mctrl(&up->port, up->port.mctrl);
885 /* Software Flow Control Configuration */
886 serial_omap_configure_xonxoff(up, termios);
887
888 spin_unlock_irqrestore(&up->port.lock, flags);
889 pm_runtime_put(&up->pdev->dev);
890 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
891 }
892
893 static void
894 serial_omap_pm(struct uart_port *port, unsigned int state,
895 unsigned int oldstate)
896 {
897 struct uart_omap_port *up = (struct uart_omap_port *)port;
898 unsigned char efr;
899
900 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
901
902 pm_runtime_get_sync(&up->pdev->dev);
903 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
904 efr = serial_in(up, UART_EFR);
905 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
906 serial_out(up, UART_LCR, 0);
907
908 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
909 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
910 serial_out(up, UART_EFR, efr);
911 serial_out(up, UART_LCR, 0);
912
913 if (!device_may_wakeup(&up->pdev->dev)) {
914 if (!state)
915 pm_runtime_forbid(&up->pdev->dev);
916 else
917 pm_runtime_allow(&up->pdev->dev);
918 }
919
920 pm_runtime_put(&up->pdev->dev);
921 }
922
923 static void serial_omap_release_port(struct uart_port *port)
924 {
925 dev_dbg(port->dev, "serial_omap_release_port+\n");
926 }
927
928 static int serial_omap_request_port(struct uart_port *port)
929 {
930 dev_dbg(port->dev, "serial_omap_request_port+\n");
931 return 0;
932 }
933
934 static void serial_omap_config_port(struct uart_port *port, int flags)
935 {
936 struct uart_omap_port *up = (struct uart_omap_port *)port;
937
938 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
939 up->port.line);
940 up->port.type = PORT_OMAP;
941 }
942
943 static int
944 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
945 {
946 /* we don't want the core code to modify any port params */
947 dev_dbg(port->dev, "serial_omap_verify_port+\n");
948 return -EINVAL;
949 }
950
951 static const char *
952 serial_omap_type(struct uart_port *port)
953 {
954 struct uart_omap_port *up = (struct uart_omap_port *)port;
955
956 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
957 return up->name;
958 }
959
960 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
961
962 static inline void wait_for_xmitr(struct uart_omap_port *up)
963 {
964 unsigned int status, tmout = 10000;
965
966 /* Wait up to 10ms for the character(s) to be sent. */
967 do {
968 status = serial_in(up, UART_LSR);
969
970 if (status & UART_LSR_BI)
971 up->lsr_break_flag = UART_LSR_BI;
972
973 if (--tmout == 0)
974 break;
975 udelay(1);
976 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
977
978 /* Wait up to 1s for flow control if necessary */
979 if (up->port.flags & UPF_CONS_FLOW) {
980 tmout = 1000000;
981 for (tmout = 1000000; tmout; tmout--) {
982 unsigned int msr = serial_in(up, UART_MSR);
983
984 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
985 if (msr & UART_MSR_CTS)
986 break;
987
988 udelay(1);
989 }
990 }
991 }
992
993 #ifdef CONFIG_CONSOLE_POLL
994
995 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
996 {
997 struct uart_omap_port *up = (struct uart_omap_port *)port;
998
999 pm_runtime_get_sync(&up->pdev->dev);
1000 wait_for_xmitr(up);
1001 serial_out(up, UART_TX, ch);
1002 pm_runtime_put(&up->pdev->dev);
1003 }
1004
1005 static int serial_omap_poll_get_char(struct uart_port *port)
1006 {
1007 struct uart_omap_port *up = (struct uart_omap_port *)port;
1008 unsigned int status;
1009
1010 pm_runtime_get_sync(&up->pdev->dev);
1011 status = serial_in(up, UART_LSR);
1012 if (!(status & UART_LSR_DR))
1013 return NO_POLL_CHAR;
1014
1015 status = serial_in(up, UART_RX);
1016 pm_runtime_put(&up->pdev->dev);
1017 return status;
1018 }
1019
1020 #endif /* CONFIG_CONSOLE_POLL */
1021
1022 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1023
1024 static struct uart_omap_port *serial_omap_console_ports[4];
1025
1026 static struct uart_driver serial_omap_reg;
1027
1028 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1029 {
1030 struct uart_omap_port *up = (struct uart_omap_port *)port;
1031
1032 wait_for_xmitr(up);
1033 serial_out(up, UART_TX, ch);
1034 }
1035
1036 static void
1037 serial_omap_console_write(struct console *co, const char *s,
1038 unsigned int count)
1039 {
1040 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1041 unsigned long flags;
1042 unsigned int ier;
1043 int locked = 1;
1044
1045 pm_runtime_get_sync(&up->pdev->dev);
1046
1047 local_irq_save(flags);
1048 if (up->port.sysrq)
1049 locked = 0;
1050 else if (oops_in_progress)
1051 locked = spin_trylock(&up->port.lock);
1052 else
1053 spin_lock(&up->port.lock);
1054
1055 /*
1056 * First save the IER then disable the interrupts
1057 */
1058 ier = serial_in(up, UART_IER);
1059 serial_out(up, UART_IER, 0);
1060
1061 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1062
1063 /*
1064 * Finally, wait for transmitter to become empty
1065 * and restore the IER
1066 */
1067 wait_for_xmitr(up);
1068 serial_out(up, UART_IER, ier);
1069 /*
1070 * The receive handling will happen properly because the
1071 * receive ready bit will still be set; it is not cleared
1072 * on read. However, modem control will not, we must
1073 * call it if we have saved something in the saved flags
1074 * while processing with interrupts off.
1075 */
1076 if (up->msr_saved_flags)
1077 check_modem_status(up);
1078
1079 pm_runtime_mark_last_busy(&up->pdev->dev);
1080 pm_runtime_put_autosuspend(&up->pdev->dev);
1081 if (locked)
1082 spin_unlock(&up->port.lock);
1083 local_irq_restore(flags);
1084 }
1085
1086 static int __init
1087 serial_omap_console_setup(struct console *co, char *options)
1088 {
1089 struct uart_omap_port *up;
1090 int baud = 115200;
1091 int bits = 8;
1092 int parity = 'n';
1093 int flow = 'n';
1094
1095 if (serial_omap_console_ports[co->index] == NULL)
1096 return -ENODEV;
1097 up = serial_omap_console_ports[co->index];
1098
1099 if (options)
1100 uart_parse_options(options, &baud, &parity, &bits, &flow);
1101
1102 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1103 }
1104
1105 static struct console serial_omap_console = {
1106 .name = OMAP_SERIAL_NAME,
1107 .write = serial_omap_console_write,
1108 .device = uart_console_device,
1109 .setup = serial_omap_console_setup,
1110 .flags = CON_PRINTBUFFER,
1111 .index = -1,
1112 .data = &serial_omap_reg,
1113 };
1114
1115 static void serial_omap_add_console_port(struct uart_omap_port *up)
1116 {
1117 serial_omap_console_ports[up->port.line] = up;
1118 }
1119
1120 #define OMAP_CONSOLE (&serial_omap_console)
1121
1122 #else
1123
1124 #define OMAP_CONSOLE NULL
1125
1126 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1127 {}
1128
1129 #endif
1130
1131 static struct uart_ops serial_omap_pops = {
1132 .tx_empty = serial_omap_tx_empty,
1133 .set_mctrl = serial_omap_set_mctrl,
1134 .get_mctrl = serial_omap_get_mctrl,
1135 .stop_tx = serial_omap_stop_tx,
1136 .start_tx = serial_omap_start_tx,
1137 .stop_rx = serial_omap_stop_rx,
1138 .enable_ms = serial_omap_enable_ms,
1139 .break_ctl = serial_omap_break_ctl,
1140 .startup = serial_omap_startup,
1141 .shutdown = serial_omap_shutdown,
1142 .set_termios = serial_omap_set_termios,
1143 .pm = serial_omap_pm,
1144 .type = serial_omap_type,
1145 .release_port = serial_omap_release_port,
1146 .request_port = serial_omap_request_port,
1147 .config_port = serial_omap_config_port,
1148 .verify_port = serial_omap_verify_port,
1149 #ifdef CONFIG_CONSOLE_POLL
1150 .poll_put_char = serial_omap_poll_put_char,
1151 .poll_get_char = serial_omap_poll_get_char,
1152 #endif
1153 };
1154
1155 static struct uart_driver serial_omap_reg = {
1156 .owner = THIS_MODULE,
1157 .driver_name = "OMAP-SERIAL",
1158 .dev_name = OMAP_SERIAL_NAME,
1159 .nr = OMAP_MAX_HSUART_PORTS,
1160 .cons = OMAP_CONSOLE,
1161 };
1162
1163 #ifdef CONFIG_SUSPEND
1164 static int serial_omap_suspend(struct device *dev)
1165 {
1166 struct uart_omap_port *up = dev_get_drvdata(dev);
1167
1168 if (up) {
1169 uart_suspend_port(&serial_omap_reg, &up->port);
1170 flush_work_sync(&up->qos_work);
1171 }
1172
1173 return 0;
1174 }
1175
1176 static int serial_omap_resume(struct device *dev)
1177 {
1178 struct uart_omap_port *up = dev_get_drvdata(dev);
1179
1180 if (up)
1181 uart_resume_port(&serial_omap_reg, &up->port);
1182 return 0;
1183 }
1184 #endif
1185
1186 static void serial_omap_rxdma_poll(unsigned long uart_no)
1187 {
1188 struct uart_omap_port *up = ui[uart_no];
1189 unsigned int curr_dma_pos, curr_transmitted_size;
1190 int ret = 0;
1191
1192 curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
1193 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1194 (curr_dma_pos == 0)) {
1195 if (jiffies_to_msecs(jiffies - up->port_activity) <
1196 up->uart_dma.rx_timeout) {
1197 mod_timer(&up->uart_dma.rx_timer, jiffies +
1198 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1199 } else {
1200 serial_omap_stop_rxdma(up);
1201 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1202 serial_out(up, UART_IER, up->ier);
1203 }
1204 return;
1205 }
1206
1207 curr_transmitted_size = curr_dma_pos -
1208 up->uart_dma.prev_rx_dma_pos;
1209 up->port.icount.rx += curr_transmitted_size;
1210 tty_insert_flip_string(up->port.state->port.tty,
1211 up->uart_dma.rx_buf +
1212 (up->uart_dma.prev_rx_dma_pos -
1213 up->uart_dma.rx_buf_dma_phys),
1214 curr_transmitted_size);
1215 tty_flip_buffer_push(up->port.state->port.tty);
1216 up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
1217 if (up->uart_dma.rx_buf_size +
1218 up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
1219 ret = serial_omap_start_rxdma(up);
1220 if (ret < 0) {
1221 serial_omap_stop_rxdma(up);
1222 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1223 serial_out(up, UART_IER, up->ier);
1224 }
1225 } else {
1226 mod_timer(&up->uart_dma.rx_timer, jiffies +
1227 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1228 }
1229 up->port_activity = jiffies;
1230 }
1231
1232 static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
1233 {
1234 return;
1235 }
1236
1237 static int serial_omap_start_rxdma(struct uart_omap_port *up)
1238 {
1239 int ret = 0;
1240
1241 if (up->uart_dma.rx_dma_channel == -1) {
1242 pm_runtime_get_sync(&up->pdev->dev);
1243 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1244 "UART Rx DMA",
1245 (void *)uart_rx_dma_callback, up,
1246 &(up->uart_dma.rx_dma_channel));
1247 if (ret < 0)
1248 return ret;
1249
1250 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
1251 OMAP_DMA_AMODE_CONSTANT,
1252 up->uart_dma.uart_base, 0, 0);
1253 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
1254 OMAP_DMA_AMODE_POST_INC,
1255 up->uart_dma.rx_buf_dma_phys, 0, 0);
1256 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
1257 OMAP_DMA_DATA_TYPE_S8,
1258 up->uart_dma.rx_buf_size, 1,
1259 OMAP_DMA_SYNC_ELEMENT,
1260 up->uart_dma.uart_dma_rx, 0);
1261 }
1262 up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
1263 /* FIXME: Cache maintenance needed here? */
1264 omap_start_dma(up->uart_dma.rx_dma_channel);
1265 mod_timer(&up->uart_dma.rx_timer, jiffies +
1266 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1267 up->uart_dma.rx_dma_used = true;
1268 return ret;
1269 }
1270
1271 static void serial_omap_continue_tx(struct uart_omap_port *up)
1272 {
1273 struct circ_buf *xmit = &up->port.state->xmit;
1274 unsigned int start = up->uart_dma.tx_buf_dma_phys
1275 + (xmit->tail & (UART_XMIT_SIZE - 1));
1276
1277 if (uart_circ_empty(xmit))
1278 return;
1279
1280 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
1281 /*
1282 * It is a circular buffer. See if the buffer has wounded back.
1283 * If yes it will have to be transferred in two separate dma
1284 * transfers
1285 */
1286 if (start + up->uart_dma.tx_buf_size >=
1287 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
1288 up->uart_dma.tx_buf_size =
1289 (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
1290 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
1291 OMAP_DMA_AMODE_CONSTANT,
1292 up->uart_dma.uart_base, 0, 0);
1293 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
1294 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
1295 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
1296 OMAP_DMA_DATA_TYPE_S8,
1297 up->uart_dma.tx_buf_size, 1,
1298 OMAP_DMA_SYNC_ELEMENT,
1299 up->uart_dma.uart_dma_tx, 0);
1300 /* FIXME: Cache maintenance needed here? */
1301 omap_start_dma(up->uart_dma.tx_dma_channel);
1302 }
1303
1304 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1305 {
1306 struct uart_omap_port *up = (struct uart_omap_port *)data;
1307 struct circ_buf *xmit = &up->port.state->xmit;
1308
1309 xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
1310 (UART_XMIT_SIZE - 1);
1311 up->port.icount.tx += up->uart_dma.tx_buf_size;
1312
1313 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1314 uart_write_wakeup(&up->port);
1315
1316 if (uart_circ_empty(xmit)) {
1317 spin_lock(&(up->uart_dma.tx_lock));
1318 serial_omap_stop_tx(&up->port);
1319 up->uart_dma.tx_dma_used = false;
1320 spin_unlock(&(up->uart_dma.tx_lock));
1321 } else {
1322 omap_stop_dma(up->uart_dma.tx_dma_channel);
1323 serial_omap_continue_tx(up);
1324 }
1325 up->port_activity = jiffies;
1326 return;
1327 }
1328
1329 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1330 {
1331 struct omap_uart_port_info *omap_up_info;
1332
1333 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1334 if (!omap_up_info)
1335 return NULL; /* out of memory */
1336
1337 of_property_read_u32(dev->of_node, "clock-frequency",
1338 &omap_up_info->uartclk);
1339 return omap_up_info;
1340 }
1341
1342 static int serial_omap_probe(struct platform_device *pdev)
1343 {
1344 struct uart_omap_port *up;
1345 struct resource *mem, *irq, *dma_tx, *dma_rx;
1346 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1347 int ret = -ENOSPC;
1348
1349 if (pdev->dev.of_node)
1350 omap_up_info = of_get_uart_port_info(&pdev->dev);
1351
1352 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1353 if (!mem) {
1354 dev_err(&pdev->dev, "no mem resource?\n");
1355 return -ENODEV;
1356 }
1357
1358 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1359 if (!irq) {
1360 dev_err(&pdev->dev, "no irq resource?\n");
1361 return -ENODEV;
1362 }
1363
1364 if (!request_mem_region(mem->start, resource_size(mem),
1365 pdev->dev.driver->name)) {
1366 dev_err(&pdev->dev, "memory region already claimed\n");
1367 return -EBUSY;
1368 }
1369
1370 dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1371 if (!dma_rx) {
1372 ret = -EINVAL;
1373 goto err;
1374 }
1375
1376 dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1377 if (!dma_tx) {
1378 ret = -EINVAL;
1379 goto err;
1380 }
1381
1382 up = kzalloc(sizeof(*up), GFP_KERNEL);
1383 if (up == NULL) {
1384 ret = -ENOMEM;
1385 goto do_release_region;
1386 }
1387 up->pdev = pdev;
1388 up->port.dev = &pdev->dev;
1389 up->port.type = PORT_OMAP;
1390 up->port.iotype = UPIO_MEM;
1391 up->port.irq = irq->start;
1392
1393 up->port.regshift = 2;
1394 up->port.fifosize = 64;
1395 up->port.ops = &serial_omap_pops;
1396
1397 if (pdev->dev.of_node)
1398 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1399 else
1400 up->port.line = pdev->id;
1401
1402 if (up->port.line < 0) {
1403 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1404 up->port.line);
1405 ret = -ENODEV;
1406 goto err;
1407 }
1408
1409 sprintf(up->name, "OMAP UART%d", up->port.line);
1410 up->port.mapbase = mem->start;
1411 up->port.membase = ioremap(mem->start, resource_size(mem));
1412 if (!up->port.membase) {
1413 dev_err(&pdev->dev, "can't ioremap UART\n");
1414 ret = -ENOMEM;
1415 goto err;
1416 }
1417
1418 up->port.flags = omap_up_info->flags;
1419 up->port.uartclk = omap_up_info->uartclk;
1420 if (!up->port.uartclk) {
1421 up->port.uartclk = DEFAULT_CLK_SPEED;
1422 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1423 "%d\n", DEFAULT_CLK_SPEED);
1424 }
1425 up->uart_dma.uart_base = mem->start;
1426 up->errata = omap_up_info->errata;
1427
1428 if (omap_up_info->dma_enabled) {
1429 up->uart_dma.uart_dma_tx = dma_tx->start;
1430 up->uart_dma.uart_dma_rx = dma_rx->start;
1431 up->use_dma = 1;
1432 up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
1433 up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
1434 up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
1435 spin_lock_init(&(up->uart_dma.tx_lock));
1436 spin_lock_init(&(up->uart_dma.rx_lock));
1437 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1438 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1439 }
1440
1441 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1442 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1443 pm_qos_add_request(&up->pm_qos_request,
1444 PM_QOS_CPU_DMA_LATENCY, up->latency);
1445 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1446 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1447
1448 pm_runtime_use_autosuspend(&pdev->dev);
1449 pm_runtime_set_autosuspend_delay(&pdev->dev,
1450 omap_up_info->autosuspend_timeout);
1451
1452 pm_runtime_irq_safe(&pdev->dev);
1453 pm_runtime_enable(&pdev->dev);
1454 pm_runtime_get_sync(&pdev->dev);
1455
1456 ui[up->port.line] = up;
1457 serial_omap_add_console_port(up);
1458
1459 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1460 if (ret != 0)
1461 goto do_release_region;
1462
1463 pm_runtime_put(&pdev->dev);
1464 platform_set_drvdata(pdev, up);
1465 return 0;
1466 err:
1467 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1468 pdev->id, __func__, ret);
1469 do_release_region:
1470 release_mem_region(mem->start, resource_size(mem));
1471 return ret;
1472 }
1473
1474 static int serial_omap_remove(struct platform_device *dev)
1475 {
1476 struct uart_omap_port *up = platform_get_drvdata(dev);
1477
1478 if (up) {
1479 pm_runtime_disable(&up->pdev->dev);
1480 uart_remove_one_port(&serial_omap_reg, &up->port);
1481 pm_qos_remove_request(&up->pm_qos_request);
1482
1483 kfree(up);
1484 }
1485
1486 platform_set_drvdata(dev, NULL);
1487 return 0;
1488 }
1489
1490 /*
1491 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1492 * The access to uart register after MDR1 Access
1493 * causes UART to corrupt data.
1494 *
1495 * Need a delay =
1496 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1497 * give 10 times as much
1498 */
1499 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1500 {
1501 u8 timeout = 255;
1502
1503 serial_out(up, UART_OMAP_MDR1, mdr1);
1504 udelay(2);
1505 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1506 UART_FCR_CLEAR_RCVR);
1507 /*
1508 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1509 * TX_FIFO_E bit is 1.
1510 */
1511 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1512 (UART_LSR_THRE | UART_LSR_DR))) {
1513 timeout--;
1514 if (!timeout) {
1515 /* Should *never* happen. we warn and carry on */
1516 dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
1517 serial_in(up, UART_LSR));
1518 break;
1519 }
1520 udelay(1);
1521 }
1522 }
1523
1524 static void serial_omap_restore_context(struct uart_omap_port *up)
1525 {
1526 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1527 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1528 else
1529 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1530
1531 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1532 serial_out(up, UART_EFR, UART_EFR_ECB);
1533 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1534 serial_out(up, UART_IER, 0x0);
1535 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1536 serial_out(up, UART_DLL, up->dll);
1537 serial_out(up, UART_DLM, up->dlh);
1538 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1539 serial_out(up, UART_IER, up->ier);
1540 serial_out(up, UART_FCR, up->fcr);
1541 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1542 serial_out(up, UART_MCR, up->mcr);
1543 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1544 serial_out(up, UART_OMAP_SCR, up->scr);
1545 serial_out(up, UART_EFR, up->efr);
1546 serial_out(up, UART_LCR, up->lcr);
1547 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1548 serial_omap_mdr1_errataset(up, up->mdr1);
1549 else
1550 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1551 }
1552
1553 #ifdef CONFIG_PM_RUNTIME
1554 static int serial_omap_runtime_suspend(struct device *dev)
1555 {
1556 struct uart_omap_port *up = dev_get_drvdata(dev);
1557 struct omap_uart_port_info *pdata = dev->platform_data;
1558
1559 if (!up)
1560 return -EINVAL;
1561
1562 if (!pdata || !pdata->enable_wakeup)
1563 return 0;
1564
1565 if (pdata->get_context_loss_count)
1566 up->context_loss_cnt = pdata->get_context_loss_count(dev);
1567
1568 if (device_may_wakeup(dev)) {
1569 if (!up->wakeups_enabled) {
1570 pdata->enable_wakeup(up->pdev, true);
1571 up->wakeups_enabled = true;
1572 }
1573 } else {
1574 if (up->wakeups_enabled) {
1575 pdata->enable_wakeup(up->pdev, false);
1576 up->wakeups_enabled = false;
1577 }
1578 }
1579
1580 /* Errata i291 */
1581 if (up->use_dma && pdata->set_forceidle &&
1582 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1583 pdata->set_forceidle(up->pdev);
1584
1585 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1586 schedule_work(&up->qos_work);
1587
1588 return 0;
1589 }
1590
1591 static int serial_omap_runtime_resume(struct device *dev)
1592 {
1593 struct uart_omap_port *up = dev_get_drvdata(dev);
1594 struct omap_uart_port_info *pdata = dev->platform_data;
1595
1596 if (up) {
1597 if (pdata->get_context_loss_count) {
1598 u32 loss_cnt = pdata->get_context_loss_count(dev);
1599
1600 if (up->context_loss_cnt != loss_cnt)
1601 serial_omap_restore_context(up);
1602 }
1603
1604 /* Errata i291 */
1605 if (up->use_dma && pdata->set_noidle &&
1606 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1607 pdata->set_noidle(up->pdev);
1608
1609 up->latency = up->calc_latency;
1610 schedule_work(&up->qos_work);
1611 }
1612
1613 return 0;
1614 }
1615 #endif
1616
1617 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1618 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1619 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1620 serial_omap_runtime_resume, NULL)
1621 };
1622
1623 #if defined(CONFIG_OF)
1624 static const struct of_device_id omap_serial_of_match[] = {
1625 { .compatible = "ti,omap2-uart" },
1626 { .compatible = "ti,omap3-uart" },
1627 { .compatible = "ti,omap4-uart" },
1628 {},
1629 };
1630 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1631 #endif
1632
1633 static struct platform_driver serial_omap_driver = {
1634 .probe = serial_omap_probe,
1635 .remove = serial_omap_remove,
1636 .driver = {
1637 .name = DRIVER_NAME,
1638 .pm = &serial_omap_dev_pm_ops,
1639 .of_match_table = of_match_ptr(omap_serial_of_match),
1640 },
1641 };
1642
1643 static int __init serial_omap_init(void)
1644 {
1645 int ret;
1646
1647 ret = uart_register_driver(&serial_omap_reg);
1648 if (ret != 0)
1649 return ret;
1650 ret = platform_driver_register(&serial_omap_driver);
1651 if (ret != 0)
1652 uart_unregister_driver(&serial_omap_reg);
1653 return ret;
1654 }
1655
1656 static void __exit serial_omap_exit(void)
1657 {
1658 platform_driver_unregister(&serial_omap_driver);
1659 uart_unregister_driver(&serial_omap_reg);
1660 }
1661
1662 module_init(serial_omap_init);
1663 module_exit(serial_omap_exit);
1664
1665 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1666 MODULE_LICENSE("GPL");
1667 MODULE_AUTHOR("Texas Instruments Inc");
Linux with added FPC-III support