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alpha: fix several security issues
[linux/fpc-iii.git] / drivers / scsi / mvsas / mv_64xx.c
blob13c960481391e8590d0b7b2e3163f58022ca424f
1 /*
2 * Marvell 88SE64xx hardware specific
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
7 *
8 * This file is licensed under GPLv2.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
13 * License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
23 * USA
24 */
25
26 #include "mv_sas.h"
27 #include "mv_64xx.h"
28 #include "mv_chips.h"
29
30 static void mvs_64xx_detect_porttype(struct mvs_info *mvi, int i)
31 {
32 void __iomem *regs = mvi->regs;
33 u32 reg;
34 struct mvs_phy *phy = &mvi->phy[i];
35
36 /* TODO check & save device type */
37 reg = mr32(MVS_GBL_PORT_TYPE);
38 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
39 if (reg & MODE_SAS_SATA & (1 << i))
40 phy->phy_type |= PORT_TYPE_SAS;
41 else
42 phy->phy_type |= PORT_TYPE_SATA;
43 }
44
45 static void __devinit mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id)
46 {
47 void __iomem *regs = mvi->regs;
48 u32 tmp;
49
50 tmp = mr32(MVS_PCS);
51 if (mvi->chip->n_phy <= 4)
52 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT);
53 else
54 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
55 mw32(MVS_PCS, tmp);
56 }
57
58 static void __devinit mvs_64xx_phy_hacks(struct mvs_info *mvi)
59 {
60 void __iomem *regs = mvi->regs;
61
62 mvs_phy_hacks(mvi);
63
64 if (!(mvi->flags & MVF_FLAG_SOC)) {
65 /* TEST - for phy decoding error, adjust voltage levels */
66 mw32(MVS_P0_VSR_ADDR + 0, 0x8);
67 mw32(MVS_P0_VSR_DATA + 0, 0x2F0);
68
69 mw32(MVS_P0_VSR_ADDR + 8, 0x8);
70 mw32(MVS_P0_VSR_DATA + 8, 0x2F0);
71
72 mw32(MVS_P0_VSR_ADDR + 16, 0x8);
73 mw32(MVS_P0_VSR_DATA + 16, 0x2F0);
74
75 mw32(MVS_P0_VSR_ADDR + 24, 0x8);
76 mw32(MVS_P0_VSR_DATA + 24, 0x2F0);
77 } else {
78 int i;
79 /* disable auto port detection */
80 mw32(MVS_GBL_PORT_TYPE, 0);
81 for (i = 0; i < mvi->chip->n_phy; i++) {
82 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7);
83 mvs_write_port_vsr_data(mvi, i, 0x90000000);
84 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9);
85 mvs_write_port_vsr_data(mvi, i, 0x50f2);
86 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11);
87 mvs_write_port_vsr_data(mvi, i, 0x0e);
88 }
89 }
90 }
91
92 static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id)
93 {
94 void __iomem *regs = mvi->regs;
95 u32 reg, tmp;
96
97 if (!(mvi->flags & MVF_FLAG_SOC)) {
98 if (phy_id < 4)
99 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &reg);
100 else
101 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &reg);
102
103 } else
104 reg = mr32(MVS_PHY_CTL);
105
106 tmp = reg;
107 if (phy_id < 4)
108 tmp |= (1U << phy_id) << PCTL_LINK_OFFS;
109 else
110 tmp |= (1U << (phy_id - 4)) << PCTL_LINK_OFFS;
111
112 if (!(mvi->flags & MVF_FLAG_SOC)) {
113 if (phy_id < 4) {
114 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
115 mdelay(10);
116 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg);
117 } else {
118 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
119 mdelay(10);
120 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, reg);
121 }
122 } else {
123 mw32(MVS_PHY_CTL, tmp);
124 mdelay(10);
125 mw32(MVS_PHY_CTL, reg);
126 }
127 }
128
129 static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
130 {
131 u32 tmp;
132 tmp = mvs_read_port_irq_stat(mvi, phy_id);
133 tmp &= ~PHYEV_RDY_CH;
134 mvs_write_port_irq_stat(mvi, phy_id, tmp);
135 tmp = mvs_read_phy_ctl(mvi, phy_id);
136 if (hard == 1)
137 tmp |= PHY_RST_HARD;
138 else if (hard == 0)
139 tmp |= PHY_RST;
140 mvs_write_phy_ctl(mvi, phy_id, tmp);
141 if (hard) {
142 do {
143 tmp = mvs_read_phy_ctl(mvi, phy_id);
144 } while (tmp & PHY_RST_HARD);
145 }
146 }
147
148 void mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all)
149 {
150 void __iomem *regs = mvi->regs;
151 u32 tmp;
152 if (clear_all) {
153 tmp = mr32(MVS_INT_STAT_SRS_0);
154 if (tmp) {
155 printk(KERN_DEBUG "check SRS 0 %08X.\n", tmp);
156 mw32(MVS_INT_STAT_SRS_0, tmp);
157 }
158 } else {
159 tmp = mr32(MVS_INT_STAT_SRS_0);
160 if (tmp & (1 << (reg_set % 32))) {
161 printk(KERN_DEBUG "register set 0x%x was stopped.\n",
162 reg_set);
163 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));
164 }
165 }
166 }
167
168 static int __devinit mvs_64xx_chip_reset(struct mvs_info *mvi)
169 {
170 void __iomem *regs = mvi->regs;
171 u32 tmp;
172 int i;
173
174 /* make sure interrupts are masked immediately (paranoia) */
175 mw32(MVS_GBL_CTL, 0);
176 tmp = mr32(MVS_GBL_CTL);
177
178 /* Reset Controller */
179 if (!(tmp & HBA_RST)) {
180 if (mvi->flags & MVF_PHY_PWR_FIX) {
181 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
182 tmp &= ~PCTL_PWR_OFF;
183 tmp |= PCTL_PHY_DSBL;
184 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
185
186 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
187 tmp &= ~PCTL_PWR_OFF;
188 tmp |= PCTL_PHY_DSBL;
189 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
190 }
191 }
192
193 /* make sure interrupts are masked immediately (paranoia) */
194 mw32(MVS_GBL_CTL, 0);
195 tmp = mr32(MVS_GBL_CTL);
196
197 /* Reset Controller */
198 if (!(tmp & HBA_RST)) {
199 /* global reset, incl. COMRESET/H_RESET_N (self-clearing) */
200 mw32_f(MVS_GBL_CTL, HBA_RST);
201 }
202
203 /* wait for reset to finish; timeout is just a guess */
204 i = 1000;
205 while (i-- > 0) {
206 msleep(10);
207
208 if (!(mr32(MVS_GBL_CTL) & HBA_RST))
209 break;
210 }
211 if (mr32(MVS_GBL_CTL) & HBA_RST) {
212 dev_printk(KERN_ERR, mvi->dev, "HBA reset failed\n");
213 return -EBUSY;
214 }
215 return 0;
216 }
217
218 static void mvs_64xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
219 {
220 void __iomem *regs = mvi->regs;
221 u32 tmp;
222 if (!(mvi->flags & MVF_FLAG_SOC)) {
223 u32 offs;
224 if (phy_id < 4)
225 offs = PCR_PHY_CTL;
226 else {
227 offs = PCR_PHY_CTL2;
228 phy_id -= 4;
229 }
230 pci_read_config_dword(mvi->pdev, offs, &tmp);
231 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id);
232 pci_write_config_dword(mvi->pdev, offs, tmp);
233 } else {
234 tmp = mr32(MVS_PHY_CTL);
235 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id);
236 mw32(MVS_PHY_CTL, tmp);
237 }
238 }
239
240 static void mvs_64xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
241 {
242 void __iomem *regs = mvi->regs;
243 u32 tmp;
244 if (!(mvi->flags & MVF_FLAG_SOC)) {
245 u32 offs;
246 if (phy_id < 4)
247 offs = PCR_PHY_CTL;
248 else {
249 offs = PCR_PHY_CTL2;
250 phy_id -= 4;
251 }
252 pci_read_config_dword(mvi->pdev, offs, &tmp);
253 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id));
254 pci_write_config_dword(mvi->pdev, offs, tmp);
255 } else {
256 tmp = mr32(MVS_PHY_CTL);
257 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id));
258 mw32(MVS_PHY_CTL, tmp);
259 }
260 }
261
262 static int __devinit mvs_64xx_init(struct mvs_info *mvi)
263 {
264 void __iomem *regs = mvi->regs;
265 int i;
266 u32 tmp, cctl;
267
268 if (mvi->pdev && mvi->pdev->revision == 0)
269 mvi->flags |= MVF_PHY_PWR_FIX;
270 if (!(mvi->flags & MVF_FLAG_SOC)) {
271 mvs_show_pcie_usage(mvi);
272 tmp = mvs_64xx_chip_reset(mvi);
273 if (tmp)
274 return tmp;
275 } else {
276 tmp = mr32(MVS_PHY_CTL);
277 tmp &= ~PCTL_PWR_OFF;
278 tmp |= PCTL_PHY_DSBL;
279 mw32(MVS_PHY_CTL, tmp);
280 }
281
282 /* Init Chip */
283 /* make sure RST is set; HBA_RST /should/ have done that for us */
284 cctl = mr32(MVS_CTL) & 0xFFFF;
285 if (cctl & CCTL_RST)
286 cctl &= ~CCTL_RST;
287 else
288 mw32_f(MVS_CTL, cctl | CCTL_RST);
289
290 if (!(mvi->flags & MVF_FLAG_SOC)) {
291 /* write to device control _AND_ device status register */
292 pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp);
293 tmp &= ~PRD_REQ_MASK;
294 tmp |= PRD_REQ_SIZE;
295 pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp);
296
297 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
298 tmp &= ~PCTL_PWR_OFF;
299 tmp &= ~PCTL_PHY_DSBL;
300 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
301
302 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
303 tmp &= PCTL_PWR_OFF;
304 tmp &= ~PCTL_PHY_DSBL;
305 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
306 } else {
307 tmp = mr32(MVS_PHY_CTL);
308 tmp &= ~PCTL_PWR_OFF;
309 tmp |= PCTL_COM_ON;
310 tmp &= ~PCTL_PHY_DSBL;
311 tmp |= PCTL_LINK_RST;
312 mw32(MVS_PHY_CTL, tmp);
313 msleep(100);
314 tmp &= ~PCTL_LINK_RST;
315 mw32(MVS_PHY_CTL, tmp);
316 msleep(100);
317 }
318
319 /* reset control */
320 mw32(MVS_PCS, 0); /* MVS_PCS */
321 /* init phys */
322 mvs_64xx_phy_hacks(mvi);
323
324 /* enable auto port detection */
325 mw32(MVS_GBL_PORT_TYPE, MODE_AUTO_DET_EN);
326
327 mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
328 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
329
330 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
331 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
332
333 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);
334 mw32(MVS_TX_LO, mvi->tx_dma);
335 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
336
337 mw32(MVS_RX_CFG, MVS_RX_RING_SZ);
338 mw32(MVS_RX_LO, mvi->rx_dma);
339 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
340
341 for (i = 0; i < mvi->chip->n_phy; i++) {
342 /* set phy local SAS address */
343 /* should set little endian SAS address to 64xx chip */
344 mvs_set_sas_addr(mvi, i, PHYR_ADDR_LO, PHYR_ADDR_HI,
345 cpu_to_be64(mvi->phy[i].dev_sas_addr));
346
347 mvs_64xx_enable_xmt(mvi, i);
348
349 mvs_64xx_phy_reset(mvi, i, 1);
350 msleep(500);
351 mvs_64xx_detect_porttype(mvi, i);
352 }
353 if (mvi->flags & MVF_FLAG_SOC) {
354 /* set select registers */
355 writel(0x0E008000, regs + 0x000);
356 writel(0x59000008, regs + 0x004);
357 writel(0x20, regs + 0x008);
358 writel(0x20, regs + 0x00c);
359 writel(0x20, regs + 0x010);
360 writel(0x20, regs + 0x014);
361 writel(0x20, regs + 0x018);
362 writel(0x20, regs + 0x01c);
363 }
364 for (i = 0; i < mvi->chip->n_phy; i++) {
365 /* clear phy int status */
366 tmp = mvs_read_port_irq_stat(mvi, i);
367 tmp &= ~PHYEV_SIG_FIS;
368 mvs_write_port_irq_stat(mvi, i, tmp);
369
370 /* set phy int mask */
371 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS |
372 PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR |
373 PHYEV_DEC_ERR;
374 mvs_write_port_irq_mask(mvi, i, tmp);
375
376 msleep(100);
377 mvs_update_phyinfo(mvi, i, 1);
378 }
379
380 /* FIXME: update wide port bitmaps */
381
382 /* little endian for open address and command table, etc. */
383 /*
384 * it seems that ( from the spec ) turning on big-endian won't
385 * do us any good on big-endian machines, need further confirmation
386 */
387 cctl = mr32(MVS_CTL);
388 cctl |= CCTL_ENDIAN_CMD;
389 cctl |= CCTL_ENDIAN_DATA;
390 cctl &= ~CCTL_ENDIAN_OPEN;
391 cctl |= CCTL_ENDIAN_RSP;
392 mw32_f(MVS_CTL, cctl);
393
394 /* reset CMD queue */
395 tmp = mr32(MVS_PCS);
396 tmp |= PCS_CMD_RST;
397 mw32(MVS_PCS, tmp);
398 /* interrupt coalescing may cause missing HW interrput in some case,
399 * and the max count is 0x1ff, while our max slot is 0x200,
400 * it will make count 0.
401 */
402 tmp = 0;
403 mw32(MVS_INT_COAL, tmp);
404
405 tmp = 0x100;
406 mw32(MVS_INT_COAL_TMOUT, tmp);
407
408 /* ladies and gentlemen, start your engines */
409 mw32(MVS_TX_CFG, 0);
410 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
411 mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);
412 /* enable CMD/CMPL_Q/RESP mode */
413 mw32(MVS_PCS, PCS_SATA_RETRY | PCS_FIS_RX_EN |
414 PCS_CMD_EN | PCS_CMD_STOP_ERR);
415
416 /* enable completion queue interrupt */
417 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP |
418 CINT_DMA_PCIE);
419
420 mw32(MVS_INT_MASK, tmp);
421
422 /* Enable SRS interrupt */
423 mw32(MVS_INT_MASK_SRS_0, 0xFFFF);
424
425 return 0;
426 }
427
428 static int mvs_64xx_ioremap(struct mvs_info *mvi)
429 {
430 if (!mvs_ioremap(mvi, 4, 2))
431 return 0;
432 return -1;
433 }
434
435 static void mvs_64xx_iounmap(struct mvs_info *mvi)
436 {
437 mvs_iounmap(mvi->regs);
438 mvs_iounmap(mvi->regs_ex);
439 }
440
441 static void mvs_64xx_interrupt_enable(struct mvs_info *mvi)
442 {
443 void __iomem *regs = mvi->regs;
444 u32 tmp;
445
446 tmp = mr32(MVS_GBL_CTL);
447 mw32(MVS_GBL_CTL, tmp | INT_EN);
448 }
449
450 static void mvs_64xx_interrupt_disable(struct mvs_info *mvi)
451 {
452 void __iomem *regs = mvi->regs;
453 u32 tmp;
454
455 tmp = mr32(MVS_GBL_CTL);
456 mw32(MVS_GBL_CTL, tmp & ~INT_EN);
457 }
458
459 static u32 mvs_64xx_isr_status(struct mvs_info *mvi, int irq)
460 {
461 void __iomem *regs = mvi->regs;
462 u32 stat;
463
464 if (!(mvi->flags & MVF_FLAG_SOC)) {
465 stat = mr32(MVS_GBL_INT_STAT);
466
467 if (stat == 0 || stat == 0xffffffff)
468 return 0;
469 } else
470 stat = 1;
471 return stat;
472 }
473
474 static irqreturn_t mvs_64xx_isr(struct mvs_info *mvi, int irq, u32 stat)
475 {
476 void __iomem *regs = mvi->regs;
477
478 /* clear CMD_CMPLT ASAP */
479 mw32_f(MVS_INT_STAT, CINT_DONE);
480 #ifndef MVS_USE_TASKLET
481 spin_lock(&mvi->lock);
482 #endif
483 mvs_int_full(mvi);
484 #ifndef MVS_USE_TASKLET
485 spin_unlock(&mvi->lock);
486 #endif
487 return IRQ_HANDLED;
488 }
489
490 static void mvs_64xx_command_active(struct mvs_info *mvi, u32 slot_idx)
491 {
492 u32 tmp;
493 mvs_cw32(mvi, 0x40 + (slot_idx >> 3), 1 << (slot_idx % 32));
494 mvs_cw32(mvi, 0x00 + (slot_idx >> 3), 1 << (slot_idx % 32));
495 do {
496 tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3));
497 } while (tmp & 1 << (slot_idx % 32));
498 do {
499 tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3));
500 } while (tmp & 1 << (slot_idx % 32));
501 }
502
503 static void mvs_64xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
504 u32 tfs)
505 {
506 void __iomem *regs = mvi->regs;
507 u32 tmp;
508
509 if (type == PORT_TYPE_SATA) {
510 tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);
511 mw32(MVS_INT_STAT_SRS_0, tmp);
512 }
513 mw32(MVS_INT_STAT, CINT_CI_STOP);
514 tmp = mr32(MVS_PCS) | 0xFF00;
515 mw32(MVS_PCS, tmp);
516 }
517
518 static void mvs_64xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
519 {
520 void __iomem *regs = mvi->regs;
521 u32 tmp, offs;
522
523 if (*tfs == MVS_ID_NOT_MAPPED)
524 return;
525
526 offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT);
527 if (*tfs < 16) {
528 tmp = mr32(MVS_PCS);
529 mw32(MVS_PCS, tmp & ~offs);
530 } else {
531 tmp = mr32(MVS_CTL);
532 mw32(MVS_CTL, tmp & ~offs);
533 }
534
535 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs);
536 if (tmp)
537 mw32(MVS_INT_STAT_SRS_0, tmp);
538
539 *tfs = MVS_ID_NOT_MAPPED;
540 return;
541 }
542
543 static u8 mvs_64xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
544 {
545 int i;
546 u32 tmp, offs;
547 void __iomem *regs = mvi->regs;
548
549 if (*tfs != MVS_ID_NOT_MAPPED)
550 return 0;
551
552 tmp = mr32(MVS_PCS);
553
554 for (i = 0; i < mvi->chip->srs_sz; i++) {
555 if (i == 16)
556 tmp = mr32(MVS_CTL);
557 offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT);
558 if (!(tmp & offs)) {
559 *tfs = i;
560
561 if (i < 16)
562 mw32(MVS_PCS, tmp | offs);
563 else
564 mw32(MVS_CTL, tmp | offs);
565 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i);
566 if (tmp)
567 mw32(MVS_INT_STAT_SRS_0, tmp);
568 return 0;
569 }
570 }
571 return MVS_ID_NOT_MAPPED;
572 }
573
574 void mvs_64xx_make_prd(struct scatterlist *scatter, int nr, void *prd)
575 {
576 int i;
577 struct scatterlist *sg;
578 struct mvs_prd *buf_prd = prd;
579 for_each_sg(scatter, sg, nr, i) {
580 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
581 buf_prd->len = cpu_to_le32(sg_dma_len(sg));
582 buf_prd++;
583 }
584 }
585
586 static int mvs_64xx_oob_done(struct mvs_info *mvi, int i)
587 {
588 u32 phy_st;
589 mvs_write_port_cfg_addr(mvi, i,
590 PHYR_PHY_STAT);
591 phy_st = mvs_read_port_cfg_data(mvi, i);
592 if (phy_st & PHY_OOB_DTCTD)
593 return 1;
594 return 0;
595 }
596
597 static void mvs_64xx_fix_phy_info(struct mvs_info *mvi, int i,
598 struct sas_identify_frame *id)
599
600 {
601 struct mvs_phy *phy = &mvi->phy[i];
602 struct asd_sas_phy *sas_phy = &phy->sas_phy;
603
604 sas_phy->linkrate =
605 (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
606 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET;
607
608 phy->minimum_linkrate =
609 (phy->phy_status &
610 PHY_MIN_SPP_PHYS_LINK_RATE_MASK) >> 8;
611 phy->maximum_linkrate =
612 (phy->phy_status &
613 PHY_MAX_SPP_PHYS_LINK_RATE_MASK) >> 12;
614
615 mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY);
616 phy->dev_info = mvs_read_port_cfg_data(mvi, i);
617
618 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO);
619 phy->att_dev_info = mvs_read_port_cfg_data(mvi, i);
620
621 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI);
622 phy->att_dev_sas_addr =
623 (u64) mvs_read_port_cfg_data(mvi, i) << 32;
624 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO);
625 phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i);
626 phy->att_dev_sas_addr = SAS_ADDR(&phy->att_dev_sas_addr);
627 }
628
629 static void mvs_64xx_phy_work_around(struct mvs_info *mvi, int i)
630 {
631 u32 tmp;
632 struct mvs_phy *phy = &mvi->phy[i];
633 /* workaround for HW phy decoding error on 1.5g disk drive */
634 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6);
635 tmp = mvs_read_port_vsr_data(mvi, i);
636 if (((phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
637 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET) ==
638 SAS_LINK_RATE_1_5_GBPS)
639 tmp &= ~PHY_MODE6_LATECLK;
640 else
641 tmp |= PHY_MODE6_LATECLK;
642 mvs_write_port_vsr_data(mvi, i, tmp);
643 }
644
645 void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
646 struct sas_phy_linkrates *rates)
647 {
648 u32 lrmin = 0, lrmax = 0;
649 u32 tmp;
650
651 tmp = mvs_read_phy_ctl(mvi, phy_id);
652 lrmin = (rates->minimum_linkrate << 8);
653 lrmax = (rates->maximum_linkrate << 12);
654
655 if (lrmin) {
656 tmp &= ~(0xf << 8);
657 tmp |= lrmin;
658 }
659 if (lrmax) {
660 tmp &= ~(0xf << 12);
661 tmp |= lrmax;
662 }
663 mvs_write_phy_ctl(mvi, phy_id, tmp);
664 mvs_64xx_phy_reset(mvi, phy_id, 1);
665 }
666
667 static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi)
668 {
669 u32 tmp;
670 void __iomem *regs = mvi->regs;
671 tmp = mr32(MVS_PCS);
672 mw32(MVS_PCS, tmp & 0xFFFF);
673 mw32(MVS_PCS, tmp);
674 tmp = mr32(MVS_CTL);
675 mw32(MVS_CTL, tmp & 0xFFFF);
676 mw32(MVS_CTL, tmp);
677 }
678
679
680 u32 mvs_64xx_spi_read_data(struct mvs_info *mvi)
681 {
682 void __iomem *regs = mvi->regs_ex;
683 return ior32(SPI_DATA_REG_64XX);
684 }
685
686 void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data)
687 {
688 void __iomem *regs = mvi->regs_ex;
689 iow32(SPI_DATA_REG_64XX, data);
690 }
691
692
693 int mvs_64xx_spi_buildcmd(struct mvs_info *mvi,
694 u32 *dwCmd,
695 u8 cmd,
696 u8 read,
697 u8 length,
698 u32 addr
699 )
700 {
701 u32 dwTmp;
702
703 dwTmp = ((u32)cmd << 24) | ((u32)length << 19);
704 if (read)
705 dwTmp |= 1U<<23;
706
707 if (addr != MV_MAX_U32) {
708 dwTmp |= 1U<<22;
709 dwTmp |= (addr & 0x0003FFFF);
710 }
711
712 *dwCmd = dwTmp;
713 return 0;
714 }
715
716
717 int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
718 {
719 void __iomem *regs = mvi->regs_ex;
720 int retry;
721
722 for (retry = 0; retry < 1; retry++) {
723 iow32(SPI_CTRL_REG_64XX, SPI_CTRL_VENDOR_ENABLE);
724 iow32(SPI_CMD_REG_64XX, cmd);
725 iow32(SPI_CTRL_REG_64XX,
726 SPI_CTRL_VENDOR_ENABLE | SPI_CTRL_SPISTART);
727 }
728
729 return 0;
730 }
731
732 int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
733 {
734 void __iomem *regs = mvi->regs_ex;
735 u32 i, dwTmp;
736
737 for (i = 0; i < timeout; i++) {
738 dwTmp = ior32(SPI_CTRL_REG_64XX);
739 if (!(dwTmp & SPI_CTRL_SPISTART))
740 return 0;
741 msleep(10);
742 }
743
744 return -1;
745 }
746
747 #ifndef DISABLE_HOTPLUG_DMA_FIX
748 void mvs_64xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from, void *prd)
749 {
750 int i;
751 struct mvs_prd *buf_prd = prd;
752 buf_prd += from;
753 for (i = 0; i < MAX_SG_ENTRY - from; i++) {
754 buf_prd->addr = cpu_to_le64(buf_dma);
755 buf_prd->len = cpu_to_le32(buf_len);
756 ++buf_prd;
757 }
758 }
759 #endif
760
761 const struct mvs_dispatch mvs_64xx_dispatch = {
762 "mv64xx",
763 mvs_64xx_init,
764 NULL,
765 mvs_64xx_ioremap,
766 mvs_64xx_iounmap,
767 mvs_64xx_isr,
768 mvs_64xx_isr_status,
769 mvs_64xx_interrupt_enable,
770 mvs_64xx_interrupt_disable,
771 mvs_read_phy_ctl,
772 mvs_write_phy_ctl,
773 mvs_read_port_cfg_data,
774 mvs_write_port_cfg_data,
775 mvs_write_port_cfg_addr,
776 mvs_read_port_vsr_data,
777 mvs_write_port_vsr_data,
778 mvs_write_port_vsr_addr,
779 mvs_read_port_irq_stat,
780 mvs_write_port_irq_stat,
781 mvs_read_port_irq_mask,
782 mvs_write_port_irq_mask,
783 mvs_get_sas_addr,
784 mvs_64xx_command_active,
785 mvs_64xx_clear_srs_irq,
786 mvs_64xx_issue_stop,
787 mvs_start_delivery,
788 mvs_rx_update,
789 mvs_int_full,
790 mvs_64xx_assign_reg_set,
791 mvs_64xx_free_reg_set,
792 mvs_get_prd_size,
793 mvs_get_prd_count,
794 mvs_64xx_make_prd,
795 mvs_64xx_detect_porttype,
796 mvs_64xx_oob_done,
797 mvs_64xx_fix_phy_info,
798 mvs_64xx_phy_work_around,
799 mvs_64xx_phy_set_link_rate,
800 mvs_hw_max_link_rate,
801 mvs_64xx_phy_disable,
802 mvs_64xx_phy_enable,
803 mvs_64xx_phy_reset,
804 mvs_64xx_stp_reset,
805 mvs_64xx_clear_active_cmds,
806 mvs_64xx_spi_read_data,
807 mvs_64xx_spi_write_data,
808 mvs_64xx_spi_buildcmd,
809 mvs_64xx_spi_issuecmd,
810 mvs_64xx_spi_waitdataready,
811 #ifndef DISABLE_HOTPLUG_DMA_FIX
812 mvs_64xx_fix_dma,
813 #endif
814 };
815
Linux with added FPC-III support