| blob | 7939bca47861202a19c2f43231ae603d5340f852 |
1 NVIDIA Tegra PCIe controller
3 Required properties:
4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
11 contain BPMP phandle and PCIe power partition ID. This is required only
12 for Tegra186.
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
16 - reg-names: Must include the following entries:
17 "pads": PADS registers
18 "afi": AFI registers
19 "cs": configuration space region
20 - interrupts: A list of interrupt outputs of the controller. Must contain an
21 entry for each entry in the interrupt-names property.
22 - interrupt-names: Must include the following entries:
23 "intr": The Tegra interrupt that is asserted for controller interrupts
24 "msi": The Tegra interrupt that is asserted when an MSI is received
25 - bus-range: Range of bus numbers associated with this controller
26 - #address-cells: Address representation for root ports (must be 3)
27 - cell 0 specifies the bus and device numbers of the root port:
28 [23:16]: bus number
29 [15:11]: device number
30 - cell 1 denotes the upper 32 address bits and should be 0
31 - cell 2 contains the lower 32 address bits and is used to translate to the
32 CPU address space
33 - #size-cells: Size representation for root ports (must be 2)
34 - ranges: Describes the translation of addresses for root ports and standard
35 PCI regions. The entries must be 6 cells each, where the first three cells
36 correspond to the address as described for the #address-cells property
37 above, the fourth cell is the physical CPU address to translate to and the
38 fifth and six cells are as described for the #size-cells property above.
39 - The first two entries are expected to translate the addresses for the root
40 port registers, which are referenced by the assigned-addresses property of
41 the root port nodes (see below).
42 - The remaining entries setup the mapping for the standard I/O, memory and
43 prefetchable PCI regions. The first cell determines the type of region
44 that is setup:
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
48 Please refer to the standard PCI bus binding document for a more detailed
49 explanation.
50 - #interrupt-cells: Size representation for interrupts (must be 1)
51 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
52 Please refer to the standard PCI bus binding document for a more detailed
53 explanation.
54 - clocks: Must contain an entry for each entry in clock-names.
55 See ../clocks/clock-bindings.txt for details.
56 - clock-names: Must include the following entries:
57 - pex
58 - afi
59 - pll_e
60 - cml (not required for Tegra20)
61 - resets: Must contain an entry for each entry in reset-names.
62 See ../reset/reset.txt for details.
63 - reset-names: Must include the following entries:
64 - pex
65 - afi
66 - pcie_x
68 Optional properties:
69 - pinctrl-names: A list of pinctrl state names. Must contain the following
70 entries:
71 - "default": active state, puts PCIe I/O out of deep power down state
72 - "idle": puts PCIe I/O into deep power down state
73 - pinctrl-0: phandle for the default/active state of pin configurations.
74 - pinctrl-1: phandle for the idle state of pin configurations.
76 Required properties on Tegra124 and later (deprecated):
77 - phys: Must contain an entry for each entry in phy-names.
78 - phy-names: Must include the following entries:
79 - pcie
81 These properties are deprecated in favour of per-lane PHYs define in each of
82 the root ports (see below).
84 Power supplies for Tegra20:
85 - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
86 - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
87 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
88 supply 1.05 V.
89 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
90 supply 1.05 V.
91 - vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
93 Power supplies for Tegra30:
94 - Required:
95 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
96 supply 1.05 V.
97 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
98 supply 1.05 V.
99 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
100 supply 1.8 V.
101 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
102 Must supply 3.3 V.
103 - Optional:
104 - If lanes 0 to 3 are used:
105 - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
106 - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
107 - If lanes 4 or 5 are used:
108 - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
109 - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
111 Power supplies for Tegra124:
112 - Required:
113 - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
114 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
115 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
116 supply 1.05 V.
117 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
118 Must supply 3.3 V.
119 - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
120 Must supply 3.3 V.
121 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
122 supply 2.8-3.3 V.
123 - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
124 supply 1.05 V.
126 Power supplies for Tegra210:
127 - Required:
128 - avdd-pll-uerefe-supply: Power supply for PLLE (shared with USB3). Must
129 supply 1.05 V.
130 - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output
131 clocks. Must supply 1.8 V.
132 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
133 - dvdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
134 supply 1.05 V.
135 - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
136 Must supply 3.3 V.
137 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
138 supply 1.8 V.
140 Power supplies for Tegra186:
141 - Required:
142 - dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
143 - hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must
144 supply 1.8 V.
145 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
146 Must supply 1.8 V.
147 - vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must
148 supply 1.8 V.
150 Root ports are defined as subnodes of the PCIe controller node.
152 Required properties:
153 - device_type: Must be "pci"
154 - assigned-addresses: Address and size of the port configuration registers
155 - reg: PCI bus address of the root port
156 - #address-cells: Must be 3
157 - #size-cells: Must be 2
158 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
159 property is sufficient.
160 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
161 are:
162 - Root port 0 uses 4 lanes, root port 1 is unused.
163 - Both root ports use 2 lanes.
165 Required properties for Tegra124 and later:
166 - phys: Must contain an phandle to a PHY for each entry in phy-names.
167 - phy-names: Must include an entry for each active lane. Note that the number
168 of entries does not have to (though usually will) be equal to the specified
169 number of lanes in the nvidia,num-lanes property. Entries are of the form
170 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
172 Examples:
173 =========
175 Tegra20:
176 --------
178 SoC DTSI:
180 pcie-controller@80003000 {
181 compatible = "nvidia,tegra20-pcie";
182 device_type = "pci";
183 reg = <0x80003000 0x00000800 /* PADS registers */
184 0x80003800 0x00000200 /* AFI registers */
185 0x90000000 0x10000000>; /* configuration space */
186 reg-names = "pads", "afi", "cs";
187 interrupts = <0 98 0x04 /* controller interrupt */
188 0 99 0x04>; /* MSI interrupt */
189 interrupt-names = "intr", "msi";
191 #interrupt-cells = <1>;
192 interrupt-map-mask = <0 0 0 0>;
193 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
195 bus-range = <0x00 0xff>;
196 #address-cells = <3>;
197 #size-cells = <2>;
199 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
200 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
201 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
202 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
203 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
205 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
206 clock-names = "pex", "afi", "pll_e";
207 resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
208 reset-names = "pex", "afi", "pcie_x";
209 status = "disabled";
211 pci@1,0 {
212 device_type = "pci";
213 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
214 reg = <0x000800 0 0 0 0>;
215 status = "disabled";
217 #address-cells = <3>;
218 #size-cells = <2>;
220 ranges;
222 nvidia,num-lanes = <2>;
223 };
225 pci@2,0 {
226 device_type = "pci";
227 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
228 reg = <0x001000 0 0 0 0>;
229 status = "disabled";
231 #address-cells = <3>;
232 #size-cells = <2>;
234 ranges;
236 nvidia,num-lanes = <2>;
237 };
238 };
240 Board DTS:
242 pcie-controller@80003000 {
243 status = "okay";
245 vdd-supply = <&pci_vdd_reg>;
246 pex-clk-supply = <&pci_clk_reg>;
248 /* root port 00:01.0 */
249 pci@1,0 {
250 status = "okay";
252 /* bridge 01:00.0 (optional) */
253 pci@0,0 {
254 reg = <0x010000 0 0 0 0>;
256 #address-cells = <3>;
257 #size-cells = <2>;
259 device_type = "pci";
261 /* endpoint 02:00.0 */
262 pci@0,0 {
263 reg = <0x020000 0 0 0 0>;
264 };
265 };
266 };
267 };
269 Note that devices on the PCI bus are dynamically discovered using PCI's bus
270 enumeration and therefore don't need corresponding device nodes in DT. However
271 if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
272 device nodes need to be added in order to allow the bus' children to be
273 instantiated at the proper location in the operating system's device tree (as
274 illustrated by the optional nodes in the example above).
276 Tegra30:
277 --------
279 SoC DTSI:
281 pcie-controller@3000 {
282 compatible = "nvidia,tegra30-pcie";
283 device_type = "pci";
284 reg = <0x00003000 0x00000800 /* PADS registers */
285 0x00003800 0x00000200 /* AFI registers */
286 0x10000000 0x10000000>; /* configuration space */
287 reg-names = "pads", "afi", "cs";
288 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
289 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
290 interrupt-names = "intr", "msi";
292 #interrupt-cells = <1>;
293 interrupt-map-mask = <0 0 0 0>;
294 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
296 bus-range = <0x00 0xff>;
297 #address-cells = <3>;
298 #size-cells = <2>;
300 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
301 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
302 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
303 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
304 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
305 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
307 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
308 <&tegra_car TEGRA30_CLK_AFI>,
309 <&tegra_car TEGRA30_CLK_PLL_E>,
310 <&tegra_car TEGRA30_CLK_CML0>;
311 clock-names = "pex", "afi", "pll_e", "cml";
312 resets = <&tegra_car 70>,
313 <&tegra_car 72>,
314 <&tegra_car 74>;
315 reset-names = "pex", "afi", "pcie_x";
316 status = "disabled";
318 pci@1,0 {
319 device_type = "pci";
320 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
321 reg = <0x000800 0 0 0 0>;
322 status = "disabled";
324 #address-cells = <3>;
325 #size-cells = <2>;
326 ranges;
328 nvidia,num-lanes = <2>;
329 };
331 pci@2,0 {
332 device_type = "pci";
333 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
334 reg = <0x001000 0 0 0 0>;
335 status = "disabled";
337 #address-cells = <3>;
338 #size-cells = <2>;
339 ranges;
341 nvidia,num-lanes = <2>;
342 };
344 pci@3,0 {
345 device_type = "pci";
346 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
347 reg = <0x001800 0 0 0 0>;
348 status = "disabled";
350 #address-cells = <3>;
351 #size-cells = <2>;
352 ranges;
354 nvidia,num-lanes = <2>;
355 };
356 };
358 Board DTS:
360 pcie-controller@3000 {
361 status = "okay";
363 avdd-pexa-supply = <&ldo1_reg>;
364 vdd-pexa-supply = <&ldo1_reg>;
365 avdd-pexb-supply = <&ldo1_reg>;
366 vdd-pexb-supply = <&ldo1_reg>;
367 avdd-pex-pll-supply = <&ldo1_reg>;
368 avdd-plle-supply = <&ldo1_reg>;
369 vddio-pex-ctl-supply = <&sys_3v3_reg>;
370 hvdd-pex-supply = <&sys_3v3_pexs_reg>;
372 pci@1,0 {
373 status = "okay";
374 };
376 pci@3,0 {
377 status = "okay";
378 };
379 };
381 Tegra124:
382 ---------
384 SoC DTSI:
386 pcie-controller@1003000 {
387 compatible = "nvidia,tegra124-pcie";
388 device_type = "pci";
389 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
390 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
391 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
392 reg-names = "pads", "afi", "cs";
393 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
394 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
395 interrupt-names = "intr", "msi";
397 #interrupt-cells = <1>;
398 interrupt-map-mask = <0 0 0 0>;
399 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
401 bus-range = <0x00 0xff>;
402 #address-cells = <3>;
403 #size-cells = <2>;
405 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
406 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
407 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
408 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
409 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
411 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
412 <&tegra_car TEGRA124_CLK_AFI>,
413 <&tegra_car TEGRA124_CLK_PLL_E>,
414 <&tegra_car TEGRA124_CLK_CML0>;
415 clock-names = "pex", "afi", "pll_e", "cml";
416 resets = <&tegra_car 70>,
417 <&tegra_car 72>,
418 <&tegra_car 74>;
419 reset-names = "pex", "afi", "pcie_x";
420 status = "disabled";
422 pci@1,0 {
423 device_type = "pci";
424 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
425 reg = <0x000800 0 0 0 0>;
426 status = "disabled";
428 #address-cells = <3>;
429 #size-cells = <2>;
430 ranges;
432 nvidia,num-lanes = <2>;
433 };
435 pci@2,0 {
436 device_type = "pci";
437 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
438 reg = <0x001000 0 0 0 0>;
439 status = "disabled";
441 #address-cells = <3>;
442 #size-cells = <2>;
443 ranges;
445 nvidia,num-lanes = <1>;
446 };
447 };
449 Board DTS:
451 pcie-controller@1003000 {
452 status = "okay";
454 avddio-pex-supply = <&vdd_1v05_run>;
455 dvddio-pex-supply = <&vdd_1v05_run>;
456 avdd-pex-pll-supply = <&vdd_1v05_run>;
457 hvdd-pex-supply = <&vdd_3v3_lp0>;
458 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
459 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
460 avdd-pll-erefe-supply = <&avdd_1v05_run>;
462 /* Mini PCIe */
463 pci@1,0 {
464 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
465 phy-names = "pcie-0";
466 status = "okay";
467 };
469 /* Gigabit Ethernet */
470 pci@2,0 {
471 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
472 phy-names = "pcie-0";
473 status = "okay";
474 };
475 };
477 Tegra210:
478 ---------
480 SoC DTSI:
482 pcie-controller@1003000 {
483 compatible = "nvidia,tegra210-pcie";
484 device_type = "pci";
485 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
486 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
487 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
488 reg-names = "pads", "afi", "cs";
489 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
490 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
491 interrupt-names = "intr", "msi";
493 #interrupt-cells = <1>;
494 interrupt-map-mask = <0 0 0 0>;
495 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
497 bus-range = <0x00 0xff>;
498 #address-cells = <3>;
499 #size-cells = <2>;
501 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
502 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
503 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
504 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
505 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
507 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
508 <&tegra_car TEGRA210_CLK_AFI>,
509 <&tegra_car TEGRA210_CLK_PLL_E>,
510 <&tegra_car TEGRA210_CLK_CML0>;
511 clock-names = "pex", "afi", "pll_e", "cml";
512 resets = <&tegra_car 70>,
513 <&tegra_car 72>,
514 <&tegra_car 74>;
515 reset-names = "pex", "afi", "pcie_x";
516 status = "disabled";
518 pci@1,0 {
519 device_type = "pci";
520 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
521 reg = <0x000800 0 0 0 0>;
522 status = "disabled";
524 #address-cells = <3>;
525 #size-cells = <2>;
526 ranges;
528 nvidia,num-lanes = <4>;
529 };
531 pci@2,0 {
532 device_type = "pci";
533 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
534 reg = <0x001000 0 0 0 0>;
535 status = "disabled";
537 #address-cells = <3>;
538 #size-cells = <2>;
539 ranges;
541 nvidia,num-lanes = <1>;
542 };
543 };
545 Board DTS:
547 pcie-controller@1003000 {
548 status = "okay";
550 avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
551 hvddio-pex-supply = <&vdd_1v8>;
552 dvddio-pex-supply = <&vdd_pex_1v05>;
553 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
554 hvdd-pex-pll-e-supply = <&vdd_1v8>;
555 vddio-pex-ctl-supply = <&vdd_1v8>;
557 pci@1,0 {
558 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
559 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
560 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
561 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
562 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
563 status = "okay";
564 };
566 pci@2,0 {
567 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
568 phy-names = "pcie-0";
569 status = "okay";
570 };
571 };
573 Tegra186:
574 ---------
576 SoC DTSI:
578 pcie@10003000 {
579 compatible = "nvidia,tegra186-pcie";
580 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
581 device_type = "pci";
582 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
583 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
584 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
585 reg-names = "pads", "afi", "cs";
587 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
588 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
589 interrupt-names = "intr", "msi";
591 #interrupt-cells = <1>;
592 interrupt-map-mask = <0 0 0 0>;
593 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
595 bus-range = <0x00 0xff>;
596 #address-cells = <3>;
597 #size-cells = <2>;
599 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
600 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
601 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
602 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
603 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
604 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
606 clocks = <&bpmp TEGRA186_CLK_AFI>,
607 <&bpmp TEGRA186_CLK_PCIE>,
608 <&bpmp TEGRA186_CLK_PLLE>;
609 clock-names = "afi", "pex", "pll_e";
611 resets = <&bpmp TEGRA186_RESET_AFI>,
612 <&bpmp TEGRA186_RESET_PCIE>,
613 <&bpmp TEGRA186_RESET_PCIEXCLK>;
614 reset-names = "afi", "pex", "pcie_x";
616 status = "disabled";
618 pci@1,0 {
619 device_type = "pci";
620 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
621 reg = <0x000800 0 0 0 0>;
622 status = "disabled";
624 #address-cells = <3>;
625 #size-cells = <2>;
626 ranges;
628 nvidia,num-lanes = <2>;
629 };
631 pci@2,0 {
632 device_type = "pci";
633 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
634 reg = <0x001000 0 0 0 0>;
635 status = "disabled";
637 #address-cells = <3>;
638 #size-cells = <2>;
639 ranges;
641 nvidia,num-lanes = <1>;
642 };
644 pci@3,0 {
645 device_type = "pci";
646 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
647 reg = <0x001800 0 0 0 0>;
648 status = "disabled";
650 #address-cells = <3>;
651 #size-cells = <2>;
652 ranges;
654 nvidia,num-lanes = <1>;
655 };
656 };
658 Board DTS:
660 pcie@10003000 {
661 status = "okay";
663 dvdd-pex-supply = <&vdd_pex>;
664 hvdd-pex-pll-supply = <&vdd_1v8>;
665 hvdd-pex-supply = <&vdd_1v8>;
666 vddio-pexctl-aud-supply = <&vdd_1v8>;
668 pci@1,0 {
669 nvidia,num-lanes = <4>;
670 status = "okay";
671 };
673 pci@2,0 {
674 nvidia,num-lanes = <0>;
675 status = "disabled";
676 };
678 pci@3,0 {
679 nvidia,num-lanes = <1>;
680 status = "disabled";
681 };
682 };