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dm writecache: correct uncommitted_block when discarding uncommitted entry
[linux/fpc-iii.git] / drivers / gpio / gpio-dwapb.c
blobed6061b5cca14693c4bff9404e924e2b4ee40816
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2011 Jamie Iles
4 *
5 * All enquiries to support@picochip.com
6 */
7 #include <linux/acpi.h>
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/ioport.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22 #include <linux/platform_device.h>
23 #include <linux/property.h>
24 #include <linux/reset.h>
25 #include <linux/spinlock.h>
26 #include <linux/platform_data/gpio-dwapb.h>
27 #include <linux/slab.h>
28
29 #include "gpiolib.h"
30 #include "gpiolib-acpi.h"
31
32 #define GPIO_SWPORTA_DR 0x00
33 #define GPIO_SWPORTA_DDR 0x04
34 #define GPIO_SWPORTB_DR 0x0c
35 #define GPIO_SWPORTB_DDR 0x10
36 #define GPIO_SWPORTC_DR 0x18
37 #define GPIO_SWPORTC_DDR 0x1c
38 #define GPIO_SWPORTD_DR 0x24
39 #define GPIO_SWPORTD_DDR 0x28
40 #define GPIO_INTEN 0x30
41 #define GPIO_INTMASK 0x34
42 #define GPIO_INTTYPE_LEVEL 0x38
43 #define GPIO_INT_POLARITY 0x3c
44 #define GPIO_INTSTATUS 0x40
45 #define GPIO_PORTA_DEBOUNCE 0x48
46 #define GPIO_PORTA_EOI 0x4c
47 #define GPIO_EXT_PORTA 0x50
48 #define GPIO_EXT_PORTB 0x54
49 #define GPIO_EXT_PORTC 0x58
50 #define GPIO_EXT_PORTD 0x5c
51
52 #define DWAPB_DRIVER_NAME "gpio-dwapb"
53 #define DWAPB_MAX_PORTS 4
54
55 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
56 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
57 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
58
59 #define GPIO_REG_OFFSET_V2 1
60
61 #define GPIO_INTMASK_V2 0x44
62 #define GPIO_INTTYPE_LEVEL_V2 0x34
63 #define GPIO_INT_POLARITY_V2 0x38
64 #define GPIO_INTSTATUS_V2 0x3c
65 #define GPIO_PORTA_EOI_V2 0x40
66
67 struct dwapb_gpio;
68
69 #ifdef CONFIG_PM_SLEEP
70 /* Store GPIO context across system-wide suspend/resume transitions */
71 struct dwapb_context {
72 u32 data;
73 u32 dir;
74 u32 ext;
75 u32 int_en;
76 u32 int_mask;
77 u32 int_type;
78 u32 int_pol;
79 u32 int_deb;
80 u32 wake_en;
81 };
82 #endif
83
84 struct dwapb_gpio_port {
85 struct gpio_chip gc;
86 bool is_registered;
87 struct dwapb_gpio *gpio;
88 #ifdef CONFIG_PM_SLEEP
89 struct dwapb_context *ctx;
90 #endif
91 unsigned int idx;
92 };
93
94 struct dwapb_gpio {
95 struct device *dev;
96 void __iomem *regs;
97 struct dwapb_gpio_port *ports;
98 unsigned int nr_ports;
99 struct irq_domain *domain;
100 unsigned int flags;
101 struct reset_control *rst;
102 struct clk *clk;
103 };
104
105 static inline u32 gpio_reg_v2_convert(unsigned int offset)
106 {
107 switch (offset) {
108 case GPIO_INTMASK:
109 return GPIO_INTMASK_V2;
110 case GPIO_INTTYPE_LEVEL:
111 return GPIO_INTTYPE_LEVEL_V2;
112 case GPIO_INT_POLARITY:
113 return GPIO_INT_POLARITY_V2;
114 case GPIO_INTSTATUS:
115 return GPIO_INTSTATUS_V2;
116 case GPIO_PORTA_EOI:
117 return GPIO_PORTA_EOI_V2;
118 }
119
120 return offset;
121 }
122
123 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
124 {
125 if (gpio->flags & GPIO_REG_OFFSET_V2)
126 return gpio_reg_v2_convert(offset);
127
128 return offset;
129 }
130
131 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
132 {
133 struct gpio_chip *gc = &gpio->ports[0].gc;
134 void __iomem *reg_base = gpio->regs;
135
136 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
137 }
138
139 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
140 u32 val)
141 {
142 struct gpio_chip *gc = &gpio->ports[0].gc;
143 void __iomem *reg_base = gpio->regs;
144
145 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
146 }
147
148 static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
149 {
150 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
151 struct dwapb_gpio *gpio = port->gpio;
152
153 return irq_find_mapping(gpio->domain, offset);
154 }
155
156 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
157 {
158 struct dwapb_gpio_port *port;
159 int i;
160
161 for (i = 0; i < gpio->nr_ports; i++) {
162 port = &gpio->ports[i];
163 if (port->idx == offs / 32)
164 return port;
165 }
166
167 return NULL;
168 }
169
170 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
171 {
172 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
173 struct gpio_chip *gc;
174 u32 pol;
175 int val;
176
177 if (!port)
178 return;
179 gc = &port->gc;
180
181 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
182 /* Just read the current value right out of the data register */
183 val = gc->get(gc, offs % 32);
184 if (val)
185 pol &= ~BIT(offs);
186 else
187 pol |= BIT(offs);
188
189 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
190 }
191
192 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
193 {
194 u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
195 u32 ret = irq_status;
196
197 while (irq_status) {
198 int hwirq = fls(irq_status) - 1;
199 int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
200
201 generic_handle_irq(gpio_irq);
202 irq_status &= ~BIT(hwirq);
203
204 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
205 == IRQ_TYPE_EDGE_BOTH)
206 dwapb_toggle_trigger(gpio, hwirq);
207 }
208
209 return ret;
210 }
211
212 static void dwapb_irq_handler(struct irq_desc *desc)
213 {
214 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
215 struct irq_chip *chip = irq_desc_get_chip(desc);
216
217 dwapb_do_irq(gpio);
218
219 if (chip->irq_eoi)
220 chip->irq_eoi(irq_desc_get_irq_data(desc));
221 }
222
223 static void dwapb_irq_enable(struct irq_data *d)
224 {
225 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
226 struct dwapb_gpio *gpio = igc->private;
227 struct gpio_chip *gc = &gpio->ports[0].gc;
228 unsigned long flags;
229 u32 val;
230
231 spin_lock_irqsave(&gc->bgpio_lock, flags);
232 val = dwapb_read(gpio, GPIO_INTEN);
233 val |= BIT(d->hwirq);
234 dwapb_write(gpio, GPIO_INTEN, val);
235 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
236 }
237
238 static void dwapb_irq_disable(struct irq_data *d)
239 {
240 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
241 struct dwapb_gpio *gpio = igc->private;
242 struct gpio_chip *gc = &gpio->ports[0].gc;
243 unsigned long flags;
244 u32 val;
245
246 spin_lock_irqsave(&gc->bgpio_lock, flags);
247 val = dwapb_read(gpio, GPIO_INTEN);
248 val &= ~BIT(d->hwirq);
249 dwapb_write(gpio, GPIO_INTEN, val);
250 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
251 }
252
253 static int dwapb_irq_reqres(struct irq_data *d)
254 {
255 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
256 struct dwapb_gpio *gpio = igc->private;
257 struct gpio_chip *gc = &gpio->ports[0].gc;
258 int ret;
259
260 ret = gpiochip_lock_as_irq(gc, irqd_to_hwirq(d));
261 if (ret) {
262 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
263 irqd_to_hwirq(d));
264 return ret;
265 }
266 return 0;
267 }
268
269 static void dwapb_irq_relres(struct irq_data *d)
270 {
271 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
272 struct dwapb_gpio *gpio = igc->private;
273 struct gpio_chip *gc = &gpio->ports[0].gc;
274
275 gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
276 }
277
278 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
279 {
280 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
281 struct dwapb_gpio *gpio = igc->private;
282 struct gpio_chip *gc = &gpio->ports[0].gc;
283 int bit = d->hwirq;
284 unsigned long level, polarity, flags;
285
286 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
287 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
288 return -EINVAL;
289
290 spin_lock_irqsave(&gc->bgpio_lock, flags);
291 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
292 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
293
294 switch (type) {
295 case IRQ_TYPE_EDGE_BOTH:
296 level |= BIT(bit);
297 dwapb_toggle_trigger(gpio, bit);
298 break;
299 case IRQ_TYPE_EDGE_RISING:
300 level |= BIT(bit);
301 polarity |= BIT(bit);
302 break;
303 case IRQ_TYPE_EDGE_FALLING:
304 level |= BIT(bit);
305 polarity &= ~BIT(bit);
306 break;
307 case IRQ_TYPE_LEVEL_HIGH:
308 level &= ~BIT(bit);
309 polarity |= BIT(bit);
310 break;
311 case IRQ_TYPE_LEVEL_LOW:
312 level &= ~BIT(bit);
313 polarity &= ~BIT(bit);
314 break;
315 }
316
317 irq_setup_alt_chip(d, type);
318
319 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
320 if (type != IRQ_TYPE_EDGE_BOTH)
321 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
322 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
323
324 return 0;
325 }
326
327 #ifdef CONFIG_PM_SLEEP
328 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
329 {
330 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
331 struct dwapb_gpio *gpio = igc->private;
332 struct dwapb_context *ctx = gpio->ports[0].ctx;
333
334 if (enable)
335 ctx->wake_en |= BIT(d->hwirq);
336 else
337 ctx->wake_en &= ~BIT(d->hwirq);
338
339 return 0;
340 }
341 #endif
342
343 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
344 unsigned offset, unsigned debounce)
345 {
346 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
347 struct dwapb_gpio *gpio = port->gpio;
348 unsigned long flags, val_deb;
349 unsigned long mask = BIT(offset);
350
351 spin_lock_irqsave(&gc->bgpio_lock, flags);
352
353 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
354 if (debounce)
355 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
356 else
357 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
358
359 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
360
361 return 0;
362 }
363
364 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
365 unsigned long config)
366 {
367 u32 debounce;
368
369 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
370 return -ENOTSUPP;
371
372 debounce = pinconf_to_config_argument(config);
373 return dwapb_gpio_set_debounce(gc, offset, debounce);
374 }
375
376 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
377 {
378 u32 worked;
379 struct dwapb_gpio *gpio = dev_id;
380
381 worked = dwapb_do_irq(gpio);
382
383 return worked ? IRQ_HANDLED : IRQ_NONE;
384 }
385
386 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
387 struct dwapb_gpio_port *port,
388 struct dwapb_port_property *pp)
389 {
390 struct gpio_chip *gc = &port->gc;
391 struct fwnode_handle *fwnode = pp->fwnode;
392 struct irq_chip_generic *irq_gc = NULL;
393 unsigned int hwirq, ngpio = gc->ngpio;
394 struct irq_chip_type *ct;
395 int err, i;
396
397 gpio->domain = irq_domain_create_linear(fwnode, ngpio,
398 &irq_generic_chip_ops, gpio);
399 if (!gpio->domain)
400 return;
401
402 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
403 DWAPB_DRIVER_NAME, handle_level_irq,
404 IRQ_NOREQUEST, 0,
405 IRQ_GC_INIT_NESTED_LOCK);
406 if (err) {
407 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
408 irq_domain_remove(gpio->domain);
409 gpio->domain = NULL;
410 return;
411 }
412
413 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
414 if (!irq_gc) {
415 irq_domain_remove(gpio->domain);
416 gpio->domain = NULL;
417 return;
418 }
419
420 irq_gc->reg_base = gpio->regs;
421 irq_gc->private = gpio;
422
423 for (i = 0; i < 2; i++) {
424 ct = &irq_gc->chip_types[i];
425 ct->chip.irq_ack = irq_gc_ack_set_bit;
426 ct->chip.irq_mask = irq_gc_mask_set_bit;
427 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
428 ct->chip.irq_set_type = dwapb_irq_set_type;
429 ct->chip.irq_enable = dwapb_irq_enable;
430 ct->chip.irq_disable = dwapb_irq_disable;
431 ct->chip.irq_request_resources = dwapb_irq_reqres;
432 ct->chip.irq_release_resources = dwapb_irq_relres;
433 #ifdef CONFIG_PM_SLEEP
434 ct->chip.irq_set_wake = dwapb_irq_set_wake;
435 #endif
436 ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI);
437 ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK);
438 ct->type = IRQ_TYPE_LEVEL_MASK;
439 }
440
441 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
442 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
443 irq_gc->chip_types[1].handler = handle_edge_irq;
444
445 if (!pp->irq_shared) {
446 int i;
447
448 for (i = 0; i < pp->ngpio; i++) {
449 if (pp->irq[i] >= 0)
450 irq_set_chained_handler_and_data(pp->irq[i],
451 dwapb_irq_handler, gpio);
452 }
453 } else {
454 /*
455 * Request a shared IRQ since where MFD would have devices
456 * using the same irq pin
457 */
458 err = devm_request_irq(gpio->dev, pp->irq[0],
459 dwapb_irq_handler_mfd,
460 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
461 if (err) {
462 dev_err(gpio->dev, "error requesting IRQ\n");
463 irq_domain_remove(gpio->domain);
464 gpio->domain = NULL;
465 return;
466 }
467 }
468
469 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
470 irq_create_mapping(gpio->domain, hwirq);
471
472 port->gc.to_irq = dwapb_gpio_to_irq;
473 }
474
475 static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
476 {
477 struct dwapb_gpio_port *port = &gpio->ports[0];
478 struct gpio_chip *gc = &port->gc;
479 unsigned int ngpio = gc->ngpio;
480 irq_hw_number_t hwirq;
481
482 if (!gpio->domain)
483 return;
484
485 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
486 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
487
488 irq_domain_remove(gpio->domain);
489 gpio->domain = NULL;
490 }
491
492 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
493 struct dwapb_port_property *pp,
494 unsigned int offs)
495 {
496 struct dwapb_gpio_port *port;
497 void __iomem *dat, *set, *dirout;
498 int err;
499
500 port = &gpio->ports[offs];
501 port->gpio = gpio;
502 port->idx = pp->idx;
503
504 #ifdef CONFIG_PM_SLEEP
505 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
506 if (!port->ctx)
507 return -ENOMEM;
508 #endif
509
510 dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_STRIDE);
511 set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_STRIDE);
512 dirout = gpio->regs + GPIO_SWPORTA_DDR +
513 (pp->idx * GPIO_SWPORT_DDR_STRIDE);
514
515 /* This registers 32 GPIO lines per port */
516 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
517 NULL, 0);
518 if (err) {
519 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
520 port->idx);
521 return err;
522 }
523
524 #ifdef CONFIG_OF_GPIO
525 port->gc.of_node = to_of_node(pp->fwnode);
526 #endif
527 port->gc.ngpio = pp->ngpio;
528 port->gc.base = pp->gpio_base;
529
530 /* Only port A support debounce */
531 if (pp->idx == 0)
532 port->gc.set_config = dwapb_gpio_set_config;
533
534 if (pp->has_irq)
535 dwapb_configure_irqs(gpio, port, pp);
536
537 err = gpiochip_add_data(&port->gc, port);
538 if (err) {
539 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
540 port->idx);
541 return err;
542 }
543
544 /* Add GPIO-signaled ACPI event support */
545 acpi_gpiochip_request_interrupts(&port->gc);
546
547 port->is_registered = true;
548
549 return 0;
550 }
551
552 static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
553 {
554 unsigned int m;
555
556 for (m = 0; m < gpio->nr_ports; ++m) {
557 struct dwapb_gpio_port *port = &gpio->ports[m];
558
559 if (!port->is_registered)
560 continue;
561
562 acpi_gpiochip_free_interrupts(&port->gc);
563 gpiochip_remove(&port->gc);
564 }
565 }
566
567 static struct dwapb_platform_data *
568 dwapb_gpio_get_pdata(struct device *dev)
569 {
570 struct fwnode_handle *fwnode;
571 struct dwapb_platform_data *pdata;
572 struct dwapb_port_property *pp;
573 int nports;
574 int i, j;
575
576 nports = device_get_child_node_count(dev);
577 if (nports == 0)
578 return ERR_PTR(-ENODEV);
579
580 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
581 if (!pdata)
582 return ERR_PTR(-ENOMEM);
583
584 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
585 if (!pdata->properties)
586 return ERR_PTR(-ENOMEM);
587
588 pdata->nports = nports;
589
590 i = 0;
591 device_for_each_child_node(dev, fwnode) {
592 struct device_node *np = NULL;
593
594 pp = &pdata->properties[i++];
595 pp->fwnode = fwnode;
596
597 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
598 pp->idx >= DWAPB_MAX_PORTS) {
599 dev_err(dev,
600 "missing/invalid port index for port%d\n", i);
601 fwnode_handle_put(fwnode);
602 return ERR_PTR(-EINVAL);
603 }
604
605 if (fwnode_property_read_u32(fwnode, "snps,nr-gpios",
606 &pp->ngpio)) {
607 dev_info(dev,
608 "failed to get number of gpios for port%d\n",
609 i);
610 pp->ngpio = 32;
611 }
612
613 pp->irq_shared = false;
614 pp->gpio_base = -1;
615
616 /*
617 * Only port A can provide interrupts in all configurations of
618 * the IP.
619 */
620 if (pp->idx != 0)
621 continue;
622
623 if (dev->of_node && fwnode_property_read_bool(fwnode,
624 "interrupt-controller")) {
625 np = to_of_node(fwnode);
626 }
627
628 for (j = 0; j < pp->ngpio; j++) {
629 pp->irq[j] = -ENXIO;
630
631 if (np)
632 pp->irq[j] = of_irq_get(np, j);
633 else if (has_acpi_companion(dev))
634 pp->irq[j] = platform_get_irq(to_platform_device(dev), j);
635
636 if (pp->irq[j] >= 0)
637 pp->has_irq = true;
638 }
639
640 if (!pp->has_irq)
641 dev_warn(dev, "no irq for port%d\n", pp->idx);
642 }
643
644 return pdata;
645 }
646
647 static const struct of_device_id dwapb_of_match[] = {
648 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
649 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
650 { /* Sentinel */ }
651 };
652 MODULE_DEVICE_TABLE(of, dwapb_of_match);
653
654 static const struct acpi_device_id dwapb_acpi_match[] = {
655 {"HISI0181", 0},
656 {"APMC0D07", 0},
657 {"APMC0D81", GPIO_REG_OFFSET_V2},
658 { }
659 };
660 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
661
662 static int dwapb_gpio_probe(struct platform_device *pdev)
663 {
664 unsigned int i;
665 struct dwapb_gpio *gpio;
666 int err;
667 struct device *dev = &pdev->dev;
668 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
669
670 if (!pdata) {
671 pdata = dwapb_gpio_get_pdata(dev);
672 if (IS_ERR(pdata))
673 return PTR_ERR(pdata);
674 }
675
676 if (!pdata->nports)
677 return -ENODEV;
678
679 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
680 if (!gpio)
681 return -ENOMEM;
682
683 gpio->dev = &pdev->dev;
684 gpio->nr_ports = pdata->nports;
685
686 gpio->rst = devm_reset_control_get_optional_shared(dev, NULL);
687 if (IS_ERR(gpio->rst))
688 return PTR_ERR(gpio->rst);
689
690 reset_control_deassert(gpio->rst);
691
692 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
693 sizeof(*gpio->ports), GFP_KERNEL);
694 if (!gpio->ports)
695 return -ENOMEM;
696
697 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
698 if (IS_ERR(gpio->regs))
699 return PTR_ERR(gpio->regs);
700
701 /* Optional bus clock */
702 gpio->clk = devm_clk_get(&pdev->dev, "bus");
703 if (!IS_ERR(gpio->clk)) {
704 err = clk_prepare_enable(gpio->clk);
705 if (err) {
706 dev_info(&pdev->dev, "Cannot enable clock\n");
707 return err;
708 }
709 }
710
711 gpio->flags = 0;
712 if (dev->of_node) {
713 gpio->flags = (uintptr_t)of_device_get_match_data(dev);
714 } else if (has_acpi_companion(dev)) {
715 const struct acpi_device_id *acpi_id;
716
717 acpi_id = acpi_match_device(dwapb_acpi_match, dev);
718 if (acpi_id) {
719 if (acpi_id->driver_data)
720 gpio->flags = acpi_id->driver_data;
721 }
722 }
723
724 for (i = 0; i < gpio->nr_ports; i++) {
725 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
726 if (err)
727 goto out_unregister;
728 }
729 platform_set_drvdata(pdev, gpio);
730
731 return 0;
732
733 out_unregister:
734 dwapb_gpio_unregister(gpio);
735 dwapb_irq_teardown(gpio);
736 clk_disable_unprepare(gpio->clk);
737
738 return err;
739 }
740
741 static int dwapb_gpio_remove(struct platform_device *pdev)
742 {
743 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
744
745 dwapb_gpio_unregister(gpio);
746 dwapb_irq_teardown(gpio);
747 reset_control_assert(gpio->rst);
748 clk_disable_unprepare(gpio->clk);
749
750 return 0;
751 }
752
753 #ifdef CONFIG_PM_SLEEP
754 static int dwapb_gpio_suspend(struct device *dev)
755 {
756 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
757 struct gpio_chip *gc = &gpio->ports[0].gc;
758 unsigned long flags;
759 int i;
760
761 spin_lock_irqsave(&gc->bgpio_lock, flags);
762 for (i = 0; i < gpio->nr_ports; i++) {
763 unsigned int offset;
764 unsigned int idx = gpio->ports[i].idx;
765 struct dwapb_context *ctx = gpio->ports[i].ctx;
766
767 BUG_ON(!ctx);
768
769 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
770 ctx->dir = dwapb_read(gpio, offset);
771
772 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
773 ctx->data = dwapb_read(gpio, offset);
774
775 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
776 ctx->ext = dwapb_read(gpio, offset);
777
778 /* Only port A can provide interrupts */
779 if (idx == 0) {
780 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
781 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
782 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
783 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
784 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
785
786 /* Mask out interrupts */
787 dwapb_write(gpio, GPIO_INTMASK,
788 0xffffffff & ~ctx->wake_en);
789 }
790 }
791 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
792
793 clk_disable_unprepare(gpio->clk);
794
795 return 0;
796 }
797
798 static int dwapb_gpio_resume(struct device *dev)
799 {
800 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
801 struct gpio_chip *gc = &gpio->ports[0].gc;
802 unsigned long flags;
803 int i;
804
805 if (!IS_ERR(gpio->clk))
806 clk_prepare_enable(gpio->clk);
807
808 spin_lock_irqsave(&gc->bgpio_lock, flags);
809 for (i = 0; i < gpio->nr_ports; i++) {
810 unsigned int offset;
811 unsigned int idx = gpio->ports[i].idx;
812 struct dwapb_context *ctx = gpio->ports[i].ctx;
813
814 BUG_ON(!ctx);
815
816 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
817 dwapb_write(gpio, offset, ctx->data);
818
819 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
820 dwapb_write(gpio, offset, ctx->dir);
821
822 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
823 dwapb_write(gpio, offset, ctx->ext);
824
825 /* Only port A can provide interrupts */
826 if (idx == 0) {
827 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
828 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
829 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
830 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
831 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
832
833 /* Clear out spurious interrupts */
834 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
835 }
836 }
837 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
838
839 return 0;
840 }
841 #endif
842
843 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
844 dwapb_gpio_resume);
845
846 static struct platform_driver dwapb_gpio_driver = {
847 .driver = {
848 .name = DWAPB_DRIVER_NAME,
849 .pm = &dwapb_gpio_pm_ops,
850 .of_match_table = of_match_ptr(dwapb_of_match),
851 .acpi_match_table = ACPI_PTR(dwapb_acpi_match),
852 },
853 .probe = dwapb_gpio_probe,
854 .remove = dwapb_gpio_remove,
855 };
856
857 module_platform_driver(dwapb_gpio_driver);
858
859 MODULE_LICENSE("GPL");
860 MODULE_AUTHOR("Jamie Iles");
861 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
862 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);
Linux with added FPC-III support