drivers/ptp/ptp_idt82p33.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (C) 2018 Integrated Device Technology, Inc
   4 //
   5
   6 #define pr_fmt(fmt) "IDT_82p33xxx: " fmt
   7
   8 #include <linux/firmware.h>
   9 #include <linux/i2c.h>
  10 #include <linux/module.h>
  11 #include <linux/ptp_clock_kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/kernel.h>
  14 #include <linux/timekeeping.h>
  15 #include <linux/bitops.h>
  16
  17 #include "ptp_private.h"
  18 #include "ptp_idt82p33.h"
  19
  20 MODULE_DESCRIPTION("Driver for IDT 82p33xxx clock devices");
  21 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
  22 MODULE_VERSION("1.0");
  23 MODULE_LICENSE("GPL");
  24
  25 /* Module Parameters */
  26 u32 sync_tod_timeout = SYNC_TOD_TIMEOUT_SEC;
  27 module_param(sync_tod_timeout, uint, 0);
  28 MODULE_PARM_DESC(sync_tod_timeout,
  29 "duration in second to keep SYNC_TOD on (set to 0 to keep it always on)");
  30
  31 u32 phase_snap_threshold = SNAP_THRESHOLD_NS;
  32 module_param(phase_snap_threshold, uint, 0);
  33 MODULE_PARM_DESC(phase_snap_threshold,
  34 "threshold (150000ns by default) below which adjtime would ignore");
  35
  36 static void idt82p33_byte_array_to_timespec(struct timespec64 *ts,
  37                                             u8 buf[TOD_BYTE_COUNT])
  38 {
  39         time64_t sec;
  40         s32 nsec;
  41         u8 i;
  42
  43         nsec = buf[3];
  44         for (i = 0; i < 3; i++) {
  45                 nsec <<= 8;
  46                 nsec |= buf[2 - i];
  47         }
  48
  49         sec = buf[9];
  50         for (i = 0; i < 5; i++) {
  51                 sec <<= 8;
  52                 sec |= buf[8 - i];
  53         }
  54
  55         ts->tv_sec = sec;
  56         ts->tv_nsec = nsec;
  57 }
  58
  59 static void idt82p33_timespec_to_byte_array(struct timespec64 const *ts,
  60                                             u8 buf[TOD_BYTE_COUNT])
  61 {
  62         time64_t sec;
  63         s32 nsec;
  64         u8 i;
  65
  66         nsec = ts->tv_nsec;
  67         sec = ts->tv_sec;
  68
  69         for (i = 0; i < 4; i++) {
  70                 buf[i] = nsec & 0xff;
  71                 nsec >>= 8;
  72         }
  73
  74         for (i = 4; i < TOD_BYTE_COUNT; i++) {
  75                 buf[i] = sec & 0xff;
  76                 sec >>= 8;
  77         }
  78 }
  79
  80 static int idt82p33_xfer(struct idt82p33 *idt82p33,
  81                          unsigned char regaddr,
  82                          unsigned char *buf,
  83                          unsigned int count,
  84                          int write)
  85 {
  86         struct i2c_client *client = idt82p33->client;
  87         struct i2c_msg msg[2];
  88         int cnt;
  89
  90         msg[0].addr = client->addr;
  91         msg[0].flags = 0;
  92         msg[0].len = 1;
  93         msg[0].buf = &regaddr;
  94
  95         msg[1].addr = client->addr;
  96         msg[1].flags = write ? 0 : I2C_M_RD;
  97         msg[1].len = count;
  98         msg[1].buf = buf;
  99
 100         cnt = i2c_transfer(client->adapter, msg, 2);
 101         if (cnt < 0) {
 102                 dev_err(&client->dev, "i2c_transfer returned %d\n", cnt);
 103                 return cnt;
 104         } else if (cnt != 2) {
 105                 dev_err(&client->dev,
 106                         "i2c_transfer sent only %d of %d messages\n", cnt, 2);
 107                 return -EIO;
 108         }
 109         return 0;
 110 }
 111
 112 static int idt82p33_page_offset(struct idt82p33 *idt82p33, unsigned char val)
 113 {
 114         int err;
 115
 116         if (idt82p33->page_offset == val)
 117                 return 0;
 118
 119         err = idt82p33_xfer(idt82p33, PAGE_ADDR, &val, sizeof(val), 1);
 120         if (err)
 121                 dev_err(&idt82p33->client->dev,
 122                         "failed to set page offset %d\n", val);
 123         else
 124                 idt82p33->page_offset = val;
 125
 126         return err;
 127 }
 128
 129 static int idt82p33_rdwr(struct idt82p33 *idt82p33, unsigned int regaddr,
 130                          unsigned char *buf, unsigned int count, bool write)
 131 {
 132         u8 offset, page;
 133         int err;
 134
 135         page = _PAGE(regaddr);
 136         offset = _OFFSET(regaddr);
 137
 138         err = idt82p33_page_offset(idt82p33, page);
 139         if (err)
 140                 goto out;
 141
 142         err = idt82p33_xfer(idt82p33, offset, buf, count, write);
 143 out:
 144         return err;
 145 }
 146
 147 static int idt82p33_read(struct idt82p33 *idt82p33, unsigned int regaddr,
 148                         unsigned char *buf, unsigned int count)
 149 {
 150         return idt82p33_rdwr(idt82p33, regaddr, buf, count, false);
 151 }
 152
 153 static int idt82p33_write(struct idt82p33 *idt82p33, unsigned int regaddr,
 154                         unsigned char *buf, unsigned int count)
 155 {
 156         return idt82p33_rdwr(idt82p33, regaddr, buf, count, true);
 157 }
 158
 159 static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel,
 160                                   enum pll_mode mode)
 161 {
 162         struct idt82p33 *idt82p33 = channel->idt82p33;
 163         u8 dpll_mode;
 164         int err;
 165
 166         if (channel->pll_mode == mode)
 167                 return 0;
 168
 169         err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg,
 170                             &dpll_mode, sizeof(dpll_mode));
 171         if (err)
 172                 return err;
 173
 174         dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
 175
 176         dpll_mode |= (mode << PLL_MODE_SHIFT);
 177
 178         err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg,
 179                              &dpll_mode, sizeof(dpll_mode));
 180         if (err)
 181                 return err;
 182
 183         channel->pll_mode = dpll_mode;
 184
 185         return 0;
 186 }
 187
 188 static int _idt82p33_gettime(struct idt82p33_channel *channel,
 189                              struct timespec64 *ts)
 190 {
 191         struct idt82p33 *idt82p33 = channel->idt82p33;
 192         u8 buf[TOD_BYTE_COUNT];
 193         u8 trigger;
 194         int err;
 195
 196         trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
 197                               HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
 198
 199
 200         err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
 201                              &trigger, sizeof(trigger));
 202
 203         if (err)
 204                 return err;
 205
 206         if (idt82p33->calculate_overhead_flag)
 207                 idt82p33->start_time = ktime_get_raw();
 208
 209         err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
 210
 211         if (err)
 212                 return err;
 213
 214         idt82p33_byte_array_to_timespec(ts, buf);
 215
 216         return 0;
 217 }
 218
 219 /*
 220  *   TOD Trigger:
 221  *   Bits[7:4] Write 0x9, MSB write
 222  *   Bits[3:0] Read 0x9, LSB read
 223  */
 224
 225 static int _idt82p33_settime(struct idt82p33_channel *channel,
 226                              struct timespec64 const *ts)
 227 {
 228         struct idt82p33 *idt82p33 = channel->idt82p33;
 229         struct timespec64 local_ts = *ts;
 230         char buf[TOD_BYTE_COUNT];
 231         s64 dynamic_overhead_ns;
 232         unsigned char trigger;
 233         int err;
 234         u8 i;
 235
 236         trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
 237                               HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
 238
 239         err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
 240                         &trigger, sizeof(trigger));
 241
 242         if (err)
 243                 return err;
 244
 245         if (idt82p33->calculate_overhead_flag) {
 246                 dynamic_overhead_ns = ktime_to_ns(ktime_get_raw())
 247                                         - ktime_to_ns(idt82p33->start_time);
 248
 249                 timespec64_add_ns(&local_ts, dynamic_overhead_ns);
 250
 251                 idt82p33->calculate_overhead_flag = 0;
 252         }
 253
 254         idt82p33_timespec_to_byte_array(&local_ts, buf);
 255
 256         /*
 257          * Store the new time value.
 258          */
 259         for (i = 0; i < TOD_BYTE_COUNT; i++) {
 260                 err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg + i,
 261                                      &buf[i], sizeof(buf[i]));
 262                 if (err)
 263                         return err;
 264         }
 265
 266         return err;
 267 }
 268
 269 static int _idt82p33_adjtime(struct idt82p33_channel *channel, s64 delta_ns)
 270 {
 271         struct idt82p33 *idt82p33 = channel->idt82p33;
 272         struct timespec64 ts;
 273         s64 now_ns;
 274         int err;
 275
 276         idt82p33->calculate_overhead_flag = 1;
 277
 278         err = _idt82p33_gettime(channel, &ts);
 279
 280         if (err)
 281                 return err;
 282
 283         now_ns = timespec64_to_ns(&ts);
 284         now_ns += delta_ns + idt82p33->tod_write_overhead_ns;
 285
 286         ts = ns_to_timespec64(now_ns);
 287
 288         err = _idt82p33_settime(channel, &ts);
 289
 290         return err;
 291 }
 292
 293 static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)
 294 {
 295         struct idt82p33 *idt82p33 = channel->idt82p33;
 296         unsigned char buf[5] = {0};
 297         int neg_adj = 0;
 298         int err, i;
 299         s64 fcw;
 300
 301         if (scaled_ppm == channel->current_freq_ppb)
 302                 return 0;
 303
 304         /*
 305          * Frequency Control Word unit is: 1.68 * 10^-10 ppm
 306          *
 307          * adjfreq:
 308          *       ppb * 10^9
 309          * FCW = ----------
 310          *          168
 311          *
 312          * adjfine:
 313          *       scaled_ppm * 5^12
 314          * FCW = -------------
 315          *         168 * 2^4
 316          */
 317         if (scaled_ppm < 0) {
 318                 neg_adj = 1;
 319                 scaled_ppm = -scaled_ppm;
 320         }
 321
 322         fcw = scaled_ppm * 244140625ULL;
 323         fcw = div_u64(fcw, 2688);
 324
 325         if (neg_adj)
 326                 fcw = -fcw;
 327
 328         for (i = 0; i < 5; i++) {
 329                 buf[i] = fcw & 0xff;
 330                 fcw >>= 8;
 331         }
 332
 333         err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
 334
 335         if (err)
 336                 return err;
 337
 338         err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg,
 339                              buf, sizeof(buf));
 340
 341         if (err == 0)
 342                 channel->current_freq_ppb = scaled_ppm;
 343
 344         return err;
 345 }
 346
 347 static int idt82p33_measure_one_byte_write_overhead(
 348                 struct idt82p33_channel *channel, s64 *overhead_ns)
 349 {
 350         struct idt82p33 *idt82p33 = channel->idt82p33;
 351         ktime_t start, stop;
 352         s64 total_ns;
 353         u8 trigger;
 354         int err;
 355         u8 i;
 356
 357         total_ns = 0;
 358         *overhead_ns = 0;
 359         trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
 360                               HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
 361
 362         for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
 363
 364                 start = ktime_get_raw();
 365
 366                 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
 367                                      &trigger, sizeof(trigger));
 368
 369                 stop = ktime_get_raw();
 370
 371                 if (err)
 372                         return err;
 373
 374                 total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
 375         }
 376
 377         *overhead_ns = div_s64(total_ns, MAX_MEASURMENT_COUNT);
 378
 379         return err;
 380 }
 381
 382 static int idt82p33_measure_tod_write_9_byte_overhead(
 383                         struct idt82p33_channel *channel)
 384 {
 385         struct idt82p33 *idt82p33 = channel->idt82p33;
 386         u8 buf[TOD_BYTE_COUNT];
 387         ktime_t start, stop;
 388         s64 total_ns;
 389         int err = 0;
 390         u8 i, j;
 391
 392         total_ns = 0;
 393         idt82p33->tod_write_overhead_ns = 0;
 394
 395         for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
 396
 397                 start = ktime_get_raw();
 398
 399                 /* Need one less byte for applicable overhead */
 400                 for (j = 0; j < (TOD_BYTE_COUNT - 1); j++) {
 401                         err = idt82p33_write(idt82p33,
 402                                              channel->dpll_tod_cnfg + i,
 403                                              &buf[i], sizeof(buf[i]));
 404                         if (err)
 405                                 return err;
 406                 }
 407
 408                 stop = ktime_get_raw();
 409
 410                 total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
 411         }
 412
 413         idt82p33->tod_write_overhead_ns = div_s64(total_ns,
 414                                                   MAX_MEASURMENT_COUNT);
 415
 416         return err;
 417 }
 418
 419 static int idt82p33_measure_settime_gettime_gap_overhead(
 420                 struct idt82p33_channel *channel, s64 *overhead_ns)
 421 {
 422         struct timespec64 ts1 = {0, 0};
 423         struct timespec64 ts2;
 424         int err;
 425
 426         *overhead_ns = 0;
 427
 428         err = _idt82p33_settime(channel, &ts1);
 429
 430         if (err)
 431                 return err;
 432
 433         err = _idt82p33_gettime(channel, &ts2);
 434
 435         if (!err)
 436                 *overhead_ns = timespec64_to_ns(&ts2) - timespec64_to_ns(&ts1);
 437
 438         return err;
 439 }
 440
 441 static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)
 442 {
 443         s64 trailing_overhead_ns, one_byte_write_ns, gap_ns;
 444         struct idt82p33 *idt82p33 = channel->idt82p33;
 445         int err;
 446
 447         idt82p33->tod_write_overhead_ns = 0;
 448
 449         err = idt82p33_measure_settime_gettime_gap_overhead(channel, &gap_ns);
 450
 451         if (err)
 452                 return err;
 453
 454         err = idt82p33_measure_one_byte_write_overhead(channel,
 455                                                        &one_byte_write_ns);
 456
 457         if (err)
 458                 return err;
 459
 460         err = idt82p33_measure_tod_write_9_byte_overhead(channel);
 461
 462         if (err)
 463                 return err;
 464
 465         trailing_overhead_ns = gap_ns - (2 * one_byte_write_ns);
 466
 467         idt82p33->tod_write_overhead_ns -= trailing_overhead_ns;
 468
 469         return err;
 470 }
 471
 472 static int idt82p33_check_and_set_masks(struct idt82p33 *idt82p33,
 473                                         u8 page,
 474                                         u8 offset,
 475                                         u8 val)
 476 {
 477         int err = 0;
 478
 479         if (page == PLLMASK_ADDR_HI && offset == PLLMASK_ADDR_LO) {
 480                 if ((val & 0xfc) || !(val & 0x3)) {
 481                         dev_err(&idt82p33->client->dev,
 482                                 "Invalid PLL mask 0x%hhx\n", val);
 483                         err = -EINVAL;
 484                 } else {
 485                         idt82p33->pll_mask = val;
 486                 }
 487         } else if (page == PLL0_OUTMASK_ADDR_HI &&
 488                 offset == PLL0_OUTMASK_ADDR_LO) {
 489                 idt82p33->channel[0].output_mask = val;
 490         } else if (page == PLL1_OUTMASK_ADDR_HI &&
 491                 offset == PLL1_OUTMASK_ADDR_LO) {
 492                 idt82p33->channel[1].output_mask = val;
 493         }
 494
 495         return err;
 496 }
 497
 498 static void idt82p33_display_masks(struct idt82p33 *idt82p33)
 499 {
 500         u8 mask, i;
 501
 502         dev_info(&idt82p33->client->dev,
 503                  "pllmask = 0x%02x\n", idt82p33->pll_mask);
 504
 505         for (i = 0; i < MAX_PHC_PLL; i++) {
 506                 mask = 1 << i;
 507
 508                 if (mask & idt82p33->pll_mask)
 509                         dev_info(&idt82p33->client->dev,
 510                                  "PLL%d output_mask = 0x%04x\n",
 511                                  i, idt82p33->channel[i].output_mask);
 512         }
 513 }
 514
 515 static int idt82p33_sync_tod(struct idt82p33_channel *channel, bool enable)
 516 {
 517         struct idt82p33 *idt82p33 = channel->idt82p33;
 518         u8 sync_cnfg;
 519         int err;
 520
 521         if (enable == channel->sync_tod_on) {
 522                 if (enable && sync_tod_timeout) {
 523                         mod_delayed_work(system_wq, &channel->sync_tod_work,
 524                                          sync_tod_timeout * HZ);
 525                 }
 526                 return 0;
 527         }
 528
 529         err = idt82p33_read(idt82p33, channel->dpll_sync_cnfg,
 530                             &sync_cnfg, sizeof(sync_cnfg));
 531         if (err)
 532                 return err;
 533
 534         sync_cnfg &= ~SYNC_TOD;
 535
 536         if (enable)
 537                 sync_cnfg |= SYNC_TOD;
 538
 539         err = idt82p33_write(idt82p33, channel->dpll_sync_cnfg,
 540                              &sync_cnfg, sizeof(sync_cnfg));
 541         if (err)
 542                 return err;
 543
 544         channel->sync_tod_on = enable;
 545
 546         if (enable && sync_tod_timeout) {
 547                 mod_delayed_work(system_wq, &channel->sync_tod_work,
 548                                  sync_tod_timeout * HZ);
 549         }
 550
 551         return 0;
 552 }
 553
 554 static void idt82p33_sync_tod_work_handler(struct work_struct *work)
 555 {
 556         struct idt82p33_channel *channel =
 557                 container_of(work, struct idt82p33_channel, sync_tod_work.work);
 558         struct idt82p33 *idt82p33 = channel->idt82p33;
 559
 560         mutex_lock(&idt82p33->reg_lock);
 561
 562         (void)idt82p33_sync_tod(channel, false);
 563
 564         mutex_unlock(&idt82p33->reg_lock);
 565 }
 566
 567 static int idt82p33_pps_enable(struct idt82p33_channel *channel, bool enable)
 568 {
 569         struct idt82p33 *idt82p33 = channel->idt82p33;
 570         u8 mask, outn, val;
 571         int err;
 572
 573         mask = channel->output_mask;
 574         outn = 0;
 575
 576         while (mask) {
 577                 if (mask & 0x1) {
 578                         err = idt82p33_read(idt82p33, OUT_MUX_CNFG(outn),
 579                                             &val, sizeof(val));
 580                         if (err)
 581                                 return err;
 582
 583                         if (enable)
 584                                 val &= ~SQUELCH_ENABLE;
 585                         else
 586                                 val |= SQUELCH_ENABLE;
 587
 588                         err = idt82p33_write(idt82p33, OUT_MUX_CNFG(outn),
 589                                              &val, sizeof(val));
 590
 591                         if (err)
 592                                 return err;
 593                 }
 594                 mask >>= 0x1;
 595                 outn++;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static int idt82p33_enable_tod(struct idt82p33_channel *channel)
 602 {
 603         struct idt82p33 *idt82p33 = channel->idt82p33;
 604         struct timespec64 ts = {0, 0};
 605         int err;
 606         u8 val;
 607
 608         val = 0;
 609         err = idt82p33_write(idt82p33, channel->dpll_input_mode_cnfg,
 610                              &val, sizeof(val));
 611         if (err)
 612                 return err;
 613
 614         err = idt82p33_pps_enable(channel, false);
 615
 616         if (err)
 617                 return err;
 618
 619         err = idt82p33_measure_tod_write_overhead(channel);
 620
 621         if (err)
 622                 return err;
 623
 624         err = _idt82p33_settime(channel, &ts);
 625
 626         if (err)
 627                 return err;
 628
 629         return idt82p33_sync_tod(channel, true);
 630 }
 631
 632 static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33)
 633 {
 634         struct idt82p33_channel *channel;
 635         u8 i;
 636
 637         for (i = 0; i < MAX_PHC_PLL; i++) {
 638
 639                 channel = &idt82p33->channel[i];
 640
 641                 if (channel->ptp_clock) {
 642                         ptp_clock_unregister(channel->ptp_clock);
 643                         cancel_delayed_work_sync(&channel->sync_tod_work);
 644                 }
 645         }
 646 }
 647
 648 static int idt82p33_enable(struct ptp_clock_info *ptp,
 649                          struct ptp_clock_request *rq, int on)
 650 {
 651         struct idt82p33_channel *channel =
 652                         container_of(ptp, struct idt82p33_channel, caps);
 653         struct idt82p33 *idt82p33 = channel->idt82p33;
 654         int err;
 655
 656         err = -EOPNOTSUPP;
 657
 658         mutex_lock(&idt82p33->reg_lock);
 659
 660         if (rq->type == PTP_CLK_REQ_PEROUT) {
 661                 if (!on)
 662                         err = idt82p33_pps_enable(channel, false);
 663
 664                 /* Only accept a 1-PPS aligned to the second. */
 665                 else if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
 666                     rq->perout.period.nsec) {
 667                         err = -ERANGE;
 668                 } else
 669                         err = idt82p33_pps_enable(channel, true);
 670         }
 671
 672         mutex_unlock(&idt82p33->reg_lock);
 673
 674         return err;
 675 }
 676
 677 static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
 678 {
 679         struct idt82p33_channel *channel =
 680                         container_of(ptp, struct idt82p33_channel, caps);
 681         struct idt82p33 *idt82p33 = channel->idt82p33;
 682         int err;
 683
 684         mutex_lock(&idt82p33->reg_lock);
 685         err = _idt82p33_adjfine(channel, scaled_ppm);
 686         mutex_unlock(&idt82p33->reg_lock);
 687
 688         return err;
 689 }
 690
 691 static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)
 692 {
 693         struct idt82p33_channel *channel =
 694                         container_of(ptp, struct idt82p33_channel, caps);
 695         struct idt82p33 *idt82p33 = channel->idt82p33;
 696         int err;
 697
 698         mutex_lock(&idt82p33->reg_lock);
 699
 700         if (abs(delta_ns) < phase_snap_threshold) {
 701                 mutex_unlock(&idt82p33->reg_lock);
 702                 return 0;
 703         }
 704
 705         err = _idt82p33_adjtime(channel, delta_ns);
 706
 707         if (err) {
 708                 mutex_unlock(&idt82p33->reg_lock);
 709                 return err;
 710         }
 711
 712         err = idt82p33_sync_tod(channel, true);
 713
 714         mutex_unlock(&idt82p33->reg_lock);
 715
 716         return err;
 717 }
 718
 719 static int idt82p33_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
 720 {
 721         struct idt82p33_channel *channel =
 722                         container_of(ptp, struct idt82p33_channel, caps);
 723         struct idt82p33 *idt82p33 = channel->idt82p33;
 724         int err;
 725
 726         mutex_lock(&idt82p33->reg_lock);
 727         err = _idt82p33_gettime(channel, ts);
 728         mutex_unlock(&idt82p33->reg_lock);
 729
 730         return err;
 731 }
 732
 733 static int idt82p33_settime(struct ptp_clock_info *ptp,
 734                         const struct timespec64 *ts)
 735 {
 736         struct idt82p33_channel *channel =
 737                         container_of(ptp, struct idt82p33_channel, caps);
 738         struct idt82p33 *idt82p33 = channel->idt82p33;
 739         int err;
 740
 741         mutex_lock(&idt82p33->reg_lock);
 742         err = _idt82p33_settime(channel, ts);
 743         mutex_unlock(&idt82p33->reg_lock);
 744
 745         return err;
 746 }
 747
 748 static int idt82p33_channel_init(struct idt82p33_channel *channel, int index)
 749 {
 750         switch (index) {
 751         case 0:
 752                 channel->dpll_tod_cnfg = DPLL1_TOD_CNFG;
 753                 channel->dpll_tod_trigger = DPLL1_TOD_TRIGGER;
 754                 channel->dpll_tod_sts = DPLL1_TOD_STS;
 755                 channel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG;
 756                 channel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG;
 757                 channel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG;
 758                 channel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG;
 759                 channel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG;
 760                 break;
 761         case 1:
 762                 channel->dpll_tod_cnfg = DPLL2_TOD_CNFG;
 763                 channel->dpll_tod_trigger = DPLL2_TOD_TRIGGER;
 764                 channel->dpll_tod_sts = DPLL2_TOD_STS;
 765                 channel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG;
 766                 channel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG;
 767                 channel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG;
 768                 channel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG;
 769                 channel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG;
 770                 break;
 771         default:
 772                 return -EINVAL;
 773         }
 774
 775         INIT_DELAYED_WORK(&channel->sync_tod_work,
 776                           idt82p33_sync_tod_work_handler);
 777         channel->sync_tod_on = false;
 778         channel->current_freq_ppb = 0;
 779
 780         return 0;
 781 }
 782
 783 static void idt82p33_caps_init(struct ptp_clock_info *caps)
 784 {
 785         caps->owner = THIS_MODULE;
 786         caps->max_adj = 92000;
 787         caps->adjfine = idt82p33_adjfine;
 788         caps->adjtime = idt82p33_adjtime;
 789         caps->gettime64 = idt82p33_gettime;
 790         caps->settime64 = idt82p33_settime;
 791         caps->enable = idt82p33_enable;
 792 }
 793
 794 static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)
 795 {
 796         struct idt82p33_channel *channel;
 797         int err;
 798
 799         if (!(index < MAX_PHC_PLL))
 800                 return -EINVAL;
 801
 802         channel = &idt82p33->channel[index];
 803
 804         err = idt82p33_channel_init(channel, index);
 805         if (err)
 806                 return err;
 807
 808         channel->idt82p33 = idt82p33;
 809
 810         idt82p33_caps_init(&channel->caps);
 811         snprintf(channel->caps.name, sizeof(channel->caps.name),
 812                  "IDT 82P33 PLL%u", index);
 813         channel->caps.n_per_out = hweight8(channel->output_mask);
 814
 815         err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
 816         if (err)
 817                 return err;
 818
 819         err = idt82p33_enable_tod(channel);
 820         if (err)
 821                 return err;
 822
 823         channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
 824
 825         if (IS_ERR(channel->ptp_clock)) {
 826                 err = PTR_ERR(channel->ptp_clock);
 827                 channel->ptp_clock = NULL;
 828                 return err;
 829         }
 830
 831         if (!channel->ptp_clock)
 832                 return -ENOTSUPP;
 833
 834         dev_info(&idt82p33->client->dev, "PLL%d registered as ptp%d\n",
 835                  index, channel->ptp_clock->index);
 836
 837         return 0;
 838 }
 839
 840 static int idt82p33_load_firmware(struct idt82p33 *idt82p33)
 841 {
 842         const struct firmware *fw;
 843         struct idt82p33_fwrc *rec;
 844         u8 loaddr, page, val;
 845         int err;
 846         s32 len;
 847
 848         dev_dbg(&idt82p33->client->dev,
 849                 "requesting firmware '%s'\n", FW_FILENAME);
 850
 851         err = request_firmware(&fw, FW_FILENAME, &idt82p33->client->dev);
 852
 853         if (err)
 854                 return err;
 855
 856         dev_dbg(&idt82p33->client->dev, "firmware size %zu bytes\n", fw->size);
 857
 858         rec = (struct idt82p33_fwrc *) fw->data;
 859
 860         for (len = fw->size; len > 0; len -= sizeof(*rec)) {
 861
 862                 if (rec->reserved) {
 863                         dev_err(&idt82p33->client->dev,
 864                                 "bad firmware, reserved field non-zero\n");
 865                         err = -EINVAL;
 866                 } else {
 867                         val = rec->value;
 868                         loaddr = rec->loaddr;
 869                         page = rec->hiaddr;
 870
 871                         rec++;
 872
 873                         err = idt82p33_check_and_set_masks(idt82p33, page,
 874                                                            loaddr, val);
 875                 }
 876
 877                 if (err == 0) {
 878                         /* maximum 8 pages  */
 879                         if (page >= PAGE_NUM)
 880                                 continue;
 881
 882                         /* Page size 128, last 4 bytes of page skipped */
 883                         if (((loaddr > 0x7b) && (loaddr <= 0x7f))
 884                              || ((loaddr > 0xfb) && (loaddr <= 0xff)))
 885                                 continue;
 886
 887                         err = idt82p33_write(idt82p33, _ADDR(page, loaddr),
 888                                              &val, sizeof(val));
 889                 }
 890
 891                 if (err)
 892                         goto out;
 893         }
 894
 895         idt82p33_display_masks(idt82p33);
 896 out:
 897         release_firmware(fw);
 898         return err;
 899 }
 900
 901
 902 static int idt82p33_probe(struct i2c_client *client,
 903                           const struct i2c_device_id *id)
 904 {
 905         struct idt82p33 *idt82p33;
 906         int err;
 907         u8 i;
 908
 909         (void)id;
 910
 911         idt82p33 = devm_kzalloc(&client->dev,
 912                                 sizeof(struct idt82p33), GFP_KERNEL);
 913         if (!idt82p33)
 914                 return -ENOMEM;
 915
 916         mutex_init(&idt82p33->reg_lock);
 917
 918         idt82p33->client = client;
 919         idt82p33->page_offset = 0xff;
 920         idt82p33->tod_write_overhead_ns = 0;
 921         idt82p33->calculate_overhead_flag = 0;
 922         idt82p33->pll_mask = DEFAULT_PLL_MASK;
 923         idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
 924         idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
 925
 926         mutex_lock(&idt82p33->reg_lock);
 927
 928         err = idt82p33_load_firmware(idt82p33);
 929
 930         if (err)
 931                 dev_warn(&idt82p33->client->dev,
 932                          "loading firmware failed with %d\n", err);
 933
 934         if (idt82p33->pll_mask) {
 935                 for (i = 0; i < MAX_PHC_PLL; i++) {
 936                         if (idt82p33->pll_mask & (1 << i)) {
 937                                 err = idt82p33_enable_channel(idt82p33, i);
 938                                 if (err)
 939                                         break;
 940                         }
 941                 }
 942         } else {
 943                 dev_err(&idt82p33->client->dev,
 944                         "no PLLs flagged as PHCs, nothing to do\n");
 945                 err = -ENODEV;
 946         }
 947
 948         mutex_unlock(&idt82p33->reg_lock);
 949
 950         if (err) {
 951                 idt82p33_ptp_clock_unregister_all(idt82p33);
 952                 return err;
 953         }
 954
 955         i2c_set_clientdata(client, idt82p33);
 956
 957         return 0;
 958 }
 959
 960 static int idt82p33_remove(struct i2c_client *client)
 961 {
 962         struct idt82p33 *idt82p33 = i2c_get_clientdata(client);
 963
 964         idt82p33_ptp_clock_unregister_all(idt82p33);
 965         mutex_destroy(&idt82p33->reg_lock);
 966
 967         return 0;
 968 }
 969
 970 #ifdef CONFIG_OF
 971 static const struct of_device_id idt82p33_dt_id[] = {
 972         { .compatible = "idt,82p33810" },
 973         { .compatible = "idt,82p33813" },
 974         { .compatible = "idt,82p33814" },
 975         { .compatible = "idt,82p33831" },
 976         { .compatible = "idt,82p33910" },
 977         { .compatible = "idt,82p33913" },
 978         { .compatible = "idt,82p33914" },
 979         { .compatible = "idt,82p33931" },
 980         {},
 981 };
 982 MODULE_DEVICE_TABLE(of, idt82p33_dt_id);
 983 #endif
 984
 985 static const struct i2c_device_id idt82p33_i2c_id[] = {
 986         { "idt82p33810", },
 987         { "idt82p33813", },
 988         { "idt82p33814", },
 989         { "idt82p33831", },
 990         { "idt82p33910", },
 991         { "idt82p33913", },
 992         { "idt82p33914", },
 993         { "idt82p33931", },
 994         {},
 995 };
 996 MODULE_DEVICE_TABLE(i2c, idt82p33_i2c_id);
 997
 998 static struct i2c_driver idt82p33_driver = {
 999         .driver = {
1000                 .of_match_table = of_match_ptr(idt82p33_dt_id),
1001                 .name           = "idt82p33",
1002         },
1003         .probe          = idt82p33_probe,
1004         .remove         = idt82p33_remove,
1005         .id_table       = idt82p33_i2c_id,
1006 };
1007
1008 module_i2c_driver(idt82p33_driver);