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dm writecache: correct uncommitted_block when discarding uncommitted entry
[linux/fpc-iii.git] / drivers / regulator / pfuze100-regulator.c
blob4c8e8b4722872a0bfc47755dd2b89f0635b4067b
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
4
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/err.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/regulator/of_regulator.h>
12 #include <linux/platform_device.h>
13 #include <linux/regulator/driver.h>
14 #include <linux/regulator/machine.h>
15 #include <linux/regulator/pfuze100.h>
16 #include <linux/i2c.h>
17 #include <linux/slab.h>
18 #include <linux/regmap.h>
19
20 #define PFUZE_FLAG_DISABLE_SW BIT(1)
21
22 #define PFUZE_NUMREGS 128
23 #define PFUZE100_VOL_OFFSET 0
24 #define PFUZE100_STANDBY_OFFSET 1
25 #define PFUZE100_MODE_OFFSET 3
26 #define PFUZE100_CONF_OFFSET 4
27
28 #define PFUZE100_DEVICEID 0x0
29 #define PFUZE100_REVID 0x3
30 #define PFUZE100_FABID 0x4
31
32 #define PFUZE100_COINVOL 0x1a
33 #define PFUZE100_SW1ABVOL 0x20
34 #define PFUZE100_SW1ABMODE 0x23
35 #define PFUZE100_SW1CVOL 0x2e
36 #define PFUZE100_SW1CMODE 0x31
37 #define PFUZE100_SW2VOL 0x35
38 #define PFUZE100_SW2MODE 0x38
39 #define PFUZE100_SW3AVOL 0x3c
40 #define PFUZE100_SW3AMODE 0x3f
41 #define PFUZE100_SW3BVOL 0x43
42 #define PFUZE100_SW3BMODE 0x46
43 #define PFUZE100_SW4VOL 0x4a
44 #define PFUZE100_SW4MODE 0x4d
45 #define PFUZE100_SWBSTCON1 0x66
46 #define PFUZE100_VREFDDRCON 0x6a
47 #define PFUZE100_VSNVSVOL 0x6b
48 #define PFUZE100_VGEN1VOL 0x6c
49 #define PFUZE100_VGEN2VOL 0x6d
50 #define PFUZE100_VGEN3VOL 0x6e
51 #define PFUZE100_VGEN4VOL 0x6f
52 #define PFUZE100_VGEN5VOL 0x70
53 #define PFUZE100_VGEN6VOL 0x71
54
55 #define PFUZE100_SWxMODE_MASK 0xf
56 #define PFUZE100_SWxMODE_APS_APS 0x8
57 #define PFUZE100_SWxMODE_APS_OFF 0x4
58
59 #define PFUZE100_VGENxLPWR BIT(6)
60 #define PFUZE100_VGENxSTBY BIT(5)
61
62 enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3, PFUZE3001 = 0x31, };
63
64 struct pfuze_regulator {
65 struct regulator_desc desc;
66 unsigned char stby_reg;
67 unsigned char stby_mask;
68 bool sw_reg;
69 };
70
71 struct pfuze_chip {
72 int chip_id;
73 int flags;
74 struct regmap *regmap;
75 struct device *dev;
76 struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
77 struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
78 struct pfuze_regulator *pfuze_regulators;
79 };
80
81 static const int pfuze100_swbst[] = {
82 5000000, 5050000, 5100000, 5150000,
83 };
84
85 static const int pfuze100_vsnvs[] = {
86 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
87 };
88
89 static const int pfuze100_coin[] = {
90 2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
91 };
92
93 static const int pfuze3000_sw1a[] = {
94 700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000,
95 900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000,
96 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000,
97 1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1800000, 3300000,
98 };
99
100 static const int pfuze3000_sw2lo[] = {
101 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000,
102 };
103
104 static const int pfuze3000_sw2hi[] = {
105 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000,
106 };
107
108 static const struct i2c_device_id pfuze_device_id[] = {
109 {.name = "pfuze100", .driver_data = PFUZE100},
110 {.name = "pfuze200", .driver_data = PFUZE200},
111 {.name = "pfuze3000", .driver_data = PFUZE3000},
112 {.name = "pfuze3001", .driver_data = PFUZE3001},
113 { }
114 };
115 MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
116
117 static const struct of_device_id pfuze_dt_ids[] = {
118 { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
119 { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
120 { .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000},
121 { .compatible = "fsl,pfuze3001", .data = (void *)PFUZE3001},
122 { }
123 };
124 MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
125
126 static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
127 {
128 struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
129 int id = rdev_get_id(rdev);
130 bool reg_has_ramp_delay;
131 unsigned int ramp_bits;
132 int ret;
133
134 switch (pfuze100->chip_id) {
135 case PFUZE3001:
136 /* no dynamic voltage scaling for PF3001 */
137 reg_has_ramp_delay = false;
138 break;
139 case PFUZE3000:
140 reg_has_ramp_delay = (id < PFUZE3000_SWBST);
141 break;
142 case PFUZE200:
143 reg_has_ramp_delay = (id < PFUZE200_SWBST);
144 break;
145 case PFUZE100:
146 default:
147 reg_has_ramp_delay = (id < PFUZE100_SWBST);
148 break;
149 }
150
151 if (reg_has_ramp_delay) {
152 ramp_delay = 12500 / ramp_delay;
153 ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
154 ret = regmap_update_bits(pfuze100->regmap,
155 rdev->desc->vsel_reg + 4,
156 0xc0, ramp_bits << 6);
157 if (ret < 0)
158 dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
159 } else {
160 ret = -EACCES;
161 }
162
163 return ret;
164 }
165
166 static const struct regulator_ops pfuze100_ldo_regulator_ops = {
167 .enable = regulator_enable_regmap,
168 .disable = regulator_disable_regmap,
169 .is_enabled = regulator_is_enabled_regmap,
170 .list_voltage = regulator_list_voltage_linear,
171 .set_voltage_sel = regulator_set_voltage_sel_regmap,
172 .get_voltage_sel = regulator_get_voltage_sel_regmap,
173 };
174
175 static const struct regulator_ops pfuze100_fixed_regulator_ops = {
176 .enable = regulator_enable_regmap,
177 .disable = regulator_disable_regmap,
178 .is_enabled = regulator_is_enabled_regmap,
179 .list_voltage = regulator_list_voltage_linear,
180 };
181
182 static const struct regulator_ops pfuze100_sw_regulator_ops = {
183 .list_voltage = regulator_list_voltage_linear,
184 .set_voltage_sel = regulator_set_voltage_sel_regmap,
185 .get_voltage_sel = regulator_get_voltage_sel_regmap,
186 .set_voltage_time_sel = regulator_set_voltage_time_sel,
187 .set_ramp_delay = pfuze100_set_ramp_delay,
188 };
189
190 static const struct regulator_ops pfuze100_sw_disable_regulator_ops = {
191 .enable = regulator_enable_regmap,
192 .disable = regulator_disable_regmap,
193 .is_enabled = regulator_is_enabled_regmap,
194 .list_voltage = regulator_list_voltage_linear,
195 .set_voltage_sel = regulator_set_voltage_sel_regmap,
196 .get_voltage_sel = regulator_get_voltage_sel_regmap,
197 .set_voltage_time_sel = regulator_set_voltage_time_sel,
198 .set_ramp_delay = pfuze100_set_ramp_delay,
199 };
200
201 static const struct regulator_ops pfuze100_swb_regulator_ops = {
202 .enable = regulator_enable_regmap,
203 .disable = regulator_disable_regmap,
204 .is_enabled = regulator_is_enabled_regmap,
205 .list_voltage = regulator_list_voltage_table,
206 .map_voltage = regulator_map_voltage_ascend,
207 .set_voltage_sel = regulator_set_voltage_sel_regmap,
208 .get_voltage_sel = regulator_get_voltage_sel_regmap,
209
210 };
211
212 static const struct regulator_ops pfuze3000_sw_regulator_ops = {
213 .enable = regulator_enable_regmap,
214 .disable = regulator_disable_regmap,
215 .is_enabled = regulator_is_enabled_regmap,
216 .list_voltage = regulator_list_voltage_table,
217 .map_voltage = regulator_map_voltage_ascend,
218 .set_voltage_sel = regulator_set_voltage_sel_regmap,
219 .get_voltage_sel = regulator_get_voltage_sel_regmap,
220 .set_voltage_time_sel = regulator_set_voltage_time_sel,
221 .set_ramp_delay = pfuze100_set_ramp_delay,
222
223 };
224
225 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
226 [_chip ## _ ## _name] = { \
227 .desc = { \
228 .name = #_name, \
229 .n_voltages = 1, \
230 .ops = &pfuze100_fixed_regulator_ops, \
231 .type = REGULATOR_VOLTAGE, \
232 .id = _chip ## _ ## _name, \
233 .owner = THIS_MODULE, \
234 .min_uV = (voltage), \
235 .enable_reg = (base), \
236 .enable_mask = 0x10, \
237 }, \
238 }
239
240 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
241 [_chip ## _ ## _name] = { \
242 .desc = { \
243 .name = #_name,\
244 .n_voltages = ((max) - (min)) / (step) + 1, \
245 .ops = &pfuze100_sw_regulator_ops, \
246 .type = REGULATOR_VOLTAGE, \
247 .id = _chip ## _ ## _name, \
248 .owner = THIS_MODULE, \
249 .min_uV = (min), \
250 .uV_step = (step), \
251 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
252 .vsel_mask = 0x3f, \
253 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
254 .enable_mask = 0xf, \
255 }, \
256 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
257 .stby_mask = 0x3f, \
258 .sw_reg = true, \
259 }
260
261 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
262 [_chip ## _ ## _name] = { \
263 .desc = { \
264 .name = #_name, \
265 .n_voltages = ARRAY_SIZE(voltages), \
266 .ops = &pfuze100_swb_regulator_ops, \
267 .type = REGULATOR_VOLTAGE, \
268 .id = _chip ## _ ## _name, \
269 .owner = THIS_MODULE, \
270 .volt_table = voltages, \
271 .vsel_reg = (base), \
272 .vsel_mask = (mask), \
273 .enable_reg = (base), \
274 .enable_mask = 0x48, \
275 }, \
276 }
277
278 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
279 [_chip ## _ ## _name] = { \
280 .desc = { \
281 .name = #_name, \
282 .n_voltages = ((max) - (min)) / (step) + 1, \
283 .ops = &pfuze100_ldo_regulator_ops, \
284 .type = REGULATOR_VOLTAGE, \
285 .id = _chip ## _ ## _name, \
286 .owner = THIS_MODULE, \
287 .min_uV = (min), \
288 .uV_step = (step), \
289 .vsel_reg = (base), \
290 .vsel_mask = 0xf, \
291 .enable_reg = (base), \
292 .enable_mask = 0x10, \
293 }, \
294 .stby_reg = (base), \
295 .stby_mask = 0x20, \
296 }
297
298 #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \
299 [_chip ## _ ## _name] = { \
300 .desc = { \
301 .name = #_name, \
302 .n_voltages = ARRAY_SIZE(voltages), \
303 .ops = &pfuze100_swb_regulator_ops, \
304 .type = REGULATOR_VOLTAGE, \
305 .id = _chip ## _ ## _name, \
306 .owner = THIS_MODULE, \
307 .volt_table = voltages, \
308 .vsel_reg = (base), \
309 .vsel_mask = (mask), \
310 .enable_reg = (base), \
311 .enable_mask = 0x8, \
312 }, \
313 }
314
315 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \
316 .desc = { \
317 .name = #_name, \
318 .n_voltages = ((max) - (min)) / (step) + 1, \
319 .ops = &pfuze100_ldo_regulator_ops, \
320 .type = REGULATOR_VOLTAGE, \
321 .id = _chip ## _ ## _name, \
322 .owner = THIS_MODULE, \
323 .min_uV = (min), \
324 .uV_step = (step), \
325 .vsel_reg = (base), \
326 .vsel_mask = 0x3, \
327 .enable_reg = (base), \
328 .enable_mask = 0x10, \
329 }, \
330 .stby_reg = (base), \
331 .stby_mask = 0x20, \
332 }
333
334 /* No linar case for the some switches of PFUZE3000 */
335 #define PFUZE3000_SW_REG(_chip, _name, base, mask, voltages) \
336 [_chip ## _ ## _name] = { \
337 .desc = { \
338 .name = #_name, \
339 .n_voltages = ARRAY_SIZE(voltages), \
340 .ops = &pfuze3000_sw_regulator_ops, \
341 .type = REGULATOR_VOLTAGE, \
342 .id = _chip ## _ ## _name, \
343 .owner = THIS_MODULE, \
344 .volt_table = voltages, \
345 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
346 .vsel_mask = (mask), \
347 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
348 .enable_mask = 0xf, \
349 .enable_val = 0x8, \
350 .enable_time = 500, \
351 }, \
352 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
353 .stby_mask = (mask), \
354 .sw_reg = true, \
355 }
356
357 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \
358 .desc = { \
359 .name = #_name,\
360 .n_voltages = ((max) - (min)) / (step) + 1, \
361 .ops = &pfuze100_sw_regulator_ops, \
362 .type = REGULATOR_VOLTAGE, \
363 .id = _chip ## _ ## _name, \
364 .owner = THIS_MODULE, \
365 .min_uV = (min), \
366 .uV_step = (step), \
367 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
368 .vsel_mask = 0xf, \
369 }, \
370 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
371 .stby_mask = 0xf, \
372 }
373
374 /* PFUZE100 */
375 static struct pfuze_regulator pfuze100_regulators[] = {
376 PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
377 PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
378 PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
379 PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
380 PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
381 PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
382 PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
383 PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
384 PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
385 PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
386 PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
387 PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
388 PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
389 PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
390 PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
391 PFUZE100_COIN_REG(PFUZE100, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
392 };
393
394 static struct pfuze_regulator pfuze200_regulators[] = {
395 PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
396 PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
397 PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
398 PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
399 PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
400 PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
401 PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
402 PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
403 PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
404 PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
405 PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
406 PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
407 PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
408 PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
409 };
410
411 static struct pfuze_regulator pfuze3000_regulators[] = {
412 PFUZE3000_SW_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
413 PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),
414 PFUZE3000_SW_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
415 PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
416 PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),
417 PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
418 PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000),
419 PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
420 PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
421 PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
422 PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
423 PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
424 PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
425 };
426
427 static struct pfuze_regulator pfuze3001_regulators[] = {
428 PFUZE3000_SW_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
429 PFUZE3000_SW_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
430 PFUZE3000_SW3_REG(PFUZE3001, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
431 PFUZE100_SWB_REG(PFUZE3001, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
432 PFUZE100_VGEN_REG(PFUZE3001, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
433 PFUZE100_VGEN_REG(PFUZE3001, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
434 PFUZE3000_VCC_REG(PFUZE3001, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
435 PFUZE3000_VCC_REG(PFUZE3001, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
436 PFUZE100_VGEN_REG(PFUZE3001, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
437 PFUZE100_VGEN_REG(PFUZE3001, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
438 };
439
440 #ifdef CONFIG_OF
441 /* PFUZE100 */
442 static struct of_regulator_match pfuze100_matches[] = {
443 { .name = "sw1ab", },
444 { .name = "sw1c", },
445 { .name = "sw2", },
446 { .name = "sw3a", },
447 { .name = "sw3b", },
448 { .name = "sw4", },
449 { .name = "swbst", },
450 { .name = "vsnvs", },
451 { .name = "vrefddr", },
452 { .name = "vgen1", },
453 { .name = "vgen2", },
454 { .name = "vgen3", },
455 { .name = "vgen4", },
456 { .name = "vgen5", },
457 { .name = "vgen6", },
458 { .name = "coin", },
459 };
460
461 /* PFUZE200 */
462 static struct of_regulator_match pfuze200_matches[] = {
463
464 { .name = "sw1ab", },
465 { .name = "sw2", },
466 { .name = "sw3a", },
467 { .name = "sw3b", },
468 { .name = "swbst", },
469 { .name = "vsnvs", },
470 { .name = "vrefddr", },
471 { .name = "vgen1", },
472 { .name = "vgen2", },
473 { .name = "vgen3", },
474 { .name = "vgen4", },
475 { .name = "vgen5", },
476 { .name = "vgen6", },
477 { .name = "coin", },
478 };
479
480 /* PFUZE3000 */
481 static struct of_regulator_match pfuze3000_matches[] = {
482
483 { .name = "sw1a", },
484 { .name = "sw1b", },
485 { .name = "sw2", },
486 { .name = "sw3", },
487 { .name = "swbst", },
488 { .name = "vsnvs", },
489 { .name = "vrefddr", },
490 { .name = "vldo1", },
491 { .name = "vldo2", },
492 { .name = "vccsd", },
493 { .name = "v33", },
494 { .name = "vldo3", },
495 { .name = "vldo4", },
496 };
497
498 /* PFUZE3001 */
499 static struct of_regulator_match pfuze3001_matches[] = {
500
501 { .name = "sw1", },
502 { .name = "sw2", },
503 { .name = "sw3", },
504 { .name = "vsnvs", },
505 { .name = "vldo1", },
506 { .name = "vldo2", },
507 { .name = "vccsd", },
508 { .name = "v33", },
509 { .name = "vldo3", },
510 { .name = "vldo4", },
511 };
512
513 static struct of_regulator_match *pfuze_matches;
514
515 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
516 {
517 struct device *dev = chip->dev;
518 struct device_node *np, *parent;
519 int ret;
520
521 np = of_node_get(dev->of_node);
522 if (!np)
523 return -EINVAL;
524
525 if (of_property_read_bool(np, "fsl,pfuze-support-disable-sw"))
526 chip->flags |= PFUZE_FLAG_DISABLE_SW;
527
528 parent = of_get_child_by_name(np, "regulators");
529 if (!parent) {
530 dev_err(dev, "regulators node not found\n");
531 return -EINVAL;
532 }
533
534 switch (chip->chip_id) {
535 case PFUZE3001:
536 pfuze_matches = pfuze3001_matches;
537 ret = of_regulator_match(dev, parent, pfuze3001_matches,
538 ARRAY_SIZE(pfuze3001_matches));
539 break;
540 case PFUZE3000:
541 pfuze_matches = pfuze3000_matches;
542 ret = of_regulator_match(dev, parent, pfuze3000_matches,
543 ARRAY_SIZE(pfuze3000_matches));
544 break;
545 case PFUZE200:
546 pfuze_matches = pfuze200_matches;
547 ret = of_regulator_match(dev, parent, pfuze200_matches,
548 ARRAY_SIZE(pfuze200_matches));
549 break;
550
551 case PFUZE100:
552 default:
553 pfuze_matches = pfuze100_matches;
554 ret = of_regulator_match(dev, parent, pfuze100_matches,
555 ARRAY_SIZE(pfuze100_matches));
556 break;
557 }
558
559 of_node_put(parent);
560 if (ret < 0) {
561 dev_err(dev, "Error parsing regulator init data: %d\n",
562 ret);
563 return ret;
564 }
565
566 return 0;
567 }
568
569 static inline struct regulator_init_data *match_init_data(int index)
570 {
571 return pfuze_matches[index].init_data;
572 }
573
574 static inline struct device_node *match_of_node(int index)
575 {
576 return pfuze_matches[index].of_node;
577 }
578 #else
579 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
580 {
581 return 0;
582 }
583
584 static inline struct regulator_init_data *match_init_data(int index)
585 {
586 return NULL;
587 }
588
589 static inline struct device_node *match_of_node(int index)
590 {
591 return NULL;
592 }
593 #endif
594
595 static struct pfuze_chip *syspm_pfuze_chip;
596
597 static void pfuze_power_off_prepare(void)
598 {
599 dev_info(syspm_pfuze_chip->dev, "Configure standby mode for power off");
600
601 /* Switch from default mode: APS/APS to APS/Off */
602 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1ABMODE,
603 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
604 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1CMODE,
605 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
606 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW2MODE,
607 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
608 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3AMODE,
609 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
610 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3BMODE,
611 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
612 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW4MODE,
613 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
614
615 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN1VOL,
616 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
617 PFUZE100_VGENxSTBY);
618 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN2VOL,
619 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
620 PFUZE100_VGENxSTBY);
621 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN3VOL,
622 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
623 PFUZE100_VGENxSTBY);
624 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN4VOL,
625 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
626 PFUZE100_VGENxSTBY);
627 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN5VOL,
628 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
629 PFUZE100_VGENxSTBY);
630 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN6VOL,
631 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
632 PFUZE100_VGENxSTBY);
633 }
634
635 static int pfuze_power_off_prepare_init(struct pfuze_chip *pfuze_chip)
636 {
637 if (pfuze_chip->chip_id != PFUZE100) {
638 dev_warn(pfuze_chip->dev, "Requested pm_power_off_prepare handler for not supported chip\n");
639 return -ENODEV;
640 }
641
642 if (pm_power_off_prepare) {
643 dev_warn(pfuze_chip->dev, "pm_power_off_prepare is already registered.\n");
644 return -EBUSY;
645 }
646
647 if (syspm_pfuze_chip) {
648 dev_warn(pfuze_chip->dev, "syspm_pfuze_chip is already set.\n");
649 return -EBUSY;
650 }
651
652 syspm_pfuze_chip = pfuze_chip;
653 pm_power_off_prepare = pfuze_power_off_prepare;
654
655 return 0;
656 }
657
658 static int pfuze_identify(struct pfuze_chip *pfuze_chip)
659 {
660 unsigned int value;
661 int ret;
662
663 ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
664 if (ret)
665 return ret;
666
667 if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
668 /*
669 * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
670 * as ID=8 in PFUZE100
671 */
672 dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
673 } else if ((value & 0x0f) != pfuze_chip->chip_id &&
674 (value & 0xf0) >> 4 != pfuze_chip->chip_id &&
675 (value != pfuze_chip->chip_id)) {
676 /* device id NOT match with your setting */
677 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
678 return -ENODEV;
679 }
680
681 ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
682 if (ret)
683 return ret;
684 dev_info(pfuze_chip->dev,
685 "Full layer: %x, Metal layer: %x\n",
686 (value & 0xf0) >> 4, value & 0x0f);
687
688 ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
689 if (ret)
690 return ret;
691 dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
692 (value & 0xc) >> 2, value & 0x3);
693
694 return 0;
695 }
696
697 static const struct regmap_config pfuze_regmap_config = {
698 .reg_bits = 8,
699 .val_bits = 8,
700 .max_register = PFUZE_NUMREGS - 1,
701 .cache_type = REGCACHE_RBTREE,
702 };
703
704 static int pfuze100_regulator_probe(struct i2c_client *client,
705 const struct i2c_device_id *id)
706 {
707 struct pfuze_chip *pfuze_chip;
708 struct pfuze_regulator_platform_data *pdata =
709 dev_get_platdata(&client->dev);
710 struct regulator_config config = { };
711 int i, ret;
712 const struct of_device_id *match;
713 u32 regulator_num;
714 u32 sw_check_start, sw_check_end, sw_hi = 0x40;
715
716 pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
717 GFP_KERNEL);
718 if (!pfuze_chip)
719 return -ENOMEM;
720
721 if (client->dev.of_node) {
722 match = of_match_device(of_match_ptr(pfuze_dt_ids),
723 &client->dev);
724 if (!match) {
725 dev_err(&client->dev, "Error: No device match found\n");
726 return -ENODEV;
727 }
728 pfuze_chip->chip_id = (int)(long)match->data;
729 } else if (id) {
730 pfuze_chip->chip_id = id->driver_data;
731 } else {
732 dev_err(&client->dev, "No dts match or id table match found\n");
733 return -ENODEV;
734 }
735
736 i2c_set_clientdata(client, pfuze_chip);
737 pfuze_chip->dev = &client->dev;
738
739 pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
740 if (IS_ERR(pfuze_chip->regmap)) {
741 ret = PTR_ERR(pfuze_chip->regmap);
742 dev_err(&client->dev,
743 "regmap allocation failed with err %d\n", ret);
744 return ret;
745 }
746
747 ret = pfuze_identify(pfuze_chip);
748 if (ret) {
749 dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
750 return ret;
751 }
752
753 /* use the right regulators after identify the right device */
754 switch (pfuze_chip->chip_id) {
755 case PFUZE3001:
756 pfuze_chip->pfuze_regulators = pfuze3001_regulators;
757 regulator_num = ARRAY_SIZE(pfuze3001_regulators);
758 sw_check_start = PFUZE3001_SW2;
759 sw_check_end = PFUZE3001_SW2;
760 sw_hi = 1 << 3;
761 break;
762 case PFUZE3000:
763 pfuze_chip->pfuze_regulators = pfuze3000_regulators;
764 regulator_num = ARRAY_SIZE(pfuze3000_regulators);
765 sw_check_start = PFUZE3000_SW2;
766 sw_check_end = PFUZE3000_SW2;
767 sw_hi = 1 << 3;
768 break;
769 case PFUZE200:
770 pfuze_chip->pfuze_regulators = pfuze200_regulators;
771 regulator_num = ARRAY_SIZE(pfuze200_regulators);
772 sw_check_start = PFUZE200_SW2;
773 sw_check_end = PFUZE200_SW3B;
774 break;
775 case PFUZE100:
776 default:
777 pfuze_chip->pfuze_regulators = pfuze100_regulators;
778 regulator_num = ARRAY_SIZE(pfuze100_regulators);
779 sw_check_start = PFUZE100_SW2;
780 sw_check_end = PFUZE100_SW4;
781 break;
782 }
783 dev_info(&client->dev, "pfuze%s found.\n",
784 (pfuze_chip->chip_id == PFUZE100) ? "100" :
785 (((pfuze_chip->chip_id == PFUZE200) ? "200" :
786 ((pfuze_chip->chip_id == PFUZE3000) ? "3000" : "3001"))));
787
788 memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators,
789 sizeof(pfuze_chip->regulator_descs));
790
791 ret = pfuze_parse_regulators_dt(pfuze_chip);
792 if (ret)
793 return ret;
794
795 for (i = 0; i < regulator_num; i++) {
796 struct regulator_init_data *init_data;
797 struct regulator_desc *desc;
798 int val;
799
800 desc = &pfuze_chip->regulator_descs[i].desc;
801
802 if (pdata)
803 init_data = pdata->init_data[i];
804 else
805 init_data = match_init_data(i);
806
807 /* SW2~SW4 high bit check and modify the voltage value table */
808 if (i >= sw_check_start && i <= sw_check_end) {
809 ret = regmap_read(pfuze_chip->regmap,
810 desc->vsel_reg, &val);
811 if (ret) {
812 dev_err(&client->dev, "Fails to read from the register.\n");
813 return ret;
814 }
815
816 if (val & sw_hi) {
817 if (pfuze_chip->chip_id == PFUZE3000 ||
818 pfuze_chip->chip_id == PFUZE3001) {
819 desc->volt_table = pfuze3000_sw2hi;
820 desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi);
821 } else {
822 desc->min_uV = 800000;
823 desc->uV_step = 50000;
824 desc->n_voltages = 51;
825 }
826 }
827 }
828
829 /*
830 * Allow SW regulators to turn off. Checking it trough a flag is
831 * a workaround to keep the backward compatibility with existing
832 * old dtb's which may relay on the fact that we didn't disable
833 * the switched regulator till yet.
834 */
835 if (pfuze_chip->flags & PFUZE_FLAG_DISABLE_SW) {
836 if (pfuze_chip->regulator_descs[i].sw_reg) {
837 desc->ops = &pfuze100_sw_disable_regulator_ops;
838 desc->enable_val = 0x8;
839 desc->disable_val = 0x0;
840 desc->enable_time = 500;
841 }
842 }
843
844 config.dev = &client->dev;
845 config.init_data = init_data;
846 config.driver_data = pfuze_chip;
847 config.of_node = match_of_node(i);
848
849 pfuze_chip->regulators[i] =
850 devm_regulator_register(&client->dev, desc, &config);
851 if (IS_ERR(pfuze_chip->regulators[i])) {
852 dev_err(&client->dev, "register regulator%s failed\n",
853 pfuze_chip->pfuze_regulators[i].desc.name);
854 return PTR_ERR(pfuze_chip->regulators[i]);
855 }
856 }
857
858 if (of_property_read_bool(client->dev.of_node,
859 "fsl,pmic-stby-poweroff"))
860 return pfuze_power_off_prepare_init(pfuze_chip);
861
862 return 0;
863 }
864
865 static int pfuze100_regulator_remove(struct i2c_client *client)
866 {
867 if (syspm_pfuze_chip) {
868 syspm_pfuze_chip = NULL;
869 pm_power_off_prepare = NULL;
870 }
871
872 return 0;
873 }
874
875 static struct i2c_driver pfuze_driver = {
876 .id_table = pfuze_device_id,
877 .driver = {
878 .name = "pfuze100-regulator",
879 .of_match_table = pfuze_dt_ids,
880 },
881 .probe = pfuze100_regulator_probe,
882 .remove = pfuze100_regulator_remove,
883 };
884 module_i2c_driver(pfuze_driver);
885
886 MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
887 MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000/3001 PMIC");
888 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support