drivers/video/fbdev/geode/lxfb.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /* Geode LX framebuffer driver
   3  *
   4  * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
   5  * Copyright (c) 2008  Andres Salomon <dilinger@debian.org>
   6  */
   7 #ifndef _LXFB_H_
   8 #define _LXFB_H_
   9
  10 #include <linux/fb.h>
  11
  12 #define GP_REG_COUNT    (0x7c / 4)
  13 #define DC_REG_COUNT    (0xf0 / 4)
  14 #define VP_REG_COUNT    (0x158 / 8)
  15 #define FP_REG_COUNT    (0x60 / 8)
  16
  17 #define DC_PAL_COUNT    0x104
  18 #define DC_HFILT_COUNT  0x100
  19 #define DC_VFILT_COUNT  0x100
  20 #define VP_COEFF_SIZE   0x1000
  21 #define VP_PAL_COUNT    0x100
  22
  23 #define OUTPUT_CRT   0x01
  24 #define OUTPUT_PANEL 0x02
  25
  26 struct lxfb_par {
  27         int output;
  28
  29         void __iomem *gp_regs;
  30         void __iomem *dc_regs;
  31         void __iomem *vp_regs;
  32 #ifdef CONFIG_PM
  33         int powered_down;
  34
  35         /* register state, for power mgmt functionality */
  36         struct {
  37                 uint64_t padsel;
  38                 uint64_t dotpll;
  39                 uint64_t dfglcfg;
  40                 uint64_t dcspare;
  41         } msr;
  42
  43         uint32_t gp[GP_REG_COUNT];
  44         uint32_t dc[DC_REG_COUNT];
  45         uint64_t vp[VP_REG_COUNT];
  46         uint64_t fp[FP_REG_COUNT];
  47
  48         uint32_t dc_pal[DC_PAL_COUNT];
  49         uint32_t vp_pal[VP_PAL_COUNT];
  50         uint32_t hcoeff[DC_HFILT_COUNT * 2];
  51         uint32_t vcoeff[DC_VFILT_COUNT];
  52         uint32_t vp_coeff[VP_COEFF_SIZE / 4];
  53 #endif
  54 };
  55
  56 static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
  57 {
  58         return (((xres * (bpp >> 3)) + 7) & ~7);
  59 }
  60
  61 void lx_set_mode(struct fb_info *);
  62 unsigned int lx_framebuffer_size(void);
  63 int lx_blank_display(struct fb_info *, int);
  64 void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
  65                         unsigned int, unsigned int);
  66
  67 #ifdef CONFIG_PM
  68 int lx_powerdown(struct fb_info *info);
  69 int lx_powerup(struct fb_info *info);
  70 #endif
  71
  72
  73 /* Graphics Processor registers (table 6-29 from the data book) */
  74 enum gp_registers {
  75         GP_DST_OFFSET = 0,
  76         GP_SRC_OFFSET,
  77         GP_STRIDE,
  78         GP_WID_HEIGHT,
  79
  80         GP_SRC_COLOR_FG,
  81         GP_SRC_COLOR_BG,
  82         GP_PAT_COLOR_0,
  83         GP_PAT_COLOR_1,
  84
  85         GP_PAT_COLOR_2,
  86         GP_PAT_COLOR_3,
  87         GP_PAT_COLOR_4,
  88         GP_PAT_COLOR_5,
  89
  90         GP_PAT_DATA_0,
  91         GP_PAT_DATA_1,
  92         GP_RASTER_MODE,
  93         GP_VECTOR_MODE,
  94
  95         GP_BLT_MODE,
  96         GP_BLT_STATUS,
  97         GP_HST_SRC,
  98         GP_BASE_OFFSET,
  99
 100         GP_CMD_TOP,
 101         GP_CMD_BOT,
 102         GP_CMD_READ,
 103         GP_CMD_WRITE,
 104
 105         GP_CH3_OFFSET,
 106         GP_CH3_MODE_STR,
 107         GP_CH3_WIDHI,
 108         GP_CH3_HSRC,
 109
 110         GP_LUT_INDEX,
 111         GP_LUT_DATA,
 112         GP_INT_CNTRL, /* 0x78 */
 113 };
 114
 115 #define GP_BLT_STATUS_CE                (1 << 4)        /* cmd buf empty */
 116 #define GP_BLT_STATUS_PB                (1 << 0)        /* primitive busy */
 117
 118
 119 /* Display Controller registers (table 6-47 from the data book) */
 120 enum dc_registers {
 121         DC_UNLOCK = 0,
 122         DC_GENERAL_CFG,
 123         DC_DISPLAY_CFG,
 124         DC_ARB_CFG,
 125
 126         DC_FB_ST_OFFSET,
 127         DC_CB_ST_OFFSET,
 128         DC_CURS_ST_OFFSET,
 129         DC_RSVD_0,
 130
 131         DC_VID_Y_ST_OFFSET,
 132         DC_VID_U_ST_OFFSET,
 133         DC_VID_V_ST_OFFSET,
 134         DC_DV_TOP,
 135
 136         DC_LINE_SIZE,
 137         DC_GFX_PITCH,
 138         DC_VID_YUV_PITCH,
 139         DC_RSVD_1,
 140
 141         DC_H_ACTIVE_TIMING,
 142         DC_H_BLANK_TIMING,
 143         DC_H_SYNC_TIMING,
 144         DC_RSVD_2,
 145
 146         DC_V_ACTIVE_TIMING,
 147         DC_V_BLANK_TIMING,
 148         DC_V_SYNC_TIMING,
 149         DC_FB_ACTIVE,
 150
 151         DC_CURSOR_X,
 152         DC_CURSOR_Y,
 153         DC_RSVD_3,
 154         DC_LINE_CNT,
 155
 156         DC_PAL_ADDRESS,
 157         DC_PAL_DATA,
 158         DC_DFIFO_DIAG,
 159         DC_CFIFO_DIAG,
 160
 161         DC_VID_DS_DELTA,
 162         DC_GLIU0_MEM_OFFSET,
 163         DC_DV_CTL,
 164         DC_DV_ACCESS,
 165
 166         DC_GFX_SCALE,
 167         DC_IRQ_FILT_CTL,
 168         DC_FILT_COEFF1,
 169         DC_FILT_COEFF2,
 170
 171         DC_VBI_EVEN_CTL,
 172         DC_VBI_ODD_CTL,
 173         DC_VBI_HOR,
 174         DC_VBI_LN_ODD,
 175
 176         DC_VBI_LN_EVEN,
 177         DC_VBI_PITCH,
 178         DC_CLR_KEY,
 179         DC_CLR_KEY_MASK,
 180
 181         DC_CLR_KEY_X,
 182         DC_CLR_KEY_Y,
 183         DC_IRQ,
 184         DC_RSVD_4,
 185
 186         DC_RSVD_5,
 187         DC_GENLK_CTL,
 188         DC_VID_EVEN_Y_ST_OFFSET,
 189         DC_VID_EVEN_U_ST_OFFSET,
 190
 191         DC_VID_EVEN_V_ST_OFFSET,
 192         DC_V_ACTIVE_EVEN_TIMING,
 193         DC_V_BLANK_EVEN_TIMING,
 194         DC_V_SYNC_EVEN_TIMING,  /* 0xec */
 195 };
 196
 197 #define DC_UNLOCK_LOCK                  0x00000000
 198 #define DC_UNLOCK_UNLOCK                0x00004758      /* magic value */
 199
 200 #define DC_GENERAL_CFG_FDTY             (1 << 17)
 201 #define DC_GENERAL_CFG_DFHPEL_SHIFT     (12)
 202 #define DC_GENERAL_CFG_DFHPSL_SHIFT     (8)
 203 #define DC_GENERAL_CFG_VGAE             (1 << 7)
 204 #define DC_GENERAL_CFG_DECE             (1 << 6)
 205 #define DC_GENERAL_CFG_CMPE             (1 << 5)
 206 #define DC_GENERAL_CFG_VIDE             (1 << 3)
 207 #define DC_GENERAL_CFG_DFLE             (1 << 0)
 208
 209 #define DC_DISPLAY_CFG_VISL             (1 << 27)
 210 #define DC_DISPLAY_CFG_PALB             (1 << 25)
 211 #define DC_DISPLAY_CFG_DCEN             (1 << 24)
 212 #define DC_DISPLAY_CFG_DISP_MODE_24BPP  (1 << 9)
 213 #define DC_DISPLAY_CFG_DISP_MODE_16BPP  (1 << 8)
 214 #define DC_DISPLAY_CFG_DISP_MODE_8BPP   (0)
 215 #define DC_DISPLAY_CFG_TRUP             (1 << 6)
 216 #define DC_DISPLAY_CFG_VDEN             (1 << 4)
 217 #define DC_DISPLAY_CFG_GDEN             (1 << 3)
 218 #define DC_DISPLAY_CFG_TGEN             (1 << 0)
 219
 220 #define DC_DV_TOP_DV_TOP_EN             (1 << 0)
 221
 222 #define DC_DV_CTL_DV_LINE_SIZE          ((1 << 10) | (1 << 11))
 223 #define DC_DV_CTL_DV_LINE_SIZE_1K       (0)
 224 #define DC_DV_CTL_DV_LINE_SIZE_2K       (1 << 10)
 225 #define DC_DV_CTL_DV_LINE_SIZE_4K       (1 << 11)
 226 #define DC_DV_CTL_DV_LINE_SIZE_8K       ((1 << 10) | (1 << 11))
 227 #define DC_DV_CTL_CLEAR_DV_RAM          (1 << 0)
 228
 229 #define DC_IRQ_FILT_CTL_H_FILT_SEL      (1 << 10)
 230
 231 #define DC_CLR_KEY_CLR_KEY_EN           (1 << 24)
 232
 233 #define DC_IRQ_VIP_VSYNC_IRQ_STATUS     (1 << 21)       /* undocumented? */
 234 #define DC_IRQ_STATUS                   (1 << 20)       /* undocumented? */
 235 #define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK  (1 << 1)
 236 #define DC_IRQ_MASK                     (1 << 0)
 237
 238 #define DC_GENLK_CTL_FLICK_SEL_MASK     (0x0F << 28)
 239 #define DC_GENLK_CTL_ALPHA_FLICK_EN     (1 << 25)
 240 #define DC_GENLK_CTL_FLICK_EN           (1 << 24)
 241 #define DC_GENLK_CTL_GENLK_EN           (1 << 18)
 242
 243
 244 /*
 245  * Video Processor registers (table 6-71).
 246  * There is space for 64 bit values, but we never use more than the
 247  * lower 32 bits.  The actual register save/restore code only bothers
 248  * to restore those 32 bits.
 249  */
 250 enum vp_registers {
 251         VP_VCFG = 0,
 252         VP_DCFG,
 253
 254         VP_VX,
 255         VP_VY,
 256
 257         VP_SCL,
 258         VP_VCK,
 259
 260         VP_VCM,
 261         VP_PAR,
 262
 263         VP_PDR,
 264         VP_SLR,
 265
 266         VP_MISC,
 267         VP_CCS,
 268
 269         VP_VYS,
 270         VP_VXS,
 271
 272         VP_RSVD_0,
 273         VP_VDC,
 274
 275         VP_RSVD_1,
 276         VP_CRC,
 277
 278         VP_CRC32,
 279         VP_VDE,
 280
 281         VP_CCK,
 282         VP_CCM,
 283
 284         VP_CC1,
 285         VP_CC2,
 286
 287         VP_A1X,
 288         VP_A1Y,
 289
 290         VP_A1C,
 291         VP_A1T,
 292
 293         VP_A2X,
 294         VP_A2Y,
 295
 296         VP_A2C,
 297         VP_A2T,
 298
 299         VP_A3X,
 300         VP_A3Y,
 301
 302         VP_A3C,
 303         VP_A3T,
 304
 305         VP_VRR,
 306         VP_AWT,
 307
 308         VP_VTM,
 309         VP_VYE,
 310
 311         VP_A1YE,
 312         VP_A2YE,
 313
 314         VP_A3YE,        /* 0x150 */
 315
 316         VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
 317 };
 318
 319 #define VP_VCFG_VID_EN                  (1 << 0)
 320
 321 #define VP_DCFG_GV_GAM                  (1 << 21)
 322 #define VP_DCFG_PWR_SEQ_DELAY           ((1 << 17) | (1 << 18) | (1 << 19))
 323 #define VP_DCFG_PWR_SEQ_DELAY_DEFAULT   (1 << 19)       /* undocumented */
 324 #define VP_DCFG_CRT_SYNC_SKW            ((1 << 14) | (1 << 15) | (1 << 16))
 325 #define VP_DCFG_CRT_SYNC_SKW_DEFAULT    (1 << 16)
 326 #define VP_DCFG_CRT_VSYNC_POL           (1 << 9)
 327 #define VP_DCFG_CRT_HSYNC_POL           (1 << 8)
 328 #define VP_DCFG_DAC_BL_EN               (1 << 3)
 329 #define VP_DCFG_VSYNC_EN                (1 << 2)
 330 #define VP_DCFG_HSYNC_EN                (1 << 1)
 331 #define VP_DCFG_CRT_EN                  (1 << 0)
 332
 333 #define VP_MISC_APWRDN                  (1 << 11)
 334 #define VP_MISC_DACPWRDN                (1 << 10)
 335 #define VP_MISC_BYP_BOTH                (1 << 0)
 336
 337
 338 /*
 339  * Flat Panel registers (table 6-71).
 340  * Also 64 bit registers; see above note about 32-bit handling.
 341  */
 342
 343 /* we're actually in the VP register space, starting at address 0x400 */
 344 #define VP_FP_START     0x400
 345
 346 enum fp_registers {
 347         FP_PT1 = 0,
 348         FP_PT2,
 349
 350         FP_PM,
 351         FP_DFC,
 352
 353         FP_RSVD_0,
 354         FP_RSVD_1,
 355
 356         FP_RSVD_2,
 357         FP_RSVD_3,
 358
 359         FP_RSVD_4,
 360         FP_DCA,
 361
 362         FP_DMD,
 363         FP_CRC, /* 0x458 */
 364 };
 365
 366 #define FP_PT2_HSP                      (1 << 22)
 367 #define FP_PT2_VSP                      (1 << 23)
 368 #define FP_PT2_SCRC                     (1 << 27)       /* shfclk free */
 369
 370 #define FP_PM_P                         (1 << 24)       /* panel power ctl */
 371 #define FP_PM_PANEL_PWR_UP              (1 << 3)        /* r/o */
 372 #define FP_PM_PANEL_PWR_DOWN            (1 << 2)        /* r/o */
 373 #define FP_PM_PANEL_OFF                 (1 << 1)        /* r/o */
 374 #define FP_PM_PANEL_ON                  (1 << 0)        /* r/o */
 375
 376 #define FP_DFC_BC                       ((1 << 4) | (1 << 5) | (1 << 6))
 377
 378
 379 /* register access functions */
 380
 381 static inline uint32_t read_gp(struct lxfb_par *par, int reg)
 382 {
 383         return readl(par->gp_regs + 4*reg);
 384 }
 385
 386 static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
 387 {
 388         writel(val, par->gp_regs + 4*reg);
 389 }
 390
 391 static inline uint32_t read_dc(struct lxfb_par *par, int reg)
 392 {
 393         return readl(par->dc_regs + 4*reg);
 394 }
 395
 396 static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
 397 {
 398         writel(val, par->dc_regs + 4*reg);
 399 }
 400
 401 static inline uint32_t read_vp(struct lxfb_par *par, int reg)
 402 {
 403         return readl(par->vp_regs + 8*reg);
 404 }
 405
 406 static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
 407 {
 408         writel(val, par->vp_regs + 8*reg);
 409 }
 410
 411 static inline uint32_t read_fp(struct lxfb_par *par, int reg)
 412 {
 413         return readl(par->vp_regs + 8*reg + VP_FP_START);
 414 }
 415
 416 static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
 417 {
 418         writel(val, par->vp_regs + 8*reg + VP_FP_START);
 419 }
 420
 421
 422 /* MSRs are defined in linux/cs5535.h; their bitfields are here */
 423
 424 #define MSR_GLCP_DOTPLL_LOCK            (1 << 25)       /* r/o */
 425 #define MSR_GLCP_DOTPLL_HALFPIX         (1 << 24)
 426 #define MSR_GLCP_DOTPLL_BYPASS          (1 << 15)
 427 #define MSR_GLCP_DOTPLL_DOTRESET        (1 << 0)
 428
 429 /* note: this is actually the VP's GLD_MSR_CONFIG */
 430 #define MSR_LX_GLD_MSR_CONFIG_FMT       ((1 << 3) | (1 << 4) | (1 << 5))
 431 #define MSR_LX_GLD_MSR_CONFIG_FMT_FP    (1 << 3)
 432 #define MSR_LX_GLD_MSR_CONFIG_FMT_CRT   (0)
 433 #define MSR_LX_GLD_MSR_CONFIG_FPC       (1 << 15)       /* FP *and* CRT */
 434
 435 #define MSR_LX_MSR_PADSEL_TFT_SEL_LOW   0xDFFFFFFF      /* ??? */
 436 #define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH  0x0000003F      /* ??? */
 437
 438 #define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO  (1 << 11)       /* undocumented */
 439 #define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL  (1 << 10)       /* undocumented */
 440 #define MSR_LX_SPARE_MSR_WM_LPEN_OVRD   (1 << 9)        /* undocumented */
 441 #define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8)        /* undocumented */
 442 #define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7)        /* undocumented */
 443 #define MSR_LX_SPARE_MSR_DIS_VIFO_WM    (1 << 6)
 444 #define MSR_LX_SPARE_MSR_DIS_CWD_CHECK  (1 << 5)        /* undocumented */
 445 #define MSR_LX_SPARE_MSR_PIX8_PAN_FIX   (1 << 4)        /* undocumented */
 446 #define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1)        /* undocumented */
 447
 448 #endif