drivers/iommu/intel_irq_remapping.c

   1 #include <linux/interrupt.h>
   2 #include <linux/dmar.h>
   3 #include <linux/spinlock.h>
   4 #include <linux/slab.h>
   5 #include <linux/jiffies.h>
   6 #include <linux/hpet.h>
   7 #include <linux/pci.h>
   8 #include <linux/irq.h>
   9 #include <linux/intel-iommu.h>
  10 #include <linux/acpi.h>
  11 #include <asm/io_apic.h>
  12 #include <asm/smp.h>
  13 #include <asm/cpu.h>
  14 #include <asm/irq_remapping.h>
  15 #include <asm/pci-direct.h>
  16 #include <asm/msidef.h>
  17
  18 #include "irq_remapping.h"
  19
  20 struct ioapic_scope {
  21         struct intel_iommu *iommu;
  22         unsigned int id;
  23         unsigned int bus;       /* PCI bus number */
  24         unsigned int devfn;     /* PCI devfn number */
  25 };
  26
  27 struct hpet_scope {
  28         struct intel_iommu *iommu;
  29         u8 id;
  30         unsigned int bus;
  31         unsigned int devfn;
  32 };
  33
  34 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
  35 #define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
  36
  37 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
  38 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
  39 static int ir_ioapic_num, ir_hpet_num;
  40
  41 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
  42
  43 static int __init parse_ioapics_under_ir(void);
  44
  45 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  46 {
  47         struct irq_cfg *cfg = irq_get_chip_data(irq);
  48         return cfg ? &cfg->irq_2_iommu : NULL;
  49 }
  50
  51 static int get_irte(int irq, struct irte *entry)
  52 {
  53         struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
  54         unsigned long flags;
  55         int index;
  56
  57         if (!entry || !irq_iommu)
  58                 return -1;
  59
  60         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
  61
  62         index = irq_iommu->irte_index + irq_iommu->sub_handle;
  63         *entry = *(irq_iommu->iommu->ir_table->base + index);
  64
  65         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
  66         return 0;
  67 }
  68
  69 static int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
  70 {
  71         struct ir_table *table = iommu->ir_table;
  72         struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
  73         struct irq_cfg *cfg = irq_get_chip_data(irq);
  74         unsigned int mask = 0;
  75         unsigned long flags;
  76         int index;
  77
  78         if (!count || !irq_iommu)
  79                 return -1;
  80
  81         if (count > 1) {
  82                 count = __roundup_pow_of_two(count);
  83                 mask = ilog2(count);
  84         }
  85
  86         if (mask > ecap_max_handle_mask(iommu->ecap)) {
  87                 printk(KERN_ERR
  88                        "Requested mask %x exceeds the max invalidation handle"
  89                        " mask value %Lx\n", mask,
  90                        ecap_max_handle_mask(iommu->ecap));
  91                 return -1;
  92         }
  93
  94         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
  95         index = bitmap_find_free_region(table->bitmap,
  96                                         INTR_REMAP_TABLE_ENTRIES, mask);
  97         if (index < 0) {
  98                 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
  99         } else {
 100                 cfg->remapped = 1;
 101                 irq_iommu->iommu = iommu;
 102                 irq_iommu->irte_index =  index;
 103                 irq_iommu->sub_handle = 0;
 104                 irq_iommu->irte_mask = mask;
 105         }
 106         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 107
 108         return index;
 109 }
 110
 111 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
 112 {
 113         struct qi_desc desc;
 114
 115         desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
 116                    | QI_IEC_SELECTIVE;
 117         desc.high = 0;
 118
 119         return qi_submit_sync(&desc, iommu);
 120 }
 121
 122 static int map_irq_to_irte_handle(int irq, u16 *sub_handle)
 123 {
 124         struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
 125         unsigned long flags;
 126         int index;
 127
 128         if (!irq_iommu)
 129                 return -1;
 130
 131         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 132         *sub_handle = irq_iommu->sub_handle;
 133         index = irq_iommu->irte_index;
 134         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 135         return index;
 136 }
 137
 138 static int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
 139 {
 140         struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
 141         struct irq_cfg *cfg = irq_get_chip_data(irq);
 142         unsigned long flags;
 143
 144         if (!irq_iommu)
 145                 return -1;
 146
 147         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 148
 149         cfg->remapped = 1;
 150         irq_iommu->iommu = iommu;
 151         irq_iommu->irte_index = index;
 152         irq_iommu->sub_handle = subhandle;
 153         irq_iommu->irte_mask = 0;
 154
 155         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 156
 157         return 0;
 158 }
 159
 160 static int modify_irte(int irq, struct irte *irte_modified)
 161 {
 162         struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
 163         struct intel_iommu *iommu;
 164         unsigned long flags;
 165         struct irte *irte;
 166         int rc, index;
 167
 168         if (!irq_iommu)
 169                 return -1;
 170
 171         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 172
 173         iommu = irq_iommu->iommu;
 174
 175         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 176         irte = &iommu->ir_table->base[index];
 177
 178         set_64bit(&irte->low, irte_modified->low);
 179         set_64bit(&irte->high, irte_modified->high);
 180         __iommu_flush_cache(iommu, irte, sizeof(*irte));
 181
 182         rc = qi_flush_iec(iommu, index, 0);
 183         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 184
 185         return rc;
 186 }
 187
 188 static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
 189 {
 190         int i;
 191
 192         for (i = 0; i < MAX_HPET_TBS; i++)
 193                 if (ir_hpet[i].id == hpet_id)
 194                         return ir_hpet[i].iommu;
 195         return NULL;
 196 }
 197
 198 static struct intel_iommu *map_ioapic_to_ir(int apic)
 199 {
 200         int i;
 201
 202         for (i = 0; i < MAX_IO_APICS; i++)
 203                 if (ir_ioapic[i].id == apic)
 204                         return ir_ioapic[i].iommu;
 205         return NULL;
 206 }
 207
 208 static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
 209 {
 210         struct dmar_drhd_unit *drhd;
 211
 212         drhd = dmar_find_matched_drhd_unit(dev);
 213         if (!drhd)
 214                 return NULL;
 215
 216         return drhd->iommu;
 217 }
 218
 219 static int clear_entries(struct irq_2_iommu *irq_iommu)
 220 {
 221         struct irte *start, *entry, *end;
 222         struct intel_iommu *iommu;
 223         int index;
 224
 225         if (irq_iommu->sub_handle)
 226                 return 0;
 227
 228         iommu = irq_iommu->iommu;
 229         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 230
 231         start = iommu->ir_table->base + index;
 232         end = start + (1 << irq_iommu->irte_mask);
 233
 234         for (entry = start; entry < end; entry++) {
 235                 set_64bit(&entry->low, 0);
 236                 set_64bit(&entry->high, 0);
 237         }
 238         bitmap_release_region(iommu->ir_table->bitmap, index,
 239                               irq_iommu->irte_mask);
 240
 241         return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 242 }
 243
 244 static int free_irte(int irq)
 245 {
 246         struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
 247         unsigned long flags;
 248         int rc;
 249
 250         if (!irq_iommu)
 251                 return -1;
 252
 253         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 254
 255         rc = clear_entries(irq_iommu);
 256
 257         irq_iommu->iommu = NULL;
 258         irq_iommu->irte_index = 0;
 259         irq_iommu->sub_handle = 0;
 260         irq_iommu->irte_mask = 0;
 261
 262         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 263
 264         return rc;
 265 }
 266
 267 /*
 268  * source validation type
 269  */
 270 #define SVT_NO_VERIFY           0x0  /* no verification is required */
 271 #define SVT_VERIFY_SID_SQ       0x1  /* verify using SID and SQ fields */
 272 #define SVT_VERIFY_BUS          0x2  /* verify bus of request-id */
 273
 274 /*
 275  * source-id qualifier
 276  */
 277 #define SQ_ALL_16       0x0  /* verify all 16 bits of request-id */
 278 #define SQ_13_IGNORE_1  0x1  /* verify most significant 13 bits, ignore
 279                               * the third least significant bit
 280                               */
 281 #define SQ_13_IGNORE_2  0x2  /* verify most significant 13 bits, ignore
 282                               * the second and third least significant bits
 283                               */
 284 #define SQ_13_IGNORE_3  0x3  /* verify most significant 13 bits, ignore
 285                               * the least three significant bits
 286                               */
 287
 288 /*
 289  * set SVT, SQ and SID fields of irte to verify
 290  * source ids of interrupt requests
 291  */
 292 static void set_irte_sid(struct irte *irte, unsigned int svt,
 293                          unsigned int sq, unsigned int sid)
 294 {
 295         if (disable_sourceid_checking)
 296                 svt = SVT_NO_VERIFY;
 297         irte->svt = svt;
 298         irte->sq = sq;
 299         irte->sid = sid;
 300 }
 301
 302 static int set_ioapic_sid(struct irte *irte, int apic)
 303 {
 304         int i;
 305         u16 sid = 0;
 306
 307         if (!irte)
 308                 return -1;
 309
 310         for (i = 0; i < MAX_IO_APICS; i++) {
 311                 if (ir_ioapic[i].id == apic) {
 312                         sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
 313                         break;
 314                 }
 315         }
 316
 317         if (sid == 0) {
 318                 pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic);
 319                 return -1;
 320         }
 321
 322         set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
 323
 324         return 0;
 325 }
 326
 327 static int set_hpet_sid(struct irte *irte, u8 id)
 328 {
 329         int i;
 330         u16 sid = 0;
 331
 332         if (!irte)
 333                 return -1;
 334
 335         for (i = 0; i < MAX_HPET_TBS; i++) {
 336                 if (ir_hpet[i].id == id) {
 337                         sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
 338                         break;
 339                 }
 340         }
 341
 342         if (sid == 0) {
 343                 pr_warning("Failed to set source-id of HPET block (%d)\n", id);
 344                 return -1;
 345         }
 346
 347         /*
 348          * Should really use SQ_ALL_16. Some platforms are broken.
 349          * While we figure out the right quirks for these broken platforms, use
 350          * SQ_13_IGNORE_3 for now.
 351          */
 352         set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
 353
 354         return 0;
 355 }
 356
 357 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
 358 {
 359         struct pci_dev *bridge;
 360
 361         if (!irte || !dev)
 362                 return -1;
 363
 364         /* PCIe device or Root Complex integrated PCI device */
 365         if (pci_is_pcie(dev) || !dev->bus->parent) {
 366                 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
 367                              (dev->bus->number << 8) | dev->devfn);
 368                 return 0;
 369         }
 370
 371         bridge = pci_find_upstream_pcie_bridge(dev);
 372         if (bridge) {
 373                 if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */
 374                         set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
 375                                 (bridge->bus->number << 8) | dev->bus->number);
 376                 else /* this is a legacy PCI bridge */
 377                         set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
 378                                 (bridge->bus->number << 8) | bridge->devfn);
 379         }
 380
 381         return 0;
 382 }
 383
 384 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
 385 {
 386         u64 addr;
 387         u32 sts;
 388         unsigned long flags;
 389
 390         addr = virt_to_phys((void *)iommu->ir_table->base);
 391
 392         raw_spin_lock_irqsave(&iommu->register_lock, flags);
 393
 394         dmar_writeq(iommu->reg + DMAR_IRTA_REG,
 395                     (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
 396
 397         /* Set interrupt-remapping table pointer */
 398         iommu->gcmd |= DMA_GCMD_SIRTP;
 399         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 400
 401         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 402                       readl, (sts & DMA_GSTS_IRTPS), sts);
 403         raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 404
 405         /*
 406          * global invalidation of interrupt entry cache before enabling
 407          * interrupt-remapping.
 408          */
 409         qi_global_iec(iommu);
 410
 411         raw_spin_lock_irqsave(&iommu->register_lock, flags);
 412
 413         /* Enable interrupt-remapping */
 414         iommu->gcmd |= DMA_GCMD_IRE;
 415         iommu->gcmd &= ~DMA_GCMD_CFI;  /* Block compatibility-format MSIs */
 416         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 417
 418         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 419                       readl, (sts & DMA_GSTS_IRES), sts);
 420
 421         /*
 422          * With CFI clear in the Global Command register, we should be
 423          * protected from dangerous (i.e. compatibility) interrupts
 424          * regardless of x2apic status.  Check just to be sure.
 425          */
 426         if (sts & DMA_GSTS_CFIS)
 427                 WARN(1, KERN_WARNING
 428                         "Compatibility-format IRQs enabled despite intr remapping;\n"
 429                         "you are vulnerable to IRQ injection.\n");
 430
 431         raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 432 }
 433
 434
 435 static int intel_setup_irq_remapping(struct intel_iommu *iommu, int mode)
 436 {
 437         struct ir_table *ir_table;
 438         struct page *pages;
 439         unsigned long *bitmap;
 440
 441         ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
 442                                              GFP_ATOMIC);
 443
 444         if (!iommu->ir_table)
 445                 return -ENOMEM;
 446
 447         pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,
 448                                  INTR_REMAP_PAGE_ORDER);
 449
 450         if (!pages) {
 451                 pr_err("IR%d: failed to allocate pages of order %d\n",
 452                        iommu->seq_id, INTR_REMAP_PAGE_ORDER);
 453                 kfree(iommu->ir_table);
 454                 return -ENOMEM;
 455         }
 456
 457         bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
 458                          sizeof(long), GFP_ATOMIC);
 459         if (bitmap == NULL) {
 460                 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
 461                 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
 462                 kfree(ir_table);
 463                 return -ENOMEM;
 464         }
 465
 466         ir_table->base = page_address(pages);
 467         ir_table->bitmap = bitmap;
 468
 469         iommu_set_irq_remapping(iommu, mode);
 470         return 0;
 471 }
 472
 473 /*
 474  * Disable Interrupt Remapping.
 475  */
 476 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
 477 {
 478         unsigned long flags;
 479         u32 sts;
 480
 481         if (!ecap_ir_support(iommu->ecap))
 482                 return;
 483
 484         /*
 485          * global invalidation of interrupt entry cache before disabling
 486          * interrupt-remapping.
 487          */
 488         qi_global_iec(iommu);
 489
 490         raw_spin_lock_irqsave(&iommu->register_lock, flags);
 491
 492         sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
 493         if (!(sts & DMA_GSTS_IRES))
 494                 goto end;
 495
 496         iommu->gcmd &= ~DMA_GCMD_IRE;
 497         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 498
 499         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 500                       readl, !(sts & DMA_GSTS_IRES), sts);
 501
 502 end:
 503         raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 504 }
 505
 506 static int __init dmar_x2apic_optout(void)
 507 {
 508         struct acpi_table_dmar *dmar;
 509         dmar = (struct acpi_table_dmar *)dmar_tbl;
 510         if (!dmar || no_x2apic_optout)
 511                 return 0;
 512         return dmar->flags & DMAR_X2APIC_OPT_OUT;
 513 }
 514
 515 static int __init intel_irq_remapping_supported(void)
 516 {
 517         struct dmar_drhd_unit *drhd;
 518         struct intel_iommu *iommu;
 519
 520         if (disable_irq_remap)
 521                 return 0;
 522         if (irq_remap_broken) {
 523                 printk(KERN_WARNING
 524                         "This system BIOS has enabled interrupt remapping\n"
 525                         "on a chipset that contains an erratum making that\n"
 526                         "feature unstable.  To maintain system stability\n"
 527                         "interrupt remapping is being disabled.  Please\n"
 528                         "contact your BIOS vendor for an update\n");
 529                 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 530                 disable_irq_remap = 1;
 531                 return 0;
 532         }
 533
 534         if (!dmar_ir_support())
 535                 return 0;
 536
 537         for_each_iommu(iommu, drhd)
 538                 if (!ecap_ir_support(iommu->ecap))
 539                         return 0;
 540
 541         return 1;
 542 }
 543
 544 static int __init intel_enable_irq_remapping(void)
 545 {
 546         struct dmar_drhd_unit *drhd;
 547         struct intel_iommu *iommu;
 548         bool x2apic_present;
 549         int setup = 0;
 550         int eim = 0;
 551
 552         x2apic_present = x2apic_supported();
 553
 554         if (parse_ioapics_under_ir() != 1) {
 555                 printk(KERN_INFO "Not enable interrupt remapping\n");
 556                 goto error;
 557         }
 558
 559         if (x2apic_present) {
 560                 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
 561
 562                 eim = !dmar_x2apic_optout();
 563                 if (!eim)
 564                         printk(KERN_WARNING
 565                                 "Your BIOS is broken and requested that x2apic be disabled.\n"
 566                                 "This will slightly decrease performance.\n"
 567                                 "Use 'intremap=no_x2apic_optout' to override BIOS request.\n");
 568         }
 569
 570         for_each_iommu(iommu, drhd) {
 571                 /*
 572                  * If the queued invalidation is already initialized,
 573                  * shouldn't disable it.
 574                  */
 575                 if (iommu->qi)
 576                         continue;
 577
 578                 /*
 579                  * Clear previous faults.
 580                  */
 581                 dmar_fault(-1, iommu);
 582
 583                 /*
 584                  * Disable intr remapping and queued invalidation, if already
 585                  * enabled prior to OS handover.
 586                  */
 587                 iommu_disable_irq_remapping(iommu);
 588
 589                 dmar_disable_qi(iommu);
 590         }
 591
 592         /*
 593          * check for the Interrupt-remapping support
 594          */
 595         for_each_iommu(iommu, drhd) {
 596                 if (!ecap_ir_support(iommu->ecap))
 597                         continue;
 598
 599                 if (eim && !ecap_eim_support(iommu->ecap)) {
 600                         printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
 601                                " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
 602                         goto error;
 603                 }
 604         }
 605
 606         /*
 607          * Enable queued invalidation for all the DRHD's.
 608          */
 609         for_each_iommu(iommu, drhd) {
 610                 int ret = dmar_enable_qi(iommu);
 611
 612                 if (ret) {
 613                         printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
 614                                " invalidation, ecap %Lx, ret %d\n",
 615                                drhd->reg_base_addr, iommu->ecap, ret);
 616                         goto error;
 617                 }
 618         }
 619
 620         /*
 621          * Setup Interrupt-remapping for all the DRHD's now.
 622          */
 623         for_each_iommu(iommu, drhd) {
 624                 if (!ecap_ir_support(iommu->ecap))
 625                         continue;
 626
 627                 if (intel_setup_irq_remapping(iommu, eim))
 628                         goto error;
 629
 630                 setup = 1;
 631         }
 632
 633         if (!setup)
 634                 goto error;
 635
 636         irq_remapping_enabled = 1;
 637
 638         /*
 639          * VT-d has a different layout for IO-APIC entries when
 640          * interrupt remapping is enabled. So it needs a special routine
 641          * to print IO-APIC entries for debugging purposes too.
 642          */
 643         x86_io_apic_ops.print_entries = intel_ir_io_apic_print_entries;
 644
 645         pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic");
 646
 647         return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
 648
 649 error:
 650         /*
 651          * handle error condition gracefully here!
 652          */
 653
 654         if (x2apic_present)
 655                 pr_warn("Failed to enable irq remapping.  You are vulnerable to irq-injection attacks.\n");
 656
 657         return -1;
 658 }
 659
 660 static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
 661                                       struct intel_iommu *iommu)
 662 {
 663         struct acpi_dmar_pci_path *path;
 664         u8 bus;
 665         int count;
 666
 667         bus = scope->bus;
 668         path = (struct acpi_dmar_pci_path *)(scope + 1);
 669         count = (scope->length - sizeof(struct acpi_dmar_device_scope))
 670                 / sizeof(struct acpi_dmar_pci_path);
 671
 672         while (--count > 0) {
 673                 /*
 674                  * Access PCI directly due to the PCI
 675                  * subsystem isn't initialized yet.
 676                  */
 677                 bus = read_pci_config_byte(bus, path->device, path->function,
 678                                            PCI_SECONDARY_BUS);
 679                 path++;
 680         }
 681         ir_hpet[ir_hpet_num].bus   = bus;
 682         ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->device, path->function);
 683         ir_hpet[ir_hpet_num].iommu = iommu;
 684         ir_hpet[ir_hpet_num].id    = scope->enumeration_id;
 685         ir_hpet_num++;
 686 }
 687
 688 static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
 689                                       struct intel_iommu *iommu)
 690 {
 691         struct acpi_dmar_pci_path *path;
 692         u8 bus;
 693         int count;
 694
 695         bus = scope->bus;
 696         path = (struct acpi_dmar_pci_path *)(scope + 1);
 697         count = (scope->length - sizeof(struct acpi_dmar_device_scope))
 698                 / sizeof(struct acpi_dmar_pci_path);
 699
 700         while (--count > 0) {
 701                 /*
 702                  * Access PCI directly due to the PCI
 703                  * subsystem isn't initialized yet.
 704                  */
 705                 bus = read_pci_config_byte(bus, path->device, path->function,
 706                                            PCI_SECONDARY_BUS);
 707                 path++;
 708         }
 709
 710         ir_ioapic[ir_ioapic_num].bus   = bus;
 711         ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->device, path->function);
 712         ir_ioapic[ir_ioapic_num].iommu = iommu;
 713         ir_ioapic[ir_ioapic_num].id    = scope->enumeration_id;
 714         ir_ioapic_num++;
 715 }
 716
 717 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
 718                                       struct intel_iommu *iommu)
 719 {
 720         struct acpi_dmar_hardware_unit *drhd;
 721         struct acpi_dmar_device_scope *scope;
 722         void *start, *end;
 723
 724         drhd = (struct acpi_dmar_hardware_unit *)header;
 725
 726         start = (void *)(drhd + 1);
 727         end = ((void *)drhd) + header->length;
 728
 729         while (start < end) {
 730                 scope = start;
 731                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
 732                         if (ir_ioapic_num == MAX_IO_APICS) {
 733                                 printk(KERN_WARNING "Exceeded Max IO APICS\n");
 734                                 return -1;
 735                         }
 736
 737                         printk(KERN_INFO "IOAPIC id %d under DRHD base "
 738                                " 0x%Lx IOMMU %d\n", scope->enumeration_id,
 739                                drhd->address, iommu->seq_id);
 740
 741                         ir_parse_one_ioapic_scope(scope, iommu);
 742                 } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) {
 743                         if (ir_hpet_num == MAX_HPET_TBS) {
 744                                 printk(KERN_WARNING "Exceeded Max HPET blocks\n");
 745                                 return -1;
 746                         }
 747
 748                         printk(KERN_INFO "HPET id %d under DRHD base"
 749                                " 0x%Lx\n", scope->enumeration_id,
 750                                drhd->address);
 751
 752                         ir_parse_one_hpet_scope(scope, iommu);
 753                 }
 754                 start += scope->length;
 755         }
 756
 757         return 0;
 758 }
 759
 760 /*
 761  * Finds the assocaition between IOAPIC's and its Interrupt-remapping
 762  * hardware unit.
 763  */
 764 static int __init parse_ioapics_under_ir(void)
 765 {
 766         struct dmar_drhd_unit *drhd;
 767         struct intel_iommu *iommu;
 768         int ir_supported = 0;
 769         int ioapic_idx;
 770
 771         for_each_iommu(iommu, drhd)
 772                 if (ecap_ir_support(iommu->ecap)) {
 773                         if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
 774                                 return -1;
 775
 776                         ir_supported = 1;
 777                 }
 778
 779         if (!ir_supported)
 780                 return 0;
 781
 782         for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
 783                 int ioapic_id = mpc_ioapic_id(ioapic_idx);
 784                 if (!map_ioapic_to_ir(ioapic_id)) {
 785                         pr_err(FW_BUG "ioapic %d has no mapping iommu, "
 786                                "interrupt remapping will be disabled\n",
 787                                ioapic_id);
 788                         return -1;
 789                 }
 790         }
 791
 792         return 1;
 793 }
 794
 795 static int __init ir_dev_scope_init(void)
 796 {
 797         if (!irq_remapping_enabled)
 798                 return 0;
 799
 800         return dmar_dev_scope_init();
 801 }
 802 rootfs_initcall(ir_dev_scope_init);
 803
 804 static void disable_irq_remapping(void)
 805 {
 806         struct dmar_drhd_unit *drhd;
 807         struct intel_iommu *iommu = NULL;
 808
 809         /*
 810          * Disable Interrupt-remapping for all the DRHD's now.
 811          */
 812         for_each_iommu(iommu, drhd) {
 813                 if (!ecap_ir_support(iommu->ecap))
 814                         continue;
 815
 816                 iommu_disable_irq_remapping(iommu);
 817         }
 818 }
 819
 820 static int reenable_irq_remapping(int eim)
 821 {
 822         struct dmar_drhd_unit *drhd;
 823         int setup = 0;
 824         struct intel_iommu *iommu = NULL;
 825
 826         for_each_iommu(iommu, drhd)
 827                 if (iommu->qi)
 828                         dmar_reenable_qi(iommu);
 829
 830         /*
 831          * Setup Interrupt-remapping for all the DRHD's now.
 832          */
 833         for_each_iommu(iommu, drhd) {
 834                 if (!ecap_ir_support(iommu->ecap))
 835                         continue;
 836
 837                 /* Set up interrupt remapping for iommu.*/
 838                 iommu_set_irq_remapping(iommu, eim);
 839                 setup = 1;
 840         }
 841
 842         if (!setup)
 843                 goto error;
 844
 845         return 0;
 846
 847 error:
 848         /*
 849          * handle error condition gracefully here!
 850          */
 851         return -1;
 852 }
 853
 854 static void prepare_irte(struct irte *irte, int vector,
 855                          unsigned int dest)
 856 {
 857         memset(irte, 0, sizeof(*irte));
 858
 859         irte->present = 1;
 860         irte->dst_mode = apic->irq_dest_mode;
 861         /*
 862          * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
 863          * actual level or edge trigger will be setup in the IO-APIC
 864          * RTE. This will help simplify level triggered irq migration.
 865          * For more details, see the comments (in io_apic.c) explainig IO-APIC
 866          * irq migration in the presence of interrupt-remapping.
 867         */
 868         irte->trigger_mode = 0;
 869         irte->dlvry_mode = apic->irq_delivery_mode;
 870         irte->vector = vector;
 871         irte->dest_id = IRTE_DEST(dest);
 872         irte->redir_hint = 1;
 873 }
 874
 875 static int intel_setup_ioapic_entry(int irq,
 876                                     struct IO_APIC_route_entry *route_entry,
 877                                     unsigned int destination, int vector,
 878                                     struct io_apic_irq_attr *attr)
 879 {
 880         int ioapic_id = mpc_ioapic_id(attr->ioapic);
 881         struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id);
 882         struct IR_IO_APIC_route_entry *entry;
 883         struct irte irte;
 884         int index;
 885
 886         if (!iommu) {
 887                 pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
 888                 return -ENODEV;
 889         }
 890
 891         entry = (struct IR_IO_APIC_route_entry *)route_entry;
 892
 893         index = alloc_irte(iommu, irq, 1);
 894         if (index < 0) {
 895                 pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id);
 896                 return -ENOMEM;
 897         }
 898
 899         prepare_irte(&irte, vector, destination);
 900
 901         /* Set source-id of interrupt request */
 902         set_ioapic_sid(&irte, ioapic_id);
 903
 904         modify_irte(irq, &irte);
 905
 906         apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
 907                 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
 908                 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
 909                 "Avail:%X Vector:%02X Dest:%08X "
 910                 "SID:%04X SQ:%X SVT:%X)\n",
 911                 attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
 912                 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
 913                 irte.avail, irte.vector, irte.dest_id,
 914                 irte.sid, irte.sq, irte.svt);
 915
 916         memset(entry, 0, sizeof(*entry));
 917
 918         entry->index2   = (index >> 15) & 0x1;
 919         entry->zero     = 0;
 920         entry->format   = 1;
 921         entry->index    = (index & 0x7fff);
 922         /*
 923          * IO-APIC RTE will be configured with virtual vector.
 924          * irq handler will do the explicit EOI to the io-apic.
 925          */
 926         entry->vector   = attr->ioapic_pin;
 927         entry->mask     = 0;                    /* enable IRQ */
 928         entry->trigger  = attr->trigger;
 929         entry->polarity = attr->polarity;
 930
 931         /* Mask level triggered irqs.
 932          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
 933          */
 934         if (attr->trigger)
 935                 entry->mask = 1;
 936
 937         return 0;
 938 }
 939
 940 /*
 941  * Migrate the IO-APIC irq in the presence of intr-remapping.
 942  *
 943  * For both level and edge triggered, irq migration is a simple atomic
 944  * update(of vector and cpu destination) of IRTE and flush the hardware cache.
 945  *
 946  * For level triggered, we eliminate the io-apic RTE modification (with the
 947  * updated vector information), by using a virtual vector (io-apic pin number).
 948  * Real vector that is used for interrupting cpu will be coming from
 949  * the interrupt-remapping table entry.
 950  *
 951  * As the migration is a simple atomic update of IRTE, the same mechanism
 952  * is used to migrate MSI irq's in the presence of interrupt-remapping.
 953  */
 954 static int
 955 intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
 956                           bool force)
 957 {
 958         struct irq_cfg *cfg = data->chip_data;
 959         unsigned int dest, irq = data->irq;
 960         struct irte irte;
 961         int err;
 962
 963         if (!config_enabled(CONFIG_SMP))
 964                 return -EINVAL;
 965
 966         if (!cpumask_intersects(mask, cpu_online_mask))
 967                 return -EINVAL;
 968
 969         if (get_irte(irq, &irte))
 970                 return -EBUSY;
 971
 972         err = assign_irq_vector(irq, cfg, mask);
 973         if (err)
 974                 return err;
 975
 976         err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
 977         if (err) {
 978                 if (assign_irq_vector(irq, cfg, data->affinity))
 979                         pr_err("Failed to recover vector for irq %d\n", irq);
 980                 return err;
 981         }
 982
 983         irte.vector = cfg->vector;
 984         irte.dest_id = IRTE_DEST(dest);
 985
 986         /*
 987          * Atomically updates the IRTE with the new destination, vector
 988          * and flushes the interrupt entry cache.
 989          */
 990         modify_irte(irq, &irte);
 991
 992         /*
 993          * After this point, all the interrupts will start arriving
 994          * at the new destination. So, time to cleanup the previous
 995          * vector allocation.
 996          */
 997         if (cfg->move_in_progress)
 998                 send_cleanup_vector(cfg);
 999
1000         cpumask_copy(data->affinity, mask);
1001         return 0;
1002 }
1003
1004 static void intel_compose_msi_msg(struct pci_dev *pdev,
1005                                   unsigned int irq, unsigned int dest,
1006                                   struct msi_msg *msg, u8 hpet_id)
1007 {
1008         struct irq_cfg *cfg;
1009         struct irte irte;
1010         u16 sub_handle = 0;
1011         int ir_index;
1012
1013         cfg = irq_get_chip_data(irq);
1014
1015         ir_index = map_irq_to_irte_handle(irq, &sub_handle);
1016         BUG_ON(ir_index == -1);
1017
1018         prepare_irte(&irte, cfg->vector, dest);
1019
1020         /* Set source-id of interrupt request */
1021         if (pdev)
1022                 set_msi_sid(&irte, pdev);
1023         else
1024                 set_hpet_sid(&irte, hpet_id);
1025
1026         modify_irte(irq, &irte);
1027
1028         msg->address_hi = MSI_ADDR_BASE_HI;
1029         msg->data = sub_handle;
1030         msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1031                           MSI_ADDR_IR_SHV |
1032                           MSI_ADDR_IR_INDEX1(ir_index) |
1033                           MSI_ADDR_IR_INDEX2(ir_index);
1034 }
1035
1036 /*
1037  * Map the PCI dev to the corresponding remapping hardware unit
1038  * and allocate 'nvec' consecutive interrupt-remapping table entries
1039  * in it.
1040  */
1041 static int intel_msi_alloc_irq(struct pci_dev *dev, int irq, int nvec)
1042 {
1043         struct intel_iommu *iommu;
1044         int index;
1045
1046         iommu = map_dev_to_ir(dev);
1047         if (!iommu) {
1048                 printk(KERN_ERR
1049                        "Unable to map PCI %s to iommu\n", pci_name(dev));
1050                 return -ENOENT;
1051         }
1052
1053         index = alloc_irte(iommu, irq, nvec);
1054         if (index < 0) {
1055                 printk(KERN_ERR
1056                        "Unable to allocate %d IRTE for PCI %s\n", nvec,
1057                        pci_name(dev));
1058                 return -ENOSPC;
1059         }
1060         return index;
1061 }
1062
1063 static int intel_msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
1064                                int index, int sub_handle)
1065 {
1066         struct intel_iommu *iommu;
1067
1068         iommu = map_dev_to_ir(pdev);
1069         if (!iommu)
1070                 return -ENOENT;
1071         /*
1072          * setup the mapping between the irq and the IRTE
1073          * base index, the sub_handle pointing to the
1074          * appropriate interrupt remap table entry.
1075          */
1076         set_irte_irq(irq, iommu, index, sub_handle);
1077
1078         return 0;
1079 }
1080
1081 static int intel_setup_hpet_msi(unsigned int irq, unsigned int id)
1082 {
1083         struct intel_iommu *iommu = map_hpet_to_ir(id);
1084         int index;
1085
1086         if (!iommu)
1087                 return -1;
1088
1089         index = alloc_irte(iommu, irq, 1);
1090         if (index < 0)
1091                 return -1;
1092
1093         return 0;
1094 }
1095
1096 struct irq_remap_ops intel_irq_remap_ops = {
1097         .supported              = intel_irq_remapping_supported,
1098         .prepare                = dmar_table_init,
1099         .enable                 = intel_enable_irq_remapping,
1100         .disable                = disable_irq_remapping,
1101         .reenable               = reenable_irq_remapping,
1102         .enable_faulting        = enable_drhd_fault_handling,
1103         .setup_ioapic_entry     = intel_setup_ioapic_entry,
1104         .set_affinity           = intel_ioapic_set_affinity,
1105         .free_irq               = free_irte,
1106         .compose_msi_msg        = intel_compose_msi_msg,
1107         .msi_alloc_irq          = intel_msi_alloc_irq,
1108         .msi_setup_irq          = intel_msi_setup_irq,
1109         .setup_hpet_msi         = intel_setup_hpet_msi,
1110 };