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Staging: unisys: Remove RETINT macro
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / hw.c
blob303ce27964c14c3469d245632c6f5739289520b0
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/time.h>
21 #include <linux/bitops.h>
22 #include <asm/unaligned.h>
23
24 #include "hw.h"
25 #include "hw-ops.h"
26 #include "rc.h"
27 #include "ar9003_mac.h"
28 #include "ar9003_mci.h"
29 #include "ar9003_phy.h"
30 #include "debug.h"
31 #include "ath9k.h"
32
33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
34
35 MODULE_AUTHOR("Atheros Communications");
36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38 MODULE_LICENSE("Dual BSD/GPL");
39
40 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
41 {
42 struct ath_common *common = ath9k_hw_common(ah);
43 struct ath9k_channel *chan = ah->curchan;
44 unsigned int clockrate;
45
46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
48 clockrate = 117;
49 else if (!chan) /* should really check for CCK instead */
50 clockrate = ATH9K_CLOCK_RATE_CCK;
51 else if (IS_CHAN_2GHZ(chan))
52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
55 else
56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
57
58 if (chan) {
59 if (IS_CHAN_HT40(chan))
60 clockrate *= 2;
61 if (IS_CHAN_HALF_RATE(chan))
62 clockrate /= 2;
63 if (IS_CHAN_QUARTER_RATE(chan))
64 clockrate /= 4;
65 }
66
67 common->clockrate = clockrate;
68 }
69
70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
71 {
72 struct ath_common *common = ath9k_hw_common(ah);
73
74 return usecs * common->clockrate;
75 }
76
77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
78 {
79 int i;
80
81 BUG_ON(timeout < AH_TIME_QUANTUM);
82
83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
84 if ((REG_READ(ah, reg) & mask) == val)
85 return true;
86
87 udelay(AH_TIME_QUANTUM);
88 }
89
90 ath_dbg(ath9k_hw_common(ah), ANY,
91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
92 timeout, reg, REG_READ(ah, reg), mask, val);
93
94 return false;
95 }
96 EXPORT_SYMBOL(ath9k_hw_wait);
97
98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
99 int hw_delay)
100 {
101 hw_delay /= 10;
102
103 if (IS_CHAN_HALF_RATE(chan))
104 hw_delay *= 2;
105 else if (IS_CHAN_QUARTER_RATE(chan))
106 hw_delay *= 4;
107
108 udelay(hw_delay + BASE_ACTIVATE_DELAY);
109 }
110
111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
112 int column, unsigned int *writecnt)
113 {
114 int r;
115
116 ENABLE_REGWRITE_BUFFER(ah);
117 for (r = 0; r < array->ia_rows; r++) {
118 REG_WRITE(ah, INI_RA(array, r, 0),
119 INI_RA(array, r, column));
120 DO_DELAY(*writecnt);
121 }
122 REGWRITE_BUFFER_FLUSH(ah);
123 }
124
125 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
126 {
127 u32 retval;
128 int i;
129
130 for (i = 0, retval = 0; i < n; i++) {
131 retval = (retval << 1) | (val & 1);
132 val >>= 1;
133 }
134 return retval;
135 }
136
137 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
138 u8 phy, int kbps,
139 u32 frameLen, u16 rateix,
140 bool shortPreamble)
141 {
142 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
143
144 if (kbps == 0)
145 return 0;
146
147 switch (phy) {
148 case WLAN_RC_PHY_CCK:
149 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
150 if (shortPreamble)
151 phyTime >>= 1;
152 numBits = frameLen << 3;
153 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
154 break;
155 case WLAN_RC_PHY_OFDM:
156 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
157 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
158 numBits = OFDM_PLCP_BITS + (frameLen << 3);
159 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
160 txTime = OFDM_SIFS_TIME_QUARTER
161 + OFDM_PREAMBLE_TIME_QUARTER
162 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
163 } else if (ah->curchan &&
164 IS_CHAN_HALF_RATE(ah->curchan)) {
165 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
166 numBits = OFDM_PLCP_BITS + (frameLen << 3);
167 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
168 txTime = OFDM_SIFS_TIME_HALF +
169 OFDM_PREAMBLE_TIME_HALF
170 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
171 } else {
172 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
173 numBits = OFDM_PLCP_BITS + (frameLen << 3);
174 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
175 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
176 + (numSymbols * OFDM_SYMBOL_TIME);
177 }
178 break;
179 default:
180 ath_err(ath9k_hw_common(ah),
181 "Unknown phy %u (rate ix %u)\n", phy, rateix);
182 txTime = 0;
183 break;
184 }
185
186 return txTime;
187 }
188 EXPORT_SYMBOL(ath9k_hw_computetxtime);
189
190 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
191 struct ath9k_channel *chan,
192 struct chan_centers *centers)
193 {
194 int8_t extoff;
195
196 if (!IS_CHAN_HT40(chan)) {
197 centers->ctl_center = centers->ext_center =
198 centers->synth_center = chan->channel;
199 return;
200 }
201
202 if (IS_CHAN_HT40PLUS(chan)) {
203 centers->synth_center =
204 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
205 extoff = 1;
206 } else {
207 centers->synth_center =
208 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
209 extoff = -1;
210 }
211
212 centers->ctl_center =
213 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
214 /* 25 MHz spacing is supported by hw but not on upper layers */
215 centers->ext_center =
216 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
217 }
218
219 /******************/
220 /* Chip Revisions */
221 /******************/
222
223 static void ath9k_hw_read_revisions(struct ath_hw *ah)
224 {
225 u32 val;
226
227 switch (ah->hw_version.devid) {
228 case AR5416_AR9100_DEVID:
229 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
230 break;
231 case AR9300_DEVID_AR9330:
232 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
233 if (ah->get_mac_revision) {
234 ah->hw_version.macRev = ah->get_mac_revision();
235 } else {
236 val = REG_READ(ah, AR_SREV);
237 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
238 }
239 return;
240 case AR9300_DEVID_AR9340:
241 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
242 val = REG_READ(ah, AR_SREV);
243 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
244 return;
245 case AR9300_DEVID_QCA955X:
246 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
247 return;
248 case AR9300_DEVID_AR953X:
249 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
250 return;
251 }
252
253 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
254
255 if (val == 0xFF) {
256 val = REG_READ(ah, AR_SREV);
257 ah->hw_version.macVersion =
258 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
259 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
260
261 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
262 ah->is_pciexpress = true;
263 else
264 ah->is_pciexpress = (val &
265 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
266 } else {
267 if (!AR_SREV_9100(ah))
268 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
269
270 ah->hw_version.macRev = val & AR_SREV_REVISION;
271
272 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
273 ah->is_pciexpress = true;
274 }
275 }
276
277 /************************************/
278 /* HW Attach, Detach, Init Routines */
279 /************************************/
280
281 static void ath9k_hw_disablepcie(struct ath_hw *ah)
282 {
283 if (!AR_SREV_5416(ah))
284 return;
285
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
295
296 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
297 }
298
299 /* This should work for all families including legacy */
300 static bool ath9k_hw_chip_test(struct ath_hw *ah)
301 {
302 struct ath_common *common = ath9k_hw_common(ah);
303 u32 regAddr[2] = { AR_STA_ID0 };
304 u32 regHold[2];
305 static const u32 patternData[4] = {
306 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
307 };
308 int i, j, loop_max;
309
310 if (!AR_SREV_9300_20_OR_LATER(ah)) {
311 loop_max = 2;
312 regAddr[1] = AR_PHY_BASE + (8 << 2);
313 } else
314 loop_max = 1;
315
316 for (i = 0; i < loop_max; i++) {
317 u32 addr = regAddr[i];
318 u32 wrData, rdData;
319
320 regHold[i] = REG_READ(ah, addr);
321 for (j = 0; j < 0x100; j++) {
322 wrData = (j << 16) | j;
323 REG_WRITE(ah, addr, wrData);
324 rdData = REG_READ(ah, addr);
325 if (rdData != wrData) {
326 ath_err(common,
327 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
328 addr, wrData, rdData);
329 return false;
330 }
331 }
332 for (j = 0; j < 4; j++) {
333 wrData = patternData[j];
334 REG_WRITE(ah, addr, wrData);
335 rdData = REG_READ(ah, addr);
336 if (wrData != rdData) {
337 ath_err(common,
338 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
339 addr, wrData, rdData);
340 return false;
341 }
342 }
343 REG_WRITE(ah, regAddr[i], regHold[i]);
344 }
345 udelay(100);
346
347 return true;
348 }
349
350 static void ath9k_hw_init_config(struct ath_hw *ah)
351 {
352 struct ath_common *common = ath9k_hw_common(ah);
353
354 ah->config.dma_beacon_response_time = 1;
355 ah->config.sw_beacon_response_time = 6;
356 ah->config.cwm_ignore_extcca = 0;
357 ah->config.analog_shiftreg = 1;
358
359 ah->config.rx_intr_mitigation = true;
360
361 if (AR_SREV_9300_20_OR_LATER(ah)) {
362 ah->config.rimt_last = 500;
363 ah->config.rimt_first = 2000;
364 } else {
365 ah->config.rimt_last = 250;
366 ah->config.rimt_first = 700;
367 }
368
369 /*
370 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
371 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
372 * This means we use it for all AR5416 devices, and the few
373 * minor PCI AR9280 devices out there.
374 *
375 * Serialization is required because these devices do not handle
376 * well the case of two concurrent reads/writes due to the latency
377 * involved. During one read/write another read/write can be issued
378 * on another CPU while the previous read/write may still be working
379 * on our hardware, if we hit this case the hardware poops in a loop.
380 * We prevent this by serializing reads and writes.
381 *
382 * This issue is not present on PCI-Express devices or pre-AR5416
383 * devices (legacy, 802.11abg).
384 */
385 if (num_possible_cpus() > 1)
386 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
387
388 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
389 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
390 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
391 !ah->is_pciexpress)) {
392 ah->config.serialize_regmode = SER_REG_MODE_ON;
393 } else {
394 ah->config.serialize_regmode = SER_REG_MODE_OFF;
395 }
396 }
397
398 ath_dbg(common, RESET, "serialize_regmode is %d\n",
399 ah->config.serialize_regmode);
400
401 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
402 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
403 else
404 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
405 }
406
407 static void ath9k_hw_init_defaults(struct ath_hw *ah)
408 {
409 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
410
411 regulatory->country_code = CTRY_DEFAULT;
412 regulatory->power_limit = MAX_RATE_POWER;
413
414 ah->hw_version.magic = AR5416_MAGIC;
415 ah->hw_version.subvendorid = 0;
416
417 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
418 AR_STA_ID1_MCAST_KSRCH;
419 if (AR_SREV_9100(ah))
420 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
421
422 ah->slottime = ATH9K_SLOT_TIME_9;
423 ah->globaltxtimeout = (u32) -1;
424 ah->power_mode = ATH9K_PM_UNDEFINED;
425 ah->htc_reset_init = true;
426
427 ah->ani_function = ATH9K_ANI_ALL;
428 if (!AR_SREV_9300_20_OR_LATER(ah))
429 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
430
431 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
432 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
433 else
434 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
435 }
436
437 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
438 {
439 struct ath_common *common = ath9k_hw_common(ah);
440 u32 sum;
441 int i;
442 u16 eeval;
443 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
444
445 sum = 0;
446 for (i = 0; i < 3; i++) {
447 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
448 sum += eeval;
449 common->macaddr[2 * i] = eeval >> 8;
450 common->macaddr[2 * i + 1] = eeval & 0xff;
451 }
452 if (sum == 0 || sum == 0xffff * 3)
453 return -EADDRNOTAVAIL;
454
455 return 0;
456 }
457
458 static int ath9k_hw_post_init(struct ath_hw *ah)
459 {
460 struct ath_common *common = ath9k_hw_common(ah);
461 int ecode;
462
463 if (common->bus_ops->ath_bus_type != ATH_USB) {
464 if (!ath9k_hw_chip_test(ah))
465 return -ENODEV;
466 }
467
468 if (!AR_SREV_9300_20_OR_LATER(ah)) {
469 ecode = ar9002_hw_rf_claim(ah);
470 if (ecode != 0)
471 return ecode;
472 }
473
474 ecode = ath9k_hw_eeprom_init(ah);
475 if (ecode != 0)
476 return ecode;
477
478 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
479 ah->eep_ops->get_eeprom_ver(ah),
480 ah->eep_ops->get_eeprom_rev(ah));
481
482 ath9k_hw_ani_init(ah);
483
484 /*
485 * EEPROM needs to be initialized before we do this.
486 * This is required for regulatory compliance.
487 */
488 if (AR_SREV_9300_20_OR_LATER(ah)) {
489 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
490 if ((regdmn & 0xF0) == CTL_FCC) {
491 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
492 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
493 }
494 }
495
496 return 0;
497 }
498
499 static int ath9k_hw_attach_ops(struct ath_hw *ah)
500 {
501 if (!AR_SREV_9300_20_OR_LATER(ah))
502 return ar9002_hw_attach_ops(ah);
503
504 ar9003_hw_attach_ops(ah);
505 return 0;
506 }
507
508 /* Called for all hardware families */
509 static int __ath9k_hw_init(struct ath_hw *ah)
510 {
511 struct ath_common *common = ath9k_hw_common(ah);
512 int r = 0;
513
514 ath9k_hw_read_revisions(ah);
515
516 switch (ah->hw_version.macVersion) {
517 case AR_SREV_VERSION_5416_PCI:
518 case AR_SREV_VERSION_5416_PCIE:
519 case AR_SREV_VERSION_9160:
520 case AR_SREV_VERSION_9100:
521 case AR_SREV_VERSION_9280:
522 case AR_SREV_VERSION_9285:
523 case AR_SREV_VERSION_9287:
524 case AR_SREV_VERSION_9271:
525 case AR_SREV_VERSION_9300:
526 case AR_SREV_VERSION_9330:
527 case AR_SREV_VERSION_9485:
528 case AR_SREV_VERSION_9340:
529 case AR_SREV_VERSION_9462:
530 case AR_SREV_VERSION_9550:
531 case AR_SREV_VERSION_9565:
532 case AR_SREV_VERSION_9531:
533 break;
534 default:
535 ath_err(common,
536 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
537 ah->hw_version.macVersion, ah->hw_version.macRev);
538 return -EOPNOTSUPP;
539 }
540
541 /*
542 * Read back AR_WA into a permanent copy and set bits 14 and 17.
543 * We need to do this to avoid RMW of this register. We cannot
544 * read the reg when chip is asleep.
545 */
546 if (AR_SREV_9300_20_OR_LATER(ah)) {
547 ah->WARegVal = REG_READ(ah, AR_WA);
548 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
549 AR_WA_ASPM_TIMER_BASED_DISABLE);
550 }
551
552 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
553 ath_err(common, "Couldn't reset chip\n");
554 return -EIO;
555 }
556
557 if (AR_SREV_9565(ah)) {
558 ah->WARegVal |= AR_WA_BIT22;
559 REG_WRITE(ah, AR_WA, ah->WARegVal);
560 }
561
562 ath9k_hw_init_defaults(ah);
563 ath9k_hw_init_config(ah);
564
565 r = ath9k_hw_attach_ops(ah);
566 if (r)
567 return r;
568
569 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
570 ath_err(common, "Couldn't wakeup chip\n");
571 return -EIO;
572 }
573
574 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
575 AR_SREV_9330(ah) || AR_SREV_9550(ah))
576 ah->is_pciexpress = false;
577
578 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
579 ath9k_hw_init_cal_settings(ah);
580
581 if (!ah->is_pciexpress)
582 ath9k_hw_disablepcie(ah);
583
584 r = ath9k_hw_post_init(ah);
585 if (r)
586 return r;
587
588 ath9k_hw_init_mode_gain_regs(ah);
589 r = ath9k_hw_fill_cap_info(ah);
590 if (r)
591 return r;
592
593 r = ath9k_hw_init_macaddr(ah);
594 if (r) {
595 ath_err(common, "Failed to initialize MAC address\n");
596 return r;
597 }
598
599 ath9k_hw_init_hang_checks(ah);
600
601 common->state = ATH_HW_INITIALIZED;
602
603 return 0;
604 }
605
606 int ath9k_hw_init(struct ath_hw *ah)
607 {
608 int ret;
609 struct ath_common *common = ath9k_hw_common(ah);
610
611 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
612 switch (ah->hw_version.devid) {
613 case AR5416_DEVID_PCI:
614 case AR5416_DEVID_PCIE:
615 case AR5416_AR9100_DEVID:
616 case AR9160_DEVID_PCI:
617 case AR9280_DEVID_PCI:
618 case AR9280_DEVID_PCIE:
619 case AR9285_DEVID_PCIE:
620 case AR9287_DEVID_PCI:
621 case AR9287_DEVID_PCIE:
622 case AR2427_DEVID_PCIE:
623 case AR9300_DEVID_PCIE:
624 case AR9300_DEVID_AR9485_PCIE:
625 case AR9300_DEVID_AR9330:
626 case AR9300_DEVID_AR9340:
627 case AR9300_DEVID_QCA955X:
628 case AR9300_DEVID_AR9580:
629 case AR9300_DEVID_AR9462:
630 case AR9485_DEVID_AR1111:
631 case AR9300_DEVID_AR9565:
632 case AR9300_DEVID_AR953X:
633 break;
634 default:
635 if (common->bus_ops->ath_bus_type == ATH_USB)
636 break;
637 ath_err(common, "Hardware device ID 0x%04x not supported\n",
638 ah->hw_version.devid);
639 return -EOPNOTSUPP;
640 }
641
642 ret = __ath9k_hw_init(ah);
643 if (ret) {
644 ath_err(common,
645 "Unable to initialize hardware; initialization status: %d\n",
646 ret);
647 return ret;
648 }
649
650 return 0;
651 }
652 EXPORT_SYMBOL(ath9k_hw_init);
653
654 static void ath9k_hw_init_qos(struct ath_hw *ah)
655 {
656 ENABLE_REGWRITE_BUFFER(ah);
657
658 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
659 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
660
661 REG_WRITE(ah, AR_QOS_NO_ACK,
662 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
663 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
664 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
665
666 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
667 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
668 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
670 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
671
672 REGWRITE_BUFFER_FLUSH(ah);
673 }
674
675 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
676 {
677 struct ath_common *common = ath9k_hw_common(ah);
678 int i = 0;
679
680 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
681 udelay(100);
682 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
683
684 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
685
686 udelay(100);
687
688 if (WARN_ON_ONCE(i >= 100)) {
689 ath_err(common, "PLL4 meaurement not done\n");
690 break;
691 }
692
693 i++;
694 }
695
696 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
697 }
698 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
699
700 static void ath9k_hw_init_pll(struct ath_hw *ah,
701 struct ath9k_channel *chan)
702 {
703 u32 pll;
704
705 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
706 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
707 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
708 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
709 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
710 AR_CH0_DPLL2_KD, 0x40);
711 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
712 AR_CH0_DPLL2_KI, 0x4);
713
714 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
715 AR_CH0_BB_DPLL1_REFDIV, 0x5);
716 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
717 AR_CH0_BB_DPLL1_NINI, 0x58);
718 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
719 AR_CH0_BB_DPLL1_NFRAC, 0x0);
720
721 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
722 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
723 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
724 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
725 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
726 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
727
728 /* program BB PLL phase_shift to 0x6 */
729 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
730 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
731
732 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
733 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
734 udelay(1000);
735 } else if (AR_SREV_9330(ah)) {
736 u32 ddr_dpll2, pll_control2, kd;
737
738 if (ah->is_clk_25mhz) {
739 ddr_dpll2 = 0x18e82f01;
740 pll_control2 = 0xe04a3d;
741 kd = 0x1d;
742 } else {
743 ddr_dpll2 = 0x19e82f01;
744 pll_control2 = 0x886666;
745 kd = 0x3d;
746 }
747
748 /* program DDR PLL ki and kd value */
749 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
750
751 /* program DDR PLL phase_shift */
752 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
753 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
754
755 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
756 udelay(1000);
757
758 /* program refdiv, nint, frac to RTC register */
759 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
760
761 /* program BB PLL kd and ki value */
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
764
765 /* program BB PLL phase_shift */
766 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
767 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
768 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
769 u32 regval, pll2_divint, pll2_divfrac, refdiv;
770
771 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
772 udelay(1000);
773
774 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
775 udelay(100);
776
777 if (ah->is_clk_25mhz) {
778 if (AR_SREV_9531(ah)) {
779 pll2_divint = 0x1c;
780 pll2_divfrac = 0xa3d2;
781 refdiv = 1;
782 } else {
783 pll2_divint = 0x54;
784 pll2_divfrac = 0x1eb85;
785 refdiv = 3;
786 }
787 } else {
788 if (AR_SREV_9340(ah)) {
789 pll2_divint = 88;
790 pll2_divfrac = 0;
791 refdiv = 5;
792 } else {
793 pll2_divint = 0x11;
794 pll2_divfrac = 0x26666;
795 refdiv = 1;
796 }
797 }
798
799 regval = REG_READ(ah, AR_PHY_PLL_MODE);
800 if (AR_SREV_9531(ah))
801 regval |= (0x1 << 22);
802 else
803 regval |= (0x1 << 16);
804 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
805 udelay(100);
806
807 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
808 (pll2_divint << 18) | pll2_divfrac);
809 udelay(100);
810
811 regval = REG_READ(ah, AR_PHY_PLL_MODE);
812 if (AR_SREV_9340(ah))
813 regval = (regval & 0x80071fff) |
814 (0x1 << 30) |
815 (0x1 << 13) |
816 (0x4 << 26) |
817 (0x18 << 19);
818 else if (AR_SREV_9531(ah))
819 regval = (regval & 0x01c00fff) |
820 (0x1 << 31) |
821 (0x2 << 29) |
822 (0xa << 25) |
823 (0x1 << 19) |
824 (0x6 << 12);
825 else
826 regval = (regval & 0x80071fff) |
827 (0x3 << 30) |
828 (0x1 << 13) |
829 (0x4 << 26) |
830 (0x60 << 19);
831 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
832
833 if (AR_SREV_9531(ah))
834 REG_WRITE(ah, AR_PHY_PLL_MODE,
835 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
836 else
837 REG_WRITE(ah, AR_PHY_PLL_MODE,
838 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
839
840 udelay(1000);
841 }
842
843 pll = ath9k_hw_compute_pll_control(ah, chan);
844 if (AR_SREV_9565(ah))
845 pll |= 0x40000;
846 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
847
848 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
849 AR_SREV_9550(ah))
850 udelay(1000);
851
852 /* Switch the core clock for ar9271 to 117Mhz */
853 if (AR_SREV_9271(ah)) {
854 udelay(500);
855 REG_WRITE(ah, 0x50040, 0x304);
856 }
857
858 udelay(RTC_PLL_SETTLE_DELAY);
859
860 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
861
862 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
863 if (ah->is_clk_25mhz) {
864 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
865 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
866 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
867 } else {
868 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
869 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
870 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
871 }
872 udelay(100);
873 }
874 }
875
876 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
877 enum nl80211_iftype opmode)
878 {
879 u32 sync_default = AR_INTR_SYNC_DEFAULT;
880 u32 imr_reg = AR_IMR_TXERR |
881 AR_IMR_TXURN |
882 AR_IMR_RXERR |
883 AR_IMR_RXORN |
884 AR_IMR_BCNMISC;
885
886 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
887 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
888
889 if (AR_SREV_9300_20_OR_LATER(ah)) {
890 imr_reg |= AR_IMR_RXOK_HP;
891 if (ah->config.rx_intr_mitigation)
892 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
893 else
894 imr_reg |= AR_IMR_RXOK_LP;
895
896 } else {
897 if (ah->config.rx_intr_mitigation)
898 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
899 else
900 imr_reg |= AR_IMR_RXOK;
901 }
902
903 if (ah->config.tx_intr_mitigation)
904 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
905 else
906 imr_reg |= AR_IMR_TXOK;
907
908 ENABLE_REGWRITE_BUFFER(ah);
909
910 REG_WRITE(ah, AR_IMR, imr_reg);
911 ah->imrs2_reg |= AR_IMR_S2_GTT;
912 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
913
914 if (!AR_SREV_9100(ah)) {
915 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
916 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
917 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
918 }
919
920 REGWRITE_BUFFER_FLUSH(ah);
921
922 if (AR_SREV_9300_20_OR_LATER(ah)) {
923 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
924 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
925 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
926 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
927 }
928 }
929
930 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
931 {
932 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
933 val = min(val, (u32) 0xFFFF);
934 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
935 }
936
937 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
938 {
939 u32 val = ath9k_hw_mac_to_clks(ah, us);
940 val = min(val, (u32) 0xFFFF);
941 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
942 }
943
944 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
945 {
946 u32 val = ath9k_hw_mac_to_clks(ah, us);
947 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
948 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
949 }
950
951 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
952 {
953 u32 val = ath9k_hw_mac_to_clks(ah, us);
954 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
955 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
956 }
957
958 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
959 {
960 if (tu > 0xFFFF) {
961 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
962 tu);
963 ah->globaltxtimeout = (u32) -1;
964 return false;
965 } else {
966 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
967 ah->globaltxtimeout = tu;
968 return true;
969 }
970 }
971
972 void ath9k_hw_init_global_settings(struct ath_hw *ah)
973 {
974 struct ath_common *common = ath9k_hw_common(ah);
975 const struct ath9k_channel *chan = ah->curchan;
976 int acktimeout, ctstimeout, ack_offset = 0;
977 int slottime;
978 int sifstime;
979 int rx_lat = 0, tx_lat = 0, eifs = 0;
980 u32 reg;
981
982 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
983 ah->misc_mode);
984
985 if (!chan)
986 return;
987
988 if (ah->misc_mode != 0)
989 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
990
991 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
992 rx_lat = 41;
993 else
994 rx_lat = 37;
995 tx_lat = 54;
996
997 if (IS_CHAN_5GHZ(chan))
998 sifstime = 16;
999 else
1000 sifstime = 10;
1001
1002 if (IS_CHAN_HALF_RATE(chan)) {
1003 eifs = 175;
1004 rx_lat *= 2;
1005 tx_lat *= 2;
1006 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1007 tx_lat += 11;
1008
1009 sifstime = 32;
1010 ack_offset = 16;
1011 slottime = 13;
1012 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1013 eifs = 340;
1014 rx_lat = (rx_lat * 4) - 1;
1015 tx_lat *= 4;
1016 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1017 tx_lat += 22;
1018
1019 sifstime = 64;
1020 ack_offset = 32;
1021 slottime = 21;
1022 } else {
1023 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1024 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1025 reg = AR_USEC_ASYNC_FIFO;
1026 } else {
1027 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1028 common->clockrate;
1029 reg = REG_READ(ah, AR_USEC);
1030 }
1031 rx_lat = MS(reg, AR_USEC_RX_LAT);
1032 tx_lat = MS(reg, AR_USEC_TX_LAT);
1033
1034 slottime = ah->slottime;
1035 }
1036
1037 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1038 slottime += 3 * ah->coverage_class;
1039 acktimeout = slottime + sifstime + ack_offset;
1040 ctstimeout = acktimeout;
1041
1042 /*
1043 * Workaround for early ACK timeouts, add an offset to match the
1044 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1045 * This was initially only meant to work around an issue with delayed
1046 * BA frames in some implementations, but it has been found to fix ACK
1047 * timeout issues in other cases as well.
1048 */
1049 if (IS_CHAN_2GHZ(chan) &&
1050 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1051 acktimeout += 64 - sifstime - ah->slottime;
1052 ctstimeout += 48 - sifstime - ah->slottime;
1053 }
1054
1055 ath9k_hw_set_sifs_time(ah, sifstime);
1056 ath9k_hw_setslottime(ah, slottime);
1057 ath9k_hw_set_ack_timeout(ah, acktimeout);
1058 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1059 if (ah->globaltxtimeout != (u32) -1)
1060 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1061
1062 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1063 REG_RMW(ah, AR_USEC,
1064 (common->clockrate - 1) |
1065 SM(rx_lat, AR_USEC_RX_LAT) |
1066 SM(tx_lat, AR_USEC_TX_LAT),
1067 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1068
1069 }
1070 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1071
1072 void ath9k_hw_deinit(struct ath_hw *ah)
1073 {
1074 struct ath_common *common = ath9k_hw_common(ah);
1075
1076 if (common->state < ATH_HW_INITIALIZED)
1077 return;
1078
1079 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1080 }
1081 EXPORT_SYMBOL(ath9k_hw_deinit);
1082
1083 /*******/
1084 /* INI */
1085 /*******/
1086
1087 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1088 {
1089 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1090
1091 if (IS_CHAN_2GHZ(chan))
1092 ctl |= CTL_11G;
1093 else
1094 ctl |= CTL_11A;
1095
1096 return ctl;
1097 }
1098
1099 /****************************************/
1100 /* Reset and Channel Switching Routines */
1101 /****************************************/
1102
1103 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1104 {
1105 struct ath_common *common = ath9k_hw_common(ah);
1106 int txbuf_size;
1107
1108 ENABLE_REGWRITE_BUFFER(ah);
1109
1110 /*
1111 * set AHB_MODE not to do cacheline prefetches
1112 */
1113 if (!AR_SREV_9300_20_OR_LATER(ah))
1114 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1115
1116 /*
1117 * let mac dma reads be in 128 byte chunks
1118 */
1119 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1120
1121 REGWRITE_BUFFER_FLUSH(ah);
1122
1123 /*
1124 * Restore TX Trigger Level to its pre-reset value.
1125 * The initial value depends on whether aggregation is enabled, and is
1126 * adjusted whenever underruns are detected.
1127 */
1128 if (!AR_SREV_9300_20_OR_LATER(ah))
1129 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1130
1131 ENABLE_REGWRITE_BUFFER(ah);
1132
1133 /*
1134 * let mac dma writes be in 128 byte chunks
1135 */
1136 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1137
1138 /*
1139 * Setup receive FIFO threshold to hold off TX activities
1140 */
1141 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1142
1143 if (AR_SREV_9300_20_OR_LATER(ah)) {
1144 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1145 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1146
1147 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1148 ah->caps.rx_status_len);
1149 }
1150
1151 /*
1152 * reduce the number of usable entries in PCU TXBUF to avoid
1153 * wrap around issues.
1154 */
1155 if (AR_SREV_9285(ah)) {
1156 /* For AR9285 the number of Fifos are reduced to half.
1157 * So set the usable tx buf size also to half to
1158 * avoid data/delimiter underruns
1159 */
1160 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1161 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1162 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1163 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1164 } else {
1165 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
1166 }
1167
1168 if (!AR_SREV_9271(ah))
1169 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1170
1171 REGWRITE_BUFFER_FLUSH(ah);
1172
1173 if (AR_SREV_9300_20_OR_LATER(ah))
1174 ath9k_hw_reset_txstatus_ring(ah);
1175 }
1176
1177 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1178 {
1179 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1180 u32 set = AR_STA_ID1_KSRCH_MODE;
1181
1182 switch (opmode) {
1183 case NL80211_IFTYPE_ADHOC:
1184 set |= AR_STA_ID1_ADHOC;
1185 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1186 break;
1187 case NL80211_IFTYPE_MESH_POINT:
1188 case NL80211_IFTYPE_AP:
1189 set |= AR_STA_ID1_STA_AP;
1190 /* fall through */
1191 case NL80211_IFTYPE_STATION:
1192 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1193 break;
1194 default:
1195 if (!ah->is_monitoring)
1196 set = 0;
1197 break;
1198 }
1199 REG_RMW(ah, AR_STA_ID1, set, mask);
1200 }
1201
1202 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1203 u32 *coef_mantissa, u32 *coef_exponent)
1204 {
1205 u32 coef_exp, coef_man;
1206
1207 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1208 if ((coef_scaled >> coef_exp) & 0x1)
1209 break;
1210
1211 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1212
1213 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1214
1215 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1216 *coef_exponent = coef_exp - 16;
1217 }
1218
1219 /* AR9330 WAR:
1220 * call external reset function to reset WMAC if:
1221 * - doing a cold reset
1222 * - we have pending frames in the TX queues.
1223 */
1224 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1225 {
1226 int i, npend = 0;
1227
1228 for (i = 0; i < AR_NUM_QCU; i++) {
1229 npend = ath9k_hw_numtxpending(ah, i);
1230 if (npend)
1231 break;
1232 }
1233
1234 if (ah->external_reset &&
1235 (npend || type == ATH9K_RESET_COLD)) {
1236 int reset_err = 0;
1237
1238 ath_dbg(ath9k_hw_common(ah), RESET,
1239 "reset MAC via external reset\n");
1240
1241 reset_err = ah->external_reset();
1242 if (reset_err) {
1243 ath_err(ath9k_hw_common(ah),
1244 "External reset failed, err=%d\n",
1245 reset_err);
1246 return false;
1247 }
1248
1249 REG_WRITE(ah, AR_RTC_RESET, 1);
1250 }
1251
1252 return true;
1253 }
1254
1255 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1256 {
1257 u32 rst_flags;
1258 u32 tmpReg;
1259
1260 if (AR_SREV_9100(ah)) {
1261 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1262 AR_RTC_DERIVED_CLK_PERIOD, 1);
1263 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1264 }
1265
1266 ENABLE_REGWRITE_BUFFER(ah);
1267
1268 if (AR_SREV_9300_20_OR_LATER(ah)) {
1269 REG_WRITE(ah, AR_WA, ah->WARegVal);
1270 udelay(10);
1271 }
1272
1273 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1274 AR_RTC_FORCE_WAKE_ON_INT);
1275
1276 if (AR_SREV_9100(ah)) {
1277 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1278 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1279 } else {
1280 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1281 if (AR_SREV_9340(ah))
1282 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1283 else
1284 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1285 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1286
1287 if (tmpReg) {
1288 u32 val;
1289 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1290
1291 val = AR_RC_HOSTIF;
1292 if (!AR_SREV_9300_20_OR_LATER(ah))
1293 val |= AR_RC_AHB;
1294 REG_WRITE(ah, AR_RC, val);
1295
1296 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1297 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1298
1299 rst_flags = AR_RTC_RC_MAC_WARM;
1300 if (type == ATH9K_RESET_COLD)
1301 rst_flags |= AR_RTC_RC_MAC_COLD;
1302 }
1303
1304 if (AR_SREV_9330(ah)) {
1305 if (!ath9k_hw_ar9330_reset_war(ah, type))
1306 return false;
1307 }
1308
1309 if (ath9k_hw_mci_is_enabled(ah))
1310 ar9003_mci_check_gpm_offset(ah);
1311
1312 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1313
1314 REGWRITE_BUFFER_FLUSH(ah);
1315
1316 if (AR_SREV_9300_20_OR_LATER(ah))
1317 udelay(50);
1318 else if (AR_SREV_9100(ah))
1319 mdelay(10);
1320 else
1321 udelay(100);
1322
1323 REG_WRITE(ah, AR_RTC_RC, 0);
1324 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1325 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1326 return false;
1327 }
1328
1329 if (!AR_SREV_9100(ah))
1330 REG_WRITE(ah, AR_RC, 0);
1331
1332 if (AR_SREV_9100(ah))
1333 udelay(50);
1334
1335 return true;
1336 }
1337
1338 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1339 {
1340 ENABLE_REGWRITE_BUFFER(ah);
1341
1342 if (AR_SREV_9300_20_OR_LATER(ah)) {
1343 REG_WRITE(ah, AR_WA, ah->WARegVal);
1344 udelay(10);
1345 }
1346
1347 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1348 AR_RTC_FORCE_WAKE_ON_INT);
1349
1350 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1351 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1352
1353 REG_WRITE(ah, AR_RTC_RESET, 0);
1354
1355 REGWRITE_BUFFER_FLUSH(ah);
1356
1357 udelay(2);
1358
1359 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1360 REG_WRITE(ah, AR_RC, 0);
1361
1362 REG_WRITE(ah, AR_RTC_RESET, 1);
1363
1364 if (!ath9k_hw_wait(ah,
1365 AR_RTC_STATUS,
1366 AR_RTC_STATUS_M,
1367 AR_RTC_STATUS_ON,
1368 AH_WAIT_TIMEOUT)) {
1369 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1370 return false;
1371 }
1372
1373 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1374 }
1375
1376 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1377 {
1378 bool ret = false;
1379
1380 if (AR_SREV_9300_20_OR_LATER(ah)) {
1381 REG_WRITE(ah, AR_WA, ah->WARegVal);
1382 udelay(10);
1383 }
1384
1385 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1386 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1387
1388 if (!ah->reset_power_on)
1389 type = ATH9K_RESET_POWER_ON;
1390
1391 switch (type) {
1392 case ATH9K_RESET_POWER_ON:
1393 ret = ath9k_hw_set_reset_power_on(ah);
1394 if (ret)
1395 ah->reset_power_on = true;
1396 break;
1397 case ATH9K_RESET_WARM:
1398 case ATH9K_RESET_COLD:
1399 ret = ath9k_hw_set_reset(ah, type);
1400 break;
1401 default:
1402 break;
1403 }
1404
1405 return ret;
1406 }
1407
1408 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1409 struct ath9k_channel *chan)
1410 {
1411 int reset_type = ATH9K_RESET_WARM;
1412
1413 if (AR_SREV_9280(ah)) {
1414 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1415 reset_type = ATH9K_RESET_POWER_ON;
1416 else
1417 reset_type = ATH9K_RESET_COLD;
1418 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1419 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1420 reset_type = ATH9K_RESET_COLD;
1421
1422 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1423 return false;
1424
1425 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1426 return false;
1427
1428 ah->chip_fullsleep = false;
1429
1430 if (AR_SREV_9330(ah))
1431 ar9003_hw_internal_regulator_apply(ah);
1432 ath9k_hw_init_pll(ah, chan);
1433
1434 return true;
1435 }
1436
1437 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1438 struct ath9k_channel *chan)
1439 {
1440 struct ath_common *common = ath9k_hw_common(ah);
1441 struct ath9k_hw_capabilities *pCap = &ah->caps;
1442 bool band_switch = false, mode_diff = false;
1443 u8 ini_reloaded = 0;
1444 u32 qnum;
1445 int r;
1446
1447 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1448 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1449 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1450 mode_diff = !!(flags_diff & ~CHANNEL_HT);
1451 }
1452
1453 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1454 if (ath9k_hw_numtxpending(ah, qnum)) {
1455 ath_dbg(common, QUEUE,
1456 "Transmit frames pending on queue %d\n", qnum);
1457 return false;
1458 }
1459 }
1460
1461 if (!ath9k_hw_rfbus_req(ah)) {
1462 ath_err(common, "Could not kill baseband RX\n");
1463 return false;
1464 }
1465
1466 if (band_switch || mode_diff) {
1467 ath9k_hw_mark_phy_inactive(ah);
1468 udelay(5);
1469
1470 if (band_switch)
1471 ath9k_hw_init_pll(ah, chan);
1472
1473 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1474 ath_err(common, "Failed to do fast channel change\n");
1475 return false;
1476 }
1477 }
1478
1479 ath9k_hw_set_channel_regs(ah, chan);
1480
1481 r = ath9k_hw_rf_set_freq(ah, chan);
1482 if (r) {
1483 ath_err(common, "Failed to set channel\n");
1484 return false;
1485 }
1486 ath9k_hw_set_clockrate(ah);
1487 ath9k_hw_apply_txpower(ah, chan, false);
1488
1489 ath9k_hw_set_delta_slope(ah, chan);
1490 ath9k_hw_spur_mitigate_freq(ah, chan);
1491
1492 if (band_switch || ini_reloaded)
1493 ah->eep_ops->set_board_values(ah, chan);
1494
1495 ath9k_hw_init_bb(ah, chan);
1496 ath9k_hw_rfbus_done(ah);
1497
1498 if (band_switch || ini_reloaded) {
1499 ah->ah_flags |= AH_FASTCC;
1500 ath9k_hw_init_cal(ah, chan);
1501 ah->ah_flags &= ~AH_FASTCC;
1502 }
1503
1504 return true;
1505 }
1506
1507 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1508 {
1509 u32 gpio_mask = ah->gpio_mask;
1510 int i;
1511
1512 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1513 if (!(gpio_mask & 1))
1514 continue;
1515
1516 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1517 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1518 }
1519 }
1520
1521 void ath9k_hw_check_nav(struct ath_hw *ah)
1522 {
1523 struct ath_common *common = ath9k_hw_common(ah);
1524 u32 val;
1525
1526 val = REG_READ(ah, AR_NAV);
1527 if (val != 0xdeadbeef && val > 0x7fff) {
1528 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1529 REG_WRITE(ah, AR_NAV, 0);
1530 }
1531 }
1532 EXPORT_SYMBOL(ath9k_hw_check_nav);
1533
1534 bool ath9k_hw_check_alive(struct ath_hw *ah)
1535 {
1536 int count = 50;
1537 u32 reg, last_val;
1538
1539 if (AR_SREV_9300(ah))
1540 return !ath9k_hw_detect_mac_hang(ah);
1541
1542 if (AR_SREV_9285_12_OR_LATER(ah))
1543 return true;
1544
1545 last_val = REG_READ(ah, AR_OBS_BUS_1);
1546 do {
1547 reg = REG_READ(ah, AR_OBS_BUS_1);
1548 if (reg != last_val)
1549 return true;
1550
1551 last_val = reg;
1552 if ((reg & 0x7E7FFFEF) == 0x00702400)
1553 continue;
1554
1555 switch (reg & 0x7E000B00) {
1556 case 0x1E000000:
1557 case 0x52000B00:
1558 case 0x18000B00:
1559 continue;
1560 default:
1561 return true;
1562 }
1563
1564 udelay(1);
1565 } while (count-- > 0);
1566
1567 return false;
1568 }
1569 EXPORT_SYMBOL(ath9k_hw_check_alive);
1570
1571 static void ath9k_hw_init_mfp(struct ath_hw *ah)
1572 {
1573 /* Setup MFP options for CCMP */
1574 if (AR_SREV_9280_20_OR_LATER(ah)) {
1575 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1576 * frames when constructing CCMP AAD. */
1577 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1578 0xc7ff);
1579 ah->sw_mgmt_crypto = false;
1580 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1581 /* Disable hardware crypto for management frames */
1582 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1583 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1584 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1585 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1586 ah->sw_mgmt_crypto = true;
1587 } else {
1588 ah->sw_mgmt_crypto = true;
1589 }
1590 }
1591
1592 static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1593 u32 macStaId1, u32 saveDefAntenna)
1594 {
1595 struct ath_common *common = ath9k_hw_common(ah);
1596
1597 ENABLE_REGWRITE_BUFFER(ah);
1598
1599 REG_RMW(ah, AR_STA_ID1, macStaId1
1600 | AR_STA_ID1_RTS_USE_DEF
1601 | ah->sta_id1_defaults,
1602 ~AR_STA_ID1_SADH_MASK);
1603 ath_hw_setbssidmask(common);
1604 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1605 ath9k_hw_write_associd(ah);
1606 REG_WRITE(ah, AR_ISR, ~0);
1607 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1608
1609 REGWRITE_BUFFER_FLUSH(ah);
1610
1611 ath9k_hw_set_operating_mode(ah, ah->opmode);
1612 }
1613
1614 static void ath9k_hw_init_queues(struct ath_hw *ah)
1615 {
1616 int i;
1617
1618 ENABLE_REGWRITE_BUFFER(ah);
1619
1620 for (i = 0; i < AR_NUM_DCU; i++)
1621 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1622
1623 REGWRITE_BUFFER_FLUSH(ah);
1624
1625 ah->intr_txqs = 0;
1626 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1627 ath9k_hw_resettxqueue(ah, i);
1628 }
1629
1630 /*
1631 * For big endian systems turn on swapping for descriptors
1632 */
1633 static void ath9k_hw_init_desc(struct ath_hw *ah)
1634 {
1635 struct ath_common *common = ath9k_hw_common(ah);
1636
1637 if (AR_SREV_9100(ah)) {
1638 u32 mask;
1639 mask = REG_READ(ah, AR_CFG);
1640 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1641 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1642 mask);
1643 } else {
1644 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1645 REG_WRITE(ah, AR_CFG, mask);
1646 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1647 REG_READ(ah, AR_CFG));
1648 }
1649 } else {
1650 if (common->bus_ops->ath_bus_type == ATH_USB) {
1651 /* Configure AR9271 target WLAN */
1652 if (AR_SREV_9271(ah))
1653 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1654 else
1655 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1656 }
1657 #ifdef __BIG_ENDIAN
1658 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1659 AR_SREV_9550(ah) || AR_SREV_9531(ah))
1660 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1661 else
1662 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1663 #endif
1664 }
1665 }
1666
1667 /*
1668 * Fast channel change:
1669 * (Change synthesizer based on channel freq without resetting chip)
1670 */
1671 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1672 {
1673 struct ath_common *common = ath9k_hw_common(ah);
1674 struct ath9k_hw_capabilities *pCap = &ah->caps;
1675 int ret;
1676
1677 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1678 goto fail;
1679
1680 if (ah->chip_fullsleep)
1681 goto fail;
1682
1683 if (!ah->curchan)
1684 goto fail;
1685
1686 if (chan->channel == ah->curchan->channel)
1687 goto fail;
1688
1689 if ((ah->curchan->channelFlags | chan->channelFlags) &
1690 (CHANNEL_HALF | CHANNEL_QUARTER))
1691 goto fail;
1692
1693 /*
1694 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1695 */
1696 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1697 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
1698 goto fail;
1699
1700 if (!ath9k_hw_check_alive(ah))
1701 goto fail;
1702
1703 /*
1704 * For AR9462, make sure that calibration data for
1705 * re-using are present.
1706 */
1707 if (AR_SREV_9462(ah) && (ah->caldata &&
1708 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1709 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1710 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1711 goto fail;
1712
1713 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1714 ah->curchan->channel, chan->channel);
1715
1716 ret = ath9k_hw_channel_change(ah, chan);
1717 if (!ret)
1718 goto fail;
1719
1720 if (ath9k_hw_mci_is_enabled(ah))
1721 ar9003_mci_2g5g_switch(ah, false);
1722
1723 ath9k_hw_loadnf(ah, ah->curchan);
1724 ath9k_hw_start_nfcal(ah, true);
1725
1726 if (AR_SREV_9271(ah))
1727 ar9002_hw_load_ani_reg(ah, chan);
1728
1729 return 0;
1730 fail:
1731 return -EINVAL;
1732 }
1733
1734 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1735 struct ath9k_hw_cal_data *caldata, bool fastcc)
1736 {
1737 struct ath_common *common = ath9k_hw_common(ah);
1738 struct timespec ts;
1739 u32 saveLedState;
1740 u32 saveDefAntenna;
1741 u32 macStaId1;
1742 u64 tsf = 0;
1743 s64 usec = 0;
1744 int r;
1745 bool start_mci_reset = false;
1746 bool save_fullsleep = ah->chip_fullsleep;
1747
1748 if (ath9k_hw_mci_is_enabled(ah)) {
1749 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1750 if (start_mci_reset)
1751 return 0;
1752 }
1753
1754 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1755 return -EIO;
1756
1757 if (ah->curchan && !ah->chip_fullsleep)
1758 ath9k_hw_getnf(ah, ah->curchan);
1759
1760 ah->caldata = caldata;
1761 if (caldata && (chan->channel != caldata->channel ||
1762 chan->channelFlags != caldata->channelFlags)) {
1763 /* Operating channel changed, reset channel calibration data */
1764 memset(caldata, 0, sizeof(*caldata));
1765 ath9k_init_nfcal_hist_buffer(ah, chan);
1766 } else if (caldata) {
1767 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
1768 }
1769 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
1770
1771 if (fastcc) {
1772 r = ath9k_hw_do_fastcc(ah, chan);
1773 if (!r)
1774 return r;
1775 }
1776
1777 if (ath9k_hw_mci_is_enabled(ah))
1778 ar9003_mci_stop_bt(ah, save_fullsleep);
1779
1780 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1781 if (saveDefAntenna == 0)
1782 saveDefAntenna = 1;
1783
1784 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1785
1786 /* Save TSF before chip reset, a cold reset clears it */
1787 tsf = ath9k_hw_gettsf64(ah);
1788 getrawmonotonic(&ts);
1789 usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000;
1790
1791 saveLedState = REG_READ(ah, AR_CFG_LED) &
1792 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1793 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1794
1795 ath9k_hw_mark_phy_inactive(ah);
1796
1797 ah->paprd_table_write_done = false;
1798
1799 /* Only required on the first reset */
1800 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1801 REG_WRITE(ah,
1802 AR9271_RESET_POWER_DOWN_CONTROL,
1803 AR9271_RADIO_RF_RST);
1804 udelay(50);
1805 }
1806
1807 if (!ath9k_hw_chip_reset(ah, chan)) {
1808 ath_err(common, "Chip reset failed\n");
1809 return -EINVAL;
1810 }
1811
1812 /* Only required on the first reset */
1813 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1814 ah->htc_reset_init = false;
1815 REG_WRITE(ah,
1816 AR9271_RESET_POWER_DOWN_CONTROL,
1817 AR9271_GATE_MAC_CTL);
1818 udelay(50);
1819 }
1820
1821 /* Restore TSF */
1822 getrawmonotonic(&ts);
1823 usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000 - usec;
1824 ath9k_hw_settsf64(ah, tsf + usec);
1825
1826 if (AR_SREV_9280_20_OR_LATER(ah))
1827 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1828
1829 if (!AR_SREV_9300_20_OR_LATER(ah))
1830 ar9002_hw_enable_async_fifo(ah);
1831
1832 r = ath9k_hw_process_ini(ah, chan);
1833 if (r)
1834 return r;
1835
1836 ath9k_hw_set_rfmode(ah, chan);
1837
1838 if (ath9k_hw_mci_is_enabled(ah))
1839 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1840
1841 /*
1842 * Some AR91xx SoC devices frequently fail to accept TSF writes
1843 * right after the chip reset. When that happens, write a new
1844 * value after the initvals have been applied, with an offset
1845 * based on measured time difference
1846 */
1847 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1848 tsf += 1500;
1849 ath9k_hw_settsf64(ah, tsf);
1850 }
1851
1852 ath9k_hw_init_mfp(ah);
1853
1854 ath9k_hw_set_delta_slope(ah, chan);
1855 ath9k_hw_spur_mitigate_freq(ah, chan);
1856 ah->eep_ops->set_board_values(ah, chan);
1857
1858 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
1859
1860 r = ath9k_hw_rf_set_freq(ah, chan);
1861 if (r)
1862 return r;
1863
1864 ath9k_hw_set_clockrate(ah);
1865
1866 ath9k_hw_init_queues(ah);
1867 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1868 ath9k_hw_ani_cache_ini_regs(ah);
1869 ath9k_hw_init_qos(ah);
1870
1871 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1872 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1873
1874 ath9k_hw_init_global_settings(ah);
1875
1876 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1877 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1878 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1879 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1880 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1881 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1882 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1883 }
1884
1885 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1886
1887 ath9k_hw_set_dma(ah);
1888
1889 if (!ath9k_hw_mci_is_enabled(ah))
1890 REG_WRITE(ah, AR_OBS, 8);
1891
1892 if (ah->config.rx_intr_mitigation) {
1893 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1894 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
1895 }
1896
1897 if (ah->config.tx_intr_mitigation) {
1898 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1899 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1900 }
1901
1902 ath9k_hw_init_bb(ah, chan);
1903
1904 if (caldata) {
1905 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1906 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
1907 }
1908 if (!ath9k_hw_init_cal(ah, chan))
1909 return -EIO;
1910
1911 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
1912 return -EIO;
1913
1914 ENABLE_REGWRITE_BUFFER(ah);
1915
1916 ath9k_hw_restore_chainmask(ah);
1917 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1918
1919 REGWRITE_BUFFER_FLUSH(ah);
1920
1921 ath9k_hw_init_desc(ah);
1922
1923 if (ath9k_hw_btcoex_is_enabled(ah))
1924 ath9k_hw_btcoex_enable(ah);
1925
1926 if (ath9k_hw_mci_is_enabled(ah))
1927 ar9003_mci_check_bt(ah);
1928
1929 ath9k_hw_loadnf(ah, chan);
1930 ath9k_hw_start_nfcal(ah, true);
1931
1932 if (AR_SREV_9300_20_OR_LATER(ah))
1933 ar9003_hw_bb_watchdog_config(ah);
1934
1935 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
1936 ar9003_hw_disable_phy_restart(ah);
1937
1938 ath9k_hw_apply_gpio_override(ah);
1939
1940 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
1941 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
1942
1943 return 0;
1944 }
1945 EXPORT_SYMBOL(ath9k_hw_reset);
1946
1947 /******************************/
1948 /* Power Management (Chipset) */
1949 /******************************/
1950
1951 /*
1952 * Notify Power Mgt is disabled in self-generated frames.
1953 * If requested, force chip to sleep.
1954 */
1955 static void ath9k_set_power_sleep(struct ath_hw *ah)
1956 {
1957 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1958
1959 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1960 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
1961 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
1962 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
1963 /* xxx Required for WLAN only case ? */
1964 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1965 udelay(100);
1966 }
1967
1968 /*
1969 * Clear the RTC force wake bit to allow the
1970 * mac to go to sleep.
1971 */
1972 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1973
1974 if (ath9k_hw_mci_is_enabled(ah))
1975 udelay(100);
1976
1977 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1978 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1979
1980 /* Shutdown chip. Active low */
1981 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
1982 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1983 udelay(2);
1984 }
1985
1986 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1987 if (AR_SREV_9300_20_OR_LATER(ah))
1988 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1989 }
1990
1991 /*
1992 * Notify Power Management is enabled in self-generating
1993 * frames. If request, set power mode of chip to
1994 * auto/normal. Duration in units of 128us (1/8 TU).
1995 */
1996 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
1997 {
1998 struct ath9k_hw_capabilities *pCap = &ah->caps;
1999
2000 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2001
2002 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2003 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2004 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2005 AR_RTC_FORCE_WAKE_ON_INT);
2006 } else {
2007
2008 /* When chip goes into network sleep, it could be waken
2009 * up by MCI_INT interrupt caused by BT's HW messages
2010 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2011 * rate (~100us). This will cause chip to leave and
2012 * re-enter network sleep mode frequently, which in
2013 * consequence will have WLAN MCI HW to generate lots of
2014 * SYS_WAKING and SYS_SLEEPING messages which will make
2015 * BT CPU to busy to process.
2016 */
2017 if (ath9k_hw_mci_is_enabled(ah))
2018 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2019 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2020 /*
2021 * Clear the RTC force wake bit to allow the
2022 * mac to go to sleep.
2023 */
2024 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2025
2026 if (ath9k_hw_mci_is_enabled(ah))
2027 udelay(30);
2028 }
2029
2030 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2031 if (AR_SREV_9300_20_OR_LATER(ah))
2032 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2033 }
2034
2035 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2036 {
2037 u32 val;
2038 int i;
2039
2040 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2041 if (AR_SREV_9300_20_OR_LATER(ah)) {
2042 REG_WRITE(ah, AR_WA, ah->WARegVal);
2043 udelay(10);
2044 }
2045
2046 if ((REG_READ(ah, AR_RTC_STATUS) &
2047 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2048 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2049 return false;
2050 }
2051 if (!AR_SREV_9300_20_OR_LATER(ah))
2052 ath9k_hw_init_pll(ah, NULL);
2053 }
2054 if (AR_SREV_9100(ah))
2055 REG_SET_BIT(ah, AR_RTC_RESET,
2056 AR_RTC_RESET_EN);
2057
2058 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2059 AR_RTC_FORCE_WAKE_EN);
2060 if (AR_SREV_9100(ah))
2061 mdelay(10);
2062 else
2063 udelay(50);
2064
2065 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2066 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2067 if (val == AR_RTC_STATUS_ON)
2068 break;
2069 udelay(50);
2070 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2071 AR_RTC_FORCE_WAKE_EN);
2072 }
2073 if (i == 0) {
2074 ath_err(ath9k_hw_common(ah),
2075 "Failed to wakeup in %uus\n",
2076 POWER_UP_TIME / 20);
2077 return false;
2078 }
2079
2080 if (ath9k_hw_mci_is_enabled(ah))
2081 ar9003_mci_set_power_awake(ah);
2082
2083 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2084
2085 return true;
2086 }
2087
2088 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2089 {
2090 struct ath_common *common = ath9k_hw_common(ah);
2091 int status = true;
2092 static const char *modes[] = {
2093 "AWAKE",
2094 "FULL-SLEEP",
2095 "NETWORK SLEEP",
2096 "UNDEFINED"
2097 };
2098
2099 if (ah->power_mode == mode)
2100 return status;
2101
2102 ath_dbg(common, RESET, "%s -> %s\n",
2103 modes[ah->power_mode], modes[mode]);
2104
2105 switch (mode) {
2106 case ATH9K_PM_AWAKE:
2107 status = ath9k_hw_set_power_awake(ah);
2108 break;
2109 case ATH9K_PM_FULL_SLEEP:
2110 if (ath9k_hw_mci_is_enabled(ah))
2111 ar9003_mci_set_full_sleep(ah);
2112
2113 ath9k_set_power_sleep(ah);
2114 ah->chip_fullsleep = true;
2115 break;
2116 case ATH9K_PM_NETWORK_SLEEP:
2117 ath9k_set_power_network_sleep(ah);
2118 break;
2119 default:
2120 ath_err(common, "Unknown power mode %u\n", mode);
2121 return false;
2122 }
2123 ah->power_mode = mode;
2124
2125 /*
2126 * XXX: If this warning never comes up after a while then
2127 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2128 * ath9k_hw_setpower() return type void.
2129 */
2130
2131 if (!(ah->ah_flags & AH_UNPLUGGED))
2132 ATH_DBG_WARN_ON_ONCE(!status);
2133
2134 return status;
2135 }
2136 EXPORT_SYMBOL(ath9k_hw_setpower);
2137
2138 /*******************/
2139 /* Beacon Handling */
2140 /*******************/
2141
2142 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2143 {
2144 int flags = 0;
2145
2146 ENABLE_REGWRITE_BUFFER(ah);
2147
2148 switch (ah->opmode) {
2149 case NL80211_IFTYPE_ADHOC:
2150 REG_SET_BIT(ah, AR_TXCFG,
2151 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2152 case NL80211_IFTYPE_MESH_POINT:
2153 case NL80211_IFTYPE_AP:
2154 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2155 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2156 TU_TO_USEC(ah->config.dma_beacon_response_time));
2157 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2158 TU_TO_USEC(ah->config.sw_beacon_response_time));
2159 flags |=
2160 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2161 break;
2162 default:
2163 ath_dbg(ath9k_hw_common(ah), BEACON,
2164 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2165 return;
2166 break;
2167 }
2168
2169 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2170 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2171 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2172
2173 REGWRITE_BUFFER_FLUSH(ah);
2174
2175 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2176 }
2177 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2178
2179 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2180 const struct ath9k_beacon_state *bs)
2181 {
2182 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2183 struct ath9k_hw_capabilities *pCap = &ah->caps;
2184 struct ath_common *common = ath9k_hw_common(ah);
2185
2186 ENABLE_REGWRITE_BUFFER(ah);
2187
2188 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2189 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2190 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
2191
2192 REGWRITE_BUFFER_FLUSH(ah);
2193
2194 REG_RMW_FIELD(ah, AR_RSSI_THR,
2195 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2196
2197 beaconintval = bs->bs_intval;
2198
2199 if (bs->bs_sleepduration > beaconintval)
2200 beaconintval = bs->bs_sleepduration;
2201
2202 dtimperiod = bs->bs_dtimperiod;
2203 if (bs->bs_sleepduration > dtimperiod)
2204 dtimperiod = bs->bs_sleepduration;
2205
2206 if (beaconintval == dtimperiod)
2207 nextTbtt = bs->bs_nextdtim;
2208 else
2209 nextTbtt = bs->bs_nexttbtt;
2210
2211 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2212 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2213 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2214 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2215
2216 ENABLE_REGWRITE_BUFFER(ah);
2217
2218 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2219 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
2220
2221 REG_WRITE(ah, AR_SLEEP1,
2222 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2223 | AR_SLEEP1_ASSUME_DTIM);
2224
2225 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2226 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2227 else
2228 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2229
2230 REG_WRITE(ah, AR_SLEEP2,
2231 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2232
2233 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2234 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
2235
2236 REGWRITE_BUFFER_FLUSH(ah);
2237
2238 REG_SET_BIT(ah, AR_TIMER_MODE,
2239 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2240 AR_DTIM_TIMER_EN);
2241
2242 /* TSF Out of Range Threshold */
2243 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2244 }
2245 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2246
2247 /*******************/
2248 /* HW Capabilities */
2249 /*******************/
2250
2251 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2252 {
2253 eeprom_chainmask &= chip_chainmask;
2254 if (eeprom_chainmask)
2255 return eeprom_chainmask;
2256 else
2257 return chip_chainmask;
2258 }
2259
2260 /**
2261 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2262 * @ah: the atheros hardware data structure
2263 *
2264 * We enable DFS support upstream on chipsets which have passed a series
2265 * of tests. The testing requirements are going to be documented. Desired
2266 * test requirements are documented at:
2267 *
2268 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2269 *
2270 * Once a new chipset gets properly tested an individual commit can be used
2271 * to document the testing for DFS for that chipset.
2272 */
2273 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2274 {
2275
2276 switch (ah->hw_version.macVersion) {
2277 /* for temporary testing DFS with 9280 */
2278 case AR_SREV_VERSION_9280:
2279 /* AR9580 will likely be our first target to get testing on */
2280 case AR_SREV_VERSION_9580:
2281 return true;
2282 default:
2283 return false;
2284 }
2285 }
2286
2287 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2288 {
2289 struct ath9k_hw_capabilities *pCap = &ah->caps;
2290 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2291 struct ath_common *common = ath9k_hw_common(ah);
2292 unsigned int chip_chainmask;
2293
2294 u16 eeval;
2295 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2296
2297 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2298 regulatory->current_rd = eeval;
2299
2300 if (ah->opmode != NL80211_IFTYPE_AP &&
2301 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2302 if (regulatory->current_rd == 0x64 ||
2303 regulatory->current_rd == 0x65)
2304 regulatory->current_rd += 5;
2305 else if (regulatory->current_rd == 0x41)
2306 regulatory->current_rd = 0x43;
2307 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2308 regulatory->current_rd);
2309 }
2310
2311 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2312 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2313 ath_err(common,
2314 "no band has been marked as supported in EEPROM\n");
2315 return -EINVAL;
2316 }
2317
2318 if (eeval & AR5416_OPFLAGS_11A)
2319 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2320
2321 if (eeval & AR5416_OPFLAGS_11G)
2322 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2323
2324 if (AR_SREV_9485(ah) ||
2325 AR_SREV_9285(ah) ||
2326 AR_SREV_9330(ah) ||
2327 AR_SREV_9565(ah))
2328 chip_chainmask = 1;
2329 else if (AR_SREV_9462(ah))
2330 chip_chainmask = 3;
2331 else if (!AR_SREV_9280_20_OR_LATER(ah))
2332 chip_chainmask = 7;
2333 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2334 chip_chainmask = 3;
2335 else
2336 chip_chainmask = 7;
2337
2338 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2339 /*
2340 * For AR9271 we will temporarilly uses the rx chainmax as read from
2341 * the EEPROM.
2342 */
2343 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2344 !(eeval & AR5416_OPFLAGS_11A) &&
2345 !(AR_SREV_9271(ah)))
2346 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2347 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2348 else if (AR_SREV_9100(ah))
2349 pCap->rx_chainmask = 0x7;
2350 else
2351 /* Use rx_chainmask from EEPROM. */
2352 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2353
2354 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2355 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2356 ah->txchainmask = pCap->tx_chainmask;
2357 ah->rxchainmask = pCap->rx_chainmask;
2358
2359 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2360
2361 /* enable key search for every frame in an aggregate */
2362 if (AR_SREV_9300_20_OR_LATER(ah))
2363 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2364
2365 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2366
2367 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2368 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2369 else
2370 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2371
2372 if (AR_SREV_9271(ah))
2373 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2374 else if (AR_DEVID_7010(ah))
2375 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2376 else if (AR_SREV_9300_20_OR_LATER(ah))
2377 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2378 else if (AR_SREV_9287_11_OR_LATER(ah))
2379 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2380 else if (AR_SREV_9285_12_OR_LATER(ah))
2381 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2382 else if (AR_SREV_9280_20_OR_LATER(ah))
2383 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2384 else
2385 pCap->num_gpio_pins = AR_NUM_GPIO;
2386
2387 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2388 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2389 else
2390 pCap->rts_aggr_limit = (8 * 1024);
2391
2392 #ifdef CONFIG_ATH9K_RFKILL
2393 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2394 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2395 ah->rfkill_gpio =
2396 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2397 ah->rfkill_polarity =
2398 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2399
2400 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2401 }
2402 #endif
2403 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2404 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2405 else
2406 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2407
2408 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2409 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2410 else
2411 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2412
2413 if (AR_SREV_9300_20_OR_LATER(ah)) {
2414 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2415 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
2416 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2417
2418 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2419 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2420 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2421 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2422 pCap->txs_len = sizeof(struct ar9003_txs);
2423 } else {
2424 pCap->tx_desc_len = sizeof(struct ath_desc);
2425 if (AR_SREV_9280_20(ah))
2426 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2427 }
2428
2429 if (AR_SREV_9300_20_OR_LATER(ah))
2430 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2431
2432 if (AR_SREV_9300_20_OR_LATER(ah))
2433 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2434
2435 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2436 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2437
2438 if (AR_SREV_9285(ah)) {
2439 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2440 ant_div_ctl1 =
2441 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2442 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
2443 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2444 ath_info(common, "Enable LNA combining\n");
2445 }
2446 }
2447 }
2448
2449 if (AR_SREV_9300_20_OR_LATER(ah)) {
2450 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2451 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2452 }
2453
2454 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2455 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2456 if ((ant_div_ctl1 >> 0x6) == 0x3) {
2457 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2458 ath_info(common, "Enable LNA combining\n");
2459 }
2460 }
2461
2462 if (ath9k_hw_dfs_tested(ah))
2463 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2464
2465 tx_chainmask = pCap->tx_chainmask;
2466 rx_chainmask = pCap->rx_chainmask;
2467 while (tx_chainmask || rx_chainmask) {
2468 if (tx_chainmask & BIT(0))
2469 pCap->max_txchains++;
2470 if (rx_chainmask & BIT(0))
2471 pCap->max_rxchains++;
2472
2473 tx_chainmask >>= 1;
2474 rx_chainmask >>= 1;
2475 }
2476
2477 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2478 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2479 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2480
2481 if (AR_SREV_9462_20_OR_LATER(ah))
2482 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2483 }
2484
2485 if (AR_SREV_9462(ah))
2486 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
2487
2488 if (AR_SREV_9300_20_OR_LATER(ah) &&
2489 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2490 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2491
2492 return 0;
2493 }
2494
2495 /****************************/
2496 /* GPIO / RFKILL / Antennae */
2497 /****************************/
2498
2499 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2500 u32 gpio, u32 type)
2501 {
2502 int addr;
2503 u32 gpio_shift, tmp;
2504
2505 if (gpio > 11)
2506 addr = AR_GPIO_OUTPUT_MUX3;
2507 else if (gpio > 5)
2508 addr = AR_GPIO_OUTPUT_MUX2;
2509 else
2510 addr = AR_GPIO_OUTPUT_MUX1;
2511
2512 gpio_shift = (gpio % 6) * 5;
2513
2514 if (AR_SREV_9280_20_OR_LATER(ah)
2515 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2516 REG_RMW(ah, addr, (type << gpio_shift),
2517 (0x1f << gpio_shift));
2518 } else {
2519 tmp = REG_READ(ah, addr);
2520 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2521 tmp &= ~(0x1f << gpio_shift);
2522 tmp |= (type << gpio_shift);
2523 REG_WRITE(ah, addr, tmp);
2524 }
2525 }
2526
2527 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2528 {
2529 u32 gpio_shift;
2530
2531 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2532
2533 if (AR_DEVID_7010(ah)) {
2534 gpio_shift = gpio;
2535 REG_RMW(ah, AR7010_GPIO_OE,
2536 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2537 (AR7010_GPIO_OE_MASK << gpio_shift));
2538 return;
2539 }
2540
2541 gpio_shift = gpio << 1;
2542 REG_RMW(ah,
2543 AR_GPIO_OE_OUT,
2544 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2545 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2546 }
2547 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2548
2549 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2550 {
2551 #define MS_REG_READ(x, y) \
2552 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2553
2554 if (gpio >= ah->caps.num_gpio_pins)
2555 return 0xffffffff;
2556
2557 if (AR_DEVID_7010(ah)) {
2558 u32 val;
2559 val = REG_READ(ah, AR7010_GPIO_IN);
2560 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2561 } else if (AR_SREV_9300_20_OR_LATER(ah))
2562 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2563 AR_GPIO_BIT(gpio)) != 0;
2564 else if (AR_SREV_9271(ah))
2565 return MS_REG_READ(AR9271, gpio) != 0;
2566 else if (AR_SREV_9287_11_OR_LATER(ah))
2567 return MS_REG_READ(AR9287, gpio) != 0;
2568 else if (AR_SREV_9285_12_OR_LATER(ah))
2569 return MS_REG_READ(AR9285, gpio) != 0;
2570 else if (AR_SREV_9280_20_OR_LATER(ah))
2571 return MS_REG_READ(AR928X, gpio) != 0;
2572 else
2573 return MS_REG_READ(AR, gpio) != 0;
2574 }
2575 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2576
2577 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2578 u32 ah_signal_type)
2579 {
2580 u32 gpio_shift;
2581
2582 if (AR_DEVID_7010(ah)) {
2583 gpio_shift = gpio;
2584 REG_RMW(ah, AR7010_GPIO_OE,
2585 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2586 (AR7010_GPIO_OE_MASK << gpio_shift));
2587 return;
2588 }
2589
2590 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2591 gpio_shift = 2 * gpio;
2592 REG_RMW(ah,
2593 AR_GPIO_OE_OUT,
2594 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2595 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2596 }
2597 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2598
2599 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2600 {
2601 if (AR_DEVID_7010(ah)) {
2602 val = val ? 0 : 1;
2603 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2604 AR_GPIO_BIT(gpio));
2605 return;
2606 }
2607
2608 if (AR_SREV_9271(ah))
2609 val = ~val;
2610
2611 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2612 AR_GPIO_BIT(gpio));
2613 }
2614 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2615
2616 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2617 {
2618 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2619 }
2620 EXPORT_SYMBOL(ath9k_hw_setantenna);
2621
2622 /*********************/
2623 /* General Operation */
2624 /*********************/
2625
2626 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2627 {
2628 u32 bits = REG_READ(ah, AR_RX_FILTER);
2629 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2630
2631 if (phybits & AR_PHY_ERR_RADAR)
2632 bits |= ATH9K_RX_FILTER_PHYRADAR;
2633 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2634 bits |= ATH9K_RX_FILTER_PHYERR;
2635
2636 return bits;
2637 }
2638 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2639
2640 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2641 {
2642 u32 phybits;
2643
2644 ENABLE_REGWRITE_BUFFER(ah);
2645
2646 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2647 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2648
2649 REG_WRITE(ah, AR_RX_FILTER, bits);
2650
2651 phybits = 0;
2652 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2653 phybits |= AR_PHY_ERR_RADAR;
2654 if (bits & ATH9K_RX_FILTER_PHYERR)
2655 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2656 REG_WRITE(ah, AR_PHY_ERR, phybits);
2657
2658 if (phybits)
2659 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2660 else
2661 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2662
2663 REGWRITE_BUFFER_FLUSH(ah);
2664 }
2665 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2666
2667 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2668 {
2669 if (ath9k_hw_mci_is_enabled(ah))
2670 ar9003_mci_bt_gain_ctrl(ah);
2671
2672 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2673 return false;
2674
2675 ath9k_hw_init_pll(ah, NULL);
2676 ah->htc_reset_init = true;
2677 return true;
2678 }
2679 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2680
2681 bool ath9k_hw_disable(struct ath_hw *ah)
2682 {
2683 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2684 return false;
2685
2686 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2687 return false;
2688
2689 ath9k_hw_init_pll(ah, NULL);
2690 return true;
2691 }
2692 EXPORT_SYMBOL(ath9k_hw_disable);
2693
2694 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2695 {
2696 enum eeprom_param gain_param;
2697
2698 if (IS_CHAN_2GHZ(chan))
2699 gain_param = EEP_ANTENNA_GAIN_2G;
2700 else
2701 gain_param = EEP_ANTENNA_GAIN_5G;
2702
2703 return ah->eep_ops->get_eeprom(ah, gain_param);
2704 }
2705
2706 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2707 bool test)
2708 {
2709 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2710 struct ieee80211_channel *channel;
2711 int chan_pwr, new_pwr, max_gain;
2712 int ant_gain, ant_reduction = 0;
2713
2714 if (!chan)
2715 return;
2716
2717 channel = chan->chan;
2718 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2719 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2720 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2721
2722 ant_gain = get_antenna_gain(ah, chan);
2723 if (ant_gain > max_gain)
2724 ant_reduction = ant_gain - max_gain;
2725
2726 ah->eep_ops->set_txpower(ah, chan,
2727 ath9k_regd_get_ctl(reg, chan),
2728 ant_reduction, new_pwr, test);
2729 }
2730
2731 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2732 {
2733 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2734 struct ath9k_channel *chan = ah->curchan;
2735 struct ieee80211_channel *channel = chan->chan;
2736
2737 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2738 if (test)
2739 channel->max_power = MAX_RATE_POWER / 2;
2740
2741 ath9k_hw_apply_txpower(ah, chan, test);
2742
2743 if (test)
2744 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2745 }
2746 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2747
2748 void ath9k_hw_setopmode(struct ath_hw *ah)
2749 {
2750 ath9k_hw_set_operating_mode(ah, ah->opmode);
2751 }
2752 EXPORT_SYMBOL(ath9k_hw_setopmode);
2753
2754 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2755 {
2756 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2757 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2758 }
2759 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2760
2761 void ath9k_hw_write_associd(struct ath_hw *ah)
2762 {
2763 struct ath_common *common = ath9k_hw_common(ah);
2764
2765 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2766 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2767 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2768 }
2769 EXPORT_SYMBOL(ath9k_hw_write_associd);
2770
2771 #define ATH9K_MAX_TSF_READ 10
2772
2773 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2774 {
2775 u32 tsf_lower, tsf_upper1, tsf_upper2;
2776 int i;
2777
2778 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2779 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2780 tsf_lower = REG_READ(ah, AR_TSF_L32);
2781 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2782 if (tsf_upper2 == tsf_upper1)
2783 break;
2784 tsf_upper1 = tsf_upper2;
2785 }
2786
2787 WARN_ON( i == ATH9K_MAX_TSF_READ );
2788
2789 return (((u64)tsf_upper1 << 32) | tsf_lower);
2790 }
2791 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2792
2793 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2794 {
2795 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2796 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2797 }
2798 EXPORT_SYMBOL(ath9k_hw_settsf64);
2799
2800 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2801 {
2802 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2803 AH_TSF_WRITE_TIMEOUT))
2804 ath_dbg(ath9k_hw_common(ah), RESET,
2805 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2806
2807 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2808 }
2809 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2810
2811 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
2812 {
2813 if (set)
2814 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2815 else
2816 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2817 }
2818 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2819
2820 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
2821 {
2822 u32 macmode;
2823
2824 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
2825 macmode = AR_2040_JOINED_RX_CLEAR;
2826 else
2827 macmode = 0;
2828
2829 REG_WRITE(ah, AR_2040_MODE, macmode);
2830 }
2831
2832 /* HW Generic timers configuration */
2833
2834 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2835 {
2836 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2837 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2838 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2839 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2840 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2841 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2842 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2843 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2844 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2845 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2846 AR_NDP2_TIMER_MODE, 0x0002},
2847 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2848 AR_NDP2_TIMER_MODE, 0x0004},
2849 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2850 AR_NDP2_TIMER_MODE, 0x0008},
2851 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2852 AR_NDP2_TIMER_MODE, 0x0010},
2853 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2854 AR_NDP2_TIMER_MODE, 0x0020},
2855 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2856 AR_NDP2_TIMER_MODE, 0x0040},
2857 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2858 AR_NDP2_TIMER_MODE, 0x0080}
2859 };
2860
2861 /* HW generic timer primitives */
2862
2863 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2864 {
2865 return REG_READ(ah, AR_TSF_L32);
2866 }
2867 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2868
2869 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2870 void (*trigger)(void *),
2871 void (*overflow)(void *),
2872 void *arg,
2873 u8 timer_index)
2874 {
2875 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2876 struct ath_gen_timer *timer;
2877
2878 if ((timer_index < AR_FIRST_NDP_TIMER) ||
2879 (timer_index >= ATH_MAX_GEN_TIMER))
2880 return NULL;
2881
2882 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2883 if (timer == NULL)
2884 return NULL;
2885
2886 /* allocate a hardware generic timer slot */
2887 timer_table->timers[timer_index] = timer;
2888 timer->index = timer_index;
2889 timer->trigger = trigger;
2890 timer->overflow = overflow;
2891 timer->arg = arg;
2892
2893 return timer;
2894 }
2895 EXPORT_SYMBOL(ath_gen_timer_alloc);
2896
2897 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2898 struct ath_gen_timer *timer,
2899 u32 timer_next,
2900 u32 timer_period)
2901 {
2902 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2903 u32 mask = 0;
2904
2905 timer_table->timer_mask |= BIT(timer->index);
2906
2907 /*
2908 * Program generic timer registers
2909 */
2910 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2911 timer_next);
2912 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2913 timer_period);
2914 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2915 gen_tmr_configuration[timer->index].mode_mask);
2916
2917 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2918 /*
2919 * Starting from AR9462, each generic timer can select which tsf
2920 * to use. But we still follow the old rule, 0 - 7 use tsf and
2921 * 8 - 15 use tsf2.
2922 */
2923 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2924 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2925 (1 << timer->index));
2926 else
2927 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2928 (1 << timer->index));
2929 }
2930
2931 if (timer->trigger)
2932 mask |= SM(AR_GENTMR_BIT(timer->index),
2933 AR_IMR_S5_GENTIMER_TRIG);
2934 if (timer->overflow)
2935 mask |= SM(AR_GENTMR_BIT(timer->index),
2936 AR_IMR_S5_GENTIMER_THRESH);
2937
2938 REG_SET_BIT(ah, AR_IMR_S5, mask);
2939
2940 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
2941 ah->imask |= ATH9K_INT_GENTIMER;
2942 ath9k_hw_set_interrupts(ah);
2943 }
2944 }
2945 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2946
2947 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2948 {
2949 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2950
2951 /* Clear generic timer enable bits. */
2952 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2953 gen_tmr_configuration[timer->index].mode_mask);
2954
2955 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2956 /*
2957 * Need to switch back to TSF if it was using TSF2.
2958 */
2959 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
2960 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2961 (1 << timer->index));
2962 }
2963 }
2964
2965 /* Disable both trigger and thresh interrupt masks */
2966 REG_CLR_BIT(ah, AR_IMR_S5,
2967 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2968 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2969
2970 timer_table->timer_mask &= ~BIT(timer->index);
2971
2972 if (timer_table->timer_mask == 0) {
2973 ah->imask &= ~ATH9K_INT_GENTIMER;
2974 ath9k_hw_set_interrupts(ah);
2975 }
2976 }
2977 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2978
2979 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2980 {
2981 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2982
2983 /* free the hardware generic timer slot */
2984 timer_table->timers[timer->index] = NULL;
2985 kfree(timer);
2986 }
2987 EXPORT_SYMBOL(ath_gen_timer_free);
2988
2989 /*
2990 * Generic Timer Interrupts handling
2991 */
2992 void ath_gen_timer_isr(struct ath_hw *ah)
2993 {
2994 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2995 struct ath_gen_timer *timer;
2996 unsigned long trigger_mask, thresh_mask;
2997 unsigned int index;
2998
2999 /* get hardware generic timer interrupt status */
3000 trigger_mask = ah->intr_gen_timer_trigger;
3001 thresh_mask = ah->intr_gen_timer_thresh;
3002 trigger_mask &= timer_table->timer_mask;
3003 thresh_mask &= timer_table->timer_mask;
3004
3005 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
3006 timer = timer_table->timers[index];
3007 if (!timer)
3008 continue;
3009 if (!timer->overflow)
3010 continue;
3011
3012 trigger_mask &= ~BIT(index);
3013 timer->overflow(timer->arg);
3014 }
3015
3016 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
3017 timer = timer_table->timers[index];
3018 if (!timer)
3019 continue;
3020 if (!timer->trigger)
3021 continue;
3022 timer->trigger(timer->arg);
3023 }
3024 }
3025 EXPORT_SYMBOL(ath_gen_timer_isr);
3026
3027 /********/
3028 /* HTC */
3029 /********/
3030
3031 static struct {
3032 u32 version;
3033 const char * name;
3034 } ath_mac_bb_names[] = {
3035 /* Devices with external radios */
3036 { AR_SREV_VERSION_5416_PCI, "5416" },
3037 { AR_SREV_VERSION_5416_PCIE, "5418" },
3038 { AR_SREV_VERSION_9100, "9100" },
3039 { AR_SREV_VERSION_9160, "9160" },
3040 /* Single-chip solutions */
3041 { AR_SREV_VERSION_9280, "9280" },
3042 { AR_SREV_VERSION_9285, "9285" },
3043 { AR_SREV_VERSION_9287, "9287" },
3044 { AR_SREV_VERSION_9271, "9271" },
3045 { AR_SREV_VERSION_9300, "9300" },
3046 { AR_SREV_VERSION_9330, "9330" },
3047 { AR_SREV_VERSION_9340, "9340" },
3048 { AR_SREV_VERSION_9485, "9485" },
3049 { AR_SREV_VERSION_9462, "9462" },
3050 { AR_SREV_VERSION_9550, "9550" },
3051 { AR_SREV_VERSION_9565, "9565" },
3052 };
3053
3054 /* For devices with external radios */
3055 static struct {
3056 u16 version;
3057 const char * name;
3058 } ath_rf_names[] = {
3059 { 0, "5133" },
3060 { AR_RAD5133_SREV_MAJOR, "5133" },
3061 { AR_RAD5122_SREV_MAJOR, "5122" },
3062 { AR_RAD2133_SREV_MAJOR, "2133" },
3063 { AR_RAD2122_SREV_MAJOR, "2122" }
3064 };
3065
3066 /*
3067 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3068 */
3069 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3070 {
3071 int i;
3072
3073 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3074 if (ath_mac_bb_names[i].version == mac_bb_version) {
3075 return ath_mac_bb_names[i].name;
3076 }
3077 }
3078
3079 return "????";
3080 }
3081
3082 /*
3083 * Return the RF name. "????" is returned if the RF is unknown.
3084 * Used for devices with external radios.
3085 */
3086 static const char *ath9k_hw_rf_name(u16 rf_version)
3087 {
3088 int i;
3089
3090 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3091 if (ath_rf_names[i].version == rf_version) {
3092 return ath_rf_names[i].name;
3093 }
3094 }
3095
3096 return "????";
3097 }
3098
3099 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3100 {
3101 int used;
3102
3103 /* chipsets >= AR9280 are single-chip */
3104 if (AR_SREV_9280_20_OR_LATER(ah)) {
3105 used = scnprintf(hw_name, len,
3106 "Atheros AR%s Rev:%x",
3107 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3108 ah->hw_version.macRev);
3109 }
3110 else {
3111 used = scnprintf(hw_name, len,
3112 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3113 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3114 ah->hw_version.macRev,
3115 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3116 & AR_RADIO_SREV_MAJOR)),
3117 ah->hw_version.phyRev);
3118 }
3119
3120 hw_name[used] = '\0';
3121 }
3122 EXPORT_SYMBOL(ath9k_hw_name);
Linux with added FPC-III support