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Staging: unisys: Remove RETINT macro
[linux/fpc-iii.git] / drivers / net / wireless / rtlwifi / rtl8192de / phy.c
blob13196cc4b1d380279e7ce3096b5861ba14087b81
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../pci.h"
32 #include "../ps.h"
33 #include "reg.h"
34 #include "def.h"
35 #include "phy.h"
36 #include "rf.h"
37 #include "dm.h"
38 #include "table.h"
39 #include "sw.h"
40 #include "hw.h"
41
42 #define MAX_RF_IMR_INDEX 12
43 #define MAX_RF_IMR_INDEX_NORMAL 13
44 #define RF_REG_NUM_FOR_C_CUT_5G 6
45 #define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7
46 #define RF_REG_NUM_FOR_C_CUT_2G 5
47 #define RF_CHNL_NUM_5G 19
48 #define RF_CHNL_NUM_5G_40M 17
49 #define TARGET_CHNL_NUM_5G 221
50 #define TARGET_CHNL_NUM_2G 14
51 #define CV_CURVE_CNT 64
52
53 static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
54 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
55 };
56
57 static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
58 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
59 };
60
61 static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
62 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
63 };
64
65 static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
66 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
67 };
68
69 static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
70 BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
71 BIT(10) | BIT(9),
72 BIT(18) | BIT(17) | BIT(16) | BIT(1),
73 BIT(2) | BIT(1),
74 BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
75 };
76
77 static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
78 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
79 112, 116, 120, 124, 128, 132, 136, 140
80 };
81
82 static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
83 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
84 118, 122, 126, 130, 134, 138
85 };
86 static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
87 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
88 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
89 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
90 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
91 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
92 };
93
94 static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
95 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
96 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
97 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
98 };
99
100 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
101
102 static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
103 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
104 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
105 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
106 };
107
108 /* [mode][patha+b][reg] */
109 static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
110 {
111 /* channel 1-14. */
112 {
113 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
114 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
115 },
116 /* path 36-64 */
117 {
118 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
119 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
120 0x32c9a
121 },
122 /* 100 -165 */
123 {
124 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
125 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
126 }
127 }
128 };
129
130 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
131
132 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
133
134 static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
135 25141, 25116, 25091, 25066, 25041,
136 25016, 24991, 24966, 24941, 24917,
137 24892, 24867, 24843, 24818, 24794,
138 24770, 24765, 24721, 24697, 24672,
139 24648, 24624, 24600, 24576, 24552,
140 24528, 24504, 24480, 24457, 24433,
141 24409, 24385, 24362, 24338, 24315,
142 24291, 24268, 24245, 24221, 24198,
143 24175, 24151, 24128, 24105, 24082,
144 24059, 24036, 24013, 23990, 23967,
145 23945, 23922, 23899, 23876, 23854,
146 23831, 23809, 23786, 23764, 23741,
147 23719, 23697, 23674, 23652, 23630,
148 23608, 23586, 23564, 23541, 23519,
149 23498, 23476, 23454, 23432, 23410,
150 23388, 23367, 23345, 23323, 23302,
151 23280, 23259, 23237, 23216, 23194,
152 23173, 23152, 23130, 23109, 23088,
153 23067, 23046, 23025, 23003, 22982,
154 22962, 22941, 22920, 22899, 22878,
155 22857, 22837, 22816, 22795, 22775,
156 22754, 22733, 22713, 22692, 22672,
157 22652, 22631, 22611, 22591, 22570,
158 22550, 22530, 22510, 22490, 22469,
159 22449, 22429, 22409, 22390, 22370,
160 22350, 22336, 22310, 22290, 22271,
161 22251, 22231, 22212, 22192, 22173,
162 22153, 22134, 22114, 22095, 22075,
163 22056, 22037, 22017, 21998, 21979,
164 21960, 21941, 21921, 21902, 21883,
165 21864, 21845, 21826, 21807, 21789,
166 21770, 21751, 21732, 21713, 21695,
167 21676, 21657, 21639, 21620, 21602,
168 21583, 21565, 21546, 21528, 21509,
169 21491, 21473, 21454, 21436, 21418,
170 21400, 21381, 21363, 21345, 21327,
171 21309, 21291, 21273, 21255, 21237,
172 21219, 21201, 21183, 21166, 21148,
173 21130, 21112, 21095, 21077, 21059,
174 21042, 21024, 21007, 20989, 20972,
175 25679, 25653, 25627, 25601, 25575,
176 25549, 25523, 25497, 25471, 25446,
177 25420, 25394, 25369, 25343, 25318,
178 25292, 25267, 25242, 25216, 25191,
179 25166
180 };
181
182 /* channel 1~14 */
183 static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
184 26084, 26030, 25976, 25923, 25869, 25816, 25764,
185 25711, 25658, 25606, 25554, 25502, 25451, 25328
186 };
187
188 static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
189 {
190 u32 i;
191
192 for (i = 0; i <= 31; i++) {
193 if (((bitmask >> i) & 0x1) == 1)
194 break;
195 }
196
197 return i;
198 }
199
200 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
201 {
202 struct rtl_priv *rtlpriv = rtl_priv(hw);
203 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
204 u32 returnvalue, originalvalue, bitshift;
205 u8 dbi_direct;
206
207 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
208 regaddr, bitmask);
209 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
210 /* mac1 use phy0 read radio_b. */
211 /* mac0 use phy1 read radio_b. */
212 if (rtlhal->during_mac1init_radioa)
213 dbi_direct = BIT(3);
214 else if (rtlhal->during_mac0init_radiob)
215 dbi_direct = BIT(3) | BIT(2);
216 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
217 dbi_direct);
218 } else {
219 originalvalue = rtl_read_dword(rtlpriv, regaddr);
220 }
221 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
222 returnvalue = (originalvalue & bitmask) >> bitshift;
223 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
224 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
225 bitmask, regaddr, originalvalue);
226 return returnvalue;
227 }
228
229 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
230 u32 regaddr, u32 bitmask, u32 data)
231 {
232 struct rtl_priv *rtlpriv = rtl_priv(hw);
233 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
234 u8 dbi_direct = 0;
235 u32 originalvalue, bitshift;
236
237 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
238 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
239 regaddr, bitmask, data);
240 if (rtlhal->during_mac1init_radioa)
241 dbi_direct = BIT(3);
242 else if (rtlhal->during_mac0init_radiob)
243 /* mac0 use phy1 write radio_b. */
244 dbi_direct = BIT(3) | BIT(2);
245 if (bitmask != BMASKDWORD) {
246 if (rtlhal->during_mac1init_radioa ||
247 rtlhal->during_mac0init_radiob)
248 originalvalue = rtl92de_read_dword_dbi(hw,
249 (u16) regaddr,
250 dbi_direct);
251 else
252 originalvalue = rtl_read_dword(rtlpriv, regaddr);
253 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
254 data = ((originalvalue & (~bitmask)) | (data << bitshift));
255 }
256 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
257 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
258 else
259 rtl_write_dword(rtlpriv, regaddr, data);
260 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
261 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
262 regaddr, bitmask, data);
263 }
264
265 static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
266 enum radio_path rfpath, u32 offset)
267 {
268
269 struct rtl_priv *rtlpriv = rtl_priv(hw);
270 struct rtl_phy *rtlphy = &(rtlpriv->phy);
271 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
272 u32 newoffset;
273 u32 tmplong, tmplong2;
274 u8 rfpi_enable = 0;
275 u32 retvalue;
276
277 newoffset = offset;
278 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD);
279 if (rfpath == RF90_PATH_A)
280 tmplong2 = tmplong;
281 else
282 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD);
283 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
284 (newoffset << 23) | BLSSIREADEDGE;
285 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
286 tmplong & (~BLSSIREADEDGE));
287 udelay(10);
288 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD, tmplong2);
289 udelay(50);
290 udelay(50);
291 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
292 tmplong | BLSSIREADEDGE);
293 udelay(10);
294 if (rfpath == RF90_PATH_A)
295 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
296 BIT(8));
297 else if (rfpath == RF90_PATH_B)
298 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
299 BIT(8));
300 if (rfpi_enable)
301 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
302 BLSSIREADBACKDATA);
303 else
304 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
305 BLSSIREADBACKDATA);
306 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",
307 rfpath, pphyreg->rf_rb, retvalue);
308 return retvalue;
309 }
310
311 static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
312 enum radio_path rfpath,
313 u32 offset, u32 data)
314 {
315 u32 data_and_addr;
316 u32 newoffset;
317 struct rtl_priv *rtlpriv = rtl_priv(hw);
318 struct rtl_phy *rtlphy = &(rtlpriv->phy);
319 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
320
321 newoffset = offset;
322 /* T65 RF */
323 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
324 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, BMASKDWORD, data_and_addr);
325 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
326 rfpath, pphyreg->rf3wire_offset, data_and_addr);
327 }
328
329 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
330 enum radio_path rfpath, u32 regaddr, u32 bitmask)
331 {
332 struct rtl_priv *rtlpriv = rtl_priv(hw);
333 u32 original_value, readback_value, bitshift;
334 unsigned long flags;
335
336 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
337 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
338 regaddr, rfpath, bitmask);
339 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
340 original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
341 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
342 readback_value = (original_value & bitmask) >> bitshift;
343 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
344 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
345 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
346 regaddr, rfpath, bitmask, original_value);
347 return readback_value;
348 }
349
350 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
351 u32 regaddr, u32 bitmask, u32 data)
352 {
353 struct rtl_priv *rtlpriv = rtl_priv(hw);
354 struct rtl_phy *rtlphy = &(rtlpriv->phy);
355 u32 original_value, bitshift;
356 unsigned long flags;
357
358 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
359 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
360 regaddr, bitmask, data, rfpath);
361 if (bitmask == 0)
362 return;
363 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
364 if (rtlphy->rf_mode != RF_OP_BY_FW) {
365 if (bitmask != BRFREGOFFSETMASK) {
366 original_value = _rtl92d_phy_rf_serial_read(hw,
367 rfpath, regaddr);
368 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
369 data = ((original_value & (~bitmask)) |
370 (data << bitshift));
371 }
372 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
373 }
374 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
375 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
376 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
377 regaddr, bitmask, data, rfpath);
378 }
379
380 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
381 {
382 struct rtl_priv *rtlpriv = rtl_priv(hw);
383 u32 i;
384 u32 arraylength;
385 u32 *ptrarray;
386
387 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
388 arraylength = MAC_2T_ARRAYLENGTH;
389 ptrarray = rtl8192de_mac_2tarray;
390 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n");
391 for (i = 0; i < arraylength; i = i + 2)
392 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
393 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
394 /* improve 2-stream TX EVM */
395 /* rtl_write_byte(rtlpriv, 0x14,0x71); */
396 /* AMPDU aggregation number 9 */
397 /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
398 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
399 } else {
400 /* 92D need to test to decide the num. */
401 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
402 }
403 return true;
404 }
405
406 static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
407 {
408 struct rtl_priv *rtlpriv = rtl_priv(hw);
409 struct rtl_phy *rtlphy = &(rtlpriv->phy);
410
411 /* RF Interface Sowrtware Control */
412 /* 16 LSBs if read 32-bit from 0x870 */
413 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
414 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
415 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
416 /* 16 LSBs if read 32-bit from 0x874 */
417 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
418 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
419
420 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
421 /* RF Interface Readback Value */
422 /* 16 LSBs if read 32-bit from 0x8E0 */
423 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
424 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
425 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
426 /* 16 LSBs if read 32-bit from 0x8E4 */
427 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
428 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
429 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
430
431 /* RF Interface Output (and Enable) */
432 /* 16 LSBs if read 32-bit from 0x860 */
433 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
434 /* 16 LSBs if read 32-bit from 0x864 */
435 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
436
437 /* RF Interface (Output and) Enable */
438 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
439 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
440 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
441 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
442
443 /* Addr of LSSI. Wirte RF register by driver */
444 /* LSSI Parameter */
445 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
446 RFPGA0_XA_LSSIPARAMETER;
447 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
448 RFPGA0_XB_LSSIPARAMETER;
449
450 /* RF parameter */
451 /* BB Band Select */
452 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
453 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
454 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
455 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
456
457 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
458 /* Tx gain stage */
459 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
460 /* Tx gain stage */
461 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
462 /* Tx gain stage */
463 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
464 /* Tx gain stage */
465 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
466
467 /* Tranceiver A~D HSSI Parameter-1 */
468 /* wire control parameter1 */
469 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
470 /* wire control parameter1 */
471 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
472
473 /* Tranceiver A~D HSSI Parameter-2 */
474 /* wire control parameter2 */
475 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
476 /* wire control parameter2 */
477 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
478
479 /* RF switch Control */
480 /* TR/Ant switch control */
481 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
482 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
483 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
484 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
485
486 /* AGC control 1 */
487 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
488 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
489 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
490 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
491
492 /* AGC control 2 */
493 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
494 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
495 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
496 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
497
498 /* RX AFE control 1 */
499 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
500 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
501 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
502 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
503
504 /*RX AFE control 1 */
505 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
506 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
507 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
508 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
509
510 /* Tx AFE control 1 */
511 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATxIQIMBALANCE;
512 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTxIQIMBALANCE;
513 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTxIQIMBALANCE;
514 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTxIQIMBALANCE;
515
516 /* Tx AFE control 2 */
517 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE;
518 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE;
519 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE;
520 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE;
521
522 /* Tranceiver LSSI Readback SI mode */
523 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
524 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
525 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
526 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
527
528 /* Tranceiver LSSI Readback PI mode */
529 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
530 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
531 }
532
533 static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
534 u8 configtype)
535 {
536 int i;
537 u32 *phy_regarray_table;
538 u32 *agctab_array_table = NULL;
539 u32 *agctab_5garray_table;
540 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
541 struct rtl_priv *rtlpriv = rtl_priv(hw);
542 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
543
544 /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */
545 if (rtlhal->interfaceindex == 0) {
546 agctab_arraylen = AGCTAB_ARRAYLENGTH;
547 agctab_array_table = rtl8192de_agctab_array;
548 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
549 " ===> phy:MAC0, Rtl819XAGCTAB_Array\n");
550 } else {
551 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
552 agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
553 agctab_array_table = rtl8192de_agctab_2garray;
554 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
555 " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n");
556 } else {
557 agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
558 agctab_5garray_table = rtl8192de_agctab_5garray;
559 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
560 " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n");
561
562 }
563 }
564 phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
565 phy_regarray_table = rtl8192de_phy_reg_2tarray;
566 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
567 " ===> phy:Rtl819XPHY_REG_Array_PG\n");
568 if (configtype == BASEBAND_CONFIG_PHY_REG) {
569 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
570 if (phy_regarray_table[i] == 0xfe)
571 mdelay(50);
572 else if (phy_regarray_table[i] == 0xfd)
573 mdelay(5);
574 else if (phy_regarray_table[i] == 0xfc)
575 mdelay(1);
576 else if (phy_regarray_table[i] == 0xfb)
577 udelay(50);
578 else if (phy_regarray_table[i] == 0xfa)
579 udelay(5);
580 else if (phy_regarray_table[i] == 0xf9)
581 udelay(1);
582 rtl_set_bbreg(hw, phy_regarray_table[i], BMASKDWORD,
583 phy_regarray_table[i + 1]);
584 udelay(1);
585 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
586 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
587 phy_regarray_table[i],
588 phy_regarray_table[i + 1]);
589 }
590 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
591 if (rtlhal->interfaceindex == 0) {
592 for (i = 0; i < agctab_arraylen; i = i + 2) {
593 rtl_set_bbreg(hw, agctab_array_table[i],
594 BMASKDWORD,
595 agctab_array_table[i + 1]);
596 /* Add 1us delay between BB/RF register
597 * setting. */
598 udelay(1);
599 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
600 "The Rtl819XAGCTAB_Array_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n",
601 agctab_array_table[i],
602 agctab_array_table[i + 1]);
603 }
604 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
605 "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n");
606 } else {
607 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
608 for (i = 0; i < agctab_arraylen; i = i + 2) {
609 rtl_set_bbreg(hw, agctab_array_table[i],
610 BMASKDWORD,
611 agctab_array_table[i + 1]);
612 /* Add 1us delay between BB/RF register
613 * setting. */
614 udelay(1);
615 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
616 "The Rtl819XAGCTAB_Array_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n",
617 agctab_array_table[i],
618 agctab_array_table[i + 1]);
619 }
620 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
621 "Load Rtl819XAGCTAB_2GArray\n");
622 } else {
623 for (i = 0; i < agctab_5garraylen; i = i + 2) {
624 rtl_set_bbreg(hw,
625 agctab_5garray_table[i],
626 BMASKDWORD,
627 agctab_5garray_table[i + 1]);
628 /* Add 1us delay between BB/RF registeri
629 * setting. */
630 udelay(1);
631 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
632 "The Rtl819XAGCTAB_5GArray_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n",
633 agctab_5garray_table[i],
634 agctab_5garray_table[i + 1]);
635 }
636 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
637 "Load Rtl819XAGCTAB_5GArray\n");
638 }
639 }
640 }
641 return true;
642 }
643
644 static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
645 u32 regaddr, u32 bitmask,
646 u32 data)
647 {
648 struct rtl_priv *rtlpriv = rtl_priv(hw);
649 struct rtl_phy *rtlphy = &(rtlpriv->phy);
650 int index;
651
652 if (regaddr == RTXAGC_A_RATE18_06)
653 index = 0;
654 else if (regaddr == RTXAGC_A_RATE54_24)
655 index = 1;
656 else if (regaddr == RTXAGC_A_CCK1_MCS32)
657 index = 6;
658 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
659 index = 7;
660 else if (regaddr == RTXAGC_A_MCS03_MCS00)
661 index = 2;
662 else if (regaddr == RTXAGC_A_MCS07_MCS04)
663 index = 3;
664 else if (regaddr == RTXAGC_A_MCS11_MCS08)
665 index = 4;
666 else if (regaddr == RTXAGC_A_MCS15_MCS12)
667 index = 5;
668 else if (regaddr == RTXAGC_B_RATE18_06)
669 index = 8;
670 else if (regaddr == RTXAGC_B_RATE54_24)
671 index = 9;
672 else if (regaddr == RTXAGC_B_CCK1_55_MCS32)
673 index = 14;
674 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
675 index = 15;
676 else if (regaddr == RTXAGC_B_MCS03_MCS00)
677 index = 10;
678 else if (regaddr == RTXAGC_B_MCS07_MCS04)
679 index = 11;
680 else if (regaddr == RTXAGC_B_MCS11_MCS08)
681 index = 12;
682 else if (regaddr == RTXAGC_B_MCS15_MCS12)
683 index = 13;
684 else
685 return;
686
687 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
688 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
689 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%ulx\n",
690 rtlphy->pwrgroup_cnt, index,
691 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);
692 if (index == 13)
693 rtlphy->pwrgroup_cnt++;
694 }
695
696 static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
697 u8 configtype)
698 {
699 struct rtl_priv *rtlpriv = rtl_priv(hw);
700 int i;
701 u32 *phy_regarray_table_pg;
702 u16 phy_regarray_pg_len;
703
704 phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
705 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
706 if (configtype == BASEBAND_CONFIG_PHY_REG) {
707 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
708 if (phy_regarray_table_pg[i] == 0xfe)
709 mdelay(50);
710 else if (phy_regarray_table_pg[i] == 0xfd)
711 mdelay(5);
712 else if (phy_regarray_table_pg[i] == 0xfc)
713 mdelay(1);
714 else if (phy_regarray_table_pg[i] == 0xfb)
715 udelay(50);
716 else if (phy_regarray_table_pg[i] == 0xfa)
717 udelay(5);
718 else if (phy_regarray_table_pg[i] == 0xf9)
719 udelay(1);
720 _rtl92d_store_pwrindex_diffrate_offset(hw,
721 phy_regarray_table_pg[i],
722 phy_regarray_table_pg[i + 1],
723 phy_regarray_table_pg[i + 2]);
724 }
725 } else {
726 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
727 "configtype != BaseBand_Config_PHY_REG\n");
728 }
729 return true;
730 }
731
732 static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
733 {
734 struct rtl_priv *rtlpriv = rtl_priv(hw);
735 struct rtl_phy *rtlphy = &(rtlpriv->phy);
736 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
737 bool rtstatus = true;
738
739 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
740 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
741 BASEBAND_CONFIG_PHY_REG);
742 if (!rtstatus) {
743 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!\n");
744 return false;
745 }
746
747 /* if (rtlphy->rf_type == RF_1T2R) {
748 * _rtl92c_phy_bb_config_1t(hw);
749 * RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
750 *} */
751
752 if (rtlefuse->autoload_failflag == false) {
753 rtlphy->pwrgroup_cnt = 0;
754 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
755 BASEBAND_CONFIG_PHY_REG);
756 }
757 if (!rtstatus) {
758 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!\n");
759 return false;
760 }
761 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
762 BASEBAND_CONFIG_AGC_TAB);
763 if (!rtstatus) {
764 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
765 return false;
766 }
767 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
768 RFPGA0_XA_HSSIPARAMETER2, 0x200));
769
770 return true;
771 }
772
773 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
774 {
775 struct rtl_priv *rtlpriv = rtl_priv(hw);
776 u16 regval;
777 u32 regvaldw;
778 u8 value;
779
780 _rtl92d_phy_init_bb_rf_register_definition(hw);
781 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
782 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
783 regval | BIT(13) | BIT(0) | BIT(1));
784 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
785 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
786 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
787 value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
788 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
789 RF_SDMRSTB);
790 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
791 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
792 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
793 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
794 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
795 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
796 }
797
798 return _rtl92d_phy_bb_config(hw);
799 }
800
801 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
802 {
803 return rtl92d_phy_rf6052_config(hw);
804 }
805
806 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
807 enum rf_content content,
808 enum radio_path rfpath)
809 {
810 int i;
811 u32 *radioa_array_table;
812 u32 *radiob_array_table;
813 u16 radioa_arraylen, radiob_arraylen;
814 struct rtl_priv *rtlpriv = rtl_priv(hw);
815
816 radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
817 radioa_array_table = rtl8192de_radioa_2tarray;
818 radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
819 radiob_array_table = rtl8192de_radiob_2tarray;
820 if (rtlpriv->efuse.internal_pa_5g[0]) {
821 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
822 radioa_array_table = rtl8192de_radioa_2t_int_paarray;
823 }
824 if (rtlpriv->efuse.internal_pa_5g[1]) {
825 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
826 radiob_array_table = rtl8192de_radiob_2t_int_paarray;
827 }
828 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
829 "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n");
830 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
831 "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n");
832 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
833
834 /* this only happens when DMDP, mac0 start on 2.4G,
835 * mac1 start on 5G, mac 0 has to set phy0&phy1
836 * pathA or mac1 has to set phy0&phy1 pathA */
837 if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
838 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
839 " ===> althougth Path A, we load radiob.txt\n");
840 radioa_arraylen = radiob_arraylen;
841 radioa_array_table = radiob_array_table;
842 }
843 switch (rfpath) {
844 case RF90_PATH_A:
845 for (i = 0; i < radioa_arraylen; i = i + 2) {
846 if (radioa_array_table[i] == 0xfe) {
847 mdelay(50);
848 } else if (radioa_array_table[i] == 0xfd) {
849 /* delay_ms(5); */
850 mdelay(5);
851 } else if (radioa_array_table[i] == 0xfc) {
852 /* delay_ms(1); */
853 mdelay(1);
854 } else if (radioa_array_table[i] == 0xfb) {
855 udelay(50);
856 } else if (radioa_array_table[i] == 0xfa) {
857 udelay(5);
858 } else if (radioa_array_table[i] == 0xf9) {
859 udelay(1);
860 } else {
861 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
862 BRFREGOFFSETMASK,
863 radioa_array_table[i + 1]);
864 /* Add 1us delay between BB/RF register set. */
865 udelay(1);
866 }
867 }
868 break;
869 case RF90_PATH_B:
870 for (i = 0; i < radiob_arraylen; i = i + 2) {
871 if (radiob_array_table[i] == 0xfe) {
872 /* Delay specific ms. Only RF configuration
873 * requires delay. */
874 mdelay(50);
875 } else if (radiob_array_table[i] == 0xfd) {
876 /* delay_ms(5); */
877 mdelay(5);
878 } else if (radiob_array_table[i] == 0xfc) {
879 /* delay_ms(1); */
880 mdelay(1);
881 } else if (radiob_array_table[i] == 0xfb) {
882 udelay(50);
883 } else if (radiob_array_table[i] == 0xfa) {
884 udelay(5);
885 } else if (radiob_array_table[i] == 0xf9) {
886 udelay(1);
887 } else {
888 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
889 BRFREGOFFSETMASK,
890 radiob_array_table[i + 1]);
891 /* Add 1us delay between BB/RF register set. */
892 udelay(1);
893 }
894 }
895 break;
896 case RF90_PATH_C:
897 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
898 "switch case not processed\n");
899 break;
900 case RF90_PATH_D:
901 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
902 "switch case not processed\n");
903 break;
904 }
905 return true;
906 }
907
908 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
909 {
910 struct rtl_priv *rtlpriv = rtl_priv(hw);
911 struct rtl_phy *rtlphy = &(rtlpriv->phy);
912
913 rtlphy->default_initialgain[0] =
914 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, BMASKBYTE0);
915 rtlphy->default_initialgain[1] =
916 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, BMASKBYTE0);
917 rtlphy->default_initialgain[2] =
918 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, BMASKBYTE0);
919 rtlphy->default_initialgain[3] =
920 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, BMASKBYTE0);
921 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
922 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
923 rtlphy->default_initialgain[0],
924 rtlphy->default_initialgain[1],
925 rtlphy->default_initialgain[2],
926 rtlphy->default_initialgain[3]);
927 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
928 BMASKBYTE0);
929 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
930 BMASKDWORD);
931 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
932 "Default framesync (0x%x) = 0x%x\n",
933 ROFDM0_RXDETECTOR3, rtlphy->framesync);
934 }
935
936 static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
937 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
938 {
939 struct rtl_priv *rtlpriv = rtl_priv(hw);
940 struct rtl_phy *rtlphy = &(rtlpriv->phy);
941 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
942 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
943 u8 index = (channel - 1);
944
945 /* 1. CCK */
946 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
947 /* RF-A */
948 cckpowerlevel[RF90_PATH_A] =
949 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
950 /* RF-B */
951 cckpowerlevel[RF90_PATH_B] =
952 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
953 } else {
954 cckpowerlevel[RF90_PATH_A] = 0;
955 cckpowerlevel[RF90_PATH_B] = 0;
956 }
957 /* 2. OFDM for 1S or 2S */
958 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
959 /* Read HT 40 OFDM TX power */
960 ofdmpowerlevel[RF90_PATH_A] =
961 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
962 ofdmpowerlevel[RF90_PATH_B] =
963 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
964 } else if (rtlphy->rf_type == RF_2T2R) {
965 /* Read HT 40 OFDM TX power */
966 ofdmpowerlevel[RF90_PATH_A] =
967 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
968 ofdmpowerlevel[RF90_PATH_B] =
969 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
970 }
971 }
972
973 static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
974 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
975 {
976 struct rtl_priv *rtlpriv = rtl_priv(hw);
977 struct rtl_phy *rtlphy = &(rtlpriv->phy);
978
979 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
980 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
981 }
982
983 static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
984 {
985 u8 channel_5g[59] = {
986 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
987 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
988 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
989 114, 116, 118, 120, 122, 124, 126, 128,
990 130, 132, 134, 136, 138, 140, 149, 151,
991 153, 155, 157, 159, 161, 163, 165
992 };
993 u8 place = chnl;
994
995 if (chnl > 14) {
996 for (place = 14; place < sizeof(channel_5g); place++) {
997 if (channel_5g[place] == chnl) {
998 place++;
999 break;
1000 }
1001 }
1002 }
1003 return place;
1004 }
1005
1006 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1007 {
1008 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1009 struct rtl_priv *rtlpriv = rtl_priv(hw);
1010 u8 cckpowerlevel[2], ofdmpowerlevel[2];
1011
1012 if (!rtlefuse->txpwr_fromeprom)
1013 return;
1014 channel = _rtl92c_phy_get_rightchnlplace(channel);
1015 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
1016 &ofdmpowerlevel[0]);
1017 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
1018 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
1019 &ofdmpowerlevel[0]);
1020 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
1021 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
1022 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
1023 }
1024
1025 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
1026 enum nl80211_channel_type ch_type)
1027 {
1028 struct rtl_priv *rtlpriv = rtl_priv(hw);
1029 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1030 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1031 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1032 unsigned long flag = 0;
1033 u8 reg_prsr_rsc;
1034 u8 reg_bw_opmode;
1035
1036 if (rtlphy->set_bwmode_inprogress)
1037 return;
1038 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
1039 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1040 "FALSE driver sleep or unload\n");
1041 return;
1042 }
1043 rtlphy->set_bwmode_inprogress = true;
1044 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
1045 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1046 "20MHz" : "40MHz");
1047 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1048 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1049 switch (rtlphy->current_chan_bw) {
1050 case HT_CHANNEL_WIDTH_20:
1051 reg_bw_opmode |= BW_OPMODE_20MHZ;
1052 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1053 break;
1054 case HT_CHANNEL_WIDTH_20_40:
1055 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1056 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1057
1058 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
1059 (mac->cur_40_prime_sc << 5);
1060 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1061 break;
1062 default:
1063 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1064 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1065 break;
1066 }
1067 switch (rtlphy->current_chan_bw) {
1068 case HT_CHANNEL_WIDTH_20:
1069 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1070 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1071 /* SET BIT10 BIT11 for receive cck */
1072 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1073 BIT(11), 3);
1074 break;
1075 case HT_CHANNEL_WIDTH_20_40:
1076 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1077 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1078 /* Set Control channel to upper or lower.
1079 * These settings are required only for 40MHz */
1080 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1081 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1082 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
1083 (mac->cur_40_prime_sc >> 1));
1084 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1085 }
1086 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1087 /* SET BIT10 BIT11 for receive cck */
1088 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1089 BIT(11), 0);
1090 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1091 (mac->cur_40_prime_sc ==
1092 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1093 break;
1094 default:
1095 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1096 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1097 break;
1098
1099 }
1100 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1101 rtlphy->set_bwmode_inprogress = false;
1102 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
1103 }
1104
1105 static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1106 {
1107 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1108 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1109 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x00);
1110 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1111 }
1112
1113 static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1114 {
1115 struct rtl_priv *rtlpriv = rtl_priv(hw);
1116 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1117 u8 value8;
1118
1119 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
1120 rtlhal->bandset = band;
1121 rtlhal->current_bandtype = band;
1122 if (IS_92D_SINGLEPHY(rtlhal->version))
1123 rtlhal->bandset = BAND_ON_BOTH;
1124 /* stop RX/Tx */
1125 _rtl92d_phy_stop_trx_before_changeband(hw);
1126 /* reconfig BB/RF according to wireless mode */
1127 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1128 /* BB & RF Config */
1129 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n");
1130 if (rtlhal->interfaceindex == 1)
1131 _rtl92d_phy_config_bb_with_headerfile(hw,
1132 BASEBAND_CONFIG_AGC_TAB);
1133 } else {
1134 /* 5G band */
1135 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n");
1136 if (rtlhal->interfaceindex == 1)
1137 _rtl92d_phy_config_bb_with_headerfile(hw,
1138 BASEBAND_CONFIG_AGC_TAB);
1139 }
1140 rtl92d_update_bbrf_configuration(hw);
1141 if (rtlhal->current_bandtype == BAND_ON_2_4G)
1142 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1143 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1144
1145 /* 20M BW. */
1146 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */
1147 rtlhal->reloadtxpowerindex = true;
1148 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
1149 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1150 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1151 0 ? REG_MAC0 : REG_MAC1));
1152 value8 |= BIT(1);
1153 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1154 0 ? REG_MAC0 : REG_MAC1), value8);
1155 } else {
1156 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1157 0 ? REG_MAC0 : REG_MAC1));
1158 value8 &= (~BIT(1));
1159 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1160 0 ? REG_MAC0 : REG_MAC1), value8);
1161 }
1162 mdelay(1);
1163 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n");
1164 }
1165
1166 static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1167 u8 channel, u8 rfpath)
1168 {
1169 struct rtl_priv *rtlpriv = rtl_priv(hw);
1170 u32 imr_num = MAX_RF_IMR_INDEX;
1171 u32 rfmask = BRFREGOFFSETMASK;
1172 u8 group, i;
1173 unsigned long flag = 0;
1174
1175 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath);
1176 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1177 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1178 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1179 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1180 /* fc area 0xd2c */
1181 if (channel > 99)
1182 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1183 BIT(14), 2);
1184 else
1185 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1186 BIT(14), 1);
1187 /* leave 0 for channel1-14. */
1188 group = channel <= 64 ? 1 : 2;
1189 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1190 for (i = 0; i < imr_num; i++)
1191 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1192 rf_reg_for_5g_swchnl_normal[i], rfmask,
1193 rf_imr_param_normal[0][group][i]);
1194 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1195 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1196 } else {
1197 /* G band. */
1198 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1199 "Load RF IMR parameters for G band. IMR already setting %d\n",
1200 rtlpriv->rtlhal.load_imrandiqk_setting_for2g);
1201 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1202 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1203 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1204 "Load RF IMR parameters for G band. %d\n",
1205 rfpath);
1206 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1207 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1208 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1209 0x00f00000, 0xf);
1210 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1211 for (i = 0; i < imr_num; i++) {
1212 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1213 rf_reg_for_5g_swchnl_normal[i],
1214 BRFREGOFFSETMASK,
1215 rf_imr_param_normal[0][0][i]);
1216 }
1217 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1218 0x00f00000, 0);
1219 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1220 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1221 }
1222 }
1223 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1224 }
1225
1226 static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1227 u8 rfpath, u32 *pu4_regval)
1228 {
1229 struct rtl_priv *rtlpriv = rtl_priv(hw);
1230 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1231 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1232
1233 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
1234 /*----Store original RFENV control type----*/
1235 switch (rfpath) {
1236 case RF90_PATH_A:
1237 case RF90_PATH_C:
1238 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1239 break;
1240 case RF90_PATH_B:
1241 case RF90_PATH_D:
1242 *pu4_regval =
1243 rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1244 break;
1245 }
1246 /*----Set RF_ENV enable----*/
1247 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1248 udelay(1);
1249 /*----Set RF_ENV output high----*/
1250 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1251 udelay(1);
1252 /* Set bit number of Address and Data for RF register */
1253 /* Set 1 to 4 bits for 8255 */
1254 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1255 udelay(1);
1256 /*Set 0 to 12 bits for 8255 */
1257 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1258 udelay(1);
1259 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
1260 }
1261
1262 static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1263 u32 *pu4_regval)
1264 {
1265 struct rtl_priv *rtlpriv = rtl_priv(hw);
1266 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1267 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1268
1269 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n");
1270 /*----Restore RFENV control type----*/
1271 switch (rfpath) {
1272 case RF90_PATH_A:
1273 case RF90_PATH_C:
1274 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1275 break;
1276 case RF90_PATH_B:
1277 case RF90_PATH_D:
1278 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1279 *pu4_regval);
1280 break;
1281 }
1282 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n");
1283 }
1284
1285 static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1286 {
1287 struct rtl_priv *rtlpriv = rtl_priv(hw);
1288 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1289 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1290 u8 path = rtlhal->current_bandtype ==
1291 BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1292 u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1293 bool need_pwr_down = false, internal_pa = false;
1294 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1295
1296 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n");
1297 /* config path A for 5G */
1298 if (rtlhal->current_bandtype == BAND_ON_5G) {
1299 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1300 u4tmp = curveindex_5g[channel - 1];
1301 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1302 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
1303 for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1304 if (channel == rf_chnl_5g[i] && channel <= 140)
1305 index = 0;
1306 }
1307 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1308 if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1309 index = 1;
1310 }
1311 if (channel == 149 || channel == 155 || channel == 161)
1312 index = 2;
1313 else if (channel == 151 || channel == 153 || channel == 163
1314 || channel == 165)
1315 index = 3;
1316 else if (channel == 157 || channel == 159)
1317 index = 4;
1318
1319 if (rtlhal->macphymode == DUALMAC_DUALPHY
1320 && rtlhal->interfaceindex == 1) {
1321 need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1322 rtlhal->during_mac1init_radioa = true;
1323 /* asume no this case */
1324 if (need_pwr_down)
1325 _rtl92d_phy_enable_rf_env(hw, path,
1326 &u4regvalue);
1327 }
1328 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1329 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1330 rtl_set_rfreg(hw, (enum radio_path)path,
1331 rf_reg_for_c_cut_5g[i],
1332 BRFREGOFFSETMASK, 0xE439D);
1333 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1334 u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1335 0x7FF) | (u4tmp << 11);
1336 if (channel == 36)
1337 u4tmp2 &= ~(BIT(7) | BIT(6));
1338 rtl_set_rfreg(hw, (enum radio_path)path,
1339 rf_reg_for_c_cut_5g[i],
1340 BRFREGOFFSETMASK, u4tmp2);
1341 } else {
1342 rtl_set_rfreg(hw, (enum radio_path)path,
1343 rf_reg_for_c_cut_5g[i],
1344 BRFREGOFFSETMASK,
1345 rf_reg_pram_c_5g[index][i]);
1346 }
1347 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1348 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n",
1349 rf_reg_for_c_cut_5g[i],
1350 rf_reg_pram_c_5g[index][i],
1351 path, index,
1352 rtl_get_rfreg(hw, (enum radio_path)path,
1353 rf_reg_for_c_cut_5g[i],
1354 BRFREGOFFSETMASK));
1355 }
1356 if (need_pwr_down)
1357 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1358 if (rtlhal->during_mac1init_radioa)
1359 rtl92d_phy_powerdown_anotherphy(hw, false);
1360 if (channel < 149)
1361 value = 0x07;
1362 else if (channel >= 149)
1363 value = 0x02;
1364 if (channel >= 36 && channel <= 64)
1365 index = 0;
1366 else if (channel >= 100 && channel <= 140)
1367 index = 1;
1368 else
1369 index = 2;
1370 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1371 rfpath++) {
1372 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1373 rtlhal->interfaceindex == 1) /* MAC 1 5G */
1374 internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1375 else
1376 internal_pa =
1377 rtlpriv->efuse.internal_pa_5g[rfpath];
1378 if (internal_pa) {
1379 for (i = 0;
1380 i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1381 i++) {
1382 rtl_set_rfreg(hw, rfpath,
1383 rf_for_c_cut_5g_internal_pa[i],
1384 BRFREGOFFSETMASK,
1385 rf_pram_c_5g_int_pa[index][i]);
1386 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
1387 "offset 0x%x value 0x%x path %d index %d\n",
1388 rf_for_c_cut_5g_internal_pa[i],
1389 rf_pram_c_5g_int_pa[index][i],
1390 rfpath, index);
1391 }
1392 } else {
1393 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1394 mask, value);
1395 }
1396 }
1397 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1398 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1399 u4tmp = curveindex_2g[channel - 1];
1400 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1401 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
1402 if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1403 || channel == 10 || channel == 11 || channel == 12)
1404 index = 0;
1405 else if (channel == 3 || channel == 13 || channel == 14)
1406 index = 1;
1407 else if (channel >= 5 && channel <= 8)
1408 index = 2;
1409 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1410 path = RF90_PATH_A;
1411 if (rtlhal->interfaceindex == 0) {
1412 need_pwr_down =
1413 rtl92d_phy_enable_anotherphy(hw, true);
1414 rtlhal->during_mac0init_radiob = true;
1415
1416 if (need_pwr_down)
1417 _rtl92d_phy_enable_rf_env(hw, path,
1418 &u4regvalue);
1419 }
1420 }
1421 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1422 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1423 rtl_set_rfreg(hw, (enum radio_path)path,
1424 rf_reg_for_c_cut_2g[i],
1425 BRFREGOFFSETMASK,
1426 (rf_reg_param_for_c_cut_2g[index][i] |
1427 BIT(17)));
1428 else
1429 rtl_set_rfreg(hw, (enum radio_path)path,
1430 rf_reg_for_c_cut_2g[i],
1431 BRFREGOFFSETMASK,
1432 rf_reg_param_for_c_cut_2g
1433 [index][i]);
1434 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1435 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n",
1436 rf_reg_for_c_cut_2g[i],
1437 rf_reg_param_for_c_cut_2g[index][i],
1438 rf_reg_mask_for_c_cut_2g[i], path, index,
1439 rtl_get_rfreg(hw, (enum radio_path)path,
1440 rf_reg_for_c_cut_2g[i],
1441 BRFREGOFFSETMASK));
1442 }
1443 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1444 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1445 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1446
1447 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1448 BRFREGOFFSETMASK,
1449 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1450 if (need_pwr_down)
1451 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1452 if (rtlhal->during_mac0init_radiob)
1453 rtl92d_phy_powerdown_anotherphy(hw, true);
1454 }
1455 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1456 }
1457
1458 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1459 {
1460 u8 channel_all[59] = {
1461 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1462 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1463 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1464 114, 116, 118, 120, 122, 124, 126, 128, 130,
1465 132, 134, 136, 138, 140, 149, 151, 153, 155,
1466 157, 159, 161, 163, 165
1467 };
1468 u8 place = chnl;
1469
1470 if (chnl > 14) {
1471 for (place = 14; place < sizeof(channel_all); place++) {
1472 if (channel_all[place] == chnl)
1473 return place - 13;
1474 }
1475 }
1476
1477 return 0;
1478 }
1479
1480 #define MAX_TOLERANCE 5
1481 #define IQK_DELAY_TIME 1 /* ms */
1482 #define MAX_TOLERANCE_92D 3
1483
1484 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1485 static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1486 {
1487 struct rtl_priv *rtlpriv = rtl_priv(hw);
1488 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1489 u32 regeac, rege94, rege9c, regea4;
1490 u8 result = 0;
1491
1492 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
1493 /* path-A IQK setting */
1494 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1495 if (rtlhal->interfaceindex == 0) {
1496 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c1f);
1497 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c1f);
1498 } else {
1499 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c22);
1500 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c22);
1501 }
1502 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140102);
1503 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x28160206);
1504 /* path-B IQK setting */
1505 if (configpathb) {
1506 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x10008c22);
1507 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x10008c22);
1508 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140102);
1509 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x28160206);
1510 }
1511 /* LO calibration setting */
1512 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1513 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1514 /* One shot, path A LOK & IQK */
1515 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
1516 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1517 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1518 /* delay x ms */
1519 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1520 "Delay %d ms for One shot, path A LOK & IQK\n",
1521 IQK_DELAY_TIME);
1522 mdelay(IQK_DELAY_TIME);
1523 /* Check failed */
1524 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1525 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1526 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
1527 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1528 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
1529 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1530 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
1531 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1532 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1533 (((rege9c & 0x03FF0000) >> 16) != 0x42))
1534 result |= 0x01;
1535 else /* if Tx not OK, ignore Rx */
1536 return result;
1537 /* if Tx is OK, check whether Rx is OK */
1538 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1539 (((regeac & 0x03FF0000) >> 16) != 0x36))
1540 result |= 0x02;
1541 else
1542 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n");
1543 return result;
1544 }
1545
1546 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1547 static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1548 bool configpathb)
1549 {
1550 struct rtl_priv *rtlpriv = rtl_priv(hw);
1551 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1552 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1553 u32 regeac, rege94, rege9c, regea4;
1554 u8 result = 0;
1555 u8 i;
1556 u8 retrycount = 2;
1557 u32 TxOKBit = BIT(28), RxOKBit = BIT(27);
1558
1559 if (rtlhal->interfaceindex == 1) { /* PHY1 */
1560 TxOKBit = BIT(31);
1561 RxOKBit = BIT(30);
1562 }
1563 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
1564 /* path-A IQK setting */
1565 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1566 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1567 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1568 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140307);
1569 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68160960);
1570 /* path-B IQK setting */
1571 if (configpathb) {
1572 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
1573 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
1574 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82110000);
1575 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68110000);
1576 }
1577 /* LO calibration setting */
1578 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1579 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1580 /* path-A PA on */
1581 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x07000f60);
1582 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD, 0x66e60e30);
1583 for (i = 0; i < retrycount; i++) {
1584 /* One shot, path A LOK & IQK */
1585 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1586 "One shot, path A LOK & IQK!\n");
1587 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1588 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1589 /* delay x ms */
1590 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1591 "Delay %d ms for One shot, path A LOK & IQK.\n",
1592 IQK_DELAY_TIME);
1593 mdelay(IQK_DELAY_TIME * 10);
1594 /* Check failed */
1595 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1596 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1597 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
1598 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1599 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
1600 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1601 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
1602 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1603 if (!(regeac & TxOKBit) &&
1604 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1605 result |= 0x01;
1606 } else { /* if Tx not OK, ignore Rx */
1607 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1608 "Path A Tx IQK fail!!\n");
1609 continue;
1610 }
1611
1612 /* if Tx is OK, check whether Rx is OK */
1613 if (!(regeac & RxOKBit) &&
1614 (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1615 result |= 0x02;
1616 break;
1617 } else {
1618 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1619 "Path A Rx IQK fail!!\n");
1620 }
1621 }
1622 /* path A PA off */
1623 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
1624 rtlphy->iqk_bb_backup[0]);
1625 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD,
1626 rtlphy->iqk_bb_backup[1]);
1627 return result;
1628 }
1629
1630 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1631 static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1632 {
1633 struct rtl_priv *rtlpriv = rtl_priv(hw);
1634 u32 regeac, regeb4, regebc, regec4, regecc;
1635 u8 result = 0;
1636
1637 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
1638 /* One shot, path B LOK & IQK */
1639 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
1640 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000002);
1641 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000000);
1642 /* delay x ms */
1643 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1644 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
1645 mdelay(IQK_DELAY_TIME);
1646 /* Check failed */
1647 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1648 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1649 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
1650 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1651 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
1652 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1653 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
1654 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1655 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
1656 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1657 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1658 (((regebc & 0x03FF0000) >> 16) != 0x42))
1659 result |= 0x01;
1660 else
1661 return result;
1662 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1663 (((regecc & 0x03FF0000) >> 16) != 0x36))
1664 result |= 0x02;
1665 else
1666 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n");
1667 return result;
1668 }
1669
1670 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1671 static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1672 {
1673 struct rtl_priv *rtlpriv = rtl_priv(hw);
1674 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1675 u32 regeac, regeb4, regebc, regec4, regecc;
1676 u8 result = 0;
1677 u8 i;
1678 u8 retrycount = 2;
1679
1680 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
1681 /* path-A IQK setting */
1682 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1683 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1684 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1685 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82110000);
1686 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68110000);
1687
1688 /* path-B IQK setting */
1689 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
1690 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
1691 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140307);
1692 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68160960);
1693
1694 /* LO calibration setting */
1695 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1696 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1697
1698 /* path-B PA on */
1699 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x0f600700);
1700 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD, 0x061f0d30);
1701
1702 for (i = 0; i < retrycount; i++) {
1703 /* One shot, path B LOK & IQK */
1704 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1705 "One shot, path A LOK & IQK!\n");
1706 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xfa000000);
1707 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1708
1709 /* delay x ms */
1710 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1711 "Delay %d ms for One shot, path B LOK & IQK.\n", 10);
1712 mdelay(IQK_DELAY_TIME * 10);
1713
1714 /* Check failed */
1715 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1716 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1717 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
1718 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1719 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
1720 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1721 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
1722 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1723 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
1724 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1725 if (!(regeac & BIT(31)) &&
1726 (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1727 result |= 0x01;
1728 else
1729 continue;
1730 if (!(regeac & BIT(30)) &&
1731 (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1732 result |= 0x02;
1733 break;
1734 } else {
1735 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1736 "Path B Rx IQK fail!!\n");
1737 }
1738 }
1739
1740 /* path B PA off */
1741 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
1742 rtlphy->iqk_bb_backup[0]);
1743 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD,
1744 rtlphy->iqk_bb_backup[2]);
1745 return result;
1746 }
1747
1748 static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1749 u32 *adda_reg, u32 *adda_backup,
1750 u32 regnum)
1751 {
1752 struct rtl_priv *rtlpriv = rtl_priv(hw);
1753 u32 i;
1754
1755 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n");
1756 for (i = 0; i < regnum; i++)
1757 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], BMASKDWORD);
1758 }
1759
1760 static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1761 u32 *macreg, u32 *macbackup)
1762 {
1763 struct rtl_priv *rtlpriv = rtl_priv(hw);
1764 u32 i;
1765
1766 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n");
1767 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1768 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1769 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1770 }
1771
1772 static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1773 u32 *adda_reg, u32 *adda_backup,
1774 u32 regnum)
1775 {
1776 struct rtl_priv *rtlpriv = rtl_priv(hw);
1777 u32 i;
1778
1779 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1780 "Reload ADDA power saving parameters !\n");
1781 for (i = 0; i < regnum; i++)
1782 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, adda_backup[i]);
1783 }
1784
1785 static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1786 u32 *macreg, u32 *macbackup)
1787 {
1788 struct rtl_priv *rtlpriv = rtl_priv(hw);
1789 u32 i;
1790
1791 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Reload MAC parameters !\n");
1792 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1793 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1794 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1795 }
1796
1797 static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1798 u32 *adda_reg, bool patha_on, bool is2t)
1799 {
1800 struct rtl_priv *rtlpriv = rtl_priv(hw);
1801 u32 pathon;
1802 u32 i;
1803
1804 RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n");
1805 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1806 if (patha_on)
1807 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1808 0x04db25a4 : 0x0b1b25a4;
1809 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1810 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, pathon);
1811 }
1812
1813 static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1814 u32 *macreg, u32 *macbackup)
1815 {
1816 struct rtl_priv *rtlpriv = rtl_priv(hw);
1817 u32 i;
1818
1819 RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n");
1820 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1821
1822 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1823 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1824 (~BIT(3))));
1825 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1826 }
1827
1828 static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1829 {
1830 struct rtl_priv *rtlpriv = rtl_priv(hw);
1831 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n");
1832
1833 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x0);
1834 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD, 0x00010000);
1835 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
1836 }
1837
1838 static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1839 {
1840 struct rtl_priv *rtlpriv = rtl_priv(hw);
1841 u32 mode;
1842
1843 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1844 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
1845 mode = pi_mode ? 0x01000100 : 0x01000000;
1846 rtl_set_bbreg(hw, 0x820, BMASKDWORD, mode);
1847 rtl_set_bbreg(hw, 0x828, BMASKDWORD, mode);
1848 }
1849
1850 static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1851 u8 t, bool is2t)
1852 {
1853 struct rtl_priv *rtlpriv = rtl_priv(hw);
1854 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1855 u32 i;
1856 u8 patha_ok, pathb_ok;
1857 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1858 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1859 0xe78, 0xe7c, 0xe80, 0xe84,
1860 0xe88, 0xe8c, 0xed0, 0xed4,
1861 0xed8, 0xedc, 0xee0, 0xeec
1862 };
1863 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1864 0x522, 0x550, 0x551, 0x040
1865 };
1866 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1867 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1868 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1869 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1870 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1871 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1872 };
1873 const u32 retrycount = 2;
1874 u32 bbvalue;
1875
1876 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n");
1877 if (t == 0) {
1878 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
1879 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
1880 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1881 is2t ? "2T2R" : "1T1R");
1882
1883 /* Save ADDA parameters, turn Path A ADDA on */
1884 _rtl92d_phy_save_adda_registers(hw, adda_reg,
1885 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1886 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1887 rtlphy->iqk_mac_backup);
1888 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1889 rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
1890 }
1891 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1892 if (t == 0)
1893 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1894 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1895
1896 /* Switch BB to PI mode to do IQ Calibration. */
1897 if (!rtlphy->rfpi_enable)
1898 _rtl92d_phy_pimode_switch(hw, true);
1899
1900 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1901 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
1902 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
1903 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22204000);
1904 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1905 if (is2t) {
1906 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD,
1907 0x00010000);
1908 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, BMASKDWORD,
1909 0x00010000);
1910 }
1911 /* MAC settings */
1912 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1913 rtlphy->iqk_mac_backup);
1914 /* Page B init */
1915 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
1916 if (is2t)
1917 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
1918 /* IQ calibration setting */
1919 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
1920 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
1921 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x01007c00);
1922 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
1923 for (i = 0; i < retrycount; i++) {
1924 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
1925 if (patha_ok == 0x03) {
1926 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1927 "Path A IQK Success!!\n");
1928 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
1929 0x3FF0000) >> 16;
1930 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
1931 0x3FF0000) >> 16;
1932 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
1933 0x3FF0000) >> 16;
1934 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
1935 0x3FF0000) >> 16;
1936 break;
1937 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
1938 /* Tx IQK OK */
1939 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1940 "Path A IQK Only Tx Success!!\n");
1941
1942 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
1943 0x3FF0000) >> 16;
1944 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
1945 0x3FF0000) >> 16;
1946 }
1947 }
1948 if (0x00 == patha_ok)
1949 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK failed!!\n");
1950 if (is2t) {
1951 _rtl92d_phy_patha_standby(hw);
1952 /* Turn Path B ADDA on */
1953 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
1954 for (i = 0; i < retrycount; i++) {
1955 pathb_ok = _rtl92d_phy_pathb_iqk(hw);
1956 if (pathb_ok == 0x03) {
1957 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1958 "Path B IQK Success!!\n");
1959 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1960 BMASKDWORD) & 0x3FF0000) >> 16;
1961 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1962 BMASKDWORD) & 0x3FF0000) >> 16;
1963 result[t][6] = (rtl_get_bbreg(hw, 0xec4,
1964 BMASKDWORD) & 0x3FF0000) >> 16;
1965 result[t][7] = (rtl_get_bbreg(hw, 0xecc,
1966 BMASKDWORD) & 0x3FF0000) >> 16;
1967 break;
1968 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1969 /* Tx IQK OK */
1970 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1971 "Path B Only Tx IQK Success!!\n");
1972 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1973 BMASKDWORD) & 0x3FF0000) >> 16;
1974 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1975 BMASKDWORD) & 0x3FF0000) >> 16;
1976 }
1977 }
1978 if (0x00 == pathb_ok)
1979 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1980 "Path B IQK failed!!\n");
1981 }
1982
1983 /* Back to BB mode, load original value */
1984 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1985 "IQK:Back to BB mode, load original value!\n");
1986
1987 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
1988 if (t != 0) {
1989 /* Switch back BB to SI mode after finish IQ Calibration. */
1990 if (!rtlphy->rfpi_enable)
1991 _rtl92d_phy_pimode_switch(hw, false);
1992 /* Reload ADDA power saving parameters */
1993 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
1994 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1995 /* Reload MAC parameters */
1996 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
1997 rtlphy->iqk_mac_backup);
1998 if (is2t)
1999 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2000 rtlphy->iqk_bb_backup,
2001 IQK_BB_REG_NUM);
2002 else
2003 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2004 rtlphy->iqk_bb_backup,
2005 IQK_BB_REG_NUM - 1);
2006 /* load 0xe30 IQC default value */
2007 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x01008c00);
2008 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x01008c00);
2009 }
2010 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n");
2011 }
2012
2013 static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2014 long result[][8], u8 t)
2015 {
2016 struct rtl_priv *rtlpriv = rtl_priv(hw);
2017 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2018 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2019 u8 patha_ok, pathb_ok;
2020 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
2021 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
2022 0xe78, 0xe7c, 0xe80, 0xe84,
2023 0xe88, 0xe8c, 0xed0, 0xed4,
2024 0xed8, 0xedc, 0xee0, 0xeec
2025 };
2026 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2027 0x522, 0x550, 0x551, 0x040
2028 };
2029 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2030 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
2031 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
2032 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
2033 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
2034 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
2035 };
2036 u32 bbvalue;
2037 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2038
2039 /* Note: IQ calibration must be performed after loading
2040 * PHY_REG.txt , and radio_a, radio_b.txt */
2041
2042 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n");
2043 mdelay(IQK_DELAY_TIME * 20);
2044 if (t == 0) {
2045 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
2046 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
2047 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
2048 is2t ? "2T2R" : "1T1R");
2049 /* Save ADDA parameters, turn Path A ADDA on */
2050 _rtl92d_phy_save_adda_registers(hw, adda_reg,
2051 rtlphy->adda_backup,
2052 IQK_ADDA_REG_NUM);
2053 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
2054 rtlphy->iqk_mac_backup);
2055 if (is2t)
2056 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2057 rtlphy->iqk_bb_backup,
2058 IQK_BB_REG_NUM);
2059 else
2060 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2061 rtlphy->iqk_bb_backup,
2062 IQK_BB_REG_NUM - 1);
2063 }
2064 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
2065 /* MAC settings */
2066 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
2067 rtlphy->iqk_mac_backup);
2068 if (t == 0)
2069 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
2070 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
2071 /* Switch BB to PI mode to do IQ Calibration. */
2072 if (!rtlphy->rfpi_enable)
2073 _rtl92d_phy_pimode_switch(hw, true);
2074 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2075 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
2076 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
2077 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22208000);
2078 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2079
2080 /* Page B init */
2081 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
2082 if (is2t)
2083 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
2084 /* IQ calibration setting */
2085 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
2086 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2087 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x10007c00);
2088 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
2089 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
2090 if (patha_ok == 0x03) {
2091 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n");
2092 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2093 0x3FF0000) >> 16;
2094 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2095 0x3FF0000) >> 16;
2096 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
2097 0x3FF0000) >> 16;
2098 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
2099 0x3FF0000) >> 16;
2100 } else if (patha_ok == 0x01) { /* Tx IQK OK */
2101 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2102 "Path A IQK Only Tx Success!!\n");
2103
2104 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2105 0x3FF0000) >> 16;
2106 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2107 0x3FF0000) >> 16;
2108 } else {
2109 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n");
2110 }
2111 if (is2t) {
2112 /* _rtl92d_phy_patha_standby(hw); */
2113 /* Turn Path B ADDA on */
2114 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2115 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2116 if (pathb_ok == 0x03) {
2117 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2118 "Path B IQK Success!!\n");
2119 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2120 0x3FF0000) >> 16;
2121 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
2122 0x3FF0000) >> 16;
2123 result[t][6] = (rtl_get_bbreg(hw, 0xec4, BMASKDWORD) &
2124 0x3FF0000) >> 16;
2125 result[t][7] = (rtl_get_bbreg(hw, 0xecc, BMASKDWORD) &
2126 0x3FF0000) >> 16;
2127 } else if (pathb_ok == 0x01) { /* Tx IQK OK */
2128 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2129 "Path B Only Tx IQK Success!!\n");
2130 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2131 0x3FF0000) >> 16;
2132 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
2133 0x3FF0000) >> 16;
2134 } else {
2135 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2136 "Path B IQK failed!!\n");
2137 }
2138 }
2139
2140 /* Back to BB mode, load original value */
2141 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2142 "IQK:Back to BB mode, load original value!\n");
2143 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
2144 if (t != 0) {
2145 if (is2t)
2146 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2147 rtlphy->iqk_bb_backup,
2148 IQK_BB_REG_NUM);
2149 else
2150 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2151 rtlphy->iqk_bb_backup,
2152 IQK_BB_REG_NUM - 1);
2153 /* Reload MAC parameters */
2154 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2155 rtlphy->iqk_mac_backup);
2156 /* Switch back BB to SI mode after finish IQ Calibration. */
2157 if (!rtlphy->rfpi_enable)
2158 _rtl92d_phy_pimode_switch(hw, false);
2159 /* Reload ADDA power saving parameters */
2160 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2161 rtlphy->adda_backup,
2162 IQK_ADDA_REG_NUM);
2163 }
2164 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n");
2165 }
2166
2167 static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2168 long result[][8], u8 c1, u8 c2)
2169 {
2170 struct rtl_priv *rtlpriv = rtl_priv(hw);
2171 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2172 u32 i, j, diff, sim_bitmap, bound;
2173 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
2174 bool bresult = true;
2175 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2176
2177 if (is2t)
2178 bound = 8;
2179 else
2180 bound = 4;
2181 sim_bitmap = 0;
2182 for (i = 0; i < bound; i++) {
2183 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2184 result[c2][i]) : (result[c2][i] - result[c1][i]);
2185 if (diff > MAX_TOLERANCE_92D) {
2186 if ((i == 2 || i == 6) && !sim_bitmap) {
2187 if (result[c1][i] + result[c1][i + 1] == 0)
2188 final_candidate[(i / 4)] = c2;
2189 else if (result[c2][i] + result[c2][i + 1] == 0)
2190 final_candidate[(i / 4)] = c1;
2191 else
2192 sim_bitmap = sim_bitmap | (1 << i);
2193 } else {
2194 sim_bitmap = sim_bitmap | (1 << i);
2195 }
2196 }
2197 }
2198 if (sim_bitmap == 0) {
2199 for (i = 0; i < (bound / 4); i++) {
2200 if (final_candidate[i] != 0xFF) {
2201 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2202 result[3][j] =
2203 result[final_candidate[i]][j];
2204 bresult = false;
2205 }
2206 }
2207 return bresult;
2208 }
2209 if (!(sim_bitmap & 0x0F)) { /* path A OK */
2210 for (i = 0; i < 4; i++)
2211 result[3][i] = result[c1][i];
2212 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */
2213 for (i = 0; i < 2; i++)
2214 result[3][i] = result[c1][i];
2215 }
2216 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */
2217 for (i = 4; i < 8; i++)
2218 result[3][i] = result[c1][i];
2219 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */
2220 for (i = 4; i < 6; i++)
2221 result[3][i] = result[c1][i];
2222 }
2223 return false;
2224 }
2225
2226 static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2227 bool iqk_ok, long result[][8],
2228 u8 final_candidate, bool txonly)
2229 {
2230 struct rtl_priv *rtlpriv = rtl_priv(hw);
2231 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2232 u32 oldval_0, val_x, tx0_a, reg;
2233 long val_y, tx0_c;
2234 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2235 rtlhal->macphymode == DUALMAC_DUALPHY;
2236
2237 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2238 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed");
2239 if (final_candidate == 0xFF) {
2240 return;
2241 } else if (iqk_ok) {
2242 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2243 BMASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */
2244 val_x = result[final_candidate][0];
2245 if ((val_x & 0x00000200) != 0)
2246 val_x = val_x | 0xFFFFFC00;
2247 tx0_a = (val_x * oldval_0) >> 8;
2248 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2249 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
2250 val_x, tx0_a, oldval_0);
2251 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a);
2252 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2253 ((val_x * oldval_0 >> 7) & 0x1));
2254 val_y = result[final_candidate][1];
2255 if ((val_y & 0x00000200) != 0)
2256 val_y = val_y | 0xFFFFFC00;
2257 /* path B IQK result + 3 */
2258 if (rtlhal->interfaceindex == 1 &&
2259 rtlhal->current_bandtype == BAND_ON_5G)
2260 val_y += 3;
2261 tx0_c = (val_y * oldval_0) >> 8;
2262 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2263 "Y = 0x%lx, tx0_c = 0x%lx\n",
2264 val_y, tx0_c);
2265 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000,
2266 ((tx0_c & 0x3C0) >> 6));
2267 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000,
2268 (tx0_c & 0x3F));
2269 if (is2t)
2270 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2271 ((val_y * oldval_0 >> 7) & 0x1));
2272 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2273 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2274 BMASKDWORD));
2275 if (txonly) {
2276 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n");
2277 return;
2278 }
2279 reg = result[final_candidate][2];
2280 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2281 reg = result[final_candidate][3] & 0x3F;
2282 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2283 reg = (result[final_candidate][3] >> 6) & 0xF;
2284 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2285 }
2286 }
2287
2288 static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2289 bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2290 {
2291 struct rtl_priv *rtlpriv = rtl_priv(hw);
2292 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2293 u32 oldval_1, val_x, tx1_a, reg;
2294 long val_y, tx1_c;
2295
2296 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n",
2297 iqk_ok ? "Success" : "Failed");
2298 if (final_candidate == 0xFF) {
2299 return;
2300 } else if (iqk_ok) {
2301 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
2302 BMASKDWORD) >> 22) & 0x3FF;
2303 val_x = result[final_candidate][4];
2304 if ((val_x & 0x00000200) != 0)
2305 val_x = val_x | 0xFFFFFC00;
2306 tx1_a = (val_x * oldval_1) >> 8;
2307 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2308 val_x, tx1_a);
2309 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a);
2310 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2311 ((val_x * oldval_1 >> 7) & 0x1));
2312 val_y = result[final_candidate][5];
2313 if ((val_y & 0x00000200) != 0)
2314 val_y = val_y | 0xFFFFFC00;
2315 if (rtlhal->current_bandtype == BAND_ON_5G)
2316 val_y += 3;
2317 tx1_c = (val_y * oldval_1) >> 8;
2318 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2319 val_y, tx1_c);
2320 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000,
2321 ((tx1_c & 0x3C0) >> 6));
2322 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000,
2323 (tx1_c & 0x3F));
2324 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2325 ((val_y * oldval_1 >> 7) & 0x1));
2326 if (txonly)
2327 return;
2328 reg = result[final_candidate][6];
2329 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2330 reg = result[final_candidate][7] & 0x3F;
2331 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2332 reg = (result[final_candidate][7] >> 6) & 0xF;
2333 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2334 }
2335 }
2336
2337 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2338 {
2339 struct rtl_priv *rtlpriv = rtl_priv(hw);
2340 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2341 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2342 long result[4][8];
2343 u8 i, final_candidate, indexforchannel;
2344 bool patha_ok, pathb_ok;
2345 long rege94, rege9c, regea4, regeac, regeb4;
2346 long regebc, regec4, regecc, regtmp = 0;
2347 bool is12simular, is13simular, is23simular;
2348 unsigned long flag = 0;
2349
2350 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2351 "IQK:Start!!!channel %d\n", rtlphy->current_channel);
2352 for (i = 0; i < 8; i++) {
2353 result[0][i] = 0;
2354 result[1][i] = 0;
2355 result[2][i] = 0;
2356 result[3][i] = 0;
2357 }
2358 final_candidate = 0xff;
2359 patha_ok = false;
2360 pathb_ok = false;
2361 is12simular = false;
2362 is23simular = false;
2363 is13simular = false;
2364 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2365 "IQK !!!currentband %d\n", rtlhal->current_bandtype);
2366 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2367 for (i = 0; i < 3; i++) {
2368 if (rtlhal->current_bandtype == BAND_ON_5G) {
2369 _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2370 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2371 if (IS_92D_SINGLEPHY(rtlhal->version))
2372 _rtl92d_phy_iq_calibrate(hw, result, i, true);
2373 else
2374 _rtl92d_phy_iq_calibrate(hw, result, i, false);
2375 }
2376 if (i == 1) {
2377 is12simular = _rtl92d_phy_simularity_compare(hw, result,
2378 0, 1);
2379 if (is12simular) {
2380 final_candidate = 0;
2381 break;
2382 }
2383 }
2384 if (i == 2) {
2385 is13simular = _rtl92d_phy_simularity_compare(hw, result,
2386 0, 2);
2387 if (is13simular) {
2388 final_candidate = 0;
2389 break;
2390 }
2391 is23simular = _rtl92d_phy_simularity_compare(hw, result,
2392 1, 2);
2393 if (is23simular) {
2394 final_candidate = 1;
2395 } else {
2396 for (i = 0; i < 8; i++)
2397 regtmp += result[3][i];
2398
2399 if (regtmp != 0)
2400 final_candidate = 3;
2401 else
2402 final_candidate = 0xFF;
2403 }
2404 }
2405 }
2406 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2407 for (i = 0; i < 4; i++) {
2408 rege94 = result[i][0];
2409 rege9c = result[i][1];
2410 regea4 = result[i][2];
2411 regeac = result[i][3];
2412 regeb4 = result[i][4];
2413 regebc = result[i][5];
2414 regec4 = result[i][6];
2415 regecc = result[i][7];
2416 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2417 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2418 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2419 regecc);
2420 }
2421 if (final_candidate != 0xff) {
2422 rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2423 rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2424 regea4 = result[final_candidate][2];
2425 regeac = result[final_candidate][3];
2426 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2427 rtlphy->reg_ebc = regebc = result[final_candidate][5];
2428 regec4 = result[final_candidate][6];
2429 regecc = result[final_candidate][7];
2430 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2431 "IQK: final_candidate is %x\n", final_candidate);
2432 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2433 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2434 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2435 regecc);
2436 patha_ok = pathb_ok = true;
2437 } else {
2438 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */
2439 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */
2440 }
2441 if ((rege94 != 0) /*&&(regea4 != 0) */)
2442 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2443 final_candidate, (regea4 == 0));
2444 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2445 if ((regeb4 != 0) /*&&(regec4 != 0) */)
2446 _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2447 final_candidate, (regec4 == 0));
2448 }
2449 if (final_candidate != 0xFF) {
2450 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2451 rtlphy->current_channel);
2452
2453 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2454 rtlphy->iqk_matrix[indexforchannel].
2455 value[0][i] = result[final_candidate][i];
2456 rtlphy->iqk_matrix[indexforchannel].iqk_done =
2457 true;
2458
2459 RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2460 "IQK OK indexforchannel %d\n", indexforchannel);
2461 }
2462 }
2463
2464 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2465 {
2466 struct rtl_priv *rtlpriv = rtl_priv(hw);
2467 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2468 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2469 u8 indexforchannel;
2470
2471 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel);
2472 /*------Do IQK for normal chip and test chip 5G band------- */
2473 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2474 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n",
2475 indexforchannel,
2476 rtlphy->iqk_matrix[indexforchannel].iqk_done);
2477 if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done &&
2478 rtlphy->need_iqk) {
2479 /* Re Do IQK. */
2480 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2481 "Do IQK Matrix reg for channel:%d....\n", channel);
2482 rtl92d_phy_iq_calibrate(hw);
2483 } else {
2484 /* Just load the value. */
2485 /* 2G band just load once. */
2486 if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2487 indexforchannel == 0) || indexforchannel > 0) {
2488 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
2489 "Just Read IQK Matrix reg for channel:%d....\n",
2490 channel);
2491 if ((rtlphy->iqk_matrix[indexforchannel].
2492 value[0] != NULL)
2493 /*&&(regea4 != 0) */)
2494 _rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2495 rtlphy->iqk_matrix[
2496 indexforchannel].value, 0,
2497 (rtlphy->iqk_matrix[
2498 indexforchannel].value[0][2] == 0));
2499 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2500 if ((rtlphy->iqk_matrix[
2501 indexforchannel].value[0][4] != 0)
2502 /*&&(regec4 != 0) */)
2503 _rtl92d_phy_pathb_fill_iqk_matrix(hw,
2504 true,
2505 rtlphy->iqk_matrix[
2506 indexforchannel].value, 0,
2507 (rtlphy->iqk_matrix[
2508 indexforchannel].value[0][6]
2509 == 0));
2510 }
2511 }
2512 }
2513 rtlphy->need_iqk = false;
2514 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2515 }
2516
2517 static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2518 {
2519 u32 ret;
2520
2521 if (val1 >= val2)
2522 ret = val1 - val2;
2523 else
2524 ret = val2 - val1;
2525 return ret;
2526 }
2527
2528 static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2529 {
2530
2531 int i;
2532 u8 channel_5g[45] = {
2533 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
2534 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
2535 114, 116, 118, 120, 122, 124, 126, 128, 130, 132,
2536 134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
2537 161, 163, 165
2538 };
2539
2540 for (i = 0; i < sizeof(channel_5g); i++)
2541 if (channel == channel_5g[i])
2542 return true;
2543 return false;
2544 }
2545
2546 static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2547 u32 *targetchnl, u32 * curvecount_val,
2548 bool is5g, u32 *curveindex)
2549 {
2550 struct rtl_priv *rtlpriv = rtl_priv(hw);
2551 u32 smallest_abs_val = 0xffffffff, u4tmp;
2552 u8 i, j;
2553 u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2554
2555 for (i = 0; i < chnl_num; i++) {
2556 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2557 continue;
2558 curveindex[i] = 0;
2559 for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2560 u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2561 curvecount_val[j]);
2562
2563 if (u4tmp < smallest_abs_val) {
2564 curveindex[i] = j;
2565 smallest_abs_val = u4tmp;
2566 }
2567 }
2568 smallest_abs_val = 0xffffffff;
2569 RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n",
2570 i, curveindex[i]);
2571 }
2572 }
2573
2574 static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2575 u8 channel)
2576 {
2577 struct rtl_priv *rtlpriv = rtl_priv(hw);
2578 u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2579 BAND_ON_5G ? RF90_PATH_A :
2580 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2581 RF90_PATH_B : RF90_PATH_A;
2582 u32 u4tmp = 0, u4regvalue = 0;
2583 bool bneed_powerdown_radio = false;
2584
2585 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath);
2586 RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n",
2587 rtlpriv->rtlhal.current_bandtype);
2588 RTPRINT(rtlpriv, FINIT, INIT_IQK, "channel = %d\n", channel);
2589 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2590 u4tmp = curveindex_5g[channel-1];
2591 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2592 "ver 1 set RF-A, 5G, 0x28 = 0x%ulx !!\n", u4tmp);
2593 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2594 rtlpriv->rtlhal.interfaceindex == 1) {
2595 bneed_powerdown_radio =
2596 rtl92d_phy_enable_anotherphy(hw, false);
2597 rtlpriv->rtlhal.during_mac1init_radioa = true;
2598 /* asume no this case */
2599 if (bneed_powerdown_radio)
2600 _rtl92d_phy_enable_rf_env(hw, erfpath,
2601 &u4regvalue);
2602 }
2603 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2604 if (bneed_powerdown_radio)
2605 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2606 if (rtlpriv->rtlhal.during_mac1init_radioa)
2607 rtl92d_phy_powerdown_anotherphy(hw, false);
2608 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2609 u4tmp = curveindex_2g[channel-1];
2610 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2611 "ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n", u4tmp);
2612 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2613 rtlpriv->rtlhal.interfaceindex == 0) {
2614 bneed_powerdown_radio =
2615 rtl92d_phy_enable_anotherphy(hw, true);
2616 rtlpriv->rtlhal.during_mac0init_radiob = true;
2617 if (bneed_powerdown_radio)
2618 _rtl92d_phy_enable_rf_env(hw, erfpath,
2619 &u4regvalue);
2620 }
2621 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2622 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2623 "ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n",
2624 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800));
2625 if (bneed_powerdown_radio)
2626 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2627 if (rtlpriv->rtlhal.during_mac0init_radiob)
2628 rtl92d_phy_powerdown_anotherphy(hw, true);
2629 }
2630 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2631 }
2632
2633 static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2634 {
2635 struct rtl_priv *rtlpriv = rtl_priv(hw);
2636 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2637 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2638 u8 tmpreg, index, rf_mode[2];
2639 u8 path = is2t ? 2 : 1;
2640 u8 i;
2641 u32 u4tmp, offset;
2642 u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2643 u16 timeout = 800, timecount = 0;
2644
2645 /* Check continuous TX and Packet TX */
2646 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2647 /* if Deal with contisuous TX case, disable all continuous TX */
2648 /* if Deal with Packet TX case, block all queues */
2649 if ((tmpreg & 0x70) != 0)
2650 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2651 else
2652 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2653 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2654 for (index = 0; index < path; index++) {
2655 /* 1. Read original RF mode */
2656 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2657 rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2658 /* 2. Set RF mode = standby mode */
2659 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2660 BRFREGOFFSETMASK, 0x010000);
2661 if (rtlpci->init_ready) {
2662 /* switch CV-curve control by LC-calibration */
2663 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2664 BIT(17), 0x0);
2665 /* 4. Set LC calibration begin */
2666 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2667 0x08000, 0x01);
2668 }
2669 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2670 BRFREGOFFSETMASK);
2671 while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2672 mdelay(50);
2673 timecount += 50;
2674 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2675 RF_SYN_G6, BRFREGOFFSETMASK);
2676 }
2677 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2678 "PHY_LCK finish delay for %d ms=2\n", timecount);
2679 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, BRFREGOFFSETMASK);
2680 if (index == 0 && rtlhal->interfaceindex == 0) {
2681 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2682 "path-A / 5G LCK\n");
2683 } else {
2684 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2685 "path-B / 2.4G LCK\n");
2686 }
2687 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2);
2688 /* Set LC calibration off */
2689 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2690 0x08000, 0x0);
2691 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n");
2692 /* save Curve-counting number */
2693 for (i = 0; i < CV_CURVE_CNT; i++) {
2694 u32 readval = 0, readval2 = 0;
2695 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2696 0x7f, i);
2697
2698 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2699 BRFREGOFFSETMASK, 0x0);
2700 readval = rtl_get_rfreg(hw, (enum radio_path)index,
2701 0x4F, BRFREGOFFSETMASK);
2702 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2703 /* reg 0x4f [4:0] */
2704 /* reg 0x50 [19:10] */
2705 readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2706 0x50, 0xffc00);
2707 curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2708 readval2);
2709 }
2710 if (index == 0 && rtlhal->interfaceindex == 0)
2711 _rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2712 curvecount_val,
2713 true, curveindex_5g);
2714 else
2715 _rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2716 curvecount_val,
2717 false, curveindex_2g);
2718 /* switch CV-curve control mode */
2719 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2720 BIT(17), 0x1);
2721 }
2722
2723 /* Restore original situation */
2724 for (index = 0; index < path; index++) {
2725 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2726 rtl_write_byte(rtlpriv, offset, 0x50);
2727 rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2728 }
2729 if ((tmpreg & 0x70) != 0)
2730 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2731 else /*Deal with Packet TX case */
2732 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2733 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2734 _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2735 }
2736
2737 static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2738 {
2739 struct rtl_priv *rtlpriv = rtl_priv(hw);
2740
2741 RTPRINT(rtlpriv, FINIT, INIT_IQK, "cosa PHY_LCK ver=2\n");
2742 _rtl92d_phy_lc_calibrate_sw(hw, is2t);
2743 }
2744
2745 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2746 {
2747 struct rtl_priv *rtlpriv = rtl_priv(hw);
2748 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2749 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2750 u32 timeout = 2000, timecount = 0;
2751
2752 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2753 udelay(50);
2754 timecount += 50;
2755 }
2756
2757 rtlphy->lck_inprogress = true;
2758 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2759 "LCK:Start!!! currentband %x delay %d ms\n",
2760 rtlhal->current_bandtype, timecount);
2761 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2762 _rtl92d_phy_lc_calibrate(hw, true);
2763 } else {
2764 /* For 1T1R */
2765 _rtl92d_phy_lc_calibrate(hw, false);
2766 }
2767 rtlphy->lck_inprogress = false;
2768 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n");
2769 }
2770
2771 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
2772 {
2773 return;
2774 }
2775
2776 static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2777 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2778 u32 para1, u32 para2, u32 msdelay)
2779 {
2780 struct swchnlcmd *pcmd;
2781
2782 if (cmdtable == NULL) {
2783 RT_ASSERT(false, "cmdtable cannot be NULL\n");
2784 return false;
2785 }
2786 if (cmdtableidx >= cmdtablesz)
2787 return false;
2788
2789 pcmd = cmdtable + cmdtableidx;
2790 pcmd->cmdid = cmdid;
2791 pcmd->para1 = para1;
2792 pcmd->para2 = para2;
2793 pcmd->msdelay = msdelay;
2794 return true;
2795 }
2796
2797 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2798 {
2799 struct rtl_priv *rtlpriv = rtl_priv(hw);
2800 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2801 u8 i;
2802
2803 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2804 "settings regs %d default regs %d\n",
2805 (int)(sizeof(rtlphy->iqk_matrix) /
2806 sizeof(struct iqk_matrix_regs)),
2807 IQK_MATRIX_REG_NUM);
2808 /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
2809 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
2810 rtlphy->iqk_matrix[i].value[0][0] = 0x100;
2811 rtlphy->iqk_matrix[i].value[0][2] = 0x100;
2812 rtlphy->iqk_matrix[i].value[0][4] = 0x100;
2813 rtlphy->iqk_matrix[i].value[0][6] = 0x100;
2814 rtlphy->iqk_matrix[i].value[0][1] = 0x0;
2815 rtlphy->iqk_matrix[i].value[0][3] = 0x0;
2816 rtlphy->iqk_matrix[i].value[0][5] = 0x0;
2817 rtlphy->iqk_matrix[i].value[0][7] = 0x0;
2818 rtlphy->iqk_matrix[i].iqk_done = false;
2819 }
2820 }
2821
2822 static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2823 u8 channel, u8 *stage, u8 *step,
2824 u32 *delay)
2825 {
2826 struct rtl_priv *rtlpriv = rtl_priv(hw);
2827 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2828 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2829 u32 precommoncmdcnt;
2830 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2831 u32 postcommoncmdcnt;
2832 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
2833 u32 rfdependcmdcnt;
2834 struct swchnlcmd *currentcmd = NULL;
2835 u8 rfpath;
2836 u8 num_total_rfpath = rtlphy->num_total_rfpath;
2837
2838 precommoncmdcnt = 0;
2839 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2840 MAX_PRECMD_CNT,
2841 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
2842 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2843 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
2844 postcommoncmdcnt = 0;
2845 _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
2846 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
2847 rfdependcmdcnt = 0;
2848 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2849 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
2850 RF_CHNLBW, channel, 0);
2851 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2852 MAX_RFDEPENDCMD_CNT, CMDID_END,
2853 0, 0, 0);
2854
2855 do {
2856 switch (*stage) {
2857 case 0:
2858 currentcmd = &precommoncmd[*step];
2859 break;
2860 case 1:
2861 currentcmd = &rfdependcmd[*step];
2862 break;
2863 case 2:
2864 currentcmd = &postcommoncmd[*step];
2865 break;
2866 }
2867 if (currentcmd->cmdid == CMDID_END) {
2868 if ((*stage) == 2) {
2869 return true;
2870 } else {
2871 (*stage)++;
2872 (*step) = 0;
2873 continue;
2874 }
2875 }
2876 switch (currentcmd->cmdid) {
2877 case CMDID_SET_TXPOWEROWER_LEVEL:
2878 rtl92d_phy_set_txpower_level(hw, channel);
2879 break;
2880 case CMDID_WRITEPORT_ULONG:
2881 rtl_write_dword(rtlpriv, currentcmd->para1,
2882 currentcmd->para2);
2883 break;
2884 case CMDID_WRITEPORT_USHORT:
2885 rtl_write_word(rtlpriv, currentcmd->para1,
2886 (u16)currentcmd->para2);
2887 break;
2888 case CMDID_WRITEPORT_UCHAR:
2889 rtl_write_byte(rtlpriv, currentcmd->para1,
2890 (u8)currentcmd->para2);
2891 break;
2892 case CMDID_RF_WRITEREG:
2893 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
2894 rtlphy->rfreg_chnlval[rfpath] =
2895 ((rtlphy->rfreg_chnlval[rfpath] &
2896 0xffffff00) | currentcmd->para2);
2897 if (rtlpriv->rtlhal.current_bandtype ==
2898 BAND_ON_5G) {
2899 if (currentcmd->para2 > 99)
2900 rtlphy->rfreg_chnlval[rfpath] =
2901 rtlphy->rfreg_chnlval
2902 [rfpath] | (BIT(18));
2903 else
2904 rtlphy->rfreg_chnlval[rfpath] =
2905 rtlphy->rfreg_chnlval
2906 [rfpath] & (~BIT(18));
2907 rtlphy->rfreg_chnlval[rfpath] |=
2908 (BIT(16) | BIT(8));
2909 } else {
2910 rtlphy->rfreg_chnlval[rfpath] &=
2911 ~(BIT(8) | BIT(16) | BIT(18));
2912 }
2913 rtl_set_rfreg(hw, (enum radio_path)rfpath,
2914 currentcmd->para1,
2915 BRFREGOFFSETMASK,
2916 rtlphy->rfreg_chnlval[rfpath]);
2917 _rtl92d_phy_reload_imr_setting(hw, channel,
2918 rfpath);
2919 }
2920 _rtl92d_phy_switch_rf_setting(hw, channel);
2921 /* do IQK when all parameters are ready */
2922 rtl92d_phy_reload_iqk_setting(hw, channel);
2923 break;
2924 default:
2925 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2926 "switch case not processed\n");
2927 break;
2928 }
2929 break;
2930 } while (true);
2931 (*delay) = currentcmd->msdelay;
2932 (*step)++;
2933 return false;
2934 }
2935
2936 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
2937 {
2938 struct rtl_priv *rtlpriv = rtl_priv(hw);
2939 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2940 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2941 u32 delay;
2942 u32 timeout = 1000, timecount = 0;
2943 u8 channel = rtlphy->current_channel;
2944 u32 ret_value;
2945
2946 if (rtlphy->sw_chnl_inprogress)
2947 return 0;
2948 if (rtlphy->set_bwmode_inprogress)
2949 return 0;
2950
2951 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
2952 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
2953 "sw_chnl_inprogress false driver sleep or unload\n");
2954 return 0;
2955 }
2956 while (rtlphy->lck_inprogress && timecount < timeout) {
2957 mdelay(50);
2958 timecount += 50;
2959 }
2960 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
2961 rtlhal->bandset == BAND_ON_BOTH) {
2962 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
2963 BMASKDWORD);
2964 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2965 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
2966 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
2967 rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
2968 }
2969 switch (rtlhal->current_bandtype) {
2970 case BAND_ON_5G:
2971 /* Get first channel error when change between
2972 * 5G and 2.4G band. */
2973 if (channel <= 14)
2974 return 0;
2975 RT_ASSERT((channel > 14), "5G but channel<=14\n");
2976 break;
2977 case BAND_ON_2_4G:
2978 /* Get first channel error when change between
2979 * 5G and 2.4G band. */
2980 if (channel > 14)
2981 return 0;
2982 RT_ASSERT((channel <= 14), "2G but channel>14\n");
2983 break;
2984 default:
2985 RT_ASSERT(false, "Invalid WirelessMode(%#x)!!\n",
2986 rtlpriv->mac80211.mode);
2987 break;
2988 }
2989 rtlphy->sw_chnl_inprogress = true;
2990 if (channel == 0)
2991 channel = 1;
2992 rtlphy->sw_chnl_stage = 0;
2993 rtlphy->sw_chnl_step = 0;
2994 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
2995 "switch to channel%d\n", rtlphy->current_channel);
2996
2997 do {
2998 if (!rtlphy->sw_chnl_inprogress)
2999 break;
3000 if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
3001 rtlphy->current_channel,
3002 &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
3003 if (delay > 0)
3004 mdelay(delay);
3005 else
3006 continue;
3007 } else {
3008 rtlphy->sw_chnl_inprogress = false;
3009 }
3010 break;
3011 } while (true);
3012 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
3013 rtlphy->sw_chnl_inprogress = false;
3014 return 1;
3015 }
3016
3017 static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
3018 {
3019 struct rtl_priv *rtlpriv = rtl_priv(hw);
3020 struct dig_t *de_digtable = &rtlpriv->dm_digtable;
3021 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3022
3023 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3024 "--->Cmd(%#x), set_io_inprogress(%d)\n",
3025 rtlphy->current_io_type, rtlphy->set_io_inprogress);
3026 switch (rtlphy->current_io_type) {
3027 case IO_CMD_RESUME_DM_BY_SCAN:
3028 de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
3029 rtl92d_dm_write_dig(hw);
3030 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
3031 break;
3032 case IO_CMD_PAUSE_DM_BY_SCAN:
3033 rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue;
3034 de_digtable->cur_igvalue = 0x37;
3035 rtl92d_dm_write_dig(hw);
3036 break;
3037 default:
3038 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3039 "switch case not processed\n");
3040 break;
3041 }
3042 rtlphy->set_io_inprogress = false;
3043 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
3044 rtlphy->current_io_type);
3045 }
3046
3047 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
3048 {
3049 struct rtl_priv *rtlpriv = rtl_priv(hw);
3050 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3051 bool postprocessing = false;
3052
3053 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3054 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
3055 iotype, rtlphy->set_io_inprogress);
3056 do {
3057 switch (iotype) {
3058 case IO_CMD_RESUME_DM_BY_SCAN:
3059 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3060 "[IO CMD] Resume DM after scan\n");
3061 postprocessing = true;
3062 break;
3063 case IO_CMD_PAUSE_DM_BY_SCAN:
3064 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3065 "[IO CMD] Pause DM before scan\n");
3066 postprocessing = true;
3067 break;
3068 default:
3069 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3070 "switch case not processed\n");
3071 break;
3072 }
3073 } while (false);
3074 if (postprocessing && !rtlphy->set_io_inprogress) {
3075 rtlphy->set_io_inprogress = true;
3076 rtlphy->current_io_type = iotype;
3077 } else {
3078 return false;
3079 }
3080 rtl92d_phy_set_io(hw);
3081 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
3082 return true;
3083 }
3084
3085 static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
3086 {
3087 struct rtl_priv *rtlpriv = rtl_priv(hw);
3088
3089 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */
3090 /* b. SPS_CTRL 0x11[7:0] = 0x2b */
3091 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3092 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
3093 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
3094 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3095 /* RF_ON_EXCEP(d~g): */
3096 /* d. APSD_CTRL 0x600[7:0] = 0x00 */
3097 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3098 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */
3099 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/
3100 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3101 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3102 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */
3103 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3104 }
3105
3106 static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3107 {
3108 struct rtl_priv *rtlpriv = rtl_priv(hw);
3109 u32 u4btmp;
3110 u8 delay = 5;
3111
3112 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
3113 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3114 /* b. RF path 0 offset 0x00 = 0x00 disable RF */
3115 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
3116 /* c. APSD_CTRL 0x600[7:0] = 0x40 */
3117 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3118 /* d. APSD_CTRL 0x600[7:0] = 0x00
3119 * APSD_CTRL 0x600[7:0] = 0x00
3120 * RF path 0 offset 0x00 = 0x00
3121 * APSD_CTRL 0x600[7:0] = 0x40
3122 * */
3123 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
3124 while (u4btmp != 0 && delay > 0) {
3125 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3126 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
3127 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3128 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
3129 delay--;
3130 }
3131 if (delay == 0) {
3132 /* Jump out the LPS turn off sequence to RF_ON_EXCEP */
3133 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3134
3135 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3136 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3137 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3138 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3139 "Fail !!! Switch RF timeout\n");
3140 return;
3141 }
3142 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
3143 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3144 /* f. SPS_CTRL 0x11[7:0] = 0x22 */
3145 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3146 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3147 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */
3148 }
3149
3150 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3151 enum rf_pwrstate rfpwr_state)
3152 {
3153
3154 bool bresult = true;
3155 struct rtl_priv *rtlpriv = rtl_priv(hw);
3156 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3157 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3158 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3159 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3160 u8 i, queue_id;
3161 struct rtl8192_tx_ring *ring = NULL;
3162
3163 if (rfpwr_state == ppsc->rfpwr_state)
3164 return false;
3165 switch (rfpwr_state) {
3166 case ERFON:
3167 if ((ppsc->rfpwr_state == ERFOFF) &&
3168 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3169 bool rtstatus;
3170 u32 InitializeCount = 0;
3171 do {
3172 InitializeCount++;
3173 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3174 "IPS Set eRf nic enable\n");
3175 rtstatus = rtl_ps_enable_nic(hw);
3176 } while (!rtstatus && (InitializeCount < 10));
3177
3178 RT_CLEAR_PS_LEVEL(ppsc,
3179 RT_RF_OFF_LEVL_HALT_NIC);
3180 } else {
3181 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3182 "awake, sleeped:%d ms state_inap:%x\n",
3183 jiffies_to_msecs(jiffies -
3184 ppsc->last_sleep_jiffies),
3185 rtlpriv->psc.state_inap);
3186 ppsc->last_awake_jiffies = jiffies;
3187 _rtl92d_phy_set_rfon(hw);
3188 }
3189
3190 if (mac->link_state == MAC80211_LINKED)
3191 rtlpriv->cfg->ops->led_control(hw,
3192 LED_CTL_LINK);
3193 else
3194 rtlpriv->cfg->ops->led_control(hw,
3195 LED_CTL_NO_LINK);
3196 break;
3197 case ERFOFF:
3198 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3199 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3200 "IPS Set eRf nic disable\n");
3201 rtl_ps_disable_nic(hw);
3202 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3203 } else {
3204 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3205 rtlpriv->cfg->ops->led_control(hw,
3206 LED_CTL_NO_LINK);
3207 else
3208 rtlpriv->cfg->ops->led_control(hw,
3209 LED_CTL_POWER_OFF);
3210 }
3211 break;
3212 case ERFSLEEP:
3213 if (ppsc->rfpwr_state == ERFOFF)
3214 return false;
3215
3216 for (queue_id = 0, i = 0;
3217 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3218 ring = &pcipriv->dev.tx_ring[queue_id];
3219 if (skb_queue_len(&ring->queue) == 0 ||
3220 queue_id == BEACON_QUEUE) {
3221 queue_id++;
3222 continue;
3223 } else if (rtlpci->pdev->current_state != PCI_D0) {
3224 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3225 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n",
3226 i + 1, queue_id);
3227 break;
3228 } else {
3229 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3230 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3231 i + 1, queue_id,
3232 skb_queue_len(&ring->queue));
3233 udelay(10);
3234 i++;
3235 }
3236
3237 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3238 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3239 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
3240 MAX_DOZE_WAITING_TIMES_9x, queue_id,
3241 skb_queue_len(&ring->queue));
3242 break;
3243 }
3244 }
3245 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3246 "Set rfsleep awaked:%d ms\n",
3247 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
3248 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3249 "sleep awaked:%d ms state_inap:%x\n",
3250 jiffies_to_msecs(jiffies -
3251 ppsc->last_awake_jiffies),
3252 rtlpriv->psc.state_inap);
3253 ppsc->last_sleep_jiffies = jiffies;
3254 _rtl92d_phy_set_rfsleep(hw);
3255 break;
3256 default:
3257 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3258 "switch case not processed\n");
3259 bresult = false;
3260 break;
3261 }
3262 if (bresult)
3263 ppsc->rfpwr_state = rfpwr_state;
3264 return bresult;
3265 }
3266
3267 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3268 {
3269 struct rtl_priv *rtlpriv = rtl_priv(hw);
3270 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3271 u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3272
3273 switch (rtlhal->macphymode) {
3274 case DUALMAC_DUALPHY:
3275 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3276 "MacPhyMode: DUALMAC_DUALPHY\n");
3277 rtl_write_byte(rtlpriv, offset, 0xF3);
3278 break;
3279 case SINGLEMAC_SINGLEPHY:
3280 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3281 "MacPhyMode: SINGLEMAC_SINGLEPHY\n");
3282 rtl_write_byte(rtlpriv, offset, 0xF4);
3283 break;
3284 case DUALMAC_SINGLEPHY:
3285 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3286 "MacPhyMode: DUALMAC_SINGLEPHY\n");
3287 rtl_write_byte(rtlpriv, offset, 0xF1);
3288 break;
3289 }
3290 }
3291
3292 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3293 {
3294 struct rtl_priv *rtlpriv = rtl_priv(hw);
3295 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3296 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3297
3298 switch (rtlhal->macphymode) {
3299 case DUALMAC_SINGLEPHY:
3300 rtlphy->rf_type = RF_2T2R;
3301 rtlhal->version |= RF_TYPE_2T2R;
3302 rtlhal->bandset = BAND_ON_BOTH;
3303 rtlhal->current_bandtype = BAND_ON_2_4G;
3304 break;
3305
3306 case SINGLEMAC_SINGLEPHY:
3307 rtlphy->rf_type = RF_2T2R;
3308 rtlhal->version |= RF_TYPE_2T2R;
3309 rtlhal->bandset = BAND_ON_BOTH;
3310 rtlhal->current_bandtype = BAND_ON_2_4G;
3311 break;
3312
3313 case DUALMAC_DUALPHY:
3314 rtlphy->rf_type = RF_1T1R;
3315 rtlhal->version &= RF_TYPE_1T1R;
3316 /* Now we let MAC0 run on 5G band. */
3317 if (rtlhal->interfaceindex == 0) {
3318 rtlhal->bandset = BAND_ON_5G;
3319 rtlhal->current_bandtype = BAND_ON_5G;
3320 } else {
3321 rtlhal->bandset = BAND_ON_2_4G;
3322 rtlhal->current_bandtype = BAND_ON_2_4G;
3323 }
3324 break;
3325 default:
3326 break;
3327 }
3328 }
3329
3330 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3331 {
3332 u8 group;
3333 u8 channel_info[59] = {
3334 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
3335 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56,
3336 58, 60, 62, 64, 100, 102, 104, 106, 108,
3337 110, 112, 114, 116, 118, 120, 122, 124,
3338 126, 128, 130, 132, 134, 136, 138, 140,
3339 149, 151, 153, 155, 157, 159, 161, 163,
3340 165
3341 };
3342
3343 if (channel_info[chnl] <= 3)
3344 group = 0;
3345 else if (channel_info[chnl] <= 9)
3346 group = 1;
3347 else if (channel_info[chnl] <= 14)
3348 group = 2;
3349 else if (channel_info[chnl] <= 44)
3350 group = 3;
3351 else if (channel_info[chnl] <= 54)
3352 group = 4;
3353 else if (channel_info[chnl] <= 64)
3354 group = 5;
3355 else if (channel_info[chnl] <= 112)
3356 group = 6;
3357 else if (channel_info[chnl] <= 126)
3358 group = 7;
3359 else if (channel_info[chnl] <= 140)
3360 group = 8;
3361 else if (channel_info[chnl] <= 153)
3362 group = 9;
3363 else if (channel_info[chnl] <= 159)
3364 group = 10;
3365 else
3366 group = 11;
3367 return group;
3368 }
3369
3370 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3371 {
3372 struct rtl_priv *rtlpriv = rtl_priv(hw);
3373 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3374 unsigned long flags;
3375 u8 value8;
3376 u16 i;
3377 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3378
3379 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
3380 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3381 value8 = rtl_read_byte(rtlpriv, mac_reg);
3382 value8 |= BIT(1);
3383 rtl_write_byte(rtlpriv, mac_reg, value8);
3384 } else {
3385 value8 = rtl_read_byte(rtlpriv, mac_reg);
3386 value8 &= (~BIT(1));
3387 rtl_write_byte(rtlpriv, mac_reg, value8);
3388 }
3389
3390 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3391 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3392 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3393 } else {
3394 spin_lock_irqsave(&globalmutex_power, flags);
3395 if (rtlhal->interfaceindex == 0) {
3396 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3397 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3398 } else {
3399 value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3400 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3401 }
3402 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3403 spin_unlock_irqrestore(&globalmutex_power, flags);
3404 for (i = 0; i < 200; i++) {
3405 if ((value8 & BIT(7)) == 0) {
3406 break;
3407 } else {
3408 udelay(500);
3409 spin_lock_irqsave(&globalmutex_power, flags);
3410 value8 = rtl_read_byte(rtlpriv,
3411 REG_POWER_OFF_IN_PROCESS);
3412 spin_unlock_irqrestore(&globalmutex_power,
3413 flags);
3414 }
3415 }
3416 if (i == 200)
3417 RT_ASSERT(false, "Another mac power off over time\n");
3418 }
3419 }
3420
3421 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3422 {
3423 struct rtl_priv *rtlpriv = rtl_priv(hw);
3424
3425 switch (rtlpriv->rtlhal.macphymode) {
3426 case DUALMAC_DUALPHY:
3427 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3428 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3429 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3430 break;
3431 case DUALMAC_SINGLEPHY:
3432 rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3433 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3434 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3435 break;
3436 case SINGLEMAC_SINGLEPHY:
3437 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3438 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3439 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3440 break;
3441 default:
3442 break;
3443 }
3444 }
3445
3446 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3447 {
3448 struct rtl_priv *rtlpriv = rtl_priv(hw);
3449 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3450 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3451 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3452 u8 rfpath, i;
3453
3454 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
3455 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
3456 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3457 /* r_select_5G for path_A/B,0x878 */
3458 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3459 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3460 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3461 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3462 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3463 }
3464 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3465 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3466 /* fc_area 0xd2c */
3467 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3468 /* 5G LAN ON */
3469 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3470 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3471 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3472 0x40000100);
3473 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3474 0x40000100);
3475 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3476 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3477 BIT(10) | BIT(6) | BIT(5),
3478 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3479 (rtlefuse->eeprom_c9 & BIT(1)) |
3480 ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3481 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3482 BIT(10) | BIT(6) | BIT(5),
3483 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3484 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3485 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3486 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3487 } else {
3488 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3489 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3490 BIT(6) | BIT(5),
3491 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3492 (rtlefuse->eeprom_c9 & BIT(1)) |
3493 ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3494 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3495 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3496 ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3497 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3498 BIT(10) | BIT(6) | BIT(5),
3499 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3500 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3501 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3502 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3503 BIT(10) | BIT(6) | BIT(5),
3504 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3505 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3506 ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3507 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3508 BIT(31) | BIT(15), 0);
3509 }
3510 /* 1.5V_LDO */
3511 } else {
3512 /* r_select_5G for path_A/B */
3513 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3514 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3515 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3516 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3517 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3518 }
3519 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3520 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3521 /* fc_area */
3522 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3523 /* 5G LAN ON */
3524 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3525 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3526 if (rtlefuse->internal_pa_5g[0])
3527 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3528 0x2d4000b5);
3529 else
3530 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3531 0x20000080);
3532 if (rtlefuse->internal_pa_5g[1])
3533 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3534 0x2d4000b5);
3535 else
3536 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3537 0x20000080);
3538 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3539 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3540 BIT(10) | BIT(6) | BIT(5),
3541 (rtlefuse->eeprom_cc & BIT(5)));
3542 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3543 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3544 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3545 (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3546 } else {
3547 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3548 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3549 BIT(6) | BIT(5),
3550 (rtlefuse->eeprom_cc & BIT(5)) |
3551 ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3552 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3553 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3554 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3555 ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3556 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3557 BIT(31) | BIT(15),
3558 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3559 ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3560 }
3561 }
3562 /* update IQK related settings */
3563 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, BMASKDWORD, 0x40000100);
3564 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, BMASKDWORD, 0x40000100);
3565 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
3566 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3567 BIT(26) | BIT(24), 0x00);
3568 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00);
3569 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3570 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3571
3572 /* Update RF */
3573 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3574 rfpath++) {
3575 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3576 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */
3577 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3578 BIT(18), 0);
3579 /* RF0x0b[16:14] =3b'111 */
3580 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3581 0x1c000, 0x07);
3582 } else {
3583 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */
3584 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3585 BIT(16) | BIT(18),
3586 (BIT(16) | BIT(8)) >> 8);
3587 }
3588 }
3589 /* Update for all band. */
3590 /* DMDP */
3591 if (rtlphy->rf_type == RF_1T1R) {
3592 /* Use antenna 0,0xc04,0xd04 */
3593 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x11);
3594 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3595
3596 /* enable ad/da clock1 for dual-phy reg0x888 */
3597 if (rtlhal->interfaceindex == 0) {
3598 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3599 BIT(13), 0x3);
3600 } else {
3601 rtl92d_phy_enable_anotherphy(hw, false);
3602 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3603 "MAC1 use DBI to update 0x888\n");
3604 /* 0x888 */
3605 rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3606 rtl92de_read_dword_dbi(hw,
3607 RFPGA0_ADDALLOCKEN,
3608 BIT(3)) | BIT(12) | BIT(13),
3609 BIT(3));
3610 rtl92d_phy_powerdown_anotherphy(hw, false);
3611 }
3612 } else {
3613 /* Single PHY */
3614 /* Use antenna 0 & 1,0xc04,0xd04 */
3615 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x33);
3616 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3617 /* disable ad/da clock1,0x888 */
3618 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3619 }
3620 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3621 rfpath++) {
3622 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3623 RF_CHNLBW, BRFREGOFFSETMASK);
3624 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3625 BRFREGOFFSETMASK);
3626 }
3627 for (i = 0; i < 2; i++)
3628 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
3629 rtlphy->rfreg_chnlval[i]);
3630 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n");
3631
3632 }
3633
3634 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3635 {
3636 struct rtl_priv *rtlpriv = rtl_priv(hw);
3637 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3638 u8 u1btmp;
3639 unsigned long flags;
3640
3641 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3642 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3643 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3644 return true;
3645 }
3646 spin_lock_irqsave(&globalmutex_power, flags);
3647 if (rtlhal->interfaceindex == 0) {
3648 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3649 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3650 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3651 u1btmp &= MAC1_ON;
3652 } else {
3653 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3654 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3655 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3656 u1btmp &= MAC0_ON;
3657 }
3658 if (u1btmp) {
3659 spin_unlock_irqrestore(&globalmutex_power, flags);
3660 return false;
3661 }
3662 u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3663 u1btmp |= BIT(7);
3664 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3665 spin_unlock_irqrestore(&globalmutex_power, flags);
3666 return true;
3667 }
Linux with added FPC-III support