drivers/staging/imx-drm/imx-ldb.c

   1 /*
   2  * i.MX drm driver - LVDS display bridge
   3  *
   4  * Copyright (C) 2012 Sascha Hauer, Pengutronix
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  18  * MA 02110-1301, USA.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/clk.h>
  23 #include <linux/component.h>
  24 #include <drm/drmP.h>
  25 #include <drm/drm_fb_helper.h>
  26 #include <drm/drm_crtc_helper.h>
  27 #include <linux/mfd/syscon.h>
  28 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_device.h>
  31 #include <video/of_videomode.h>
  32 #include <linux/regmap.h>
  33 #include <linux/videodev2.h>
  34
  35 #include "imx-drm.h"
  36
  37 #define DRIVER_NAME "imx-ldb"
  38
  39 #define LDB_CH0_MODE_EN_TO_DI0          (1 << 0)
  40 #define LDB_CH0_MODE_EN_TO_DI1          (3 << 0)
  41 #define LDB_CH0_MODE_EN_MASK            (3 << 0)
  42 #define LDB_CH1_MODE_EN_TO_DI0          (1 << 2)
  43 #define LDB_CH1_MODE_EN_TO_DI1          (3 << 2)
  44 #define LDB_CH1_MODE_EN_MASK            (3 << 2)
  45 #define LDB_SPLIT_MODE_EN               (1 << 4)
  46 #define LDB_DATA_WIDTH_CH0_24           (1 << 5)
  47 #define LDB_BIT_MAP_CH0_JEIDA           (1 << 6)
  48 #define LDB_DATA_WIDTH_CH1_24           (1 << 7)
  49 #define LDB_BIT_MAP_CH1_JEIDA           (1 << 8)
  50 #define LDB_DI0_VS_POL_ACT_LOW          (1 << 9)
  51 #define LDB_DI1_VS_POL_ACT_LOW          (1 << 10)
  52 #define LDB_BGREF_RMODE_INT             (1 << 15)
  53
  54 #define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector)
  55 #define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder)
  56
  57 struct imx_ldb;
  58
  59 struct imx_ldb_channel {
  60         struct imx_ldb *ldb;
  61         struct drm_connector connector;
  62         struct drm_encoder encoder;
  63         struct device_node *child;
  64         int chno;
  65         void *edid;
  66         int edid_len;
  67         struct drm_display_mode mode;
  68         int mode_valid;
  69 };
  70
  71 struct bus_mux {
  72         int reg;
  73         int shift;
  74         int mask;
  75 };
  76
  77 struct imx_ldb {
  78         struct regmap *regmap;
  79         struct device *dev;
  80         struct imx_ldb_channel channel[2];
  81         struct clk *clk[2]; /* our own clock */
  82         struct clk *clk_sel[4]; /* parent of display clock */
  83         struct clk *clk_pll[2]; /* upstream clock we can adjust */
  84         u32 ldb_ctrl;
  85         const struct bus_mux *lvds_mux;
  86 };
  87
  88 static enum drm_connector_status imx_ldb_connector_detect(
  89                 struct drm_connector *connector, bool force)
  90 {
  91         return connector_status_connected;
  92 }
  93
  94 static int imx_ldb_connector_get_modes(struct drm_connector *connector)
  95 {
  96         struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
  97         int num_modes = 0;
  98
  99         if (imx_ldb_ch->edid) {
 100                 drm_mode_connector_update_edid_property(connector,
 101                                                         imx_ldb_ch->edid);
 102                 num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
 103         }
 104
 105         if (imx_ldb_ch->mode_valid) {
 106                 struct drm_display_mode *mode;
 107
 108                 mode = drm_mode_create(connector->dev);
 109                 if (!mode)
 110                         return -EINVAL;
 111                 drm_mode_copy(mode, &imx_ldb_ch->mode);
 112                 mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 113                 drm_mode_probed_add(connector, mode);
 114                 num_modes++;
 115         }
 116
 117         return num_modes;
 118 }
 119
 120 static struct drm_encoder *imx_ldb_connector_best_encoder(
 121                 struct drm_connector *connector)
 122 {
 123         struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
 124
 125         return &imx_ldb_ch->encoder;
 126 }
 127
 128 static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode)
 129 {
 130 }
 131
 132 static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder,
 133                            const struct drm_display_mode *mode,
 134                            struct drm_display_mode *adjusted_mode)
 135 {
 136         return true;
 137 }
 138
 139 static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
 140                 unsigned long serial_clk, unsigned long di_clk)
 141 {
 142         int ret;
 143
 144         dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
 145                         clk_get_rate(ldb->clk_pll[chno]), serial_clk);
 146         clk_set_rate(ldb->clk_pll[chno], serial_clk);
 147
 148         dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
 149                         clk_get_rate(ldb->clk_pll[chno]));
 150
 151         dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
 152                         clk_get_rate(ldb->clk[chno]),
 153                         (long int)di_clk);
 154         clk_set_rate(ldb->clk[chno], di_clk);
 155
 156         dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
 157                         clk_get_rate(ldb->clk[chno]));
 158
 159         /* set display clock mux to LDB input clock */
 160         ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
 161         if (ret)
 162                 dev_err(ldb->dev,
 163                         "unable to set di%d parent clock to ldb_di%d\n", mux,
 164                         chno);
 165 }
 166
 167 static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
 168 {
 169         struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
 170         struct imx_ldb *ldb = imx_ldb_ch->ldb;
 171         struct drm_display_mode *mode = &encoder->crtc->mode;
 172         u32 pixel_fmt;
 173         unsigned long serial_clk;
 174         unsigned long di_clk = mode->clock * 1000;
 175         int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
 176
 177         if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
 178                 /* dual channel LVDS mode */
 179                 serial_clk = 3500UL * mode->clock;
 180                 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
 181                 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
 182         } else {
 183                 serial_clk = 7000UL * mode->clock;
 184                 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
 185                                 di_clk);
 186         }
 187
 188         switch (imx_ldb_ch->chno) {
 189         case 0:
 190                 pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH0_24) ?
 191                         V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
 192                 break;
 193         case 1:
 194                 pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH1_24) ?
 195                         V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
 196                 break;
 197         default:
 198                 dev_err(ldb->dev, "unable to config di%d panel format\n",
 199                         imx_ldb_ch->chno);
 200                 pixel_fmt = V4L2_PIX_FMT_RGB24;
 201         }
 202
 203         imx_drm_panel_format(encoder, pixel_fmt);
 204 }
 205
 206 static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
 207 {
 208         struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
 209         struct imx_ldb *ldb = imx_ldb_ch->ldb;
 210         int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
 211         int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
 212
 213         if (dual) {
 214                 clk_prepare_enable(ldb->clk[0]);
 215                 clk_prepare_enable(ldb->clk[1]);
 216         }
 217
 218         if (imx_ldb_ch == &ldb->channel[0] || dual) {
 219                 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
 220                 if (mux == 0 || ldb->lvds_mux)
 221                         ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
 222                 else if (mux == 1)
 223                         ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
 224         }
 225         if (imx_ldb_ch == &ldb->channel[1] || dual) {
 226                 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
 227                 if (mux == 1 || ldb->lvds_mux)
 228                         ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
 229                 else if (mux == 0)
 230                         ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
 231         }
 232
 233         if (ldb->lvds_mux) {
 234                 const struct bus_mux *lvds_mux = NULL;
 235
 236                 if (imx_ldb_ch == &ldb->channel[0])
 237                         lvds_mux = &ldb->lvds_mux[0];
 238                 else if (imx_ldb_ch == &ldb->channel[1])
 239                         lvds_mux = &ldb->lvds_mux[1];
 240
 241                 regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
 242                                    mux << lvds_mux->shift);
 243         }
 244
 245         regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
 246 }
 247
 248 static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
 249                          struct drm_display_mode *mode,
 250                          struct drm_display_mode *adjusted_mode)
 251 {
 252         struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
 253         struct imx_ldb *ldb = imx_ldb_ch->ldb;
 254         int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
 255
 256         if (mode->clock > 170000) {
 257                 dev_warn(ldb->dev,
 258                          "%s: mode exceeds 170 MHz pixel clock\n", __func__);
 259         }
 260         if (mode->clock > 85000 && !dual) {
 261                 dev_warn(ldb->dev,
 262                          "%s: mode exceeds 85 MHz pixel clock\n", __func__);
 263         }
 264
 265         /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
 266         if (imx_ldb_ch == &ldb->channel[0]) {
 267                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 268                         ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
 269                 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 270                         ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
 271         }
 272         if (imx_ldb_ch == &ldb->channel[1]) {
 273                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 274                         ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
 275                 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 276                         ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
 277         }
 278 }
 279
 280 static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
 281 {
 282         struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
 283         struct imx_ldb *ldb = imx_ldb_ch->ldb;
 284
 285         /*
 286          * imx_ldb_encoder_disable is called by
 287          * drm_helper_disable_unused_functions without
 288          * the encoder being enabled before.
 289          */
 290         if (imx_ldb_ch == &ldb->channel[0] &&
 291             (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0)
 292                 return;
 293         else if (imx_ldb_ch == &ldb->channel[1] &&
 294                  (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0)
 295                 return;
 296
 297         if (imx_ldb_ch == &ldb->channel[0])
 298                 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
 299         else if (imx_ldb_ch == &ldb->channel[1])
 300                 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
 301
 302         regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
 303
 304         if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
 305                 clk_disable_unprepare(ldb->clk[0]);
 306                 clk_disable_unprepare(ldb->clk[1]);
 307         }
 308 }
 309
 310 static struct drm_connector_funcs imx_ldb_connector_funcs = {
 311         .dpms = drm_helper_connector_dpms,
 312         .fill_modes = drm_helper_probe_single_connector_modes,
 313         .detect = imx_ldb_connector_detect,
 314         .destroy = imx_drm_connector_destroy,
 315 };
 316
 317 static struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
 318         .get_modes = imx_ldb_connector_get_modes,
 319         .best_encoder = imx_ldb_connector_best_encoder,
 320         .mode_valid = imx_drm_connector_mode_valid,
 321 };
 322
 323 static struct drm_encoder_funcs imx_ldb_encoder_funcs = {
 324         .destroy = imx_drm_encoder_destroy,
 325 };
 326
 327 static struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
 328         .dpms = imx_ldb_encoder_dpms,
 329         .mode_fixup = imx_ldb_encoder_mode_fixup,
 330         .prepare = imx_ldb_encoder_prepare,
 331         .commit = imx_ldb_encoder_commit,
 332         .mode_set = imx_ldb_encoder_mode_set,
 333         .disable = imx_ldb_encoder_disable,
 334 };
 335
 336 static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
 337 {
 338         char clkname[16];
 339
 340         snprintf(clkname, sizeof(clkname), "di%d", chno);
 341         ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
 342         if (IS_ERR(ldb->clk[chno]))
 343                 return PTR_ERR(ldb->clk[chno]);
 344
 345         snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
 346         ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
 347
 348         return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
 349 }
 350
 351 static int imx_ldb_register(struct drm_device *drm,
 352         struct imx_ldb_channel *imx_ldb_ch)
 353 {
 354         struct imx_ldb *ldb = imx_ldb_ch->ldb;
 355         int ret;
 356
 357         ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder,
 358                                        imx_ldb_ch->child);
 359         if (ret)
 360                 return ret;
 361
 362         ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
 363         if (ret)
 364                 return ret;
 365
 366         if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
 367                 ret = imx_ldb_get_clk(ldb, 1);
 368                 if (ret)
 369                         return ret;
 370         }
 371
 372         drm_encoder_helper_add(&imx_ldb_ch->encoder,
 373                         &imx_ldb_encoder_helper_funcs);
 374         drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs,
 375                          DRM_MODE_ENCODER_LVDS);
 376
 377         drm_connector_helper_add(&imx_ldb_ch->connector,
 378                         &imx_ldb_connector_helper_funcs);
 379         drm_connector_init(drm, &imx_ldb_ch->connector,
 380                            &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
 381
 382         drm_mode_connector_attach_encoder(&imx_ldb_ch->connector,
 383                         &imx_ldb_ch->encoder);
 384
 385         return 0;
 386 }
 387
 388 enum {
 389         LVDS_BIT_MAP_SPWG,
 390         LVDS_BIT_MAP_JEIDA
 391 };
 392
 393 static const char * const imx_ldb_bit_mappings[] = {
 394         [LVDS_BIT_MAP_SPWG]  = "spwg",
 395         [LVDS_BIT_MAP_JEIDA] = "jeida",
 396 };
 397
 398 static const int of_get_data_mapping(struct device_node *np)
 399 {
 400         const char *bm;
 401         int ret, i;
 402
 403         ret = of_property_read_string(np, "fsl,data-mapping", &bm);
 404         if (ret < 0)
 405                 return ret;
 406
 407         for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++)
 408                 if (!strcasecmp(bm, imx_ldb_bit_mappings[i]))
 409                         return i;
 410
 411         return -EINVAL;
 412 }
 413
 414 static struct bus_mux imx6q_lvds_mux[2] = {
 415         {
 416                 .reg = IOMUXC_GPR3,
 417                 .shift = 6,
 418                 .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
 419         }, {
 420                 .reg = IOMUXC_GPR3,
 421                 .shift = 8,
 422                 .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
 423         }
 424 };
 425
 426 /*
 427  * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
 428  * of_match_device will walk through this list and take the first entry
 429  * matching any of its compatible values. Therefore, the more generic
 430  * entries (in this case fsl,imx53-ldb) need to be ordered last.
 431  */
 432 static const struct of_device_id imx_ldb_dt_ids[] = {
 433         { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
 434         { .compatible = "fsl,imx53-ldb", .data = NULL, },
 435         { }
 436 };
 437 MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
 438
 439 static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
 440 {
 441         struct drm_device *drm = data;
 442         struct device_node *np = dev->of_node;
 443         const struct of_device_id *of_id =
 444                         of_match_device(imx_ldb_dt_ids, dev);
 445         struct device_node *child;
 446         const u8 *edidp;
 447         struct imx_ldb *imx_ldb;
 448         int datawidth;
 449         int mapping;
 450         int dual;
 451         int ret;
 452         int i;
 453
 454         imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
 455         if (!imx_ldb)
 456                 return -ENOMEM;
 457
 458         imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
 459         if (IS_ERR(imx_ldb->regmap)) {
 460                 dev_err(dev, "failed to get parent regmap\n");
 461                 return PTR_ERR(imx_ldb->regmap);
 462         }
 463
 464         imx_ldb->dev = dev;
 465
 466         if (of_id)
 467                 imx_ldb->lvds_mux = of_id->data;
 468
 469         dual = of_property_read_bool(np, "fsl,dual-channel");
 470         if (dual)
 471                 imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
 472
 473         /*
 474          * There are three different possible clock mux configurations:
 475          * i.MX53:  ipu1_di0_sel, ipu1_di1_sel
 476          * i.MX6q:  ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
 477          * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
 478          * Map them all to di0_sel...di3_sel.
 479          */
 480         for (i = 0; i < 4; i++) {
 481                 char clkname[16];
 482
 483                 sprintf(clkname, "di%d_sel", i);
 484                 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
 485                 if (IS_ERR(imx_ldb->clk_sel[i])) {
 486                         ret = PTR_ERR(imx_ldb->clk_sel[i]);
 487                         imx_ldb->clk_sel[i] = NULL;
 488                         break;
 489                 }
 490         }
 491         if (i == 0)
 492                 return ret;
 493
 494         for_each_child_of_node(np, child) {
 495                 struct imx_ldb_channel *channel;
 496
 497                 ret = of_property_read_u32(child, "reg", &i);
 498                 if (ret || i < 0 || i > 1)
 499                         return -EINVAL;
 500
 501                 if (dual && i > 0) {
 502                         dev_warn(dev, "dual-channel mode, ignoring second output\n");
 503                         continue;
 504                 }
 505
 506                 if (!of_device_is_available(child))
 507                         continue;
 508
 509                 channel = &imx_ldb->channel[i];
 510                 channel->ldb = imx_ldb;
 511                 channel->chno = i;
 512                 channel->child = child;
 513
 514                 edidp = of_get_property(child, "edid", &channel->edid_len);
 515                 if (edidp) {
 516                         channel->edid = kmemdup(edidp, channel->edid_len,
 517                                                 GFP_KERNEL);
 518                 } else {
 519                         ret = of_get_drm_display_mode(child, &channel->mode, 0);
 520                         if (!ret)
 521                                 channel->mode_valid = 1;
 522                 }
 523
 524                 ret = of_property_read_u32(child, "fsl,data-width", &datawidth);
 525                 if (ret)
 526                         datawidth = 0;
 527                 else if (datawidth != 18 && datawidth != 24)
 528                         return -EINVAL;
 529
 530                 mapping = of_get_data_mapping(child);
 531                 switch (mapping) {
 532                 case LVDS_BIT_MAP_SPWG:
 533                         if (datawidth == 24) {
 534                                 if (i == 0 || dual)
 535                                         imx_ldb->ldb_ctrl |=
 536                                                 LDB_DATA_WIDTH_CH0_24;
 537                                 if (i == 1 || dual)
 538                                         imx_ldb->ldb_ctrl |=
 539                                                 LDB_DATA_WIDTH_CH1_24;
 540                         }
 541                         break;
 542                 case LVDS_BIT_MAP_JEIDA:
 543                         if (datawidth == 18) {
 544                                 dev_err(dev, "JEIDA standard only supported in 24 bit\n");
 545                                 return -EINVAL;
 546                         }
 547                         if (i == 0 || dual)
 548                                 imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
 549                                         LDB_BIT_MAP_CH0_JEIDA;
 550                         if (i == 1 || dual)
 551                                 imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
 552                                         LDB_BIT_MAP_CH1_JEIDA;
 553                         break;
 554                 default:
 555                         dev_err(dev, "data mapping not specified or invalid\n");
 556                         return -EINVAL;
 557                 }
 558
 559                 ret = imx_ldb_register(drm, channel);
 560                 if (ret)
 561                         return ret;
 562         }
 563
 564         dev_set_drvdata(dev, imx_ldb);
 565
 566         return 0;
 567 }
 568
 569 static void imx_ldb_unbind(struct device *dev, struct device *master,
 570         void *data)
 571 {
 572         struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
 573         int i;
 574
 575         for (i = 0; i < 2; i++) {
 576                 struct imx_ldb_channel *channel = &imx_ldb->channel[i];
 577
 578                 channel->connector.funcs->destroy(&channel->connector);
 579                 channel->encoder.funcs->destroy(&channel->encoder);
 580         }
 581 }
 582
 583 static const struct component_ops imx_ldb_ops = {
 584         .bind   = imx_ldb_bind,
 585         .unbind = imx_ldb_unbind,
 586 };
 587
 588 static int imx_ldb_probe(struct platform_device *pdev)
 589 {
 590         return component_add(&pdev->dev, &imx_ldb_ops);
 591 }
 592
 593 static int imx_ldb_remove(struct platform_device *pdev)
 594 {
 595         component_del(&pdev->dev, &imx_ldb_ops);
 596         return 0;
 597 }
 598
 599 static struct platform_driver imx_ldb_driver = {
 600         .probe          = imx_ldb_probe,
 601         .remove         = imx_ldb_remove,
 602         .driver         = {
 603                 .of_match_table = imx_ldb_dt_ids,
 604                 .name   = DRIVER_NAME,
 605                 .owner  = THIS_MODULE,
 606         },
 607 };
 608
 609 module_platform_driver(imx_ldb_driver);
 610
 611 MODULE_DESCRIPTION("i.MX LVDS driver");
 612 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
 613 MODULE_LICENSE("GPL");
 614 MODULE_ALIAS("platform:" DRIVER_NAME);