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Staging: unisys: Remove RETINT macro
[linux/fpc-iii.git] / drivers / staging / rtl8821ae / wifi.h
blob17a9d9f8781d53b95688cff21a654e95183d91e1
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
32
33 #include <linux/interrupt.h>
34 #include <linux/sched.h>
35 #include <linux/firmware.h>
36 #include <linux/version.h>
37 #include <linux/etherdevice.h>
38 #include <net/mac80211.h>
39 #include "debug.h"
40
41
42 #define RF_CHANGE_BY_INIT 0
43 #define RF_CHANGE_BY_IPS BIT(28)
44 #define RF_CHANGE_BY_PS BIT(29)
45 #define RF_CHANGE_BY_HW BIT(30)
46 #define RF_CHANGE_BY_SW BIT(31)
47
48 #define IQK_ADDA_REG_NUM 16
49 #define IQK_MAC_REG_NUM 4
50 #define IQK_THRESHOLD 8
51
52 #define MAX_KEY_LEN 61
53 #define KEY_BUF_SIZE 5
54
55 /* QoS related. */
56 /*aci: 0x00 Best Effort*/
57 /*aci: 0x01 Background*/
58 /*aci: 0x10 Video*/
59 /*aci: 0x11 Voice*/
60 /*Max: define total number.*/
61 #define AC0_BE 0
62 #define AC1_BK 1
63 #define AC2_VI 2
64 #define AC3_VO 3
65 #define AC_MAX 4
66 #define QOS_QUEUE_NUM 4
67 #define RTL_MAC80211_NUM_QUEUE 5
68
69 #define QBSS_LOAD_SIZE 5
70 #define MAX_WMMELE_LENGTH 64
71
72 #define TOTAL_CAM_ENTRY 32
73
74 /*slot time for 11g. */
75 #define RTL_SLOT_TIME_9 9
76 #define RTL_SLOT_TIME_20 20
77
78 /*related with tcp/ip. */
79 /*if_ether.h*/
80 #define ETH_P_PAE 0x888E /*Port Access Entity
81 *(IEEE 802.1X) */
82 #define ETH_P_IP 0x0800 /*Internet Protocol packet */
83 #define ETH_P_ARP 0x0806 /*Address Resolution packet */
84 #define SNAP_SIZE 6
85 #define PROTOC_TYPE_SIZE 2
86
87 /*related with 802.11 frame*/
88 #define MAC80211_3ADDR_LEN 24
89 #define MAC80211_4ADDR_LEN 30
90
91 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max
92 * channel number */
93 #define CHANNEL_MAX_NUMBER_2G 14
94 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
95 *"phy_GetChnlGroup8812A" and
96 * "Hal_ReadTxPowerInfo8812A"*/
97 #define CHANNEL_MAX_NUMBER_5G_80M 7
98 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, ch4~9, ch10~14
99 * total three groups */
100 #define MAX_PG_GROUP 13
101 #define CHANNEL_GROUP_MAX_2G 3
102 #define CHANNEL_GROUP_IDX_5GL 3
103 #define CHANNEL_GROUP_IDX_5GM 6
104 #define CHANNEL_GROUP_IDX_5GH 9
105 #define CHANNEL_GROUP_MAX_5G 9
106 #define CHANNEL_MAX_NUMBER_2G 14
107 #define AVG_THERMAL_NUM 8
108 #define AVG_THERMAL_NUM_92E 4
109 #define AVG_THERMAL_NUM_88E 4
110 #define AVG_THERMAL_NUM_8723BE 4
111 #define MAX_TID_COUNT 9
112 #define MAX_NUM_RATES 264
113
114 /*for 88E use*/
115 /*It must always set to 4, otherwise read efuse table sequence will be wrong.*/
116 #define MAX_TX_COUNT 4
117 #define MAX_RF_PATH 4
118 #define MAX_CHNL_GROUP_24G 6
119 #define MAX_CHNL_GROUP_5G 14
120
121 /* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
122 #define MAX_TX_QUEUE 9
123
124 #define TX_PWR_BY_RATE_NUM_BAND 2
125 #define TX_PWR_BY_RATE_NUM_RF 4
126 #define TX_PWR_BY_RATE_NUM_SECTION 12
127 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
128 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
129
130 #define DELTA_SWINGIDX_SIZE 30
131 #define BAND_NUM 3
132 /*Now, it's just for 8192ee
133 *not OK yet, keep it 0*/
134 #define DMA_IS_64BIT 0
135 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
136
137 struct txpower_info_2g {
138 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
139 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
140 /*If only one tx, only BW20 and OFDM are used.*/
141 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
142 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
143 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
144 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
145 };
146
147 struct txpower_info_5g {
148 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
149 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
150 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
151 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
152 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
153 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
154 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
155 };
156
157
158 /* for early mode */
159 #define EM_HDR_LEN 8
160 #define FCS_LEN 4
161
162 #define MAX_VIRTUAL_MAC 1
163
164 enum rf_tx_num {
165 RF_1TX = 0,
166 RF_2TX,
167 RF_MAX_TX_NUM,
168 RF_TX_NUM_NONIMPLEMENT,
169 };
170
171 enum rate_section {
172 CCK = 0,
173 OFDM,
174 HT_MCS0_MCS7,
175 HT_MCS8_MCS15,
176 VHT_1SSMCS0_1SSMCS9,
177 VHT_2SSMCS0_2SSMCS9,
178 };
179
180 enum intf_type {
181 INTF_PCI = 0,
182 INTF_USB = 1,
183 };
184
185 enum radio_path {
186 RF90_PATH_A = 0,
187 RF90_PATH_B = 1,
188 RF90_PATH_C = 2,
189 RF90_PATH_D = 3,
190 };
191
192 enum rt_eeprom_type {
193 EEPROM_93C46,
194 EEPROM_93C56,
195 EEPROM_BOOT_EFUSE,
196 };
197
198 enum rtl_status {
199 RTL_STATUS_INTERFACE_START = 0,
200 };
201
202 enum hardware_type {
203 HARDWARE_TYPE_RTL8192E,
204 HARDWARE_TYPE_RTL8192U,
205 HARDWARE_TYPE_RTL8192SE,
206 HARDWARE_TYPE_RTL8192SU,
207 HARDWARE_TYPE_RTL8192CE,
208 HARDWARE_TYPE_RTL8192CU,
209 HARDWARE_TYPE_RTL8192DE,
210 HARDWARE_TYPE_RTL8192DU,
211 HARDWARE_TYPE_RTL8723AE,
212 HARDWARE_TYPE_RTL8188EE,
213 HARDWARE_TYPE_RTL8723BE,
214 HARDWARE_TYPE_RTL8192EE,
215 HARDWARE_TYPE_RTL8821AE,
216 HARDWARE_TYPE_RTL8812AE,
217 /* keep it last */
218 HARDWARE_TYPE_NUM
219 };
220
221 enum scan_operation_backup_opt {
222 SCAN_OPT_BACKUP_BAND0 = 0,
223 SCAN_OPT_BACKUP_BAND1,
224 SCAN_OPT_RESTORE,
225 SCAN_OPT_MAX
226 };
227
228 /*RF state.*/
229 enum rf_pwrstate {
230 ERFON,
231 ERFSLEEP,
232 ERFOFF
233 };
234
235 struct bb_reg_def {
236 u32 rfintfs;
237 u32 rfintfi;
238 u32 rfintfo;
239 u32 rfintfe;
240 u32 rf3wire_offset;
241 u32 rflssi_select;
242 u32 rftxgain_stage;
243 u32 rfhssi_para1;
244 u32 rfhssi_para2;
245 u32 rfswitch_control;
246 u32 rfagc_control1;
247 u32 rfagc_control2;
248 u32 rfrxiq_imbalance;
249 u32 rfrx_afe;
250 u32 rftxiq_imbalance;
251 u32 rftx_afe;
252 u32 rflssi_readback;
253 u32 rflssi_readbackpi;
254 };
255
256 enum io_type {
257 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
258 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
259 IO_CMD_RESUME_DM_BY_SCAN = 2,
260 };
261
262 enum hw_variables {
263 HW_VAR_ETHER_ADDR,
264 HW_VAR_MULTICAST_REG,
265 HW_VAR_BASIC_RATE,
266 HW_VAR_BSSID,
267 HW_VAR_MEDIA_STATUS,
268 HW_VAR_SECURITY_CONF,
269 HW_VAR_BEACON_INTERVAL,
270 HW_VAR_ATIM_WINDOW,
271 HW_VAR_LISTEN_INTERVAL,
272 HW_VAR_CS_COUNTER,
273 HW_VAR_DEFAULTKEY0,
274 HW_VAR_DEFAULTKEY1,
275 HW_VAR_DEFAULTKEY2,
276 HW_VAR_DEFAULTKEY3,
277 HW_VAR_SIFS,
278 HW_VAR_DIFS,
279 HW_VAR_EIFS,
280 HW_VAR_SLOT_TIME,
281 HW_VAR_ACK_PREAMBLE,
282 HW_VAR_CW_CONFIG,
283 HW_VAR_CW_VALUES,
284 HW_VAR_RATE_FALLBACK_CONTROL,
285 HW_VAR_CONTENTION_WINDOW,
286 HW_VAR_RETRY_COUNT,
287 HW_VAR_TR_SWITCH,
288 HW_VAR_COMMAND,
289 HW_VAR_WPA_CONFIG,
290 HW_VAR_AMPDU_MIN_SPACE,
291 HW_VAR_SHORTGI_DENSITY,
292 HW_VAR_AMPDU_FACTOR,
293 HW_VAR_MCS_RATE_AVAILABLE,
294 HW_VAR_AC_PARAM,
295 HW_VAR_ACM_CTRL,
296 HW_VAR_DIS_Req_Qsize,
297 HW_VAR_CCX_CHNL_LOAD,
298 HW_VAR_CCX_NOISE_HISTOGRAM,
299 HW_VAR_CCX_CLM_NHM,
300 HW_VAR_TxOPLimit,
301 HW_VAR_TURBO_MODE,
302 HW_VAR_RF_STATE,
303 HW_VAR_RF_OFF_BY_HW,
304 HW_VAR_BUS_SPEED,
305 HW_VAR_SET_DEV_POWER,
306
307 HW_VAR_RCR,
308 HW_VAR_RATR_0,
309 HW_VAR_RRSR,
310 HW_VAR_CPU_RST,
311 HW_VAR_CECHK_BSSID,
312 HW_VAR_LBK_MODE,
313 HW_VAR_AES_11N_FIX,
314 HW_VAR_USB_RX_AGGR,
315 HW_VAR_USER_CONTROL_TURBO_MODE,
316 HW_VAR_RETRY_LIMIT,
317 HW_VAR_INIT_TX_RATE,
318 HW_VAR_TX_RATE_REG,
319 HW_VAR_EFUSE_USAGE,
320 HW_VAR_EFUSE_BYTES,
321 HW_VAR_AUTOLOAD_STATUS,
322 HW_VAR_RF_2R_DISABLE,
323 HW_VAR_SET_RPWM,
324 HW_VAR_H2C_FW_PWRMODE,
325 HW_VAR_H2C_FW_JOINBSSRPT,
326 HW_VAR_H2C_FW_MEDIASTATUSRPT,
327 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
328 HW_VAR_FW_PSMODE_STATUS,
329 HW_VAR_RESUME_CLK_ON,
330 HW_VAR_FW_LPS_ACTION,
331 HW_VAR_1X1_RECV_COMBINE,
332 HW_VAR_STOP_SEND_BEACON,
333 HW_VAR_TSF_TIMER,
334 HW_VAR_IO_CMD,
335
336 HW_VAR_RF_RECOVERY,
337 HW_VAR_H2C_FW_UPDATE_GTK,
338 HW_VAR_WF_MASK,
339 HW_VAR_WF_CRC,
340 HW_VAR_WF_IS_MAC_ADDR,
341 HW_VAR_H2C_FW_OFFLOAD,
342 HW_VAR_RESET_WFCRC,
343
344 HW_VAR_HANDLE_FW_C2H,
345 HW_VAR_DL_FW_RSVD_PAGE,
346 HW_VAR_AID,
347 HW_VAR_HW_SEQ_ENABLE,
348 HW_VAR_CORRECT_TSF,
349 HW_VAR_BCN_VALID,
350 HW_VAR_FWLPS_RF_ON,
351 HW_VAR_DUAL_TSF_RST,
352 HW_VAR_SWITCH_EPHY_WoWLAN,
353 HW_VAR_INT_MIGRATION,
354 HW_VAR_INT_AC,
355 HW_VAR_RF_TIMING,
356
357 HAL_DEF_WOWLAN,
358 HW_VAR_MRC,
359 HW_VAR_KEEP_ALIVE,
360 HW_VAR_NAV_UPPER,
361 };
362
363 enum rt_media_status {
364 RT_MEDIA_DISCONNECT = 0,
365 RT_MEDIA_CONNECT = 1
366 };
367
368 enum rt_oem_id {
369 RT_CID_DEFAULT = 0,
370 RT_CID_8187_ALPHA0 = 1,
371 RT_CID_8187_SERCOMM_PS = 2,
372 RT_CID_8187_HW_LED = 3,
373 RT_CID_8187_NETGEAR = 4,
374 RT_CID_WHQL = 5,
375 RT_CID_819x_CAMEO = 6,
376 RT_CID_819x_RUNTOP = 7,
377 RT_CID_819x_Senao = 8,
378 RT_CID_TOSHIBA = 9,
379 RT_CID_819x_Netcore = 10,
380 RT_CID_Nettronix = 11,
381 RT_CID_DLINK = 12,
382 RT_CID_PRONET = 13,
383 RT_CID_COREGA = 14,
384 RT_CID_819x_ALPHA = 15,
385 RT_CID_819x_Sitecom = 16,
386 RT_CID_CCX = 17,
387 RT_CID_819x_Lenovo = 18,
388 RT_CID_819x_QMI = 19,
389 RT_CID_819x_Edimax_Belkin = 20,
390 RT_CID_819x_Sercomm_Belkin = 21,
391 RT_CID_819x_CAMEO1 = 22,
392 RT_CID_819x_MSI = 23,
393 RT_CID_819x_Acer = 24,
394 RT_CID_819x_HP = 27,
395 RT_CID_819x_CLEVO = 28,
396 RT_CID_819x_Arcadyan_Belkin = 29,
397 RT_CID_819x_SAMSUNG = 30,
398 RT_CID_819x_WNC_COREGA = 31,
399 RT_CID_819x_Foxcoon = 32,
400 RT_CID_819x_DELL = 33,
401 RT_CID_819x_PRONETS = 34,
402 RT_CID_819x_Edimax_ASUS = 35,
403 RT_CID_NETGEAR = 36,
404 RT_CID_PLANEX = 37,
405 RT_CID_CC_C = 38,
406 };
407
408 enum hw_descs {
409 HW_DESC_OWN,
410 HW_DESC_RXOWN,
411 HW_DESC_TX_NEXTDESC_ADDR,
412 HW_DESC_TXBUFF_ADDR,
413 HW_DESC_RXBUFF_ADDR,
414 HW_DESC_RXPKT_LEN,
415 HW_DESC_RXERO,
416 HW_DESC_RX_PREPARE,
417 };
418
419 enum prime_sc {
420 PRIME_CHNL_OFFSET_DONT_CARE = 0,
421 PRIME_CHNL_OFFSET_LOWER = 1,
422 PRIME_CHNL_OFFSET_UPPER = 2,
423 };
424
425 enum rf_type {
426 RF_1T1R = 0,
427 RF_1T2R = 1,
428 RF_2T2R = 2,
429 RF_2T2R_GREEN = 3,
430 };
431
432 enum ht_channel_width {
433 HT_CHANNEL_WIDTH_20 = 0,
434 HT_CHANNEL_WIDTH_20_40 = 1,
435 HT_CHANNEL_WIDTH_80 = 2,
436 };
437
438 /* Ref: 802.11i spec D10.0 7.3.2.25.1
439 Cipher Suites Encryption Algorithms */
440 enum rt_enc_alg {
441 NO_ENCRYPTION = 0,
442 WEP40_ENCRYPTION = 1,
443 TKIP_ENCRYPTION = 2,
444 RSERVED_ENCRYPTION = 3,
445 AESCCMP_ENCRYPTION = 4,
446 WEP104_ENCRYPTION = 5,
447 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
448 };
449
450 enum rtl_hal_state {
451 _HAL_STATE_STOP = 0,
452 _HAL_STATE_START = 1,
453 };
454
455 enum rtl_var_map {
456 /*reg map */
457 SYS_ISO_CTRL = 0,
458 SYS_FUNC_EN,
459 SYS_CLK,
460 MAC_RCR_AM,
461 MAC_RCR_AB,
462 MAC_RCR_ACRC32,
463 MAC_RCR_ACF,
464 MAC_RCR_AAP,
465 MAC_HIMR,
466 MAC_HIMRE,
467 MAC_HSISR,
468
469 /*efuse map */
470 EFUSE_TEST,
471 EFUSE_CTRL,
472 EFUSE_CLK,
473 EFUSE_CLK_CTRL,
474 EFUSE_PWC_EV12V,
475 EFUSE_FEN_ELDR,
476 EFUSE_LOADER_CLK_EN,
477 EFUSE_ANA8M,
478 EFUSE_HWSET_MAX_SIZE,
479 EFUSE_MAX_SECTION_MAP,
480 EFUSE_REAL_CONTENT_SIZE,
481 EFUSE_OOB_PROTECT_BYTES_LEN,
482 EFUSE_ACCESS,
483 /*CAM map */
484 RWCAM,
485 WCAMI,
486 RCAMO,
487 CAMDBG,
488 SECR,
489 SEC_CAM_NONE,
490 SEC_CAM_WEP40,
491 SEC_CAM_TKIP,
492 SEC_CAM_AES,
493 SEC_CAM_WEP104,
494
495 /*IMR map */
496 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
497 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
498 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
499 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
500 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
501 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
502 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrupt 8 */
503 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrupt 7 */
504 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrupt 6 */
505 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrupt 5 */
506 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrupt 4 */
507 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrupt 3 */
508 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrupt 2 */
509 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrupt 1 */
510 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
511 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
512 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
513 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
514 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
515 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
516 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
517 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
518 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrupt */
519 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
520 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
521 RTL_IMR_TBDOK, /*Transmit Beacon OK interrupt */
522 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
523 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
524 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
525 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
526 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
527 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
528 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
529 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
530 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
531 * RTL_IMR_TBDER) */
532 RTL_IMR_C2HCMD, /*fw interrupt*/
533
534 /*CCK Rates, TxHT = 0 */
535 RTL_RC_CCK_RATE1M,
536 RTL_RC_CCK_RATE2M,
537 RTL_RC_CCK_RATE5_5M,
538 RTL_RC_CCK_RATE11M,
539
540 /*OFDM Rates, TxHT = 0 */
541 RTL_RC_OFDM_RATE6M,
542 RTL_RC_OFDM_RATE9M,
543 RTL_RC_OFDM_RATE12M,
544 RTL_RC_OFDM_RATE18M,
545 RTL_RC_OFDM_RATE24M,
546 RTL_RC_OFDM_RATE36M,
547 RTL_RC_OFDM_RATE48M,
548 RTL_RC_OFDM_RATE54M,
549
550 RTL_RC_HT_RATEMCS7,
551 RTL_RC_HT_RATEMCS15,
552
553 /*keep it last */
554 RTL_VAR_MAP_MAX,
555 };
556
557 /*Firmware PS mode for control LPS.*/
558 enum _fw_ps_mode {
559 FW_PS_ACTIVE_MODE = 0,
560 FW_PS_MIN_MODE = 1,
561 FW_PS_MAX_MODE = 2,
562 FW_PS_DTIM_MODE = 3,
563 FW_PS_VOIP_MODE = 4,
564 FW_PS_UAPSD_WMM_MODE = 5,
565 FW_PS_UAPSD_MODE = 6,
566 FW_PS_IBSS_MODE = 7,
567 FW_PS_WWLAN_MODE = 8,
568 FW_PS_PM_Radio_Off = 9,
569 FW_PS_PM_Card_Disable = 10,
570 };
571
572 enum rt_psmode {
573 EACTIVE, /*Active/Continuous access. */
574 EMAXPS, /*Max power save mode. */
575 EFASTPS, /*Fast power save mode. */
576 EAUTOPS, /*Auto power save mode. */
577 };
578
579 /*LED related.*/
580 enum led_ctl_mode {
581 LED_CTL_POWER_ON = 1,
582 LED_CTL_LINK = 2,
583 LED_CTL_NO_LINK = 3,
584 LED_CTL_TX = 4,
585 LED_CTL_RX = 5,
586 LED_CTL_SITE_SURVEY = 6,
587 LED_CTL_POWER_OFF = 7,
588 LED_CTL_START_TO_LINK = 8,
589 LED_CTL_START_WPS = 9,
590 LED_CTL_STOP_WPS = 10,
591 };
592
593 enum rtl_led_pin {
594 LED_PIN_GPIO0,
595 LED_PIN_LED0,
596 LED_PIN_LED1,
597 LED_PIN_LED2
598 };
599
600 /*QoS related.*/
601 /*acm implementation method.*/
602 enum acm_method {
603 eAcmWay0_SwAndHw = 0,
604 eAcmWay1_HW = 1,
605 eAcmWay2_SW = 2,
606 };
607
608 enum macphy_mode {
609 SINGLEMAC_SINGLEPHY = 0,
610 DUALMAC_DUALPHY,
611 DUALMAC_SINGLEPHY,
612 };
613
614 enum band_type {
615 BAND_ON_2_4G = 0,
616 BAND_ON_5G,
617 BAND_ON_BOTH,
618 BANDMAX
619 };
620
621 /*aci/aifsn Field.
622 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
623 union aci_aifsn {
624 u8 char_data;
625
626 struct {
627 u8 aifsn:4;
628 u8 acm:1;
629 u8 aci:2;
630 u8 reserved:1;
631 } f; /* Field */
632 };
633
634 /*mlme related.*/
635 enum wireless_mode {
636 WIRELESS_MODE_UNKNOWN = 0x00,
637 WIRELESS_MODE_A = 0x01,
638 WIRELESS_MODE_B = 0x02,
639 WIRELESS_MODE_G = 0x04,
640 WIRELESS_MODE_AUTO = 0x08,
641 WIRELESS_MODE_N_24G = 0x10,
642 WIRELESS_MODE_N_5G = 0x20,
643 WIRELESS_MODE_AC_5G = 0x40,
644 WIRELESS_MODE_AC_24G = 0x80
645 };
646
647 enum ratr_table_mode {
648 RATR_INX_WIRELESS_NGB = 0, /* BGN 40 Mhz 2SS 1SS */
649 RATR_INX_WIRELESS_NG = 1, /* GN or N */
650 RATR_INX_WIRELESS_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */
651 RATR_INX_WIRELESS_N = 3,
652 RATR_INX_WIRELESS_GB = 4,
653 RATR_INX_WIRELESS_G = 5,
654 RATR_INX_WIRELESS_B = 6,
655 RATR_INX_WIRELESS_MC = 7,
656 RATR_INX_WIRELESS_AC_5N = 8,
657 RATR_INX_WIRELESS_AC_24N = 9,
658 };
659
660 enum rtl_link_state {
661 MAC80211_NOLINK = 0,
662 MAC80211_LINKING = 1,
663 MAC80211_LINKED = 2,
664 MAC80211_LINKED_SCANNING = 3,
665 };
666
667 enum act_category {
668 ACT_CAT_QOS = 1,
669 ACT_CAT_DLS = 2,
670 ACT_CAT_BA = 3,
671 ACT_CAT_HT = 7,
672 ACT_CAT_WMM = 17,
673 };
674
675 enum ba_action {
676 ACT_ADDBAREQ = 0,
677 ACT_ADDBARSP = 1,
678 ACT_DELBA = 2,
679 };
680
681 enum rt_polarity_ctl {
682 RT_POLARITY_LOW_ACT = 0,
683 RT_POLARITY_HIGH_ACT = 1,
684 };
685
686
687 struct octet_string {
688 u8 *octet;
689 u16 length;
690 };
691
692 struct rtl_hdr_3addr {
693 __le16 frame_ctl;
694 __le16 duration_id;
695 u8 addr1[ETH_ALEN];
696 u8 addr2[ETH_ALEN];
697 u8 addr3[ETH_ALEN];
698 __le16 seq_ctl;
699 u8 payload[0];
700 } __packed;
701
702 struct rtl_info_element {
703 u8 id;
704 u8 len;
705 u8 data[0];
706 } __packed;
707
708 struct rtl_probe_rsp {
709 struct rtl_hdr_3addr header;
710 u32 time_stamp[2];
711 __le16 beacon_interval;
712 __le16 capability;
713 /*SSID, supported rates, FH params, DS params,
714 CF params, IBSS params, TIM (if beacon), RSN */
715 struct rtl_info_element info_element[0];
716 } __packed;
717
718 /*LED related.*/
719 /*ledpin Identify how to implement this SW led.*/
720 struct rtl_led {
721 void *hw;
722 enum rtl_led_pin ledpin;
723 bool b_ledon;
724 };
725
726 struct rtl_led_ctl {
727 bool bled_opendrain;
728 struct rtl_led sw_led0;
729 struct rtl_led sw_led1;
730 };
731
732 struct rtl_qos_parameters {
733 __le16 cw_min;
734 __le16 cw_max;
735 u8 aifs;
736 u8 flag;
737 __le16 tx_op;
738 } __packed;
739
740 struct rt_smooth_data {
741 u32 elements[100]; /*array to store values */
742 u32 index; /*index to current array to store */
743 u32 total_num; /*num of valid elements */
744 u32 total_val; /*sum of valid elements */
745 };
746
747 struct rtl_ht_agg {
748 u16 txq_id;
749 u16 wait_for_ba;
750 u16 start_idx;
751 u64 bitmap;
752 u32 rate_n_flags;
753 u8 agg_state;
754 u8 rx_agg_state;
755 };
756
757 struct rtl_tid_data {
758 u16 seq_number;
759 struct rtl_ht_agg agg;
760 };
761
762 struct rssi_sta {
763 long undecorated_smoothed_pwdb;
764 };
765
766 struct rtl_sta_info {
767 struct list_head list;
768 u8 ratr_index;
769 u8 wireless_mode;
770 u8 mimo_ps;
771 u8 mac_addr[6];
772 struct rtl_tid_data tids[MAX_TID_COUNT];
773
774 /* just used for ap adhoc or mesh*/
775 struct rssi_sta rssi_stat;
776 } __packed;
777
778 #ifdef VIF_TODO
779 struct rtl_vif {
780 unsigned int id;
781 /* struct ieee80211_vif __rcu *vif; */
782 struct ieee80211_vif *vif;
783 };
784
785 struct rtl_vif_info {
786 struct list_head list;
787 bool active;
788 unsigned int id;
789 struct sk_buff *beacon;
790 bool enable_beacon;
791 };
792
793 struct vif_priv {
794 struct list_head vif_list;
795
796 /* interface mode settings */
797 unsigned long vif_bitmap;
798 unsigned int vifs;
799 struct rtl_vif vif[MAX_VIRTUAL_MAC];
800
801 /* beaconing */
802 spinlock_t beacon_lock;
803 unsigned int global_pretbtt;
804 unsigned int global_beacon_int;
805 /* struct rtl_vif_info __rcu *beacon_iter; */
806 struct rtl_vif_info *beacon_iter;
807 unsigned int beacon_enabled;
808 };
809 #endif
810
811 struct false_alarm_statistics {
812 u32 cnt_parity_fail;
813 u32 cnt_rate_illegal;
814 u32 cnt_crc8_fail;
815 u32 cnt_mcs_fail;
816 u32 cnt_fast_fsync_fail;
817 u32 cnt_sb_search_fail;
818 u32 cnt_ofdm_fail;
819 u32 cnt_cck_fail;
820 u32 cnt_all;
821 u32 cnt_ofdm_cca;
822 u32 cnt_cck_cca;
823 u32 cnt_cca_all;
824 u32 cnt_bw_usc;
825 u32 cnt_bw_lsc;
826 };
827
828 struct init_gain {
829 u8 xaagccore1;
830 u8 xbagccore1;
831 u8 xcagccore1;
832 u8 xdagccore1;
833 u8 cca;
834
835 };
836
837 struct wireless_stats {
838 unsigned long txbytesunicast;
839 unsigned long txbytesmulticast;
840 unsigned long txbytesbroadcast;
841 unsigned long rxbytesunicast;
842
843 long rx_snr_db[4];
844 /*Correct smoothed ss in Dbm, only used
845 in driver to report real power now. */
846 long recv_signal_power;
847 long signal_quality;
848 long last_sigstrength_inpercent;
849
850 u32 rssi_calculate_cnt;
851 u32 pwdb_all_cnt;
852
853 /*Transformed, in dbm. Beautified signal
854 strength for UI, not correct. */
855 long signal_strength;
856
857 u8 rx_rssi_percentage[4];
858 u8 rx_evm_dbm[4];
859 u8 rx_evm_percentage[2];
860
861 u16 rx_cfo_short[4];
862 u16 rx_cfo_tail[4];
863
864 struct rt_smooth_data ui_rssi;
865 struct rt_smooth_data ui_link_quality;
866 };
867
868 struct rate_adaptive {
869 u8 rate_adaptive_disabled;
870 u8 ratr_state;
871 u16 reserve;
872
873 u32 high_rssi_thresh_for_ra;
874 u32 high2low_rssi_thresh_for_ra;
875 u8 low2high_rssi_thresh_for_ra;
876 u32 low_rssi_thresh_for_ra;
877 u32 upper_rssi_threshold_ratr;
878 u32 middleupper_rssi_threshold_ratr;
879 u32 middle_rssi_threshold_ratr;
880 u32 middlelow_rssi_threshold_ratr;
881 u32 low_rssi_threshold_ratr;
882 u32 ultralow_rssi_threshold_ratr;
883 u32 low_rssi_threshold_ratr_40m;
884 u32 low_rssi_threshold_ratr_20m;
885 u8 ping_rssi_enable;
886 u32 ping_rssi_ratr;
887 u32 ping_rssi_thresh_for_ra;
888 u32 last_ratr;
889 u8 pre_ratr_state;
890 u8 ldpc_thres;
891 bool use_ldpc;
892 bool lower_rts_rate;
893 bool is_special_data;
894 };
895
896 struct regd_pair_mapping {
897 u16 reg_dmnenum;
898 u16 reg_5ghz_ctl;
899 u16 reg_2ghz_ctl;
900 };
901
902 struct dynamic_primary_cca {
903 u8 pricca_flag;
904 u8 intf_flag;
905 u8 intf_type;
906 u8 dup_rts_flag;
907 u8 monitor_flag;
908 u8 ch_offset;
909 u8 mf_state;
910 };
911
912 struct rtl_regulatory {
913 char alpha2[2];
914 u16 country_code;
915 u16 max_power_level;
916 u32 tp_scale;
917 u16 current_rd;
918 u16 current_rd_ext;
919 int16_t power_limit;
920 struct regd_pair_mapping *regpair;
921 };
922
923 struct rtl_rfkill {
924 bool rfkill_state; /*0 is off, 1 is on */
925 };
926
927 /*for P2P PS**/
928 #define P2P_MAX_NOA_NUM 2
929
930 enum p2p_role {
931 P2P_ROLE_DISABLE = 0,
932 P2P_ROLE_DEVICE = 1,
933 P2P_ROLE_CLIENT = 2,
934 P2P_ROLE_GO = 3
935 };
936
937 enum p2p_ps_state {
938 P2P_PS_DISABLE = 0,
939 P2P_PS_ENABLE = 1,
940 P2P_PS_SCAN = 2,
941 P2P_PS_SCAN_DONE = 3,
942 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
943 };
944
945 enum p2p_ps_mode {
946 P2P_PS_NONE = 0,
947 P2P_PS_CTWINDOW = 1,
948 P2P_PS_NOA = 2,
949 P2P_PS_MIX = 3, /* CTWindow and NoA */
950 };
951
952 struct rtl_p2p_ps_info {
953 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
954 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
955 u8 noa_index; /* Identifies and instance of Notice of Absence timing. */
956 /* Client traffic window. A period of time in TU after TBTT. */
957 u8 ctwindow;
958 u8 opp_ps; /* opportunistic power save. */
959 u8 noa_num; /* number of NoA descriptor in P2P IE. */
960 /* Count for owner, Type of client. */
961 u8 noa_count_type[P2P_MAX_NOA_NUM];
962 /* Max duration for owner, preferred or
963 * min acceptable duration for client. */
964 u32 noa_duration[P2P_MAX_NOA_NUM];
965 /* Length of interval for owner, preferred or
966 * max acceptable interval of client. */
967 u32 noa_interval[P2P_MAX_NOA_NUM];
968 /* schedule expressed in terms of the lower 4 bytes of the TSF timer. */
969 u32 noa_start_time[P2P_MAX_NOA_NUM];
970 };
971
972 struct p2p_ps_offload_t {
973 u8 Offload_En:1;
974 u8 role:1; /* 1: Owner, 0: Client */
975 u8 CTWindow_En:1;
976 u8 NoA0_En:1;
977 u8 NoA1_En:1;
978 u8 AllStaSleep:1;
979 u8 discovery:1;
980 u8 reserved:1;
981 };
982
983 #define IQK_MATRIX_REG_NUM 8
984 #define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
985 struct iqk_matrix_regs {
986 bool b_iqk_done;
987 long value[1][IQK_MATRIX_REG_NUM];
988 };
989
990 struct rtl_phy {
991 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
992 struct init_gain initgain_backup;
993 enum io_type current_io_type;
994
995 u8 rf_mode;
996 u8 rf_type;
997 u8 current_chan_bw;
998 u8 set_bwmode_inprogress;
999 u8 sw_chnl_inprogress;
1000 u8 sw_chnl_stage;
1001 u8 sw_chnl_step;
1002 u8 current_channel;
1003 u8 h2c_box_num;
1004 u8 set_io_inprogress;
1005 u8 lck_inprogress;
1006
1007 /* record for power tracking */
1008 s32 reg_e94;
1009 s32 reg_e9c;
1010 s32 reg_ea4;
1011 s32 reg_eac;
1012 s32 reg_eb4;
1013 s32 reg_ebc;
1014 s32 reg_ec4;
1015 s32 reg_ecc;
1016 u8 rfpienable;
1017 u8 reserve_0;
1018 u16 reserve_1;
1019 u32 reg_c04, reg_c08, reg_874;
1020 u32 adda_backup[16];
1021 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1022 u32 iqk_bb_backup[10];
1023 bool iqk_initialized;
1024
1025 bool rfpath_rx_enable[MAX_RF_PATH];
1026 /*Jaguar*/
1027 u8 reg_837;
1028 /* Dul mac */
1029 bool b_need_iqk;
1030 struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
1031
1032 bool b_rfpi_enable;
1033
1034 bool b_iqk_in_progress;
1035
1036 u8 pwrgroup_cnt;
1037 u8 bcck_high_power;
1038 /* this is for 88E & 8723A */
1039 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1040 /* this is for 92EE */
1041 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1042 [TX_PWR_BY_RATE_NUM_RF]
1043 [TX_PWR_BY_RATE_NUM_RF]
1044 [TX_PWR_BY_RATE_NUM_SECTION];
1045 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1046 [TX_PWR_BY_RATE_NUM_RF]
1047 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1048
1049 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1050 [TX_PWR_BY_RATE_NUM_RF]
1051 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1052 u8 default_initialgain[4];
1053
1054 /* the current Tx power level */
1055 u8 cur_cck_txpwridx;
1056 u8 cur_ofdm24g_txpwridx;
1057 u8 cur_bw20_txpwridx;
1058 u8 cur_bw40_txpwridx;
1059
1060 u32 rfreg_chnlval[2];
1061 bool b_apk_done;
1062 u32 reg_rf3c[2]; /* pathA / pathB */
1063
1064 u32 backup_rf_0x1a;/*92ee*/
1065 /* bfsync */
1066 u8 framesync;
1067 u32 framesync_c34;
1068
1069 u8 num_total_rfpath;
1070 u16 rf_pathmap;
1071
1072 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1073
1074 enum rt_polarity_ctl polarity_ctl;
1075 };
1076
1077 #define RTL_AGG_STOP 0
1078 #define RTL_AGG_PROGRESS 1
1079 #define RTL_AGG_START 2
1080 #define RTL_AGG_OPERATIONAL 3
1081 #define RTL_RX_AGG_START 1
1082 #define RTL_RX_AGG_STOP 0
1083
1084 struct rtl_priv;
1085 struct rtl_io {
1086 struct device *dev;
1087
1088 /*PCI MEM map */
1089 unsigned long pci_mem_end; /*shared mem end */
1090 unsigned long pci_mem_start; /*shared mem start */
1091
1092 /*PCI IO map */
1093 unsigned long pci_base_addr; /*device I/O address */
1094
1095 void (*write8_async)(struct rtl_priv *rtlpriv, u32 addr, u8 val);
1096 void (*write16_async)(struct rtl_priv *rtlpriv, u32 addr, u16 val);
1097 void (*write32_async)(struct rtl_priv *rtlpriv, u32 addr, u32 val);
1098
1099 u8 (*read8_sync)(struct rtl_priv *rtlpriv, u32 addr);
1100 u16 (*read16_sync)(struct rtl_priv *rtlpriv, u32 addr);
1101 u32 (*read32_sync)(struct rtl_priv *rtlpriv, u32 addr);
1102
1103 };
1104
1105 struct rtl_mac {
1106 u8 mac_addr[ETH_ALEN];
1107 u8 mac80211_registered;
1108 u8 beacon_enabled;
1109
1110 u32 tx_ss_num;
1111 u32 rx_ss_num;
1112
1113 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1114 struct ieee80211_hw *hw;
1115 struct ieee80211_vif *vif;
1116 enum nl80211_iftype opmode;
1117
1118 /*Probe Beacon management */
1119 enum rtl_link_state link_state;
1120
1121 int n_channels;
1122 int n_bitrates;
1123
1124 bool offchan_deley;
1125 u8 p2p; /*using p2p role*/
1126 bool p2p_in_use;
1127
1128 /*filters */
1129 u32 rx_conf;
1130
1131 bool act_scanning;
1132 u8 cnt_after_linked;
1133 bool skip_scan;
1134
1135 /* early mode */
1136 /* skb wait queue */
1137 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1138
1139 /*RDG*/
1140 bool rdg_en;
1141
1142 /*AP*/
1143 u8 bssid[6];
1144 u32 vendor;
1145 u32 basic_rates; /* b/g rates */
1146 u8 ht_enable;
1147 u8 bw_40;
1148 u8 mode; /* wireless mode */
1149 u8 slot_time;
1150 u8 short_preamble;
1151 u8 use_cts_protect;
1152 u8 cur_40_prime_sc;
1153 u8 cur_40_prime_sc_bk;
1154 u8 cur_80_prime_sc;
1155 u64 tsf;
1156 u8 retry_short;
1157 u8 retry_long;
1158 u16 assoc_id;
1159 bool bhiddenssid;
1160
1161 /*IBSS*/
1162 int beacon_interval;
1163
1164 /*AMPDU*/
1165 u8 min_space_cfg; /*For Min spacing configurations */
1166 u8 max_mss_density;
1167 u8 current_ampdu_factor;
1168 u8 current_ampdu_density;
1169
1170 /*QOS & EDCA */
1171 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1172 struct rtl_qos_parameters ac[AC_MAX];
1173 };
1174
1175 struct rtl_hal {
1176 struct ieee80211_hw *hw;
1177
1178 bool driver_is_goingto_unload;
1179 bool up_first_time;
1180 bool bfirst_init;
1181 bool being_init_adapter;
1182 bool b_bbrf_ready;
1183 bool b_mac_func_enable;
1184 bool b_pre_edcca_enable;
1185
1186 enum intf_type interface;
1187 u16 hw_type; /*92c or 92d or 92s and so on */
1188 u8 ic_class;
1189 u8 oem_id;
1190 u32 version; /*version of chip */
1191 u8 state; /*stop 0, start 1 */
1192 u8 boad_type;
1193
1194 /*firmware */
1195 u32 fwsize;
1196 u8 *pfirmware;
1197 u16 fw_version;
1198 u16 fw_subversion;
1199 bool b_h2c_setinprogress;
1200 u8 last_hmeboxnum;
1201 bool bfw_ready;
1202
1203 /*Reserve page start offset except beacon in TxQ. */
1204 u8 fw_rsvdpage_startoffset;
1205 u8 h2c_txcmd_seq;
1206 u8 current_ra_rate;
1207
1208 /* FW Cmd IO related */
1209 u16 fwcmd_iomap;
1210 u32 fwcmd_ioparam;
1211 bool set_fwcmd_inprogress;
1212 u8 current_fwcmd_io;
1213
1214 bool bfw_clk_change_in_progress;
1215 bool ballow_sw_to_change_hwclc;
1216 u8 fw_ps_state;
1217 struct p2p_ps_offload_t p2p_ps_offload;
1218 /**/
1219 bool driver_going2unload;
1220
1221 /*AMPDU init min space*/
1222 u8 minspace_cfg; /*For Min spacing configurations */
1223
1224 /* Dul mac */
1225 enum macphy_mode macphymode;
1226 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1227 enum band_type current_bandtypebackup;
1228 enum band_type bandset;
1229 /* dual MAC 0--Mac0 1--Mac1 */
1230 u32 interfaceindex;
1231 /* just for DulMac S3S4 */
1232 u8 macphyctl_reg;
1233 bool b_earlymode_enable;
1234 u8 max_earlymode_num;
1235 /* Dul mac*/
1236 bool during_mac0init_radiob;
1237 bool during_mac1init_radioa;
1238 bool reloadtxpowerindex;
1239 /* True if IMR or IQK have done
1240 for 2.4G in scan progress */
1241 bool b_load_imrandiqk_setting_for2g;
1242
1243 bool disable_amsdu_8k;
1244 bool bmaster_of_dmsp;
1245 bool bslave_of_dmsp;
1246
1247 u16 rx_tag;/*for 92ee*/
1248 u8 rts_en;
1249 };
1250
1251 struct rtl_security {
1252 /*default 0 */
1253 bool use_sw_sec;
1254
1255 bool being_setkey;
1256 bool use_defaultkey;
1257 /*Encryption Algorithm for Unicast Packet */
1258 enum rt_enc_alg pairwise_enc_algorithm;
1259 /*Encryption Algorithm for Broadcast/Multicast */
1260 enum rt_enc_alg group_enc_algorithm;
1261 /*Cam Entry Bitmap */
1262 u32 hwsec_cam_bitmap;
1263 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1264 /*local Key buffer, indx 0 is for
1265 pairwise key 1-4 is for agoup key. */
1266 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1267 u8 key_len[KEY_BUF_SIZE];
1268
1269 /*The pointer of Pairwise Key,
1270 it always points to KeyBuf[4] */
1271 u8 *pairwise_key;
1272 };
1273
1274 struct rtl_dig {
1275 u8 dig_enable_flag;
1276 u8 dig_ext_port_stage;
1277
1278 u32 rssi_lowthresh;
1279 u32 rssi_highthresh;
1280
1281 u32 fa_lowthresh;
1282 u32 fa_highthresh;
1283
1284 u8 cursta_connectstate;
1285 u8 presta_connectstate;
1286 u8 curmultista_connectstate;
1287
1288 u8 pre_igvalue;
1289 u8 cur_igvalue;
1290
1291 char backoff_val;
1292 char backoff_val_range_max;
1293 char backoff_val_range_min;
1294 u8 rx_gain_range_max;
1295 u8 rx_gain_range_min;
1296 u8 rssi_val_min;
1297 u8 min_undecorated_pwdb_for_dm;
1298 long last_min_undecorated_pwdb_for_dm;
1299
1300 u8 pre_cck_pd_state;
1301 u8 cur_cck_pd_state;
1302
1303 u8 large_fa_hit;
1304 u8 forbidden_igi;
1305 u32 recover_cnt;
1306
1307 };
1308
1309 struct rtl_pstbl {
1310 u8 pre_ccastate;
1311 u8 cur_ccasate;
1312
1313 u8 pre_rfstate;
1314 u8 cur_rfstate;
1315
1316 long rssi_val_min;
1317
1318 };
1319
1320 #define ASSOCIATE_ENTRY_NUM (32+1)
1321
1322 struct fast_ant_trainning {
1323 u8 bssid[6];
1324 u8 antsel_rx_keep_0;
1325 u8 antsel_rx_keep_1;
1326 u8 antsel_rx_keep_2;
1327 u32 ant_sum_rssi[7];
1328 u32 ant_rssi_cnt[7];
1329 u32 ant_ave_rssi[7];
1330 u8 fat_state;
1331 u32 train_idx;
1332 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1333 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1334 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1335 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1336 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1337 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1338 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1339 u8 rx_idle_ant;
1340 bool b_becomelinked;
1341 };
1342
1343 struct dm_phy_dbg_info {
1344 char rx_snrdb[4];
1345 u64 num_qry_phy_status;
1346 u64 num_qry_phy_status_cck;
1347 u64 num_qry_phy_status_ofdm;
1348 u16 num_qry_beacon_pkt;
1349 u16 num_non_be_pkt;
1350 s32 rx_evm[4];
1351 };
1352
1353 struct rtl_dm {
1354 /*PHY status for DM */
1355 long entry_min_undecoratedsmoothed_pwdb;
1356 long undecorated_smoothed_pwdb; /*out dm */
1357 long entry_max_undecoratedsmoothed_pwdb;
1358 bool b_dm_initialgain_enable;
1359 bool bdynamic_txpower_enable;
1360 bool bcurrent_turbo_edca;
1361 bool bis_any_nonbepkts; /*out dm */
1362 bool bis_cur_rdlstate;
1363 bool btxpower_trackinginit;
1364 bool b_disable_framebursting;
1365 bool b_cck_inch14;
1366 bool btxpower_tracking;
1367 bool b_useramask;
1368 bool brfpath_rxenable[4];
1369 bool binform_fw_driverctrldm;
1370 bool bcurrent_mrc_switch;
1371 u8 txpowercount;
1372
1373 u8 thermalvalue_rxgain;
1374 u8 thermalvalue_iqk;
1375 u8 thermalvalue_lck;
1376 u8 thermalvalue;
1377 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1378 u8 thermalvalue_avg_index;
1379 bool bdone_txpower;
1380 u8 last_dtp_lvl;
1381 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1382 u8 dm_flag; /*Indicate if each dynamic mechanism's status. */
1383 u8 dm_type;
1384 u8 txpower_track_control;
1385 bool binterrupt_migration;
1386 bool bdisable_tx_int;
1387 char ofdm_index[MAX_RF_PATH];
1388 u8 default_ofdm_index;
1389 u8 default_cck_index;
1390 char cck_index;
1391 char delta_power_index[MAX_RF_PATH];
1392 char delta_power_index_last[MAX_RF_PATH];
1393 char power_index_offset[MAX_RF_PATH];
1394 char aboslute_ofdm_swing_idx[MAX_RF_PATH];
1395 char remnant_ofdm_swing_idx[MAX_RF_PATH];
1396 char remnant_cck_idx;
1397 bool modify_txagc_flag_path_a;
1398 bool modify_txagc_flag_path_b;
1399
1400 bool b_one_entry_only;
1401 struct dm_phy_dbg_info dbginfo;
1402 /* Dynamic ATC switch */
1403
1404 bool atc_status;
1405 bool large_cfo_hit;
1406 bool is_freeze;
1407 int cfo_tail[2];
1408 int cfo_ave_pre;
1409 int crystal_cap;
1410 u8 cfo_threshold;
1411 u32 packet_count;
1412 u32 packet_count_pre;
1413 u8 tx_rate;
1414
1415
1416 /*88e tx power tracking*/
1417 u8 bb_swing_idx_ofdm[MAX_RF_PATH];
1418 u8 bb_swing_idx_ofdm_current;
1419 u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
1420 bool bb_swing_flag_Ofdm;
1421 u8 bb_swing_idx_cck;
1422 u8 bb_swing_idx_cck_current;
1423 u8 bb_swing_idx_cck_base;
1424 bool bb_swing_flag_cck;
1425
1426 char bb_swing_diff_2g;
1427 char bb_swing_diff_5g;
1428
1429 u8 delta_swing_table_idx_24gccka_p[DELTA_SWINGIDX_SIZE];
1430 u8 delta_swing_table_idx_24gccka_n[DELTA_SWINGIDX_SIZE];
1431 u8 delta_swing_table_idx_24gcckb_p[DELTA_SWINGIDX_SIZE];
1432 u8 delta_swing_table_idx_24gcckb_n[DELTA_SWINGIDX_SIZE];
1433 u8 delta_swing_table_idx_24ga_p[DELTA_SWINGIDX_SIZE];
1434 u8 delta_swing_table_idx_24ga_n[DELTA_SWINGIDX_SIZE];
1435 u8 delta_swing_table_idx_24gb_p[DELTA_SWINGIDX_SIZE];
1436 u8 delta_swing_table_idx_24gb_n[DELTA_SWINGIDX_SIZE];
1437 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
1438 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
1439 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
1440 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
1441 u8 delta_swing_table_idx_24ga_p_8188e[DELTA_SWINGIDX_SIZE];
1442 u8 delta_swing_table_idx_24ga_n_8188e[DELTA_SWINGIDX_SIZE];
1443
1444
1445 /* DMSP */
1446 bool supp_phymode_switch;
1447
1448 /* DulMac */
1449 struct rtl_dig dm_digtable;
1450 struct rtl_pstbl dm_pstable;
1451 struct fast_ant_trainning fat_table;
1452
1453 u8 resp_tx_path;
1454 u8 path_sel;
1455 u32 patha_sum;
1456 u32 pathb_sum;
1457 u32 patha_cnt;
1458 u32 pathb_cnt;
1459
1460 u8 pre_channel;
1461 u8 *p_channel;
1462 u8 linked_interval;
1463
1464 u64 last_tx_ok_cnt;
1465 u64 last_rx_ok_cnt;
1466 };
1467
1468 #define EFUSE_MAX_LOGICAL_SIZE 256
1469
1470 struct rtl_efuse {
1471 bool bautoLoad_ok;
1472 bool bootfromefuse;
1473 u16 max_physical_size;
1474
1475 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1476 u16 efuse_usedbytes;
1477 u8 efuse_usedpercentage;
1478 #ifdef EFUSE_REPG_WORKAROUND
1479 bool efuse_re_pg_sec1flag;
1480 u8 efuse_re_pg_data[8];
1481 #endif
1482
1483 u8 autoload_failflag;
1484 u8 autoload_status;
1485
1486 short epromtype;
1487 u16 eeprom_vid;
1488 u16 eeprom_did;
1489 u16 eeprom_svid;
1490 u16 eeprom_smid;
1491 u8 eeprom_oemid;
1492 u16 eeprom_channelplan;
1493 u8 eeprom_version;
1494
1495 u8 dev_addr[6];
1496 u8 board_type;
1497 u8 wowlan_enable;
1498 u8 antenna_div_cfg;
1499 u8 antenna_div_type;
1500
1501 bool b_txpwr_fromeprom;
1502 u8 eeprom_crystalcap;
1503 u8 eeprom_tssi[2];
1504 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1505 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1506 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1507 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1508 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1509 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1510
1511
1512 u8 internal_pa_5g[2]; /* pathA / pathB */
1513 u8 eeprom_c9;
1514 u8 eeprom_cc;
1515
1516 /*For power group */
1517 u8 eeprom_pwrgroup[2][3];
1518 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1519 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1520
1521 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1522 /*For HT 40MHZ pwr */
1523 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1524 /*For HT 40MHZ pwr */
1525 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1526 char txpwr_cckdiff[MAX_RF_PATH][MAX_TX_COUNT]; /*CCK_24G_Diff*/
1527 /*HT 20<->40 Pwr diff */
1528 char txpwr_ht20diff[MAX_RF_PATH][MAX_TX_COUNT]; /*BW20_24G_Diff*/
1529 char txpwr_ht40diff[MAX_RF_PATH][MAX_TX_COUNT];/*BW40_24G_Diff*/
1530 /*For HT<->legacy pwr diff */
1531 char txpwr_legacyhtdiff[MAX_RF_PATH][MAX_TX_COUNT];/*OFDM_24G_Diff*/
1532
1533 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1534 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1535 char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1536 char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1537 char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1538 char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1539
1540 u8 txpwr_safetyflag; /* Band edge enable flag */
1541 u16 eeprom_txpowerdiff;
1542 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1543 u8 antenna_txpwdiff[3];
1544
1545 u8 eeprom_regulatory;
1546 u8 eeprom_thermalmeter;
1547 u8 thermalmeter[2];/*ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
1548 u16 tssi_13dbm;
1549 u8 crystalcap; /* CrystalCap. */
1550 u8 delta_iqk;
1551 u8 delta_lck;
1552
1553 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1554 bool b_apk_thermalmeterignore;
1555
1556 bool b1x1_recvcombine;
1557 bool b1ss_support;
1558
1559 /*channel plan */
1560 u8 channel_plan;
1561 };
1562
1563 struct rtl_ps_ctl {
1564 bool pwrdomain_protect;
1565 bool b_in_powersavemode;
1566 bool rfchange_inprogress;
1567 bool b_swrf_processing;
1568 bool b_hwradiooff;
1569 /*
1570 * just for PCIE ASPM
1571 * If it supports ASPM, Offset[560h] = 0x40,
1572 * otherwise Offset[560h] = 0x00.
1573 * */
1574 bool b_support_aspm;
1575 bool b_support_backdoor;
1576
1577 /*for LPS */
1578 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1579 bool b_swctrl_lps;
1580 bool b_fwctrl_lps;
1581 u8 fwctrl_psmode;
1582 /*For Fw control LPS mode */
1583 u8 b_reg_fwctrl_lps;
1584 /*Record Fw PS mode status. */
1585 bool b_fw_current_inpsmode;
1586 u8 reg_max_lps_awakeintvl;
1587 bool report_linked;
1588 bool b_low_power_enable;/*for 32k*/
1589
1590 /*for IPS */
1591 bool b_inactiveps;
1592
1593 u32 rfoff_reason;
1594
1595 /*RF OFF Level */
1596 u32 cur_ps_level;
1597 u32 reg_rfps_level;
1598
1599 /*just for PCIE ASPM */
1600 u8 const_amdpci_aspm;
1601
1602 enum rf_pwrstate inactive_pwrstate;
1603 enum rf_pwrstate rfpwr_state; /*cur power state */
1604
1605 /* for SW LPS*/
1606 bool sw_ps_enabled;
1607 bool state;
1608 bool state_inap;
1609 bool multi_buffered;
1610 u16 nullfunc_seq;
1611 unsigned int dtim_counter;
1612 unsigned int sleep_ms;
1613 unsigned long last_sleep_jiffies;
1614 unsigned long last_awake_jiffies;
1615 unsigned long last_delaylps_stamp_jiffies;
1616 unsigned long last_dtim;
1617 unsigned long last_beacon;
1618 unsigned long last_action;
1619 unsigned long last_slept;
1620
1621 /*For P2P PS */
1622 struct rtl_p2p_ps_info p2p_ps_info;
1623 u8 pwr_mode;
1624 u8 smart_ps;
1625 };
1626
1627 struct rtl_stats {
1628 u8 psaddr[ETH_ALEN];
1629 u32 mac_time[2];
1630 s8 rssi;
1631 u8 signal;
1632 u8 noise;
1633 u8 rate; /* hw desc rate */
1634 u8 rawdata;
1635 u8 received_channel;
1636 u8 control;
1637 u8 mask;
1638 u8 freq;
1639 u16 len;
1640 u64 tsf;
1641 u32 beacon_time;
1642 u8 nic_type;
1643 u16 length;
1644 u8 signalquality; /*in 0-100 index. */
1645 /*
1646 * Real power in dBm for this packet,
1647 * no beautification and aggregation.
1648 * */
1649 s32 recvsignalpower;
1650 s8 rxpower; /*in dBm Translate from PWdB */
1651 u8 signalstrength; /*in 0-100 index. */
1652 u16 b_hwerror:1;
1653 u16 b_crc:1;
1654 u16 b_icv:1;
1655 u16 b_shortpreamble:1;
1656 u16 antenna:1;
1657 u16 decrypted:1;
1658 u16 wakeup:1;
1659 u32 timestamp_low;
1660 u32 timestamp_high;
1661 bool b_shift;
1662
1663 u8 rx_drvinfo_size;
1664 u8 rx_bufshift;
1665 bool b_isampdu;
1666 bool b_isfirst_ampdu;
1667 bool rx_is40Mhzpacket;
1668 u32 rx_pwdb_all;
1669 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1670 s8 rx_mimo_signalquality[4];
1671 u8 rx_mimo_evm_dbm[4];
1672 u16 cfo_short[4]; /* per-path's Cfo_short */
1673 u16 cfo_tail[4];
1674 u8 rx_pwr[4]; /* per-path's pwdb */
1675 u8 rx_snr[4]; /* per-path's SNR */
1676 u8 bandwidth;
1677 u8 bt_coex_pwr_adjust;
1678 bool b_packet_matchbssid;
1679 bool b_is_cck;
1680 bool b_is_ht;
1681 bool b_packet_toself;
1682 bool b_packet_beacon; /*for rssi */
1683 char cck_adc_pwdb[4]; /*for rx path selection */
1684
1685 u8 packet_report_type;
1686
1687 u32 macid;
1688 u8 wake_match;
1689 u32 bt_rx_rssi_percentage;
1690 u32 macid_valid_entry[2];
1691 };
1692
1693 struct rt_link_detect {
1694 /* count for roaming */
1695 u32 bcn_rx_inperiod;
1696 u32 roam_times;
1697
1698 u32 num_tx_in4period[4];
1699 u32 num_rx_in4period[4];
1700
1701 u32 num_tx_inperiod;
1702 u32 num_rx_inperiod;
1703
1704 bool b_busytraffic;
1705 bool b_tx_busy_traffic;
1706 bool b_rx_busy_traffic;
1707 bool b_higher_busytraffic;
1708 bool b_higher_busyrxtraffic;
1709
1710 u32 tidtx_in4period[MAX_TID_COUNT][4];
1711 u32 tidtx_inperiod[MAX_TID_COUNT];
1712 bool higher_busytxtraffic[MAX_TID_COUNT];
1713 };
1714
1715 struct rtl_tcb_desc {
1716 u8 b_packet_bw:1;
1717 u8 b_multicast:1;
1718 u8 b_broadcast:1;
1719
1720 u8 b_rts_stbc:1;
1721 u8 b_rts_enable:1;
1722 u8 b_cts_enable:1;
1723 u8 b_rts_use_shortpreamble:1;
1724 u8 b_rts_use_shortgi:1;
1725 u8 rts_sc:1;
1726 u8 b_rts_bw:1;
1727 u8 rts_rate;
1728
1729 u8 use_shortgi:1;
1730 u8 use_shortpreamble:1;
1731 u8 use_driver_rate:1;
1732 u8 disable_ratefallback:1;
1733
1734 u8 ratr_index;
1735 u8 mac_id;
1736 u8 hw_rate;
1737
1738 u8 b_last_inipkt:1;
1739 u8 b_cmd_or_init:1;
1740 u8 queue_index;
1741
1742 /* early mode */
1743 u8 empkt_num;
1744 /* The max value by HW */
1745 u32 empkt_len[10];
1746 bool btx_enable_sw_calc_duration;
1747 /* used for hal construct pkt,
1748 * we may set desc when tx */
1749 u8 self_desc;
1750 };
1751
1752 struct proxim {
1753 bool proxim_on;
1754
1755 void *proximity_priv;
1756 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
1757 struct sk_buff *skb);
1758 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
1759 };
1760
1761 struct rtl_hal_ops {
1762 int (*init_sw_vars)(struct ieee80211_hw *hw);
1763 void (*deinit_sw_vars)(struct ieee80211_hw *hw);
1764 void (*read_eeprom_info)(struct ieee80211_hw *hw);
1765 void (*interrupt_recognized)(struct ieee80211_hw *hw,
1766 u32 *p_inta, u32 *p_intb);
1767 int (*hw_init)(struct ieee80211_hw *hw);
1768 void (*hw_disable)(struct ieee80211_hw *hw);
1769 void (*hw_suspend)(struct ieee80211_hw *hw);
1770 void (*hw_resume)(struct ieee80211_hw *hw);
1771 void (*enable_interrupt)(struct ieee80211_hw *hw);
1772 void (*disable_interrupt)(struct ieee80211_hw *hw);
1773 int (*set_network_type)(struct ieee80211_hw *hw,
1774 enum nl80211_iftype type);
1775 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1776 bool check_bssid);
1777 void (*set_bw_mode)(struct ieee80211_hw *hw,
1778 enum nl80211_channel_type ch_type);
1779 u8 (*switch_channel)(struct ieee80211_hw *hw);
1780 void (*set_qos)(struct ieee80211_hw *hw, int aci);
1781 void (*set_bcn_reg)(struct ieee80211_hw *hw);
1782 void (*set_bcn_intv)(struct ieee80211_hw *hw);
1783 void (*update_interrupt_mask)(struct ieee80211_hw *hw,
1784 u32 add_msr, u32 rm_msr);
1785 void (*get_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
1786 void (*set_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
1787 void (*update_rate_tbl)(struct ieee80211_hw *hw,
1788 struct ieee80211_sta *sta, u8 rssi_level);
1789 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
1790 u8 *desc, u8 queue_index,
1791 struct sk_buff *skb, dma_addr_t addr);
1792 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
1793 u8 queue_index);
1794 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
1795 u8 queue_index);
1796 void (*fill_tx_desc)(struct ieee80211_hw *hw,
1797 struct ieee80211_hdr *hdr,
1798 u8 *pdesc_tx, u8 *pbd_desc,
1799 struct ieee80211_tx_info *info,
1800 /*<delete in kernel start>*/
1801 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
1802 /*<delete in kernel end>*/
1803 struct ieee80211_sta *sta,
1804 /*<delete in kernel start>*/
1805 #endif
1806 /*<delete in kernel end>*/
1807 struct sk_buff *skb, u8 hw_queue,
1808 struct rtl_tcb_desc *ptcb_desc);
1809 void (*fill_tx_cmddesc)(struct ieee80211_hw *hw, u8 *pdesc,
1810 bool b_firstseg, bool b_lastseg,
1811 struct sk_buff *skb);
1812 bool (*query_rx_desc)(struct ieee80211_hw *hw,
1813 struct rtl_stats *status,
1814 struct ieee80211_rx_status *rx_status,
1815 u8 *pdesc, struct sk_buff *skb);
1816 void (*set_channel_access)(struct ieee80211_hw *hw);
1817 bool (*radio_onoff_checking)(struct ieee80211_hw *hw, u8 *valid);
1818 void (*dm_watchdog)(struct ieee80211_hw *hw);
1819 void (*scan_operation_backup)(struct ieee80211_hw *hw, u8 operation);
1820 bool (*set_rf_power_state)(struct ieee80211_hw *hw,
1821 enum rf_pwrstate rfpwr_state);
1822 void (*led_control)(struct ieee80211_hw *hw,
1823 enum led_ctl_mode ledaction);
1824 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
1825 u8 desc_name, u8 *val);
1826 u32 (*get_desc)(u8 *pdesc, bool istx, u8 desc_name);
1827 bool (*is_tx_desc_closed)(struct ieee80211_hw *hw,
1828 u8 hw_queue, u16 index);
1829 void (*tx_polling)(struct ieee80211_hw *hw, u8 hw_queue);
1830 void (*enable_hw_sec)(struct ieee80211_hw *hw);
1831 void (*set_key)(struct ieee80211_hw *hw, u32 key_index,
1832 u8 *p_macaddr, bool is_group, u8 enc_algo,
1833 bool is_wepkey, bool clear_all);
1834 void (*init_sw_leds)(struct ieee80211_hw *hw);
1835 u32 (*get_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1836 void (*set_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1837 u32 data);
1838 u32 (*get_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
1839 u32 regaddr, u32 bitmask);
1840 void (*set_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
1841 u32 regaddr, u32 bitmask, u32 data);
1842 void (*allow_all_destaddr)(struct ieee80211_hw *hw,
1843 bool allow_all_da, bool write_into_reg);
1844 void (*linked_set_reg)(struct ieee80211_hw *hw);
1845 void (*check_switch_to_dmdp)(struct ieee80211_hw *hw);
1846 void (*dualmac_easy_concurrent)(struct ieee80211_hw *hw);
1847 void (*dualmac_switch_to_dmdp)(struct ieee80211_hw *hw);
1848 void (*c2h_command_handle)(struct ieee80211_hw *hw);
1849 void (*bt_wifi_media_status_notify)(struct ieee80211_hw *hw,
1850 bool mstate);
1851 void (*bt_turn_off_bt_coexist_before_enter_lps)(struct ieee80211_hw *hw);
1852 void (*fill_h2c_cmd)(struct ieee80211_hw *hw, u8 element_id,
1853 u32 cmd_len, u8 *p_cmdbuffer);
1854 bool (*get_btc_status)(void);
1855 u32 (*rx_command_packet_handler)(struct ieee80211_hw *hw,
1856 struct rtl_stats status,
1857 struct sk_buff *skb);
1858 };
1859
1860 struct rtl_intf_ops {
1861 /*com */
1862 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1863 int (*adapter_start)(struct ieee80211_hw *hw);
1864 void (*adapter_stop)(struct ieee80211_hw *hw);
1865 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
1866 struct rtl_priv **buddy_priv);
1867
1868 /*<delete in kernel start>*/
1869 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1870 int (*adapter_tx)(struct ieee80211_hw *hw, struct sk_buff *skb,
1871 struct rtl_tcb_desc *ptcb_desc);
1872 #else
1873 /*<delete in kernel end>*/
1874 int (*adapter_tx)(struct ieee80211_hw *hw,
1875 struct ieee80211_sta *sta,
1876 struct sk_buff *skb,
1877 struct rtl_tcb_desc *ptcb_desc);
1878 /*<delete in kernel start>*/
1879 #endif
1880 /*<delete in kernel end>*/
1881 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
1882 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
1883 #else
1884 void (*flush)(struct ieee80211_hw *hw, bool drop);
1885 #endif
1886 int (*reset_trx_ring)(struct ieee80211_hw *hw);
1887 /*<delete in kernel start>*/
1888 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1889 bool (*waitq_insert)(struct ieee80211_hw *hw, struct sk_buff *skb);
1890 #else
1891 /*<delete in kernel end>*/
1892 bool (*waitq_insert)(struct ieee80211_hw *hw,
1893 struct ieee80211_sta *sta,
1894 struct sk_buff *skb);
1895 /*<delete in kernel start>*/
1896 #endif
1897 /*<delete in kernel end>*/
1898
1899 /*pci */
1900 void (*disable_aspm)(struct ieee80211_hw *hw);
1901 void (*enable_aspm)(struct ieee80211_hw *hw);
1902
1903 /*usb */
1904 };
1905
1906 struct rtl_mod_params {
1907 /* default: 0 = using hardware encryption */
1908 bool sw_crypto;
1909
1910 /* default: 1 = using no linked power save */
1911 bool b_inactiveps;
1912
1913 /* default: 1 = using linked sw power save */
1914 bool b_swctrl_lps;
1915
1916 /* default: 1 = using linked fw power save */
1917 bool b_fwctrl_lps;
1918 };
1919
1920 struct rtl_hal_cfg {
1921 u8 bar_id;
1922 bool write_readback;
1923 char *name;
1924 char *fw_name;
1925 struct rtl_hal_ops *ops;
1926 struct rtl_mod_params *mod_params;
1927
1928 /*this map used for some registers or vars
1929 defined int HAL but used in MAIN */
1930 u32 maps[RTL_VAR_MAP_MAX];
1931
1932 };
1933
1934 struct rtl_locks {
1935 /* mutex */
1936 struct mutex conf_mutex;
1937
1938 /*spin lock */
1939 spinlock_t ips_lock;
1940 spinlock_t irq_th_lock;
1941 spinlock_t h2c_lock;
1942 spinlock_t rf_ps_lock;
1943 spinlock_t rf_lock;
1944 spinlock_t lps_lock;
1945 spinlock_t waitq_lock;
1946 spinlock_t entry_list_lock;
1947
1948 /*FW clock change */
1949 spinlock_t fw_ps_lock;
1950
1951 /*Dul mac*/
1952 spinlock_t cck_and_rw_pagea_lock;
1953
1954 /*Easy concurrent*/
1955 spinlock_t check_sendpkt_lock;
1956
1957 spinlock_t iqk_lock;
1958 };
1959
1960 struct rtl_works {
1961 struct ieee80211_hw *hw;
1962
1963 /*timer */
1964 struct timer_list watchdog_timer;
1965 struct timer_list dualmac_easyconcurrent_retrytimer;
1966 struct timer_list fw_clockoff_timer;
1967 struct timer_list fast_antenna_trainning_timer;
1968 /*task */
1969 struct tasklet_struct irq_tasklet;
1970 struct tasklet_struct irq_prepare_bcn_tasklet;
1971
1972 /*work queue */
1973 struct workqueue_struct *rtl_wq;
1974 struct delayed_work watchdog_wq;
1975 struct delayed_work ips_nic_off_wq;
1976
1977 /* For SW LPS */
1978 struct delayed_work ps_work;
1979 struct delayed_work ps_rfon_wq;
1980 struct delayed_work fwevt_wq;
1981 };
1982
1983 struct rtl_debug {
1984 u32 dbgp_type[DBGP_TYPE_MAX];
1985 u32 global_debuglevel;
1986 u64 global_debugcomponents;
1987
1988 /* add for proc debug */
1989 struct proc_dir_entry *proc_dir;
1990 char proc_name[20];
1991 };
1992
1993 #define MIMO_PS_STATIC 0
1994 #define MIMO_PS_DYNAMIC 1
1995 #define MIMO_PS_NOLIMIT 3
1996
1997 struct rtl_dualmac_easy_concurrent_ctl {
1998 enum band_type currentbandtype_backfordmdp;
1999 bool bclose_bbandrf_for_dmsp;
2000 bool bchange_to_dmdp;
2001 bool bchange_to_dmsp;
2002 bool bswitch_in_process;
2003 };
2004
2005 struct rtl_dmsp_ctl {
2006 bool bactivescan_for_slaveofdmsp;
2007 bool bscan_for_anothermac_fordmsp;
2008 bool bscan_for_itself_fordmsp;
2009 bool bwritedig_for_anothermacofdmsp;
2010 u32 curdigvalue_for_anothermacofdmsp;
2011 bool bchangecckpdstate_for_anothermacofdmsp;
2012 u8 curcckpdstate_for_anothermacofdmsp;
2013 bool bchangetxhighpowerlvl_for_anothermacofdmsp;
2014 u8 curtxhighlvl_for_anothermacofdmsp;
2015 long rssivalmin_for_anothermacofdmsp;
2016 };
2017
2018 struct rtl_global_var {
2019 /* from this list we can get
2020 * other adapter's rtl_priv */
2021 struct list_head glb_priv_list;
2022 spinlock_t glb_list_lock;
2023 };
2024
2025 struct rtl_btc_info {
2026 u8 bt_type;
2027 u8 btcoexist;
2028 u8 ant_num;
2029 };
2030
2031 struct rtl_btc_ops {
2032 void (*btc_init_variables)(struct rtl_priv *rtlpriv);
2033 void (*btc_init_hal_vars)(struct rtl_priv *rtlpriv);
2034 void (*btc_init_hw_config)(struct rtl_priv *rtlpriv);
2035 void (*btc_ips_notify)(struct rtl_priv *rtlpriv, u8 type);
2036 void (*btc_scan_notify)(struct rtl_priv *rtlpriv, u8 scantype);
2037 void (*btc_connect_notify)(struct rtl_priv *rtlpriv, u8 action);
2038 void (*btc_mediastatus_notify)(struct rtl_priv *rtlpriv,
2039 enum rt_media_status mstatus);
2040 void (*btc_periodical)(struct rtl_priv *rtlpriv);
2041 void (*btc_halt_notify)(void);
2042 void (*btc_btinfo_notify)(struct rtl_priv *rtlpriv,
2043 u8 *tmp_buf, u8 length);
2044 bool (*btc_is_limited_dig)(struct rtl_priv *rtlpriv);
2045 bool (*btc_is_disable_edca_turbo)(struct rtl_priv *rtlpriv);
2046 bool (*btc_is_bt_disabled)(struct rtl_priv *rtlpriv);
2047 };
2048
2049 struct rtl_bt_coexist {
2050 struct rtl_btc_ops *btc_ops;
2051 struct rtl_btc_info btc_info;
2052 };
2053
2054
2055 struct rtl_priv {
2056 struct list_head list;
2057 #ifdef VIF_TODO
2058 struct vif_priv vif_priv;
2059 #endif
2060 struct rtl_priv *buddy_priv;
2061 struct rtl_global_var *glb_var;
2062 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2063 struct rtl_dmsp_ctl dmsp_ctl;
2064 struct rtl_locks locks;
2065 struct rtl_works works;
2066 struct rtl_mac mac80211;
2067 struct rtl_hal rtlhal;
2068 struct rtl_regulatory regd;
2069 struct rtl_rfkill rfkill;
2070 struct rtl_io io;
2071 struct rtl_phy phy;
2072 struct rtl_dm dm;
2073 struct rtl_security sec;
2074 struct rtl_efuse efuse;
2075
2076 struct rtl_ps_ctl psc;
2077 struct rate_adaptive ra;
2078 struct dynamic_primary_cca primarycca;
2079 struct wireless_stats stats;
2080 struct rt_link_detect link_info;
2081 struct false_alarm_statistics falsealm_cnt;
2082
2083 struct rtl_rate_priv *rate_priv;
2084
2085 struct rtl_debug dbg;
2086
2087 /* sta entry list for ap adhoc or mesh */
2088 struct list_head entry_list;
2089
2090 /*
2091 *hal_cfg : for diff cards
2092 *intf_ops : for diff interface usb/pcie
2093 */
2094 struct rtl_hal_cfg *cfg;
2095 struct rtl_intf_ops *intf_ops;
2096
2097 /*this var will be set by set_bit,
2098 and was used to indicate status of
2099 interface or hardware */
2100 unsigned long status;
2101
2102 /* intel Proximity, should be alloc mem
2103 * in intel Proximity module and can only
2104 * be used in intel Proximity mode */
2105 struct proxim proximity;
2106
2107 /*for bt coexist use*/
2108 struct rtl_bt_coexist btcoexist;
2109
2110 /* separate 92ee from other ICs,
2111 * 92ee use new trx flow. */
2112 bool use_new_trx_flow;
2113 /*This must be the last item so
2114 that it points to the data allocated
2115 beyond this structure like:
2116 rtl_pci_priv or rtl_usb_priv */
2117 u8 priv[0];
2118 };
2119
2120 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2121 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2122 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2123 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2124 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2125 #define rtl_sec(rtlpriv) (&((rtlpriv)->sec))
2126 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2127 /***************************************
2128 Bluetooth Co-existance Related
2129 ****************************************/
2130
2131 enum bt_ant_num {
2132 ANT_X2 = 0,
2133 ANT_X1 = 1,
2134 };
2135
2136 enum bt_co_type {
2137 BT_2WIRE = 0,
2138 BT_ISSC_3WIRE = 1,
2139 BT_ACCEL = 2,
2140 BT_CSR_BC4 = 3,
2141 BT_CSR_BC8 = 4,
2142 BT_RTL8756 = 5,
2143 BT_RTL8723A = 6,
2144 BT_RTL8821A = 7,
2145 BT_RTL8723B = 8,
2146 BT_RTL8192E = 9,
2147 BT_RTL8812A = 11,
2148 };
2149
2150 enum bt_total_ant_num {
2151 ANT_TOTAL_X2 = 0,
2152 ANT_TOTAL_X1 = 1
2153 };
2154
2155 enum bt_cur_state {
2156 BT_OFF = 0,
2157 BT_ON = 1,
2158 };
2159
2160 enum bt_service_type {
2161 BT_SCO = 0,
2162 BT_A2DP = 1,
2163 BT_HID = 2,
2164 BT_HID_IDLE = 3,
2165 BT_SCAN = 4,
2166 BT_IDLE = 5,
2167 BT_OTHER_ACTION = 6,
2168 BT_BUSY = 7,
2169 BT_OTHERBUSY = 8,
2170 BT_PAN = 9,
2171 };
2172
2173 enum bt_radio_shared {
2174 BT_RADIO_SHARED = 0,
2175 BT_RADIO_INDIVIDUAL = 1,
2176 };
2177
2178 struct bt_coexist_info {
2179
2180 /* EEPROM BT info. */
2181 u8 eeprom_bt_coexist;
2182 u8 eeprom_bt_type;
2183 u8 eeprom_bt_ant_num;
2184 u8 eeprom_bt_ant_isolation;
2185 u8 eeprom_bt_radio_shared;
2186
2187 u8 bt_coexistence;
2188 u8 bt_ant_num;
2189 u8 bt_coexist_type;
2190 u8 bt_state;
2191 u8 bt_cur_state; /* 0:on, 1:off */
2192 u8 bt_ant_isolation; /* 0:good, 1:bad */
2193 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2194 u8 bt_service;
2195 u8 bt_radio_shared_type;
2196 u8 bt_rfreg_origin_1e;
2197 u8 bt_rfreg_origin_1f;
2198 u8 bt_rssi_state;
2199 u32 ratio_tx;
2200 u32 ratio_pri;
2201 u32 bt_edca_ul;
2202 u32 bt_edca_dl;
2203
2204 bool b_init_set;
2205 bool b_bt_busy_traffic;
2206 bool b_bt_traffic_mode_set;
2207 bool b_bt_non_traffic_mode_set;
2208
2209 bool b_fw_coexist_all_off;
2210 bool b_sw_coexist_all_off;
2211 bool b_hw_coexist_all_off;
2212 u32 current_state;
2213 u32 previous_state;
2214 u32 current_state_h;
2215 u32 previous_state_h;
2216
2217 u8 bt_pre_rssi_state;
2218 u8 bt_pre_rssi_state1;
2219
2220 u8 b_reg_bt_iso;
2221 u8 b_reg_bt_sco;
2222 bool b_balance_on;
2223 u8 bt_active_zero_cnt;
2224 bool b_cur_bt_disabled;
2225 bool b_pre_bt_disabled;
2226
2227 u8 bt_profile_case;
2228 u8 bt_profile_action;
2229 bool b_bt_busy;
2230 bool b_hold_for_bt_operation;
2231 u8 lps_counter;
2232 };
2233
2234
2235 /****************************************
2236 mem access macro define start
2237 Call endian free function when
2238 1. Read/write packet content.
2239 2. Before write integer to IO.
2240 3. After read integer from IO.
2241 ****************************************/
2242 /* Convert little data endian to host */
2243 #define EF1BYTE(_val) \
2244 ((u8)(_val))
2245 #define EF2BYTE(_val) \
2246 (le16_to_cpu(_val))
2247 #define EF4BYTE(_val) \
2248 (le32_to_cpu(_val))
2249
2250 /* Read data from memory */
2251 #define READEF1BYTE(_ptr) \
2252 EF1BYTE(*((u8 *)(_ptr)))
2253 #define READEF2BYTE(_ptr) \
2254 EF2BYTE(*((u16 *)(_ptr)))
2255 #define READEF4BYTE(_ptr) \
2256 EF4BYTE(*((u32 *)(_ptr)))
2257
2258 /* Write data to memory */
2259 #define WRITEEF1BYTE(_ptr, _val) \
2260 ((*((u8 *)(_ptr))) = EF1BYTE(_val))
2261 #define WRITEEF2BYTE(_ptr, _val) \
2262 ((*((u16 *)(_ptr))) = EF2BYTE(_val))
2263 #define WRITEEF4BYTE(_ptr, _val) \
2264 ((*((u32 *)(_ptr))) = EF4BYTE(_val))
2265
2266 /*Example:
2267 BIT_LEN_MASK_32(0) => 0x00000000
2268 BIT_LEN_MASK_32(1) => 0x00000001
2269 BIT_LEN_MASK_32(2) => 0x00000003
2270 BIT_LEN_MASK_32(32) => 0xFFFFFFFF*/
2271 #define BIT_LEN_MASK_32(__bitlen) \
2272 (0xFFFFFFFF >> (32 - (__bitlen)))
2273 #define BIT_LEN_MASK_16(__bitlen) \
2274 (0xFFFF >> (16 - (__bitlen)))
2275 #define BIT_LEN_MASK_8(__bitlen) \
2276 (0xFF >> (8 - (__bitlen)))
2277
2278 /*Example:
2279 BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2280 BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000*/
2281 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2282 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2283 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2284 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2285 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2286 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2287
2288 /*Description:
2289 Return 4-byte value in host byte ordering from
2290 4-byte pointer in little-endian system.*/
2291 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2292 (EF4BYTE(*((u32 *)(__pstart))))
2293 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2294 (EF2BYTE(*((u16 *)(__pstart))))
2295 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2296 (EF1BYTE(*((u8 *)(__pstart))))
2297
2298 /*Description:
2299 Translate subfield (continuous bits in little-endian) of 4-byte
2300 value to host byte ordering.*/
2301 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2302 ( \
2303 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2304 BIT_LEN_MASK_32(__bitlen) \
2305 )
2306 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2307 ( \
2308 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2309 BIT_LEN_MASK_16(__bitlen) \
2310 )
2311 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2312 ( \
2313 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2314 BIT_LEN_MASK_8(__bitlen) \
2315 )
2316
2317 /*Description:
2318 Mask subfield (continuous bits in little-endian) of 4-byte value
2319 and return the result in 4-byte value in host byte ordering.*/
2320 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2321 ( \
2322 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2323 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2324 )
2325 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2326 ( \
2327 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2328 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2329 )
2330 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2331 ( \
2332 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2333 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2334 )
2335
2336 /*Description:
2337 Set subfield of little-endian 4-byte value to specified value. */
2338 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2339 *((u32 *)(__pstart)) = EF4BYTE \
2340 ( \
2341 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2342 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset))\
2343 );
2344 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2345 *((u16 *)(__pstart)) = EF2BYTE \
2346 ( \
2347 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2348 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset))\
2349 );
2350 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2351 *((u8 *)(__pstart)) = EF1BYTE \
2352 ( \
2353 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2354 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2355 );
2356
2357 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2358 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2359
2360 /****************************************
2361 mem access macro define end
2362 ****************************************/
2363
2364 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2365
2366 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2367 #define RTL_WATCH_DOG_TIME 2000
2368 #define MSECS(t) msecs_to_jiffies(t)
2369 #define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS)
2370 #define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE)
2371 #define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE)
2372 #define WLAN_FC_MORE_DATA(fc) ((fc) & IEEE80211_FCTL_MOREDATA)
2373 #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
2374 #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
2375 #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
2376
2377 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2378 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2379 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2380 /*NIC halt, re-initialize hw parameters*/
2381 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2382 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2383 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2384 /*Always enable ASPM and Clock Req in initialization.*/
2385 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2386 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2387 #define RT_PS_LEVEL_ASPM BIT(7)
2388 /*When LPS is on, disable 2R if no packet is received or transmitted.*/
2389 #define RT_RF_LPS_DISALBE_2R BIT(30)
2390 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2391 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2392 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2393 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2394 (ppsc->cur_ps_level &= (~(_ps_flg)))
2395 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2396 (ppsc->cur_ps_level |= _ps_flg)
2397
2398 #define container_of_dwork_rtl(x,y,z) \
2399 container_of(container_of(x, struct delayed_work, work), y, z)
2400
2401 #define FILL_OCTET_STRING(_os,_octet,_len) \
2402 (_os).octet = (u8 *)(_octet); \
2403 (_os).length = (_len);
2404
2405 #define CP_MACADDR(des,src) \
2406 ((des)[0] = (src)[0],(des)[1] = (src)[1],\
2407 (des)[2] = (src)[2],(des)[3] = (src)[3],\
2408 (des)[4] = (src)[4],(des)[5] = (src)[5])
2409
2410 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2411 {
2412 return rtlpriv->io.read8_sync(rtlpriv, addr);
2413 }
2414
2415 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2416 {
2417 return rtlpriv->io.read16_sync(rtlpriv, addr);
2418 }
2419
2420 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2421 {
2422 return rtlpriv->io.read32_sync(rtlpriv, addr);
2423 }
2424
2425 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2426 {
2427 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2428
2429 if (rtlpriv->cfg->write_readback)
2430 rtlpriv->io.read8_sync(rtlpriv, addr);
2431 }
2432
2433 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2434 {
2435 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2436
2437 if (rtlpriv->cfg->write_readback)
2438 rtlpriv->io.read16_sync(rtlpriv, addr);
2439 }
2440
2441 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2442 u32 addr, u32 val32)
2443 {
2444 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2445
2446 if (rtlpriv->cfg->write_readback)
2447 rtlpriv->io.read32_sync(rtlpriv, addr);
2448 }
2449
2450 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2451 u32 regaddr, u32 bitmask)
2452 {
2453 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
2454 regaddr,
2455 bitmask);
2456 }
2457
2458 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2459 u32 bitmask, u32 data)
2460 {
2461 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
2462 regaddr, bitmask,
2463 data);
2464
2465 }
2466
2467 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2468 enum radio_path rfpath, u32 regaddr,
2469 u32 bitmask)
2470 {
2471 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
2472 rfpath,
2473 regaddr,
2474 bitmask);
2475 }
2476
2477 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2478 enum radio_path rfpath, u32 regaddr,
2479 u32 bitmask, u32 data)
2480 {
2481 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
2482 rfpath, regaddr,
2483 bitmask, data);
2484 }
2485
2486 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2487 {
2488 return (_HAL_STATE_STOP == rtlhal->state);
2489 }
2490
2491 static inline void set_hal_start(struct rtl_hal *rtlhal)
2492 {
2493 rtlhal->state = _HAL_STATE_START;
2494 }
2495
2496 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2497 {
2498 rtlhal->state = _HAL_STATE_STOP;
2499 }
2500
2501 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2502 {
2503 return rtlphy->rf_type;
2504 }
2505
2506 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2507 {
2508 return (struct ieee80211_hdr *)(skb->data);
2509 }
2510
2511 static inline u16 rtl_get_fc(struct sk_buff *skb)
2512 {
2513 return le16_to_cpu(rtl_get_hdr(skb)->frame_control);
2514 }
2515
2516 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2517 {
2518 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2519 }
2520
2521 static inline u16 rtl_get_tid(struct sk_buff *skb)
2522 {
2523 return rtl_get_tid_h(rtl_get_hdr(skb));
2524 }
2525
2526 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
2527 u8 *mac_addr)
2528 {
2529 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2530 return ieee80211_find_sta(mac->vif, mac_addr);
2531 }
2532
2533 struct ieee80211_hw *rtl_pci_get_hw_pointer(void);
2534 #endif
Linux with added FPC-III support