drivers/spi/spi-bcm63xx.c

   1 /*
   2  * Broadcom BCM63xx SPI controller support
   3  *
   4  * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
   5  * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the
  19  * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/delay.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/completion.h>
  32 #include <linux/err.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/pm_runtime.h>
  35
  36 #include <bcm63xx_dev_spi.h>
  37
  38 #define PFX             KBUILD_MODNAME
  39
  40 #define BCM63XX_SPI_MAX_PREPEND         15
  41
  42 struct bcm63xx_spi {
  43         struct completion       done;
  44
  45         void __iomem            *regs;
  46         int                     irq;
  47
  48         /* Platform data */
  49         unsigned                fifo_size;
  50         unsigned int            msg_type_shift;
  51         unsigned int            msg_ctl_width;
  52
  53         /* data iomem */
  54         u8 __iomem              *tx_io;
  55         const u8 __iomem        *rx_io;
  56
  57         struct clk              *clk;
  58         struct platform_device  *pdev;
  59 };
  60
  61 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
  62                                 unsigned int offset)
  63 {
  64         return bcm_readb(bs->regs + bcm63xx_spireg(offset));
  65 }
  66
  67 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
  68                                 unsigned int offset)
  69 {
  70         return bcm_readw(bs->regs + bcm63xx_spireg(offset));
  71 }
  72
  73 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
  74                                   u8 value, unsigned int offset)
  75 {
  76         bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
  77 }
  78
  79 static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
  80                                   u16 value, unsigned int offset)
  81 {
  82         bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
  83 }
  84
  85 static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
  86         { 20000000, SPI_CLK_20MHZ },
  87         { 12500000, SPI_CLK_12_50MHZ },
  88         {  6250000, SPI_CLK_6_250MHZ },
  89         {  3125000, SPI_CLK_3_125MHZ },
  90         {  1563000, SPI_CLK_1_563MHZ },
  91         {   781000, SPI_CLK_0_781MHZ },
  92         {   391000, SPI_CLK_0_391MHZ }
  93 };
  94
  95 static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
  96                                       struct spi_transfer *t)
  97 {
  98         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
  99         u8 clk_cfg, reg;
 100         int i;
 101
 102         /* Find the closest clock configuration */
 103         for (i = 0; i < SPI_CLK_MASK; i++) {
 104                 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
 105                         clk_cfg = bcm63xx_spi_freq_table[i][1];
 106                         break;
 107                 }
 108         }
 109
 110         /* No matching configuration found, default to lowest */
 111         if (i == SPI_CLK_MASK)
 112                 clk_cfg = SPI_CLK_0_391MHZ;
 113
 114         /* clear existing clock configuration bits of the register */
 115         reg = bcm_spi_readb(bs, SPI_CLK_CFG);
 116         reg &= ~SPI_CLK_MASK;
 117         reg |= clk_cfg;
 118
 119         bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
 120         dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
 121                 clk_cfg, t->speed_hz);
 122 }
 123
 124 /* the spi->mode bits understood by this driver: */
 125 #define MODEBITS (SPI_CPOL | SPI_CPHA)
 126
 127 static int bcm63xx_spi_setup(struct spi_device *spi)
 128 {
 129         if (spi->bits_per_word != 8) {
 130                 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
 131                         __func__, spi->bits_per_word);
 132                 return -EINVAL;
 133         }
 134
 135         return 0;
 136 }
 137
 138 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
 139                                 unsigned int num_transfers)
 140 {
 141         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 142         u16 msg_ctl;
 143         u16 cmd;
 144         u8 rx_tail;
 145         unsigned int i, timeout = 0, prepend_len = 0, len = 0;
 146         struct spi_transfer *t = first;
 147         bool do_rx = false;
 148         bool do_tx = false;
 149
 150         /* Disable the CMD_DONE interrupt */
 151         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 152
 153         dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 154                 t->tx_buf, t->rx_buf, t->len);
 155
 156         if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
 157                 prepend_len = t->len;
 158
 159         /* prepare the buffer */
 160         for (i = 0; i < num_transfers; i++) {
 161                 if (t->tx_buf) {
 162                         do_tx = true;
 163                         memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
 164
 165                         /* don't prepend more than one tx */
 166                         if (t != first)
 167                                 prepend_len = 0;
 168                 }
 169
 170                 if (t->rx_buf) {
 171                         do_rx = true;
 172                         /* prepend is half-duplex write only */
 173                         if (t == first)
 174                                 prepend_len = 0;
 175                 }
 176
 177                 len += t->len;
 178
 179                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 180                                transfer_list);
 181         }
 182
 183         init_completion(&bs->done);
 184
 185         /* Fill in the Message control register */
 186         msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
 187
 188         if (do_rx && do_tx && prepend_len == 0)
 189                 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
 190         else if (do_rx)
 191                 msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
 192         else if (do_tx)
 193                 msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
 194
 195         switch (bs->msg_ctl_width) {
 196         case 8:
 197                 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
 198                 break;
 199         case 16:
 200                 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
 201                 break;
 202         }
 203
 204         /* Issue the transfer */
 205         cmd = SPI_CMD_START_IMMEDIATE;
 206         cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 207         cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 208         bcm_spi_writew(bs, cmd, SPI_CMD);
 209
 210         /* Enable the CMD_DONE interrupt */
 211         bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 212
 213         timeout = wait_for_completion_timeout(&bs->done, HZ);
 214         if (!timeout)
 215                 return -ETIMEDOUT;
 216
 217         /* read out all data */
 218         rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
 219
 220         if (do_rx && rx_tail != len)
 221                 return -EIO;
 222
 223         if (!rx_tail)
 224                 return 0;
 225
 226         len = 0;
 227         t = first;
 228         /* Read out all the data */
 229         for (i = 0; i < num_transfers; i++) {
 230                 if (t->rx_buf)
 231                         memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
 232
 233                 if (t != first || prepend_len == 0)
 234                         len += t->len;
 235
 236                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 237                                transfer_list);
 238         }
 239
 240         return 0;
 241 }
 242
 243 static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
 244 {
 245         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 246
 247         pm_runtime_get_sync(&bs->pdev->dev);
 248
 249         return 0;
 250 }
 251
 252 static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
 253 {
 254         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 255
 256         pm_runtime_put(&bs->pdev->dev);
 257
 258         return 0;
 259 }
 260
 261 static int bcm63xx_spi_transfer_one(struct spi_master *master,
 262                                         struct spi_message *m)
 263 {
 264         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 265         struct spi_transfer *t, *first = NULL;
 266         struct spi_device *spi = m->spi;
 267         int status = 0;
 268         unsigned int n_transfers = 0, total_len = 0;
 269         bool can_use_prepend = false;
 270
 271         /*
 272          * This SPI controller does not support keeping CS active after a
 273          * transfer.
 274          * Work around this by merging as many transfers we can into one big
 275          * full-duplex transfers.
 276          */
 277         list_for_each_entry(t, &m->transfers, transfer_list) {
 278                 if (t->bits_per_word != 8) {
 279                         dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
 280                                 __func__, t->bits_per_word);
 281                         status = -EINVAL;
 282                         goto exit;
 283                 }
 284
 285                 if (!first)
 286                         first = t;
 287
 288                 n_transfers++;
 289                 total_len += t->len;
 290
 291                 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
 292                     first->len <= BCM63XX_SPI_MAX_PREPEND)
 293                         can_use_prepend = true;
 294                 else if (can_use_prepend && t->tx_buf)
 295                         can_use_prepend = false;
 296
 297                 /* we can only transfer one fifo worth of data */
 298                 if ((can_use_prepend &&
 299                      total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
 300                     (!can_use_prepend && total_len > bs->fifo_size)) {
 301                         dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
 302                                 total_len, bs->fifo_size);
 303                         status = -EINVAL;
 304                         goto exit;
 305                 }
 306
 307                 /* all combined transfers have to have the same speed */
 308                 if (t->speed_hz != first->speed_hz) {
 309                         dev_err(&spi->dev, "unable to change speed between transfers\n");
 310                         status = -EINVAL;
 311                         goto exit;
 312                 }
 313
 314                 /* CS will be deasserted directly after transfer */
 315                 if (t->delay_usecs) {
 316                         dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
 317                         status = -EINVAL;
 318                         goto exit;
 319                 }
 320
 321                 if (t->cs_change ||
 322                     list_is_last(&t->transfer_list, &m->transfers)) {
 323                         /* configure adapter for a new transfer */
 324                         bcm63xx_spi_setup_transfer(spi, first);
 325
 326                         /* send the data */
 327                         status = bcm63xx_txrx_bufs(spi, first, n_transfers);
 328                         if (status)
 329                                 goto exit;
 330
 331                         m->actual_length += total_len;
 332
 333                         first = NULL;
 334                         n_transfers = 0;
 335                         total_len = 0;
 336                         can_use_prepend = false;
 337                 }
 338         }
 339 exit:
 340         m->status = status;
 341         spi_finalize_current_message(master);
 342
 343         return 0;
 344 }
 345
 346 /* This driver supports single master mode only. Hence
 347  * CMD_DONE is the only interrupt we care about
 348  */
 349 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 350 {
 351         struct spi_master *master = (struct spi_master *)dev_id;
 352         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 353         u8 intr;
 354
 355         /* Read interupts and clear them immediately */
 356         intr = bcm_spi_readb(bs, SPI_INT_STATUS);
 357         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 358         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 359
 360         /* A transfer completed */
 361         if (intr & SPI_INTR_CMD_DONE)
 362                 complete(&bs->done);
 363
 364         return IRQ_HANDLED;
 365 }
 366
 367
 368 static int bcm63xx_spi_probe(struct platform_device *pdev)
 369 {
 370         struct resource *r;
 371         struct device *dev = &pdev->dev;
 372         struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
 373         int irq;
 374         struct spi_master *master;
 375         struct clk *clk;
 376         struct bcm63xx_spi *bs;
 377         int ret;
 378
 379         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 380         if (!r) {
 381                 dev_err(dev, "no iomem\n");
 382                 ret = -ENXIO;
 383                 goto out;
 384         }
 385
 386         irq = platform_get_irq(pdev, 0);
 387         if (irq < 0) {
 388                 dev_err(dev, "no irq\n");
 389                 ret = -ENXIO;
 390                 goto out;
 391         }
 392
 393         clk = clk_get(dev, "spi");
 394         if (IS_ERR(clk)) {
 395                 dev_err(dev, "no clock for device\n");
 396                 ret = PTR_ERR(clk);
 397                 goto out;
 398         }
 399
 400         master = spi_alloc_master(dev, sizeof(*bs));
 401         if (!master) {
 402                 dev_err(dev, "out of memory\n");
 403                 ret = -ENOMEM;
 404                 goto out_clk;
 405         }
 406
 407         bs = spi_master_get_devdata(master);
 408
 409         platform_set_drvdata(pdev, master);
 410         bs->pdev = pdev;
 411
 412         bs->regs = devm_ioremap_resource(&pdev->dev, r);
 413         if (IS_ERR(bs->regs)) {
 414                 ret = PTR_ERR(bs->regs);
 415                 goto out_err;
 416         }
 417
 418         bs->irq = irq;
 419         bs->clk = clk;
 420         bs->fifo_size = pdata->fifo_size;
 421
 422         ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
 423                                                         pdev->name, master);
 424         if (ret) {
 425                 dev_err(dev, "unable to request irq\n");
 426                 goto out_err;
 427         }
 428
 429         master->bus_num = pdata->bus_num;
 430         master->num_chipselect = pdata->num_chipselect;
 431         master->setup = bcm63xx_spi_setup;
 432         master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
 433         master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
 434         master->transfer_one_message = bcm63xx_spi_transfer_one;
 435         master->mode_bits = MODEBITS;
 436         bs->msg_type_shift = pdata->msg_type_shift;
 437         bs->msg_ctl_width = pdata->msg_ctl_width;
 438         bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
 439         bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
 440
 441         switch (bs->msg_ctl_width) {
 442         case 8:
 443         case 16:
 444                 break;
 445         default:
 446                 dev_err(dev, "unsupported MSG_CTL width: %d\n",
 447                          bs->msg_ctl_width);
 448                 goto out_err;
 449         }
 450
 451         /* Initialize hardware */
 452         clk_prepare_enable(bs->clk);
 453         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 454
 455         /* register and we are done */
 456         ret = spi_register_master(master);
 457         if (ret) {
 458                 dev_err(dev, "spi register failed\n");
 459                 goto out_clk_disable;
 460         }
 461
 462         dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
 463                  r->start, irq, bs->fifo_size);
 464
 465         return 0;
 466
 467 out_clk_disable:
 468         clk_disable_unprepare(clk);
 469 out_err:
 470         platform_set_drvdata(pdev, NULL);
 471         spi_master_put(master);
 472 out_clk:
 473         clk_put(clk);
 474 out:
 475         return ret;
 476 }
 477
 478 static int bcm63xx_spi_remove(struct platform_device *pdev)
 479 {
 480         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
 481         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 482
 483         spi_unregister_master(master);
 484
 485         /* reset spi block */
 486         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 487
 488         /* HW shutdown */
 489         clk_disable_unprepare(bs->clk);
 490         clk_put(bs->clk);
 491
 492         platform_set_drvdata(pdev, 0);
 493
 494         spi_master_put(master);
 495
 496         return 0;
 497 }
 498
 499 #ifdef CONFIG_PM
 500 static int bcm63xx_spi_suspend(struct device *dev)
 501 {
 502         struct spi_master *master =
 503                         platform_get_drvdata(to_platform_device(dev));
 504         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 505
 506         spi_master_suspend(master);
 507
 508         clk_disable_unprepare(bs->clk);
 509
 510         return 0;
 511 }
 512
 513 static int bcm63xx_spi_resume(struct device *dev)
 514 {
 515         struct spi_master *master =
 516                         platform_get_drvdata(to_platform_device(dev));
 517         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 518
 519         clk_prepare_enable(bs->clk);
 520
 521         spi_master_resume(master);
 522
 523         return 0;
 524 }
 525
 526 static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
 527         .suspend        = bcm63xx_spi_suspend,
 528         .resume         = bcm63xx_spi_resume,
 529 };
 530
 531 #define BCM63XX_SPI_PM_OPS      (&bcm63xx_spi_pm_ops)
 532 #else
 533 #define BCM63XX_SPI_PM_OPS      NULL
 534 #endif
 535
 536 static struct platform_driver bcm63xx_spi_driver = {
 537         .driver = {
 538                 .name   = "bcm63xx-spi",
 539                 .owner  = THIS_MODULE,
 540                 .pm     = BCM63XX_SPI_PM_OPS,
 541         },
 542         .probe          = bcm63xx_spi_probe,
 543         .remove         = bcm63xx_spi_remove,
 544 };
 545
 546 module_platform_driver(bcm63xx_spi_driver);
 547
 548 MODULE_ALIAS("platform:bcm63xx_spi");
 549 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 550 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
 551 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 552 MODULE_LICENSE("GPL");