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usblp: do not set TASK_INTERRUPTIBLE before lock
[linux/fpc-iii.git] / drivers / tty / serial / samsung.c
blobb8366b154fb9e8b9746111761f61f32c6febc054
1 /*
2 * Driver core for Samsung SoC onboard UARTs.
3 *
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 /* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25 */
26
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #define SUPPORT_SYSRQ
29 #endif
30
31 #include <linux/module.h>
32 #include <linux/ioport.h>
33 #include <linux/io.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/serial_s3c.h>
43 #include <linux/delay.h>
44 #include <linux/clk.h>
45 #include <linux/cpufreq.h>
46 #include <linux/of.h>
47
48 #include <asm/irq.h>
49
50 #ifdef CONFIG_SAMSUNG_CLOCK
51 #include <plat/clock.h>
52 #endif
53
54 #include "samsung.h"
55
56 /* UART name and device definitions */
57
58 #define S3C24XX_SERIAL_NAME "ttySAC"
59 #define S3C24XX_SERIAL_MAJOR 204
60 #define S3C24XX_SERIAL_MINOR 64
61
62 /* macros to change one thing to another */
63
64 #define tx_enabled(port) ((port)->unused[0])
65 #define rx_enabled(port) ((port)->unused[1])
66
67 /* flag to ignore all characters coming in */
68 #define RXSTAT_DUMMY_READ (0x10000000)
69
70 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
71 {
72 return container_of(port, struct s3c24xx_uart_port, port);
73 }
74
75 /* translate a port to the device name */
76
77 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
78 {
79 return to_platform_device(port->dev)->name;
80 }
81
82 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
83 {
84 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
85 }
86
87 /*
88 * s3c64xx and later SoC's include the interrupt mask and status registers in
89 * the controller itself, unlike the s3c24xx SoC's which have these registers
90 * in the interrupt controller. Check if the port type is s3c64xx or higher.
91 */
92 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
93 {
94 return to_ourport(port)->info->type == PORT_S3C6400;
95 }
96
97 static void s3c24xx_serial_rx_enable(struct uart_port *port)
98 {
99 unsigned long flags;
100 unsigned int ucon, ufcon;
101 int count = 10000;
102
103 spin_lock_irqsave(&port->lock, flags);
104
105 while (--count && !s3c24xx_serial_txempty_nofifo(port))
106 udelay(100);
107
108 ufcon = rd_regl(port, S3C2410_UFCON);
109 ufcon |= S3C2410_UFCON_RESETRX;
110 wr_regl(port, S3C2410_UFCON, ufcon);
111
112 ucon = rd_regl(port, S3C2410_UCON);
113 ucon |= S3C2410_UCON_RXIRQMODE;
114 wr_regl(port, S3C2410_UCON, ucon);
115
116 rx_enabled(port) = 1;
117 spin_unlock_irqrestore(&port->lock, flags);
118 }
119
120 static void s3c24xx_serial_rx_disable(struct uart_port *port)
121 {
122 unsigned long flags;
123 unsigned int ucon;
124
125 spin_lock_irqsave(&port->lock, flags);
126
127 ucon = rd_regl(port, S3C2410_UCON);
128 ucon &= ~S3C2410_UCON_RXIRQMODE;
129 wr_regl(port, S3C2410_UCON, ucon);
130
131 rx_enabled(port) = 0;
132 spin_unlock_irqrestore(&port->lock, flags);
133 }
134
135 static void s3c24xx_serial_stop_tx(struct uart_port *port)
136 {
137 struct s3c24xx_uart_port *ourport = to_ourport(port);
138
139 if (tx_enabled(port)) {
140 if (s3c24xx_serial_has_interrupt_mask(port))
141 __set_bit(S3C64XX_UINTM_TXD,
142 portaddrl(port, S3C64XX_UINTM));
143 else
144 disable_irq_nosync(ourport->tx_irq);
145 tx_enabled(port) = 0;
146 if (port->flags & UPF_CONS_FLOW)
147 s3c24xx_serial_rx_enable(port);
148 }
149 }
150
151 static void s3c24xx_serial_start_tx(struct uart_port *port)
152 {
153 struct s3c24xx_uart_port *ourport = to_ourport(port);
154
155 if (!tx_enabled(port)) {
156 if (port->flags & UPF_CONS_FLOW)
157 s3c24xx_serial_rx_disable(port);
158
159 if (s3c24xx_serial_has_interrupt_mask(port))
160 __clear_bit(S3C64XX_UINTM_TXD,
161 portaddrl(port, S3C64XX_UINTM));
162 else
163 enable_irq(ourport->tx_irq);
164 tx_enabled(port) = 1;
165 }
166 }
167
168 static void s3c24xx_serial_stop_rx(struct uart_port *port)
169 {
170 struct s3c24xx_uart_port *ourport = to_ourport(port);
171
172 if (rx_enabled(port)) {
173 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
174 if (s3c24xx_serial_has_interrupt_mask(port))
175 __set_bit(S3C64XX_UINTM_RXD,
176 portaddrl(port, S3C64XX_UINTM));
177 else
178 disable_irq_nosync(ourport->rx_irq);
179 rx_enabled(port) = 0;
180 }
181 }
182
183 static void s3c24xx_serial_enable_ms(struct uart_port *port)
184 {
185 }
186
187 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
188 {
189 return to_ourport(port)->info;
190 }
191
192 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
193 {
194 struct s3c24xx_uart_port *ourport;
195
196 if (port->dev == NULL)
197 return NULL;
198
199 ourport = container_of(port, struct s3c24xx_uart_port, port);
200 return ourport->cfg;
201 }
202
203 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
204 unsigned long ufstat)
205 {
206 struct s3c24xx_uart_info *info = ourport->info;
207
208 if (ufstat & info->rx_fifofull)
209 return ourport->port.fifosize;
210
211 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
212 }
213
214
215 /* ? - where has parity gone?? */
216 #define S3C2410_UERSTAT_PARITY (0x1000)
217
218 static irqreturn_t
219 s3c24xx_serial_rx_chars(int irq, void *dev_id)
220 {
221 struct s3c24xx_uart_port *ourport = dev_id;
222 struct uart_port *port = &ourport->port;
223 unsigned int ufcon, ch, flag, ufstat, uerstat;
224 unsigned long flags;
225 int max_count = 64;
226
227 spin_lock_irqsave(&port->lock, flags);
228
229 while (max_count-- > 0) {
230 ufcon = rd_regl(port, S3C2410_UFCON);
231 ufstat = rd_regl(port, S3C2410_UFSTAT);
232
233 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
234 break;
235
236 uerstat = rd_regl(port, S3C2410_UERSTAT);
237 ch = rd_regb(port, S3C2410_URXH);
238
239 if (port->flags & UPF_CONS_FLOW) {
240 int txe = s3c24xx_serial_txempty_nofifo(port);
241
242 if (rx_enabled(port)) {
243 if (!txe) {
244 rx_enabled(port) = 0;
245 continue;
246 }
247 } else {
248 if (txe) {
249 ufcon |= S3C2410_UFCON_RESETRX;
250 wr_regl(port, S3C2410_UFCON, ufcon);
251 rx_enabled(port) = 1;
252 goto out;
253 }
254 continue;
255 }
256 }
257
258 /* insert the character into the buffer */
259
260 flag = TTY_NORMAL;
261 port->icount.rx++;
262
263 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
264 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
265 ch, uerstat);
266
267 /* check for break */
268 if (uerstat & S3C2410_UERSTAT_BREAK) {
269 dbg("break!\n");
270 port->icount.brk++;
271 if (uart_handle_break(port))
272 goto ignore_char;
273 }
274
275 if (uerstat & S3C2410_UERSTAT_FRAME)
276 port->icount.frame++;
277 if (uerstat & S3C2410_UERSTAT_OVERRUN)
278 port->icount.overrun++;
279
280 uerstat &= port->read_status_mask;
281
282 if (uerstat & S3C2410_UERSTAT_BREAK)
283 flag = TTY_BREAK;
284 else if (uerstat & S3C2410_UERSTAT_PARITY)
285 flag = TTY_PARITY;
286 else if (uerstat & (S3C2410_UERSTAT_FRAME |
287 S3C2410_UERSTAT_OVERRUN))
288 flag = TTY_FRAME;
289 }
290
291 if (uart_handle_sysrq_char(port, ch))
292 goto ignore_char;
293
294 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
295 ch, flag);
296
297 ignore_char:
298 continue;
299 }
300 tty_flip_buffer_push(&port->state->port);
301
302 out:
303 spin_unlock_irqrestore(&port->lock, flags);
304 return IRQ_HANDLED;
305 }
306
307 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
308 {
309 struct s3c24xx_uart_port *ourport = id;
310 struct uart_port *port = &ourport->port;
311 struct circ_buf *xmit = &port->state->xmit;
312 unsigned long flags;
313 int count = 256;
314
315 spin_lock_irqsave(&port->lock, flags);
316
317 if (port->x_char) {
318 wr_regb(port, S3C2410_UTXH, port->x_char);
319 port->icount.tx++;
320 port->x_char = 0;
321 goto out;
322 }
323
324 /* if there isn't anything more to transmit, or the uart is now
325 * stopped, disable the uart and exit
326 */
327
328 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
329 s3c24xx_serial_stop_tx(port);
330 goto out;
331 }
332
333 /* try and drain the buffer... */
334
335 while (!uart_circ_empty(xmit) && count-- > 0) {
336 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
337 break;
338
339 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
340 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
341 port->icount.tx++;
342 }
343
344 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
345 spin_unlock(&port->lock);
346 uart_write_wakeup(port);
347 spin_lock(&port->lock);
348 }
349
350 if (uart_circ_empty(xmit))
351 s3c24xx_serial_stop_tx(port);
352
353 out:
354 spin_unlock_irqrestore(&port->lock, flags);
355 return IRQ_HANDLED;
356 }
357
358 /* interrupt handler for s3c64xx and later SoC's.*/
359 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
360 {
361 struct s3c24xx_uart_port *ourport = id;
362 struct uart_port *port = &ourport->port;
363 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
364 irqreturn_t ret = IRQ_HANDLED;
365
366 if (pend & S3C64XX_UINTM_RXD_MSK) {
367 ret = s3c24xx_serial_rx_chars(irq, id);
368 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
369 }
370 if (pend & S3C64XX_UINTM_TXD_MSK) {
371 ret = s3c24xx_serial_tx_chars(irq, id);
372 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
373 }
374 return ret;
375 }
376
377 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
378 {
379 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
380 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
381 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
382
383 if (ufcon & S3C2410_UFCON_FIFOMODE) {
384 if ((ufstat & info->tx_fifomask) != 0 ||
385 (ufstat & info->tx_fifofull))
386 return 0;
387
388 return 1;
389 }
390
391 return s3c24xx_serial_txempty_nofifo(port);
392 }
393
394 /* no modem control lines */
395 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
396 {
397 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
398
399 if (umstat & S3C2410_UMSTAT_CTS)
400 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
401 else
402 return TIOCM_CAR | TIOCM_DSR;
403 }
404
405 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
406 {
407 /* todo - possibly remove AFC and do manual CTS */
408 }
409
410 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
411 {
412 unsigned long flags;
413 unsigned int ucon;
414
415 spin_lock_irqsave(&port->lock, flags);
416
417 ucon = rd_regl(port, S3C2410_UCON);
418
419 if (break_state)
420 ucon |= S3C2410_UCON_SBREAK;
421 else
422 ucon &= ~S3C2410_UCON_SBREAK;
423
424 wr_regl(port, S3C2410_UCON, ucon);
425
426 spin_unlock_irqrestore(&port->lock, flags);
427 }
428
429 static void s3c24xx_serial_shutdown(struct uart_port *port)
430 {
431 struct s3c24xx_uart_port *ourport = to_ourport(port);
432
433 if (ourport->tx_claimed) {
434 if (!s3c24xx_serial_has_interrupt_mask(port))
435 free_irq(ourport->tx_irq, ourport);
436 tx_enabled(port) = 0;
437 ourport->tx_claimed = 0;
438 }
439
440 if (ourport->rx_claimed) {
441 if (!s3c24xx_serial_has_interrupt_mask(port))
442 free_irq(ourport->rx_irq, ourport);
443 ourport->rx_claimed = 0;
444 rx_enabled(port) = 0;
445 }
446
447 /* Clear pending interrupts and mask all interrupts */
448 if (s3c24xx_serial_has_interrupt_mask(port)) {
449 free_irq(port->irq, ourport);
450
451 wr_regl(port, S3C64XX_UINTP, 0xf);
452 wr_regl(port, S3C64XX_UINTM, 0xf);
453 }
454 }
455
456 static int s3c24xx_serial_startup(struct uart_port *port)
457 {
458 struct s3c24xx_uart_port *ourport = to_ourport(port);
459 int ret;
460
461 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
462 port->mapbase, port->membase);
463
464 rx_enabled(port) = 1;
465
466 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
467 s3c24xx_serial_portname(port), ourport);
468
469 if (ret != 0) {
470 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
471 return ret;
472 }
473
474 ourport->rx_claimed = 1;
475
476 dbg("requesting tx irq...\n");
477
478 tx_enabled(port) = 1;
479
480 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
481 s3c24xx_serial_portname(port), ourport);
482
483 if (ret) {
484 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
485 goto err;
486 }
487
488 ourport->tx_claimed = 1;
489
490 dbg("s3c24xx_serial_startup ok\n");
491
492 /* the port reset code should have done the correct
493 * register setup for the port controls */
494
495 return ret;
496
497 err:
498 s3c24xx_serial_shutdown(port);
499 return ret;
500 }
501
502 static int s3c64xx_serial_startup(struct uart_port *port)
503 {
504 struct s3c24xx_uart_port *ourport = to_ourport(port);
505 int ret;
506
507 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
508 port->mapbase, port->membase);
509
510 wr_regl(port, S3C64XX_UINTM, 0xf);
511
512 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
513 s3c24xx_serial_portname(port), ourport);
514 if (ret) {
515 dev_err(port->dev, "cannot get irq %d\n", port->irq);
516 return ret;
517 }
518
519 /* For compatibility with s3c24xx Soc's */
520 rx_enabled(port) = 1;
521 ourport->rx_claimed = 1;
522 tx_enabled(port) = 0;
523 ourport->tx_claimed = 1;
524
525 /* Enable Rx Interrupt */
526 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
527 dbg("s3c64xx_serial_startup ok\n");
528 return ret;
529 }
530
531 /* power power management control */
532
533 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
534 unsigned int old)
535 {
536 struct s3c24xx_uart_port *ourport = to_ourport(port);
537 int timeout = 10000;
538
539 ourport->pm_level = level;
540
541 switch (level) {
542 case 3:
543 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
544 udelay(100);
545
546 if (!IS_ERR(ourport->baudclk))
547 clk_disable_unprepare(ourport->baudclk);
548
549 clk_disable_unprepare(ourport->clk);
550 break;
551
552 case 0:
553 clk_prepare_enable(ourport->clk);
554
555 if (!IS_ERR(ourport->baudclk))
556 clk_prepare_enable(ourport->baudclk);
557
558 break;
559 default:
560 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
561 }
562 }
563
564 /* baud rate calculation
565 *
566 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
567 * of different sources, including the peripheral clock ("pclk") and an
568 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
569 * with a programmable extra divisor.
570 *
571 * The following code goes through the clock sources, and calculates the
572 * baud clocks (and the resultant actual baud rates) and then tries to
573 * pick the closest one and select that.
574 *
575 */
576
577 #define MAX_CLK_NAME_LENGTH 15
578
579 static inline int s3c24xx_serial_getsource(struct uart_port *port)
580 {
581 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
582 unsigned int ucon;
583
584 if (info->num_clks == 1)
585 return 0;
586
587 ucon = rd_regl(port, S3C2410_UCON);
588 ucon &= info->clksel_mask;
589 return ucon >> info->clksel_shift;
590 }
591
592 static void s3c24xx_serial_setsource(struct uart_port *port,
593 unsigned int clk_sel)
594 {
595 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
596 unsigned int ucon;
597
598 if (info->num_clks == 1)
599 return;
600
601 ucon = rd_regl(port, S3C2410_UCON);
602 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
603 return;
604
605 ucon &= ~info->clksel_mask;
606 ucon |= clk_sel << info->clksel_shift;
607 wr_regl(port, S3C2410_UCON, ucon);
608 }
609
610 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
611 unsigned int req_baud, struct clk **best_clk,
612 unsigned int *clk_num)
613 {
614 struct s3c24xx_uart_info *info = ourport->info;
615 struct clk *clk;
616 unsigned long rate;
617 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
618 char clkname[MAX_CLK_NAME_LENGTH];
619 int calc_deviation, deviation = (1 << 30) - 1;
620
621 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
622 ourport->info->def_clk_sel;
623 for (cnt = 0; cnt < info->num_clks; cnt++) {
624 if (!(clk_sel & (1 << cnt)))
625 continue;
626
627 sprintf(clkname, "clk_uart_baud%d", cnt);
628 clk = clk_get(ourport->port.dev, clkname);
629 if (IS_ERR(clk))
630 continue;
631
632 rate = clk_get_rate(clk);
633 if (!rate)
634 continue;
635
636 if (ourport->info->has_divslot) {
637 unsigned long div = rate / req_baud;
638
639 /* The UDIVSLOT register on the newer UARTs allows us to
640 * get a divisor adjustment of 1/16th on the baud clock.
641 *
642 * We don't keep the UDIVSLOT value (the 16ths we
643 * calculated by not multiplying the baud by 16) as it
644 * is easy enough to recalculate.
645 */
646
647 quot = div / 16;
648 baud = rate / div;
649 } else {
650 quot = (rate + (8 * req_baud)) / (16 * req_baud);
651 baud = rate / (quot * 16);
652 }
653 quot--;
654
655 calc_deviation = req_baud - baud;
656 if (calc_deviation < 0)
657 calc_deviation = -calc_deviation;
658
659 if (calc_deviation < deviation) {
660 *best_clk = clk;
661 best_quot = quot;
662 *clk_num = cnt;
663 deviation = calc_deviation;
664 }
665 }
666
667 return best_quot;
668 }
669
670 /* udivslot_table[]
671 *
672 * This table takes the fractional value of the baud divisor and gives
673 * the recommended setting for the UDIVSLOT register.
674 */
675 static u16 udivslot_table[16] = {
676 [0] = 0x0000,
677 [1] = 0x0080,
678 [2] = 0x0808,
679 [3] = 0x0888,
680 [4] = 0x2222,
681 [5] = 0x4924,
682 [6] = 0x4A52,
683 [7] = 0x54AA,
684 [8] = 0x5555,
685 [9] = 0xD555,
686 [10] = 0xD5D5,
687 [11] = 0xDDD5,
688 [12] = 0xDDDD,
689 [13] = 0xDFDD,
690 [14] = 0xDFDF,
691 [15] = 0xFFDF,
692 };
693
694 static void s3c24xx_serial_set_termios(struct uart_port *port,
695 struct ktermios *termios,
696 struct ktermios *old)
697 {
698 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
699 struct s3c24xx_uart_port *ourport = to_ourport(port);
700 struct clk *clk = ERR_PTR(-EINVAL);
701 unsigned long flags;
702 unsigned int baud, quot, clk_sel = 0;
703 unsigned int ulcon;
704 unsigned int umcon;
705 unsigned int udivslot = 0;
706
707 /*
708 * We don't support modem control lines.
709 */
710 termios->c_cflag &= ~(HUPCL | CMSPAR);
711 termios->c_cflag |= CLOCAL;
712
713 /*
714 * Ask the core to calculate the divisor for us.
715 */
716
717 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
718 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
719 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
720 quot = port->custom_divisor;
721 if (IS_ERR(clk))
722 return;
723
724 /* check to see if we need to change clock source */
725
726 if (ourport->baudclk != clk) {
727 s3c24xx_serial_setsource(port, clk_sel);
728
729 if (!IS_ERR(ourport->baudclk)) {
730 clk_disable_unprepare(ourport->baudclk);
731 ourport->baudclk = ERR_PTR(-EINVAL);
732 }
733
734 clk_prepare_enable(clk);
735
736 ourport->baudclk = clk;
737 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
738 }
739
740 if (ourport->info->has_divslot) {
741 unsigned int div = ourport->baudclk_rate / baud;
742
743 if (cfg->has_fracval) {
744 udivslot = (div & 15);
745 dbg("fracval = %04x\n", udivslot);
746 } else {
747 udivslot = udivslot_table[div & 15];
748 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
749 }
750 }
751
752 switch (termios->c_cflag & CSIZE) {
753 case CS5:
754 dbg("config: 5bits/char\n");
755 ulcon = S3C2410_LCON_CS5;
756 break;
757 case CS6:
758 dbg("config: 6bits/char\n");
759 ulcon = S3C2410_LCON_CS6;
760 break;
761 case CS7:
762 dbg("config: 7bits/char\n");
763 ulcon = S3C2410_LCON_CS7;
764 break;
765 case CS8:
766 default:
767 dbg("config: 8bits/char\n");
768 ulcon = S3C2410_LCON_CS8;
769 break;
770 }
771
772 /* preserve original lcon IR settings */
773 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
774
775 if (termios->c_cflag & CSTOPB)
776 ulcon |= S3C2410_LCON_STOPB;
777
778 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
779
780 if (termios->c_cflag & PARENB) {
781 if (termios->c_cflag & PARODD)
782 ulcon |= S3C2410_LCON_PODD;
783 else
784 ulcon |= S3C2410_LCON_PEVEN;
785 } else {
786 ulcon |= S3C2410_LCON_PNONE;
787 }
788
789 spin_lock_irqsave(&port->lock, flags);
790
791 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
792 ulcon, quot, udivslot);
793
794 wr_regl(port, S3C2410_ULCON, ulcon);
795 wr_regl(port, S3C2410_UBRDIV, quot);
796 wr_regl(port, S3C2410_UMCON, umcon);
797
798 if (ourport->info->has_divslot)
799 wr_regl(port, S3C2443_DIVSLOT, udivslot);
800
801 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
802 rd_regl(port, S3C2410_ULCON),
803 rd_regl(port, S3C2410_UCON),
804 rd_regl(port, S3C2410_UFCON));
805
806 /*
807 * Update the per-port timeout.
808 */
809 uart_update_timeout(port, termios->c_cflag, baud);
810
811 /*
812 * Which character status flags are we interested in?
813 */
814 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
815 if (termios->c_iflag & INPCK)
816 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
817
818 /*
819 * Which character status flags should we ignore?
820 */
821 port->ignore_status_mask = 0;
822 if (termios->c_iflag & IGNPAR)
823 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
824 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
825 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
826
827 /*
828 * Ignore all characters if CREAD is not set.
829 */
830 if ((termios->c_cflag & CREAD) == 0)
831 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
832
833 spin_unlock_irqrestore(&port->lock, flags);
834 }
835
836 static const char *s3c24xx_serial_type(struct uart_port *port)
837 {
838 switch (port->type) {
839 case PORT_S3C2410:
840 return "S3C2410";
841 case PORT_S3C2440:
842 return "S3C2440";
843 case PORT_S3C2412:
844 return "S3C2412";
845 case PORT_S3C6400:
846 return "S3C6400/10";
847 default:
848 return NULL;
849 }
850 }
851
852 #define MAP_SIZE (0x100)
853
854 static void s3c24xx_serial_release_port(struct uart_port *port)
855 {
856 release_mem_region(port->mapbase, MAP_SIZE);
857 }
858
859 static int s3c24xx_serial_request_port(struct uart_port *port)
860 {
861 const char *name = s3c24xx_serial_portname(port);
862 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
863 }
864
865 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
866 {
867 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
868
869 if (flags & UART_CONFIG_TYPE &&
870 s3c24xx_serial_request_port(port) == 0)
871 port->type = info->type;
872 }
873
874 /*
875 * verify the new serial_struct (for TIOCSSERIAL).
876 */
877 static int
878 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
879 {
880 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
881
882 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
883 return -EINVAL;
884
885 return 0;
886 }
887
888
889 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
890
891 static struct console s3c24xx_serial_console;
892
893 static int __init s3c24xx_serial_console_init(void)
894 {
895 register_console(&s3c24xx_serial_console);
896 return 0;
897 }
898 console_initcall(s3c24xx_serial_console_init);
899
900 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
901 #else
902 #define S3C24XX_SERIAL_CONSOLE NULL
903 #endif
904
905 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
906 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
907 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
908 unsigned char c);
909 #endif
910
911 static struct uart_ops s3c24xx_serial_ops = {
912 .pm = s3c24xx_serial_pm,
913 .tx_empty = s3c24xx_serial_tx_empty,
914 .get_mctrl = s3c24xx_serial_get_mctrl,
915 .set_mctrl = s3c24xx_serial_set_mctrl,
916 .stop_tx = s3c24xx_serial_stop_tx,
917 .start_tx = s3c24xx_serial_start_tx,
918 .stop_rx = s3c24xx_serial_stop_rx,
919 .enable_ms = s3c24xx_serial_enable_ms,
920 .break_ctl = s3c24xx_serial_break_ctl,
921 .startup = s3c24xx_serial_startup,
922 .shutdown = s3c24xx_serial_shutdown,
923 .set_termios = s3c24xx_serial_set_termios,
924 .type = s3c24xx_serial_type,
925 .release_port = s3c24xx_serial_release_port,
926 .request_port = s3c24xx_serial_request_port,
927 .config_port = s3c24xx_serial_config_port,
928 .verify_port = s3c24xx_serial_verify_port,
929 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
930 .poll_get_char = s3c24xx_serial_get_poll_char,
931 .poll_put_char = s3c24xx_serial_put_poll_char,
932 #endif
933 };
934
935 static struct uart_driver s3c24xx_uart_drv = {
936 .owner = THIS_MODULE,
937 .driver_name = "s3c2410_serial",
938 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
939 .cons = S3C24XX_SERIAL_CONSOLE,
940 .dev_name = S3C24XX_SERIAL_NAME,
941 .major = S3C24XX_SERIAL_MAJOR,
942 .minor = S3C24XX_SERIAL_MINOR,
943 };
944
945 static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
946 [0] = {
947 .port = {
948 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
949 .iotype = UPIO_MEM,
950 .uartclk = 0,
951 .fifosize = 16,
952 .ops = &s3c24xx_serial_ops,
953 .flags = UPF_BOOT_AUTOCONF,
954 .line = 0,
955 }
956 },
957 [1] = {
958 .port = {
959 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
960 .iotype = UPIO_MEM,
961 .uartclk = 0,
962 .fifosize = 16,
963 .ops = &s3c24xx_serial_ops,
964 .flags = UPF_BOOT_AUTOCONF,
965 .line = 1,
966 }
967 },
968 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
969
970 [2] = {
971 .port = {
972 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
973 .iotype = UPIO_MEM,
974 .uartclk = 0,
975 .fifosize = 16,
976 .ops = &s3c24xx_serial_ops,
977 .flags = UPF_BOOT_AUTOCONF,
978 .line = 2,
979 }
980 },
981 #endif
982 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
983 [3] = {
984 .port = {
985 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
986 .iotype = UPIO_MEM,
987 .uartclk = 0,
988 .fifosize = 16,
989 .ops = &s3c24xx_serial_ops,
990 .flags = UPF_BOOT_AUTOCONF,
991 .line = 3,
992 }
993 }
994 #endif
995 };
996
997 /* s3c24xx_serial_resetport
998 *
999 * reset the fifos and other the settings.
1000 */
1001
1002 static void s3c24xx_serial_resetport(struct uart_port *port,
1003 struct s3c2410_uartcfg *cfg)
1004 {
1005 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1006 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1007 unsigned int ucon_mask;
1008
1009 ucon_mask = info->clksel_mask;
1010 if (info->type == PORT_S3C2440)
1011 ucon_mask |= S3C2440_UCON0_DIVMASK;
1012
1013 ucon &= ucon_mask;
1014 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1015
1016 /* reset both fifos */
1017 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1018 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1019
1020 /* some delay is required after fifo reset */
1021 udelay(1);
1022 }
1023
1024
1025 #ifdef CONFIG_CPU_FREQ
1026
1027 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1028 unsigned long val, void *data)
1029 {
1030 struct s3c24xx_uart_port *port;
1031 struct uart_port *uport;
1032
1033 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1034 uport = &port->port;
1035
1036 /* check to see if port is enabled */
1037
1038 if (port->pm_level != 0)
1039 return 0;
1040
1041 /* try and work out if the baudrate is changing, we can detect
1042 * a change in rate, but we do not have support for detecting
1043 * a disturbance in the clock-rate over the change.
1044 */
1045
1046 if (IS_ERR(port->baudclk))
1047 goto exit;
1048
1049 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1050 goto exit;
1051
1052 if (val == CPUFREQ_PRECHANGE) {
1053 /* we should really shut the port down whilst the
1054 * frequency change is in progress. */
1055
1056 } else if (val == CPUFREQ_POSTCHANGE) {
1057 struct ktermios *termios;
1058 struct tty_struct *tty;
1059
1060 if (uport->state == NULL)
1061 goto exit;
1062
1063 tty = uport->state->port.tty;
1064
1065 if (tty == NULL)
1066 goto exit;
1067
1068 termios = &tty->termios;
1069
1070 if (termios == NULL) {
1071 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1072 goto exit;
1073 }
1074
1075 s3c24xx_serial_set_termios(uport, termios, NULL);
1076 }
1077
1078 exit:
1079 return 0;
1080 }
1081
1082 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1083 {
1084 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1085
1086 return cpufreq_register_notifier(&port->freq_transition,
1087 CPUFREQ_TRANSITION_NOTIFIER);
1088 }
1089
1090 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1091 {
1092 cpufreq_unregister_notifier(&port->freq_transition,
1093 CPUFREQ_TRANSITION_NOTIFIER);
1094 }
1095
1096 #else
1097 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1098 {
1099 return 0;
1100 }
1101
1102 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1103 {
1104 }
1105 #endif
1106
1107 /* s3c24xx_serial_init_port
1108 *
1109 * initialise a single serial port from the platform device given
1110 */
1111
1112 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1113 struct platform_device *platdev)
1114 {
1115 struct uart_port *port = &ourport->port;
1116 struct s3c2410_uartcfg *cfg = ourport->cfg;
1117 struct resource *res;
1118 int ret;
1119
1120 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1121
1122 if (platdev == NULL)
1123 return -ENODEV;
1124
1125 if (port->mapbase != 0)
1126 return 0;
1127
1128 /* setup info for port */
1129 port->dev = &platdev->dev;
1130
1131 /* Startup sequence is different for s3c64xx and higher SoC's */
1132 if (s3c24xx_serial_has_interrupt_mask(port))
1133 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1134
1135 port->uartclk = 1;
1136
1137 if (cfg->uart_flags & UPF_CONS_FLOW) {
1138 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1139 port->flags |= UPF_CONS_FLOW;
1140 }
1141
1142 /* sort our the physical and virtual addresses for each UART */
1143
1144 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1145 if (res == NULL) {
1146 dev_err(port->dev, "failed to find memory resource for uart\n");
1147 return -EINVAL;
1148 }
1149
1150 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1151
1152 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1153 if (!port->membase) {
1154 dev_err(port->dev, "failed to remap controller address\n");
1155 return -EBUSY;
1156 }
1157
1158 port->mapbase = res->start;
1159 ret = platform_get_irq(platdev, 0);
1160 if (ret < 0)
1161 port->irq = 0;
1162 else {
1163 port->irq = ret;
1164 ourport->rx_irq = ret;
1165 ourport->tx_irq = ret + 1;
1166 }
1167
1168 ret = platform_get_irq(platdev, 1);
1169 if (ret > 0)
1170 ourport->tx_irq = ret;
1171
1172 ourport->clk = clk_get(&platdev->dev, "uart");
1173 if (IS_ERR(ourport->clk)) {
1174 pr_err("%s: Controller clock not found\n",
1175 dev_name(&platdev->dev));
1176 return PTR_ERR(ourport->clk);
1177 }
1178
1179 ret = clk_prepare_enable(ourport->clk);
1180 if (ret) {
1181 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1182 clk_put(ourport->clk);
1183 return ret;
1184 }
1185
1186 /* Keep all interrupts masked and cleared */
1187 if (s3c24xx_serial_has_interrupt_mask(port)) {
1188 wr_regl(port, S3C64XX_UINTM, 0xf);
1189 wr_regl(port, S3C64XX_UINTP, 0xf);
1190 wr_regl(port, S3C64XX_UINTSP, 0xf);
1191 }
1192
1193 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1194 port->mapbase, port->membase, port->irq,
1195 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1196
1197 /* reset the fifos (and setup the uart) */
1198 s3c24xx_serial_resetport(port, cfg);
1199 clk_disable_unprepare(ourport->clk);
1200 return 0;
1201 }
1202
1203 #ifdef CONFIG_SAMSUNG_CLOCK
1204 static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1205 struct device_attribute *attr,
1206 char *buf)
1207 {
1208 struct uart_port *port = s3c24xx_dev_to_port(dev);
1209 struct s3c24xx_uart_port *ourport = to_ourport(port);
1210
1211 if (IS_ERR(ourport->baudclk))
1212 return -EINVAL;
1213
1214 return snprintf(buf, PAGE_SIZE, "* %s\n",
1215 ourport->baudclk->name ?: "(null)");
1216 }
1217
1218 static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1219 #endif
1220
1221 /* Device driver serial port probe */
1222
1223 static const struct of_device_id s3c24xx_uart_dt_match[];
1224 static int probe_index;
1225
1226 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1227 struct platform_device *pdev)
1228 {
1229 #ifdef CONFIG_OF
1230 if (pdev->dev.of_node) {
1231 const struct of_device_id *match;
1232 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1233 return (struct s3c24xx_serial_drv_data *)match->data;
1234 }
1235 #endif
1236 return (struct s3c24xx_serial_drv_data *)
1237 platform_get_device_id(pdev)->driver_data;
1238 }
1239
1240 static int s3c24xx_serial_probe(struct platform_device *pdev)
1241 {
1242 struct s3c24xx_uart_port *ourport;
1243 int ret;
1244
1245 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
1246
1247 ourport = &s3c24xx_serial_ports[probe_index];
1248
1249 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1250 if (!ourport->drv_data) {
1251 dev_err(&pdev->dev, "could not find driver data\n");
1252 return -ENODEV;
1253 }
1254
1255 ourport->baudclk = ERR_PTR(-EINVAL);
1256 ourport->info = ourport->drv_data->info;
1257 ourport->cfg = (pdev->dev.platform_data) ?
1258 (struct s3c2410_uartcfg *)pdev->dev.platform_data :
1259 ourport->drv_data->def_cfg;
1260
1261 ourport->port.fifosize = (ourport->info->fifosize) ?
1262 ourport->info->fifosize :
1263 ourport->drv_data->fifosize[probe_index];
1264
1265 probe_index++;
1266
1267 dbg("%s: initialising port %p...\n", __func__, ourport);
1268
1269 ret = s3c24xx_serial_init_port(ourport, pdev);
1270 if (ret < 0)
1271 goto probe_err;
1272
1273 dbg("%s: adding port\n", __func__);
1274 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1275 platform_set_drvdata(pdev, &ourport->port);
1276
1277 #ifdef CONFIG_SAMSUNG_CLOCK
1278 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
1279 if (ret < 0)
1280 dev_err(&pdev->dev, "failed to add clock source attr.\n");
1281 #endif
1282
1283 ret = s3c24xx_serial_cpufreq_register(ourport);
1284 if (ret < 0)
1285 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1286
1287 return 0;
1288
1289 probe_err:
1290 return ret;
1291 }
1292
1293 static int s3c24xx_serial_remove(struct platform_device *dev)
1294 {
1295 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1296
1297 if (port) {
1298 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1299 #ifdef CONFIG_SAMSUNG_CLOCK
1300 device_remove_file(&dev->dev, &dev_attr_clock_source);
1301 #endif
1302 uart_remove_one_port(&s3c24xx_uart_drv, port);
1303 }
1304
1305 return 0;
1306 }
1307
1308 /* UART power management code */
1309 #ifdef CONFIG_PM_SLEEP
1310 static int s3c24xx_serial_suspend(struct device *dev)
1311 {
1312 struct uart_port *port = s3c24xx_dev_to_port(dev);
1313
1314 if (port)
1315 uart_suspend_port(&s3c24xx_uart_drv, port);
1316
1317 return 0;
1318 }
1319
1320 static int s3c24xx_serial_resume(struct device *dev)
1321 {
1322 struct uart_port *port = s3c24xx_dev_to_port(dev);
1323 struct s3c24xx_uart_port *ourport = to_ourport(port);
1324
1325 if (port) {
1326 clk_prepare_enable(ourport->clk);
1327 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1328 clk_disable_unprepare(ourport->clk);
1329
1330 uart_resume_port(&s3c24xx_uart_drv, port);
1331 }
1332
1333 return 0;
1334 }
1335
1336 static int s3c24xx_serial_resume_noirq(struct device *dev)
1337 {
1338 struct uart_port *port = s3c24xx_dev_to_port(dev);
1339
1340 if (port) {
1341 /* restore IRQ mask */
1342 if (s3c24xx_serial_has_interrupt_mask(port)) {
1343 unsigned int uintm = 0xf;
1344 if (tx_enabled(port))
1345 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1346 if (rx_enabled(port))
1347 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1348 wr_regl(port, S3C64XX_UINTM, uintm);
1349 }
1350 }
1351
1352 return 0;
1353 }
1354
1355 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1356 .suspend = s3c24xx_serial_suspend,
1357 .resume = s3c24xx_serial_resume,
1358 .resume_noirq = s3c24xx_serial_resume_noirq,
1359 };
1360 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1361
1362 #else /* !CONFIG_PM_SLEEP */
1363
1364 #define SERIAL_SAMSUNG_PM_OPS NULL
1365 #endif /* CONFIG_PM_SLEEP */
1366
1367 /* Console code */
1368
1369 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1370
1371 static struct uart_port *cons_uart;
1372
1373 static int
1374 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1375 {
1376 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1377 unsigned long ufstat, utrstat;
1378
1379 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1380 /* fifo mode - check amount of data in fifo registers... */
1381
1382 ufstat = rd_regl(port, S3C2410_UFSTAT);
1383 return (ufstat & info->tx_fifofull) ? 0 : 1;
1384 }
1385
1386 /* in non-fifo mode, we go and use the tx buffer empty */
1387
1388 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1389 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1390 }
1391
1392 static bool
1393 s3c24xx_port_configured(unsigned int ucon)
1394 {
1395 /* consider the serial port configured if the tx/rx mode set */
1396 return (ucon & 0xf) != 0;
1397 }
1398
1399 #ifdef CONFIG_CONSOLE_POLL
1400 /*
1401 * Console polling routines for writing and reading from the uart while
1402 * in an interrupt or debug context.
1403 */
1404
1405 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1406 {
1407 struct s3c24xx_uart_port *ourport = to_ourport(port);
1408 unsigned int ufstat;
1409
1410 ufstat = rd_regl(port, S3C2410_UFSTAT);
1411 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1412 return NO_POLL_CHAR;
1413
1414 return rd_regb(port, S3C2410_URXH);
1415 }
1416
1417 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1418 unsigned char c)
1419 {
1420 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1421 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1422
1423 /* not possible to xmit on unconfigured port */
1424 if (!s3c24xx_port_configured(ucon))
1425 return;
1426
1427 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1428 cpu_relax();
1429 wr_regb(cons_uart, S3C2410_UTXH, c);
1430 }
1431
1432 #endif /* CONFIG_CONSOLE_POLL */
1433
1434 static void
1435 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1436 {
1437 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1438 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1439
1440 /* not possible to xmit on unconfigured port */
1441 if (!s3c24xx_port_configured(ucon))
1442 return;
1443
1444 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1445 barrier();
1446 wr_regb(cons_uart, S3C2410_UTXH, ch);
1447 }
1448
1449 static void
1450 s3c24xx_serial_console_write(struct console *co, const char *s,
1451 unsigned int count)
1452 {
1453 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1454 }
1455
1456 static void __init
1457 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1458 int *parity, int *bits)
1459 {
1460 struct clk *clk;
1461 unsigned int ulcon;
1462 unsigned int ucon;
1463 unsigned int ubrdiv;
1464 unsigned long rate;
1465 unsigned int clk_sel;
1466 char clk_name[MAX_CLK_NAME_LENGTH];
1467
1468 ulcon = rd_regl(port, S3C2410_ULCON);
1469 ucon = rd_regl(port, S3C2410_UCON);
1470 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1471
1472 dbg("s3c24xx_serial_get_options: port=%p\n"
1473 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1474 port, ulcon, ucon, ubrdiv);
1475
1476 if (s3c24xx_port_configured(ucon)) {
1477 switch (ulcon & S3C2410_LCON_CSMASK) {
1478 case S3C2410_LCON_CS5:
1479 *bits = 5;
1480 break;
1481 case S3C2410_LCON_CS6:
1482 *bits = 6;
1483 break;
1484 case S3C2410_LCON_CS7:
1485 *bits = 7;
1486 break;
1487 default:
1488 case S3C2410_LCON_CS8:
1489 *bits = 8;
1490 break;
1491 }
1492
1493 switch (ulcon & S3C2410_LCON_PMASK) {
1494 case S3C2410_LCON_PEVEN:
1495 *parity = 'e';
1496 break;
1497
1498 case S3C2410_LCON_PODD:
1499 *parity = 'o';
1500 break;
1501
1502 case S3C2410_LCON_PNONE:
1503 default:
1504 *parity = 'n';
1505 }
1506
1507 /* now calculate the baud rate */
1508
1509 clk_sel = s3c24xx_serial_getsource(port);
1510 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
1511
1512 clk = clk_get(port->dev, clk_name);
1513 if (!IS_ERR(clk))
1514 rate = clk_get_rate(clk);
1515 else
1516 rate = 1;
1517
1518 *baud = rate / (16 * (ubrdiv + 1));
1519 dbg("calculated baud %d\n", *baud);
1520 }
1521
1522 }
1523
1524 static int __init
1525 s3c24xx_serial_console_setup(struct console *co, char *options)
1526 {
1527 struct uart_port *port;
1528 int baud = 9600;
1529 int bits = 8;
1530 int parity = 'n';
1531 int flow = 'n';
1532
1533 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1534 co, co->index, options);
1535
1536 /* is this a valid port */
1537
1538 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1539 co->index = 0;
1540
1541 port = &s3c24xx_serial_ports[co->index].port;
1542
1543 /* is the port configured? */
1544
1545 if (port->mapbase == 0x0)
1546 return -ENODEV;
1547
1548 cons_uart = port;
1549
1550 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1551
1552 /*
1553 * Check whether an invalid uart number has been specified, and
1554 * if so, search for the first available port that does have
1555 * console support.
1556 */
1557 if (options)
1558 uart_parse_options(options, &baud, &parity, &bits, &flow);
1559 else
1560 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1561
1562 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1563
1564 return uart_set_options(port, co, baud, parity, bits, flow);
1565 }
1566
1567 static struct console s3c24xx_serial_console = {
1568 .name = S3C24XX_SERIAL_NAME,
1569 .device = uart_console_device,
1570 .flags = CON_PRINTBUFFER,
1571 .index = -1,
1572 .write = s3c24xx_serial_console_write,
1573 .setup = s3c24xx_serial_console_setup,
1574 .data = &s3c24xx_uart_drv,
1575 };
1576 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1577
1578 #ifdef CONFIG_CPU_S3C2410
1579 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1580 .info = &(struct s3c24xx_uart_info) {
1581 .name = "Samsung S3C2410 UART",
1582 .type = PORT_S3C2410,
1583 .fifosize = 16,
1584 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1585 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1586 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1587 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1588 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1589 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1590 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1591 .num_clks = 2,
1592 .clksel_mask = S3C2410_UCON_CLKMASK,
1593 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1594 },
1595 .def_cfg = &(struct s3c2410_uartcfg) {
1596 .ucon = S3C2410_UCON_DEFAULT,
1597 .ufcon = S3C2410_UFCON_DEFAULT,
1598 },
1599 };
1600 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1601 #else
1602 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1603 #endif
1604
1605 #ifdef CONFIG_CPU_S3C2412
1606 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1607 .info = &(struct s3c24xx_uart_info) {
1608 .name = "Samsung S3C2412 UART",
1609 .type = PORT_S3C2412,
1610 .fifosize = 64,
1611 .has_divslot = 1,
1612 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1613 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1614 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1615 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1616 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1617 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1618 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1619 .num_clks = 4,
1620 .clksel_mask = S3C2412_UCON_CLKMASK,
1621 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1622 },
1623 .def_cfg = &(struct s3c2410_uartcfg) {
1624 .ucon = S3C2410_UCON_DEFAULT,
1625 .ufcon = S3C2410_UFCON_DEFAULT,
1626 },
1627 };
1628 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1629 #else
1630 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1631 #endif
1632
1633 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1634 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
1635 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1636 .info = &(struct s3c24xx_uart_info) {
1637 .name = "Samsung S3C2440 UART",
1638 .type = PORT_S3C2440,
1639 .fifosize = 64,
1640 .has_divslot = 1,
1641 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1642 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1643 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1644 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1645 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1646 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1647 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1648 .num_clks = 4,
1649 .clksel_mask = S3C2412_UCON_CLKMASK,
1650 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1651 },
1652 .def_cfg = &(struct s3c2410_uartcfg) {
1653 .ucon = S3C2410_UCON_DEFAULT,
1654 .ufcon = S3C2410_UFCON_DEFAULT,
1655 },
1656 };
1657 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1658 #else
1659 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1660 #endif
1661
1662 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1663 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1664 defined(CONFIG_CPU_S5PC100)
1665 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1666 .info = &(struct s3c24xx_uart_info) {
1667 .name = "Samsung S3C6400 UART",
1668 .type = PORT_S3C6400,
1669 .fifosize = 64,
1670 .has_divslot = 1,
1671 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1672 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1673 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1674 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1675 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1676 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1677 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1678 .num_clks = 4,
1679 .clksel_mask = S3C6400_UCON_CLKMASK,
1680 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1681 },
1682 .def_cfg = &(struct s3c2410_uartcfg) {
1683 .ucon = S3C2410_UCON_DEFAULT,
1684 .ufcon = S3C2410_UFCON_DEFAULT,
1685 },
1686 };
1687 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1688 #else
1689 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1690 #endif
1691
1692 #ifdef CONFIG_CPU_S5PV210
1693 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1694 .info = &(struct s3c24xx_uart_info) {
1695 .name = "Samsung S5PV210 UART",
1696 .type = PORT_S3C6400,
1697 .has_divslot = 1,
1698 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1699 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1700 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1701 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1702 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1703 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1704 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1705 .num_clks = 2,
1706 .clksel_mask = S5PV210_UCON_CLKMASK,
1707 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1708 },
1709 .def_cfg = &(struct s3c2410_uartcfg) {
1710 .ucon = S5PV210_UCON_DEFAULT,
1711 .ufcon = S5PV210_UFCON_DEFAULT,
1712 },
1713 .fifosize = { 256, 64, 16, 16 },
1714 };
1715 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1716 #else
1717 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1718 #endif
1719
1720 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
1721 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
1722 defined(CONFIG_SOC_EXYNOS5440)
1723 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1724 .info = &(struct s3c24xx_uart_info) {
1725 .name = "Samsung Exynos4 UART",
1726 .type = PORT_S3C6400,
1727 .has_divslot = 1,
1728 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1729 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1730 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1731 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1732 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1733 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1734 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1735 .num_clks = 1,
1736 .clksel_mask = 0,
1737 .clksel_shift = 0,
1738 },
1739 .def_cfg = &(struct s3c2410_uartcfg) {
1740 .ucon = S5PV210_UCON_DEFAULT,
1741 .ufcon = S5PV210_UFCON_DEFAULT,
1742 .has_fracval = 1,
1743 },
1744 .fifosize = { 256, 64, 16, 16 },
1745 };
1746 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1747 #else
1748 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1749 #endif
1750
1751 static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1752 {
1753 .name = "s3c2410-uart",
1754 .driver_data = S3C2410_SERIAL_DRV_DATA,
1755 }, {
1756 .name = "s3c2412-uart",
1757 .driver_data = S3C2412_SERIAL_DRV_DATA,
1758 }, {
1759 .name = "s3c2440-uart",
1760 .driver_data = S3C2440_SERIAL_DRV_DATA,
1761 }, {
1762 .name = "s3c6400-uart",
1763 .driver_data = S3C6400_SERIAL_DRV_DATA,
1764 }, {
1765 .name = "s5pv210-uart",
1766 .driver_data = S5PV210_SERIAL_DRV_DATA,
1767 }, {
1768 .name = "exynos4210-uart",
1769 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1770 },
1771 { },
1772 };
1773 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1774
1775 #ifdef CONFIG_OF
1776 static const struct of_device_id s3c24xx_uart_dt_match[] = {
1777 { .compatible = "samsung,s3c2410-uart",
1778 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1779 { .compatible = "samsung,s3c2412-uart",
1780 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1781 { .compatible = "samsung,s3c2440-uart",
1782 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1783 { .compatible = "samsung,s3c6400-uart",
1784 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1785 { .compatible = "samsung,s5pv210-uart",
1786 .data = (void *)S5PV210_SERIAL_DRV_DATA },
1787 { .compatible = "samsung,exynos4210-uart",
1788 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
1789 {},
1790 };
1791 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
1792 #endif
1793
1794 static struct platform_driver samsung_serial_driver = {
1795 .probe = s3c24xx_serial_probe,
1796 .remove = s3c24xx_serial_remove,
1797 .id_table = s3c24xx_serial_driver_ids,
1798 .driver = {
1799 .name = "samsung-uart",
1800 .owner = THIS_MODULE,
1801 .pm = SERIAL_SAMSUNG_PM_OPS,
1802 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
1803 },
1804 };
1805
1806 /* module initialisation code */
1807
1808 static int __init s3c24xx_serial_modinit(void)
1809 {
1810 int ret;
1811
1812 ret = uart_register_driver(&s3c24xx_uart_drv);
1813 if (ret < 0) {
1814 pr_err("Failed to register Samsung UART driver\n");
1815 return ret;
1816 }
1817
1818 return platform_driver_register(&samsung_serial_driver);
1819 }
1820
1821 static void __exit s3c24xx_serial_modexit(void)
1822 {
1823 platform_driver_unregister(&samsung_serial_driver);
1824 uart_unregister_driver(&s3c24xx_uart_drv);
1825 }
1826
1827 module_init(s3c24xx_serial_modinit);
1828 module_exit(s3c24xx_serial_modexit);
1829
1830 MODULE_ALIAS("platform:samsung-uart");
1831 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1832 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1833 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support